Semiconductor device

Abstract

This semiconductor device includes: a first region which has a first conductivity type and is formed on a surface portion of a first main surface of an SiC chip; a plurality of second regions which have a second conductivity type, are formed on a surface portion of the first region, and provide a plurality of unit cells to the SiC chip; third regions which have the first conductivity type and are formed on surface portions of the second regions of the unit cells; planar-type gate structures which face channel regions in the second regions of the respective unit cells and control conduction of the channels between the first region and the third regions; a plurality of first pillar regions which have the second conductivity type, are commonly connected to the corresponding second region of each of the unit cells, extend in the depth direction of the SiC chip toward a second main surface of the SiC chip from the first main surface, and are physically separated and independent from each other; and second pillar regions which have the first conductivity type, are adjacent to the first pillar regions, and extend in the depth direction.

Description

Semiconductor Devices Related Applications

[0001] This application corresponds to Japanese Patent Application No. 2024-027706 filed with the Japan Patent Office on February 27, 2024, the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates to SiC semiconductor devices.

[0003] US Pat. No. 6,299,499 discloses an electronic device having an impurity region introduced into a silicon carbide layer by channeling implantation.

[0004] US Patent Application Publication No. 2015 / 0028351

[0005] [Summary] One embodiment of the present disclosure provides a semiconductor device including: a SiC chip having a first main surface and a second main surface; a first region of a first conductivity type formed in a surface layer portion of the first main surface of the SiC chip; a plurality of second regions of a second conductivity type formed in a surface layer portion of the first region, the second regions providing a plurality of unit cells in the SiC chip; a third region of the first conductivity type formed in a surface layer portion of the second region in each of the unit cells; a planar gate structure facing a channel region in the second region of each of the unit cells and controlling channel conduction between the first region and the third region; a plurality of first pillar regions of a second conductivity type connected to the second region of a common unit cell, extending in a depth direction of the SiC chip from the first main surface toward the second main surface, and physically separated and independent from each other; and a second pillar region of the first conductivity type adjacent to the first pillar regions within the SiC chip and extending in the depth direction.

[0006] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1 . FIG. 3 is a plan view showing an example of a chip layout. FIG. 4 is a perspective view showing an example of a chip layout. FIG. 5 is a plan view showing a main portion of an active region. FIG. 6 is a plan view showing a main portion of an active region. FIG. 7 is a cross-sectional perspective view showing a superjunction structure according to a first embodiment. FIG. 8 is an enlarged cross-sectional view of a region surrounded by a two-dot chain line VI in FIG. 7 . FIG. 9 is a cross-sectional view showing a main portion of a peripheral region. FIG. 10 is a schematic diagram showing a wafer used in manufacturing a semiconductor device. FIG. 11 is a flowchart showing an example of a method for manufacturing a superjunction structure according to the first embodiment. FIG. 12A is a cross-sectional view showing an example of a method for manufacturing a superjunction structure according to the first embodiment. FIG. 12B is a cross-sectional view showing a process subsequent to FIG. 12A . FIG. 12C is a cross-sectional view showing a process subsequent to FIG. 12B . FIG. 13 is a graph showing the relationship between withstand voltage and on-resistance for each pitch of a SiC device having a superjunction structure. FIG. 14 is a diagram showing a first modified example of the superjunction structure according to the first embodiment. FIG. 15 is a diagram showing a second modified example of the superjunction structure according to the first embodiment. FIG. 16 is a diagram showing a third modified example of the superjunction structure according to the first embodiment. FIG. 17 is a diagram showing a fourth modified example of the superjunction structure according to the first embodiment. FIG. 18 is a cross-sectional perspective view showing the superjunction structure according to the second embodiment. FIG. 19 is a diagram showing a first modified example of the superjunction structure according to the second embodiment. FIG. 20 is a diagram showing a second modified example of the superjunction structure according to the second embodiment. FIG. 21 is a diagram showing a third modified example of the superjunction structure according to the second embodiment. FIG. 22 is a cross-sectional perspective view showing the superjunction structure according to the third embodiment. FIG. 23 is a diagram showing a first modified example of the superjunction structure according to the third embodiment. FIG. 24 is a diagram showing a second modified example of the superjunction structure according to the third embodiment. FIG. 25 is a diagram showing a third modified example of the superjunction structure according to the third embodiment. FIG. 26 is a cross-sectional perspective view showing the superjunction structure according to the fourth embodiment. FIG. 27 is an enlarged cross-sectional view of the area surrounded by the two-dot chain line XXVII in FIG.FIG. 28 is a flowchart showing an example of a method for manufacturing a superjunction structure according to the fourth embodiment. FIG. 29A is a cross-sectional perspective view showing an example of a method for manufacturing a superjunction structure according to the fourth embodiment. FIG. 29B is a cross-sectional view showing a step after FIG. 29A . FIG. 29C is a cross-sectional view showing a step after FIG. 29B . FIG. 29D is a cross-sectional view showing a step after FIG. 29C . FIG. 29E is a cross-sectional view showing a step after FIG. 29D . FIG. 30 is a view showing a first modified example of the superjunction structure according to the fourth embodiment. FIG. 31 is a view showing a second modified example of the superjunction structure according to the fourth embodiment. FIG. 32 is a view showing a third modified example of the superjunction structure according to the fourth embodiment. FIG. 33 is a view showing a fourth modified example of the superjunction structure according to the fourth embodiment. FIG. 34 is a plan view showing a superjunction structure according to the fifth embodiment. FIG. 35 is a cross-sectional perspective view showing a superjunction structure according to the fifth embodiment. FIG. 36 is a plan view showing a superjunction structure according to the sixth embodiment. FIG. 37 is a plan view showing a superjunction structure according to the seventh embodiment. Fig. 38 is a plan view showing a superjunction structure according to an eighth embodiment. Fig. 39 is a plan view showing a superjunction structure according to a ninth embodiment.

[0007] [Detailed Description] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The accompanying drawings are all schematic views and are not strictly illustrative, and the scale, ratio, angle, etc. are not necessarily the same. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions will be omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0008] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0009] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Of course, "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." "p-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. Unless otherwise specified, the trivalent element is at least one of boron, aluminum, gallium, and indium. Unless otherwise specified, the pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0010] Fig. 1 is a plan view showing a semiconductor device 1A according to a first embodiment. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. Fig. 3 is a plan view showing an example layout of a chip 2. Fig. 4 is a perspective view showing an example layout of the chip 2.

[0011] 1 to 4, semiconductor device 1A is a SiC semiconductor device in this embodiment. Semiconductor device 1A includes chip 2 including SiC single crystal. Chip 2 may also be referred to as a "SiC chip" or a "semiconductor chip." In this embodiment, chip 2 is made of hexagonal SiC single crystal and is formed in a rectangular parallelepiped shape. Hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, and the like. In this embodiment, an example is shown in which chip 2 is made of 4H-SiC single crystal, but chip 2 may be made of another polytype.

[0012] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as a "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction to the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view.

[0013] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0014] In the circumferential direction of the chip 2 (counterclockwise in FIG. 1 ) starting from the first side surface 5A, the second side surface 5B is connected to the first side surface 5A, the third side surface 5C is connected to the second side surface 5B, and the fourth side surface 5D is connected to the first side surface 5A and the third side surface 5C. The first side surface 5A and the third side surface 5C extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The second side surface 5B and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0015] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0016] The XY plane including the first direction X and the second direction Y forms a horizontal plane perpendicular to the vertical direction Z. Hereinafter, an axis extending along the vertical direction Z may be referred to as a "vertical axis." Hereinafter, the first direction X and the second direction Y may be referred to as a "horizontal direction." The horizontal direction is also a direction extending along the first main surface 3.

[0017] The chip 2 includes an n-type base layer 6 made of SiC single crystal. The base layer 6 may also be referred to as a "semiconductor substrate," "SiC substrate," "base SiC layer," "base region," or the like. The base layer 6 extends horizontally in a layered manner and forms part of the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the base layer 6 is made of a substrate (SiC substrate) made of SiC single crystal.

[0018] The base layer 6 is 1×10 １８ cm －３ 1x10 or more ２１ cm －３The n-type impurity concentration of the base layer 6 may have the following peak value. The base layer 6 preferably has an almost constant n-type impurity concentration in the thickness direction. The n-type impurity concentration of the base layer 6 is preferably adjusted with a single pentavalent element. It is particularly preferable that the n-type impurity concentration of the base layer 6 is adjusted with a pentavalent element other than phosphorus. In this embodiment, the n-type impurity concentration of the base layer 6 is adjusted with nitrogen.

[0019] The base layer 6 has a base thickness TB. The base thickness TB may be 5 μm or more and 300 μm or less. The base thickness TB may have a value belonging to any one of the following ranges: 5 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or more and 300 μm or less. The base thickness TB is preferably 50 μm or more and 250 μm or less.

[0020] The chip 2 includes a stacked layer 7 stacked on a base layer 6. The stacked layer 7 may be referred to as a "semiconductor layer," "SiC layer," "epitaxial layer," "SiC epitaxial layer," "SiC stacked layer," "semiconductor stacked layer," or the like. In this embodiment, the stacked layer 7 is provided as a layer for forming a superjunction structure SJ. In this embodiment, the stacked layer 7 is formed of a single semiconductor layer, but may be formed of multiple semiconductor layers. When the stacked layer 7 is formed of multiple semiconductor layers, the number of layers is arbitrary and is adjusted appropriately depending on the electrical characteristics to be achieved. Examples of electrical characteristics include a breakdown voltage and a resistance value.

[0021] The stacked portion 7 extends in layers in the horizontal direction and forms part of the first to fourth side surfaces 5A to 5D of the chip 2. The stacked portion 7 is made of an epitaxial layer (SiC epitaxial layer) grown from the base layer 6 as a starting point.

[0022] The laminated portion 7 has a lower end and an upper end. The lower end of the laminated portion 7 is the starting point of crystal growth, and the upper end of the laminated portion 7 is the ending point of crystal growth. Since the laminated portion 7 is formed by continuous crystal growth from the base layer 6, the lower end of the laminated portion 7 coincides with the upper end of the base layer 6. The boundary between the base layer 6 and the laminated portion 7 is not necessarily visible, but can be indirectly evaluated and / or determined from other configurations or elements.

[0023] The stacked layer 7 may be entirely referred to as the drift region 8, which is an example of a first region. The drift region 8 is a region that serves as the base of impurity regions (such as the second pillar region 13, the first pillar region 12, the body region 32, the source region 33, and the contact region 34, which will be described later) that are selectively formed by implanting impurity ions into the stacked layer 7. By implanting n-type impurity ions or p-type impurity ions into the stacked layer 7 to a concentration that exceeds the impurity concentration of the drift region 8, various n-type or p-type impurity regions having characteristics according to the respective concentrations are formed.

[0024] Although the drift region 8 is replaced by various impurity regions in the target region of the stacked layer 7 by ion implantation, the n-type impurity ions added during epitaxial growth of the stacked layer 7 remain at the concentration at the time of growth. As a result, the drift region 8 provides an n-type background concentration within a range that does not impair the characteristics (electrical behavior) of the various impurity regions. On the other hand, even if only a small amount of n-type or p-type impurity ions are implanted into the stacked layer 7, the characteristics of the drift region 8 are maintained in the region, and the drift region 8 remains.

[0025] The n-type impurity concentration of the stacked layer 7 (drift region 8) is preferably lower than the n-type impurity concentration of the base layer 6. １５ cm －３ 1x10 or more １６ cm －３ The n-type impurity concentration of the stacked portion 7 may have a peak value of the following: The n-type impurity concentration of the stacked portion 7 may be approximately constant in the thickness direction. Of course, the n-type impurity concentration of the stacked portion 7 may have a concentration gradient that gradually increases and / or decreases in the thickness direction (crystal growth direction) of the chip 2.

[0026] The stacked layer 7 (drift region 8) has an n-type impurity concentration adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the stacked layer 7 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. The stacked layer 7 preferably contains a pentavalent element other than phosphorus.

[0027] The n-type impurity concentration of the stacked layer 7 (drift region 8) is preferably adjusted by at least nitrogen. When the stacked layer 7 contains two or more pentavalent elements, the stacked layer 7 preferably contains nitrogen and a pentavalent element other than nitrogen. In this case, the stacked layer 7 preferably contains either arsenic or antimony, or both, as the pentavalent element other than phosphorus and nitrogen. In this embodiment, the stacked layer 7 (drift region 8) does not contain phosphorus, but contains nitrogen as a pentavalent element.

[0028] The stacked portion 7 has an epitaxial thickness TE. The epitaxial thickness TE is preferably less than the base thickness TB. The epitaxial thickness TE is preferably 1 μm or more. The epitaxial thickness TE is preferably 5 μm or less. The epitaxial thickness TE may have a value belonging to any one of the following ranges: 1 μm or more to 1.5 μm or less, 1.5 μm or more to 2 μm or less, 2 μm or more to 2.5 μm or less, 2.5 μm or more to 3 μm or less, 3 μm or more to 3.5 μm or less, 3.5 μm or more to 4 μm or less, 4 μm or more to 4.5 μm or less, and 4.5 μm or more to 5 μm or less.

[0029] The semiconductor device 1A includes an active region 10 set in a chip 2. The active region 10 is set in an inner portion of the chip 2 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the chip 2 in a plan view. The active region 10 is set in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The planar area of ​​the active region 10 is preferably 50% to 90% of the planar area of ​​the first main surface 3.

[0030] The semiconductor device 1A includes a peripheral region 11 set outside the active region 10 in the chip 2. The peripheral region 11 is provided in a region between the periphery of the chip 2 and the active region 10 in a plan view. The peripheral region 11 extends in a band shape along the active region 10 in a plan view, and is set in a polygonal ring shape (a square ring shape in this embodiment) surrounding the active region 10.

[0031] The semiconductor device 1A includes a plurality of p-type first pillar regions 12 formed in the stacked layer 7 in the active region 10. The first pillar regions 12 may also be referred to as "pillar layers," "column layers (regions)," "p-type layers (regions)," "p-type zones," etc. The plurality of first pillar regions 12 are formed at intervals in the horizontal direction within the stacked layer 7, and define a plurality of n-type second pillar regions 13, each consisting of a part of the stacked layer 7.

[0032] The multiple first pillar regions 12 are formed by part of the stacked layer 7. The multiple first pillar regions 12, together with the multiple second pillar regions 13, form multiple pn junctions that have charge balance. As a result, the multiple first pillar regions 12, together with the multiple second pillar regions 13, form a super junction structure SJ within the stacked layer 7. The state of having charge balance means that, with respect to multiple adjacent first pillar regions 12, a depletion layer extending from one pn junction and a depletion layer extending from the other pn junction are connected within the multiple second pillar regions 13.

[0033] The multiple first pillar regions 12 are arranged at intervals in the first direction X within the stacked portion 7, and are each formed in a strip shape extending in the second direction Y. The multiple first pillar regions 12 are formed in a strip shape extending in the second direction Y, and the multiple second pillar regions 13 are formed in a strip shape extending in the second direction Y. The multiple first pillar regions 12 are arranged at intervals in the m-axis direction of the SiC single crystal, and extend in the a-axis direction of the SiC single crystal.

[0034] The plurality of first pillar regions 12 are 1×10 １５ cm －３ 1x10 or more １８ cm －３The p-type impurity concentration of the first pillar region 12 may have the following peak value. The p-type impurity concentration of the first pillar region 12 is preferably adjusted with at least one trivalent element. In this embodiment, the p-type impurity concentration of the first pillar region 12 is adjusted with aluminum.

[0035] The plurality of second pillar regions 13 are 1×10 １５ cm －３ 1x10 or more １８ cm －３ The second pillar region 13 may have the following n-type impurity concentration as a peak value. The n-type impurity concentration is adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the second pillar region 13 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. In this embodiment, the n-type impurity concentration of the second pillar region 13 is adjusted by phosphorus.

[0036] In this embodiment, the drift region 8 of the active region 10 is wholly or partially replaced by the first pillar region 12 and the second pillar region 13. The drift region 8 may be formed (remain) outside the formation region of the first pillar region 12 and the second pillar region 13 in the active region 10.

[0037] The second pillar region 13 may be simply referred to as a drift region because it is an impurity region that maintains the conductivity type of the drift region 8. Considering the concentration difference between the second pillar region 13 and the drift region 8 (the concentration of the second pillar region 13 > the concentration of the drift region 8), the second pillar region 13 may be referred to as a "high-concentration drift region" and the drift region 8 may be referred to as a "low-concentration drift region." Considering that the second pillar region 13 is formed in the drift region 8 after the formation of the drift region 8, the drift region 8 may be referred to as a "base drift region" and the second pillar region 13 may be referred to as a "second drift region."

[0038] FIG. 5 is a plan view showing a main portion of the active region 10. FIG. 5 mainly shows the planar layout of the body region 32, the first pillar region 12, and the second pillar region 13. FIG. 6 is a plan view showing a main portion of the active region 10. FIG. 6 mainly shows the planar layout of the body region 32, the source region 33, and the contact region 34. FIG. 7 is a cross-sectional perspective view showing a superjunction structure according to the first embodiment. FIG. 8 is an enlarged cross-sectional view of a region surrounded by a two-dot chain line VIII in FIG. 7. FIG. 9 is a cross-sectional view showing a main portion of the peripheral region 11.

[0039] 5 to 9, the semiconductor device 1A in this embodiment includes a MIS structure 31 (Metal Insulator Semiconductor structure) formed in the active region 10. The MIS structure 31 may also be referred to as a "field effect transistor structure."

[0040] The semiconductor device 1A includes a plurality of p-type body regions 32 as an example of second regions formed in the active region 10. In this embodiment, the plurality of body regions 32 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. The plurality of body regions 32 are arranged at intervals in the m-axis direction of the SiC single crystal and extend in stripes in the a-axis direction of the SiC single crystal. The extension direction of the plurality of body regions 32 coincides with the extension direction of the plurality of first pillar regions 12.

[0041] A p-type connection region 28 is formed at an end in the extension direction of the plurality of body regions 32. The connection region 28 is formed in a strip shape extending in a direction (in this embodiment, the first direction X) perpendicular to the extension direction of the plurality of body regions 32, and integrally connects the plurality of body regions 32. The plurality of body regions 32 are electrically connected to each other via the connection region 28, but are physically independent from each other.

[0042] 5 to 7 , lines 27 are set between adjacent body regions 32 to partition each unit cell 14 of the MIS structure 31 (switching element structure). This forms a plurality of unit cells 14 arranged in a stripe pattern in the active region 10. Each body region 32 is provided in one-to-one correspondence with each unit cell 14. The pitch PCL of the plurality of unit cells 14 (e.g., the distance between the centers of adjacent lines 27 in the first direction X) is, for example, not less than 3 μm and not more than 6 μm, and preferably not less than 3 μm and not more than 5 μm.

[0043] The plurality of body regions 32 may be, for example, 1×10 １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration may have the following peak value:

[0044] The p-type impurity concentrations of the plurality of body regions 32 are preferably adjusted by at least one trivalent element. The trivalent element of the body regions 32 may be the same as the trivalent element of the first pillar regions 12, etc., or may be a different species from the trivalent element of the first pillar regions 12, etc. The trivalent element of the body regions 32 may be at least one of boron, aluminum, gallium, and indium.

[0045] 5 , 7 , and 8 , the first pillar region 12 is formed to overlap the body region 32 corresponding to the thickness direction of the chip 2 (the stacking direction of the stack unit 7). As shown in Fig. 5 , in a plan view, the first pillar region 12 may be formed in an annular shape in a region below the body region 32. The annular first pillar region 12 may be separated into a plurality of pillar regions in the first direction X.

[0046] In this embodiment, the first pillar region 12 may include a plurality of pillar main body portions 71 arranged at intervals in the first direction X and each formed in a strip shape extending in the second direction Y, and a pillar connecting portion 72 connecting the plurality of pillar main body portions 71 to each other at ends of the plurality of pillar main body portions 71 in the extension direction. The pillar connecting portion 72 may be arranged more inward in the extension direction of the body region 32 than an end 86 of the line 27. As a result, the entire annular first pillar region 12 may be arranged between adjacent lines 27.

[0047] Focusing on the multiple pillar body portions 71 extending parallel to the extension direction (stripe direction) of the body regions 32 (without taking into consideration the pillar connection portions 72), the semiconductor device 1A may have a feature in which the multiple first pillar regions 12 are arranged at intervals in a direction (in this embodiment, the first direction X) intersecting the extension direction (in this embodiment, the second direction Y) of the multiple body regions 32, and are arranged in a stripe pattern extending parallel to each other along the extension direction of the body regions 32.

[0048] In the following description of the cross-sectional structure of the first pillar region 12 in the arrangement direction (first direction X) of the plurality of unit cells 14, the plurality of pillar body portions 71 may be simply defined as the plurality of first pillar regions 12.

[0049] 8 , in a cross-sectional view taken along a direction (first direction X in this embodiment) intersecting the extension direction of the plurality of body regions 32, a plurality of first pillar regions 12 (pillar main body portions 71) overlap one body region 32 in a one-to-many correspondence. The plurality of first pillar regions 12 are connected to the body region 32 of a common unit cell 14, extend in the depth direction of the chip 2 from the first main surface 3 toward the second main surface 4, and are physically separated and independent from one another.

[0050] The configuration in which "plurality of first pillar regions 12 are connected to a common unit cell 14" may be defined as, for example, a configuration in which a plurality of first pillar regions 12 are connected to unit cells 14 (body regions 32), each of which is formed independently in the shape of a strip. In this configuration, the plurality of first pillar regions 12 are arranged at intervals in a direction intersecting the extension direction of the plurality of body regions 32, and extend parallel to each other along the extension direction of the body regions 32, forming a stripe pattern. In this configuration, a pair of first pillar regions 12 are connected to one body region 32.

[0051] 8 , the plurality of first pillar regions 12 each have a first lower end 12a on the lower end side of the laminate 7 and a first upper end 12b on the upper end side of the laminate 7. The first lower end 12a is located in a region on the lower end side of the laminate 7 relative to the intermediate part of the thickness range of the laminate 7, and the first upper end 12b is located in a region on the upper end side of the laminate 7 relative to the intermediate part of the thickness range of the laminate 7. The first lower end 12a may be formed at a distance from the lower end to the upper end side of the laminate 7, and may face the base layer 6 with a part (lower end) of the laminate 7 in between.

[0052] The distance between the lower end of laminated portion 7 and first lower end 12a may be 0 μm or more and 2 μm or less. The distance between the lower end of laminated portion 7 and first lower end 12a may have a value belonging to any one of the ranges of 0 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 2 μm or less.

[0053] The first upper end 12b is connected to the body region 32. The first upper end 12b may be substantially coincident with the lower end of the body region 32. The first upper end 12b may be integral with the body region 32, and no visible boundary may exist between them.

[0054] The multiple first pillar regions 12 are arranged in a region that is more inward than the outer edge of each body region 32 in the first direction X. In this embodiment, the pair of first pillar regions 12 have first side portions 12c that extend continuously from the side portions (body side portions 32a) of the body region 32 in the depth direction of the chip 2.

[0055] More specifically, the body side portion 32 a and the first side portion 12 c are continuous with almost no step in the depth direction of the chip 2. The phrase "without a step" between the two may include, for example, a configuration in which a flat surface is formed spanning the body side portion 32 a and the first side portion 12 c in the depth direction of the chip 2, or a configuration in which a minute step is formed between the body side portion 32 a and the first side portion 12 c that is not intentionally formed. The minute step may be, for example, a step that occurs when the ends of the ion implantation masks used to form the body region 32 and the first pillar region 12 in the first direction X coincide with each other, or a step that occurs as a result of one of the masks being significantly expanded in the lateral direction due to the impurity diffusion conditions.

[0056] Each of the multiple first pillar regions 12 has a first width W1. The first width W1 is the width in a direction perpendicular to the extension direction of the first pillar regions 12. The first width W1 is preferably less than the epitaxial thickness TE of the stacked portion 7. Of course, the first width W1 may be equal to or greater than the epitaxial thickness TE.

[0057] The first width W1 may be 0.1 μm or more and 10 μm or less. The first width W1 may be 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, 4.5 μm or less The first width W1 may have a value belonging to any one of the following ranges: 5 μm or less, 5 μm or more and 5.5 μm or less, 5.5 μm or more and 6 μm or less, 6 μm or more and 6.5 μm or less, 6.5 μm or more and 7 μm or less, 7 μm or more and 7.5 μm or less, 7.5 μm or more and 8 μm or less, 8 μm or more and 8.5 μm or less, 8.5 μm or more and 9 μm or less, 9 μm or more and 9.5 μm or more and 10 μm or less. The first width W1 is preferably 0.5 μm or more and 1.5 μm or less.

[0058] Each of the first pillar regions 12 has a first thickness T1. The first thickness T1 may also be referred to as the depth of the first pillar regions 12. The first thickness T1 may be less than the epitaxial thickness TE of the stack 7. The first thickness T1 may also be greater than the epitaxial thickness TE. The first thickness T1 may also be approximately equal to the epitaxial thickness TE.

[0059] The first thickness T1 is preferably 1 μm or more. The first thickness T1 is preferably 30 μm or less. The first thickness T1 may have a value belonging to any one of the ranges of 1 μm or more to 1.5 μm or less, 1.5 μm or more to 2 μm or less, 2 μm or more to 2.5 μm or less, 2.5 μm or more to 3 μm or less, 3 μm or more to 3.5 μm or less, 3.5 μm or more to 4 μm or less, 4 μm or more to 4.5 μm or less, 4.5 μm or more to 5 μm or less, 5 μm or more to 10 μm or less, 10 μm or more to 15 μm or less, 15 μm or more to 20 μm or less, 20 μm or more to 25 μm or less, and 25 μm or more to 30 μm or less.

[0060] Preferably, the first width W1 is less than the epitaxial thickness TE of the stacked portion 7, and the first thickness T1 is greater than the first width W1. Preferably, the plurality of first pillar regions 12 each have a first aspect ratio T1 / W1 such that they extend in a vertically elongated columnar shape along the thickness direction of the stacked portion 7. The first aspect ratio T1 / W1 is the ratio of the first thickness T1 to the first width W1. In this case, it is particularly preferable that the first thickness T1 be greater than the epitaxial thickness TE. For example, the first aspect ratio T1 / W1 may be greater than 1 and not greater than 100.

[0061] The multiple first pillar regions 12 are formed at intervals of a first pitch P1 in the first direction X. The first pitch P1 is preferably less than the epitaxial thickness TE of the stacked portion 7. Of course, the first pitch P1 may be equal to or greater than the epitaxial thickness TE.

[0062] The first pitch P1 is narrower than the pitch PCL of the unit cells 14 and may be, for example, 0.1 μm to 3 μm, preferably 0.5 μm to 2 μm. The first pitch P1 may have a value belonging to any one of the following ranges: 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, or 2.5 μm to 3 μm.

[0063] In the stack portion 7, a plurality of second pillar regions 13 are defined by a plurality of first pillar regions 12. The plurality of second pillar regions 13 are adjacent to the first pillar regions 12 within the chip 2 and extend in the depth direction of the chip 2.

[0064] The multiple second pillar regions 13 include a first portion 29 and a second portion 30. The first portion 29 is a pillar region of the multiple second pillar regions 13 that extends in the depth direction of the chip 2 from a region sandwiched between the multiple unit cells 14 in the drift region 8. The first portion 29 of the second pillar region 13 is located outside the lower region of each unit cell 14 (body region 32) and does not face the body region 32 in the depth direction of the chip 2. The first portion 29 extends in the depth direction of the chip 2 from the first main surface 3 toward the base layer 6. The upper end of the first portion 29 is exposed from the first main surface 3, and the lower end is connected to the base layer 6.

[0065] The first portion 29 of the second pillar region 13 may be referred to as an "outer pillar region," a "second outer pillar region," a "second pillar outer portion," etc. The first portion 29 is exposed from the first main surface 3 and may be referred to as an "exposed pillar region."

[0066] Referring to FIG. 8, the first portion 29 may include a first pillar adjacent portion 29a, a cell adjacent portion 29b, and a first protrusion portion 29c.

[0067] The first pillar adjacent portion 29 a is a first portion 29 arranged in contact with the first pillar region 12 in the lateral direction along the first main surface 3. The first pillar adjacent portion 29 a may be a first portion 29 sandwiched between first pillar regions 12 extending from each of the adjacent body regions 32 in the depth direction of the chip 2.

[0068] The cell adjacent portion 29b is the first portion 29 sandwiched between adjacent unit cells 14 (body regions 32) in the horizontal direction along the first main surface 3. The cell adjacent portion 29b laterally contacts the body region 32. The cell adjacent portion 29b provides the upper end of the first portion 29 and is exposed from the first main surface 3.

[0069] The first protruding portion 29c is not adjacent to either the first pillar region 12 or the unit cell 14 in the lateral direction along the first main surface 3. The first protruding portion 29c is a first portion 29 that protrudes toward the base layer 6 beyond the bottom of the first pillar region 12. The first protruding portion 29c provides the lower end of the first portion 29 and is connected to the base layer 6.

[0070] The second portion 30 of the second pillar region 13 is a pillar region sandwiched between multiple first pillar regions 12 in the region below each unit cell 14 (body region 32). The second portion 30 of the second pillar region 13 is located inside the region below each unit cell 14 (body region 32) and faces the body region 32 in the depth direction of the chip 2. The second portion 30 extends from the body region 32 toward the base layer 6 in the depth direction of the chip 2. The upper end of the second portion 30 is connected to the body region 32, and the lower end is connected to the base layer 6.

[0071] The second portion 30 of the second pillar region 13 may be referred to as an "inner pillar region," "second inner pillar region," "second pillar inner portion," etc. The second portion 30 is covered (capped) by the body region 32 and is not exposed from the first main surface 3, and may be referred to as a "covered pillar region" or a "cap pillar region."

[0072] The second portion 30 may include a second pillar-adjacent portion 30a and a second protruding portion 30c. The second pillar-adjacent portion 30a is the second portion 30 sandwiched between adjacent first pillar regions 12. The second pillar-adjacent portion 30a provides the upper end of the second portion 30 and contacts the body region 32 from below.

[0073] The second protruding portion 30c is not adjacent to the first pillar region 12 in the lateral direction along the first main surface 3. The second protruding portion 30c is a second portion 30 that protrudes toward the base layer 6 beyond the bottom of the first pillar region 12. The second protruding portion 30c provides the lower end of the second portion 30 and is connected to the base layer 6.

[0074] In this embodiment, the first protrusion 29c and the second protrusion 30c are continuous in the lateral direction along the first main surface 3 via the drift region 8 below the first pillar region 12, and as a whole spread out in a layered manner near the boundary with the base layer 6. The first protrusion 29c and the second protrusion 30c may be defined as parts of the first portion 29 and the second portion 30, respectively, or may be defined as parts different from the second pillar region 13.

[0075] In the latter case, for example, the first protrusion 29 c, the second protrusion 30 c, and the drift region 8 below the first pillar region 12 may be collectively referred to as an n-type base region 39 that extends across the bottoms of the multiple first pillar regions 12, the bottoms of the first pillar-adjacent portions 29 a, and the second pillar-adjacent portions 30 a along the first main surface 3. The base region 39 is integrally continuous with the first pillar-adjacent portions 29 a and the second pillar-adjacent portions 30 a.

[0076] The base region 39 provides a boundary with the base layer 6 throughout the entire in-plane direction of the chip 2 (all directions along the first main surface 3). The thickness of the base region 39 may be 0 μm or more and 2 μm or less. The thickness of the base region 39 may have a value belonging to any one of the ranges of 0 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 2 μm or less.

[0077] Each of the multiple second pillar regions 13 has a second width W2. The second width W2 is the width in a direction perpendicular to the extension direction of the second pillar regions 13. The second width W2 is preferably the same as the first width W1. Of course, the second width W2 may be wider or narrower than the first width W1. The second width W2 is preferably less than the epitaxial thickness TE of the stacked portion 7. Of course, the second width W2 may be equal to or greater than the epitaxial thickness TE.

[0078] The second width W2 may be 0.1 μm or more and 10 μm or less. The second width W2 may be 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, 4.5 μm or less The second width W2 may have a value belonging to any one of the following ranges: 5 μm or less, 5 μm or more and 5.5 μm or less, 5.5 μm or more and 6 μm or less, 6 μm or more and 6.5 μm or less, 6.5 μm or more and 7 μm or less, 7 μm or more and 7.5 μm or less, 7.5 μm or more and 8 μm or less, 8 μm or more and 8.5 μm or less, 8.5 μm or more and 9 μm or less, 9 μm or more and 9.5 μm or more and 10 μm or less. The second width W2 is preferably 0.5 μm or more and 1.5 μm or less.

[0079] Each of the second pillar regions 13 has a second thickness T2. The second thickness T2 may be referred to as the depth of the second pillar regions 13. The second thickness T2 may be less than the epitaxial thickness TE of the stack 7. The second thickness T2 may be greater than the epitaxial thickness TE. The second thickness T2 may be approximately equal to the epitaxial thickness TE.

[0080] The second thickness T2 is preferably 1 μm or more. The second thickness T2 is preferably 30 μm or less. The second thickness T2 may have a value belonging to any one of the ranges of 1 μm or more to 1.5 μm or less, 1.5 μm or more to 2 μm or less, 2 μm or more to 2.5 μm or less, 2.5 μm or more to 3 μm or less, 3 μm or more to 3.5 μm or less, 3.5 μm or more to 4 μm or less, 4 μm or more to 4.5 μm or less, 4.5 μm or more to 5 μm or less, 5 μm or more to 10 μm or less, 10 μm or more to 15 μm or less, 15 μm or more to 20 μm or less, 20 μm or more to 25 μm or less, and 25 μm or more to 30 μm or less.

[0081] Preferably, the second width W2 is less than the epitaxial thickness TE of the stacked portion 7, and the second thickness T2 is greater than the second width W2. Preferably, the second pillar regions 13 each have a second aspect ratio T2 / W2 such that they extend in a vertically elongated columnar shape along the thickness direction of the stacked portion 7. The second aspect ratio T2 / W2 is the ratio of the second thickness T2 to the second width W2. In this case, it is particularly preferable that the second thickness T2 be greater than the epitaxial thickness TE. For example, the second aspect ratio T2 / W2 may be greater than 1 and not greater than 100.

[0082] The multiple second pillar regions 13 are formed at intervals of a second pitch P2 in the first direction X. The second pitch P2 is preferably less than the epitaxial thickness TE of the stacked portion 7. Of course, the second pitch P2 may be equal to or greater than the epitaxial thickness TE.

[0083] The second pitch P2 may be narrower than the pitch PCL of the unit cells 14. The second pitch P2 may be equal to the first pitch P1. The second pitch P2 may be, for example, 0.1 μm or more and 3 μm or less, and preferably 0.5 μm or more and 2 μm or less. The first pitch P1 may have a value belonging to any one of the following ranges: 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less.

[0084] 6 to 8 , semiconductor device 1A includes one or more n-type source regions 33 formed in the surface layer portions of a plurality of body regions 32 in active region 10. In plan view as shown in FIG. 6 , each source region 33 includes an annular source region 33 arranged inwardly and spaced apart from the outer edge of each body region 32.

[0085] 8, in this embodiment, a plurality of (two in this embodiment) source regions 33 are formed at intervals in the surface layer portion of each body region 32. The plurality of source regions 33 have an n-type impurity concentration higher than the n-type impurity concentration of the second pillar region 13 and the drift region 8 of the stacked portion 7. The plurality of source regions 33 have an n-type impurity concentration of 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The n-type impurity concentration may have the following peak value:

[0086] The plurality of source regions 33 may each extend in a strip shape along the extension direction of the corresponding body region 32. Of course, the plurality of source regions 33 may be formed at intervals along the extension direction of the corresponding body region 32. The plurality of source regions 33 are formed at intervals from the bottom of the corresponding body region 32 toward the first main surface 3, and are formed at intervals inward from the periphery of the corresponding body region 32.

[0087] The plurality of source regions 33, together with the plurality of second pillar regions 13 (cell adjacent portions 29 b) at the periphery of the body region 32, define a channel region 73 (current path) along the first main surface 3. The plurality of source regions 33 face the plurality of first pillar regions 12 with the corresponding body regions 32 interposed therebetween.

[0088] 6 to 8 , semiconductor device 1A includes one or more p-type contact regions 34 formed in the surface layer portions of the plurality of body regions 32 in active region 10. Contact region 34 may also be referred to as a "back gate region." As shown in FIG. 6 , in plan view, each contact region 34 includes a strip-shaped contact region 34 arranged inward and spaced apart from the outer edge of each source region 33.

[0089] As shown in FIG. 8 , in a cross-sectional view, one contact region 34 is formed in a region between a plurality of adjacent source regions 33 in the surface layer portion of each body region 32 .

[0090] The plurality of contact regions 34 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the plurality of body regions 32. The p-type impurity concentration (peak value) of the plurality of contact regions 34 is higher than the p-type impurity concentration (peak value) of the plurality of first pillar regions 12. The plurality of contact regions 34 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the plurality of first pillar regions 12. １８ cm －３ 1x10 or more ２１ cm －３ The p-type impurity concentration may have the following peak value:

[0091] The plurality of contact regions 34 may each extend in a strip shape along the extension direction of the corresponding body region 32. Of course, the plurality of contact regions 34 may also be formed at intervals along the extension direction of the corresponding body region 32. The plurality of contact regions 34 are formed at intervals from the bottom of the corresponding body region 32 toward the first main surface 3, and are formed at intervals inward from the peripheral edge of the corresponding body region 32.

[0092] The semiconductor device 1A includes a plurality of planar electrode type gate structures 35 arranged on the first main surface 3 in the active region 10. The gate structures 35 may also be referred to as "planar gate structures." The plurality of gate structures 35 are arranged at intervals on the first main surface 3 so as to overlap at least one body region 32 (channel region 73) in the thickness direction of the chip 2. A gate potential is applied to the plurality of gate structures 35 as a control potential. The plurality of gate structures 35 control the inversion and non-inversion of a channel (current path) in the body region 32 in response to the gate potential.

[0093] In this embodiment, the multiple gate structures 35 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. The multiple gate structures 35 are arranged at intervals in the m-axis direction of the SiC single crystal and extend in the a-axis direction of the SiC single crystal. The extending direction of the multiple gate structures 35 coincides with the extending direction of the multiple first pillar regions 12.

[0094] The plurality of gate structures 35 are arranged shifted from the plurality of first pillar regions 12 toward the first portions 29 of the plurality of second pillar regions 13, and overlap the first portions 29 of the plurality of second pillar regions 13 in a one-to-one correspondence in the thickness direction of the chip 2. In this embodiment, the plurality of gate structures 35 are each arranged to straddle two adjacent body regions 32, and each cover the plurality of source regions 33 located in one and the other body regions 32.

[0095] Each of the plurality of gate structures 35 has a stacked structure including a gate insulating film 36 disposed on the first main surface 3 and a gate electrode 37 disposed on the gate insulating film 36. The gate insulating film 36 may include a silicon oxide film. The gate electrode 37 may include conductive polysilicon.

[0096] Either or both of the gate insulating film 36 and the gate electrode 37 may be arranged so as to partially overlap the first pillar region 12 in the thickness direction of the chip 2. Of course, either or both of the gate insulating film 36 and the gate electrode 37 may be arranged so as not to partially overlap the first pillar region 12 in the thickness direction of the chip 2.

[0097] The following describes the configuration on the side of peripheral region 11. Semiconductor device 1A includes at least one (preferably two to 20) p-type field region 38 formed in the surface layer portion of first main surface 3 in peripheral region 11.

[0098] The number of field regions 38 is typically 4 to 8. The field regions 38 are formed in an electrically floating state and relieve the electric field within chip 2 at the periphery of first main surface 3. The number, width, depth, p-type impurity concentration, etc. of field regions 38 are arbitrary and can take various values ​​depending on the electric field to be relieved.

[0099] The multiple field regions 38 are formed at intervals in a region between the periphery of the chip 2 and the active region 10. The multiple field regions 38 are formed in strip shapes extending along the active region 10 in a plan view. Each of the multiple field regions 38 has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y. In this embodiment, the multiple field regions 38 are formed in an annular shape (specifically, a quadrangular annular shape) surrounding the active region 10 (the multiple first pillar regions 12) in a plan view.

[0100] The multiple field regions 38 are formed in the stack 7 at intervals from the lower end of the stack 7 (drift region 8) toward the first main surface 3, and each form a p-n junction with the drift region 8. The multiple field regions 38 preferably have bottoms located on the first main surface 3 side of the intermediate portion of the thickness range of the stack 7. In this embodiment, the multiple field regions 38 are formed at intervals from the multiple first pillar regions 12 toward the peripheral edge of the chip 2. Therefore, the multiple field regions 38 do not face the multiple first pillar regions 12 in the thickness direction of the chip 2.

[0101] The bottoms of the multiple field regions 38 may be located closer to the first main surface 3 than the depth position of the first upper end 12b of the first pillar region 12. Of course, the bottoms of the multiple field regions 38 may be located closer to the first lower end 12a of the first pillar region 12 than the depth position of the first upper end 12b of the first pillar region 12. In this case, it is preferable that the bottoms of the multiple field regions 38 are located closer to the first main surface 3 than the intermediate portion of the thickness range of the first pillar region 12.

[0102] The field regions 38 may have a thickness approximately equal to that of the body regions 32. In this case, the field regions 38 may be formed simultaneously with the body regions 32. Of course, the field regions 38 may have a thickness greater than that of the body regions 32. The field regions 38 may have a thickness less than that of the body regions 32.

[0103] The plurality of field regions 38 are 1×10 １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration may have the following peak value:

[0104] The p-type impurity concentration of the field region 38 may be approximately equal to the p-type impurity concentration of the body region 32. Of course, the p-type impurity concentrations of the plurality of field regions 38 may be higher than the p-type impurity concentrations of the plurality of body regions 32. The p-type impurity concentrations of the plurality of field regions 38 may be lower than the p-type impurity concentrations of the plurality of body regions 32.

[0105] The p-type impurity concentrations of the plurality of field regions 38 are preferably adjusted by at least one trivalent element. The trivalent element in the field regions 38 may be the same as the trivalent element in the first pillar regions 12, etc., or may be a different species from the trivalent element in the first pillar regions 12, etc. The trivalent element in the field regions 38 may be at least one of boron, aluminum, gallium, and indium.

[0106] The plurality of field regions 38 preferably have a width different from the first width W1 of the first pillar region 12. The electric field relaxation effect of the plurality of field regions 38 is preferably adjusted separately from the plurality of first pillar regions 12.

[0107] It is particularly preferable that the widths of the plurality of field regions 38 be greater than the first width W1 of the first pillar region 12. Of course, the widths of the plurality of field regions 38 may be smaller than the first width W1. The widths of the plurality of field regions 38 may also be approximately equal to the first width W1.

[0108] The field regions 38 are preferably formed at a pitch different from the first pitch P1 of the first pillar regions 12. It is particularly preferable that the pitch of the field regions 38 be larger than the first pitch P1. Of course, the pitch of the field regions 38 may be smaller than the first pitch P1. The pitch of the field regions 38 may also be approximately equal to the first pitch P1.

[0109] The semiconductor device 1A includes an interlayer insulating film 40 covering the first main surface 3. The interlayer insulating film 40 may also be referred to as an "insulating film," an "interlayer film," an "intermediate insulating film," or the like. In this embodiment, the interlayer insulating film 40 has a stacked structure including a first insulating film 41 and a second insulating film 42 (see FIG. 9). The first insulating film 41 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is particularly preferable that the first insulating film 41 include a silicon oxide film made of an oxide of the chip 2 (stacked portion 7).

[0110] The first insulating film 41 selectively covers the first main surface 3 in the active region 10 and the peripheral region 11. The first insulating film 41 covers the region outside the gate insulating film 36 in the active region 10 and is connected to the gate insulating film 36. The first insulating film 41 covers a plurality of field regions 38 in the peripheral region 11. In this embodiment, the first insulating film 41 is continuous with the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D). Of course, the first insulating film 41 may be formed at a distance inward from the periphery of the first main surface 3, with the stacked portion 7 exposed from the periphery of the first main surface 3.

[0111] The second insulating film 42 is stacked on the first insulating film 41. The second insulating film 42 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer insulating film 40 preferably includes a silicon oxide film. The second insulating film 42 covers the first main surface 3 in the active region 10 and the peripheral region 11, sandwiching the first insulating film 41 therebetween.

[0112] The second insulating film 42 covers the plurality of gate structures 35 in the active region 10. The second insulating film 42 covers the plurality of field regions 38 in the peripheral region 11, sandwiching the first insulating film 41 therebetween. In this embodiment, the second insulating film 42 is continuous with the periphery of the first main surface 3. Of course, the second insulating film 42 may be formed at a distance inward from the periphery of the first main surface 3, and may expose the periphery of the first main surface 3 together with the first insulating film 41.

[0113] The semiconductor device 1A includes a plurality of contact openings 43 formed in the interlayer insulating film 40. The plurality of contact openings 43 include a plurality of contact openings 43 (not shown) that expose a plurality of gate structures 35 (gate electrodes 37) and a plurality of contact openings 43 that expose a plurality of source regions 33. The plurality of contact openings 43 for the source regions 33 are formed in regions between adjacent plurality of gate structures 35, and expose a plurality of source regions 33 and a plurality of contact regions 34.

[0114] 1 , the semiconductor device 1A includes a gate pad 45 disposed on an interlayer insulating film 40. The gate pad 45 is an electrode to which a gate potential is applied from the outside. The gate pad 45 may also be referred to as a "gate pad electrode," a "first pad electrode," or the like. The gate pad 45 may have a layered structure including a Ti-based metal film and an Al-based metal film layered in this order from the interlayer insulating film 40 side.

[0115] In this embodiment, the gate pad 45 is disposed on a portion of the interlayer insulating film 40 that covers the active region 10. The gate pad 45 may be disposed at an interval from the outer periphery region 11 toward the active region 10. In this embodiment, the gate pad 45 is disposed on the periphery of the active region 10 in plan view.

[0116] 1 shows an example in which the gate pad 45 is arranged in a region along the center of the second side surface 5B on the periphery of the active region 10. Of course, the gate pad 45 may also be arranged in a region along the center of any of the first to fourth side surfaces 5A to 5D. Of course, the gate pad 45 may also be arranged at any corner of the active region 10 in a plan view. The gate pad 45 may also be arranged in the center of the active region 10 in a plan view. In this embodiment, the gate pad 45 is formed in a quadrangular shape in a plan view.

[0117] The semiconductor device 1A includes at least one gate wiring 46 (multiple in this embodiment) extending from the gate pad 45 onto the interlayer insulating film 40. The gate wiring 46 may also be referred to as a "wiring" or "wiring electrode." The multiple gate wirings 46 may have a layered structure including a Ti-based metal film and an Al-based metal film stacked in this order from the interlayer insulating film 40 side. In this embodiment, the multiple gate wirings 46 include a first gate wiring 46A and a second gate wiring 46B.

[0118] The first gate wiring 46A is drawn out from the gate pad 45 toward the first side surface 5A and extends in a line along the periphery of the active region 10 so as to intersect (specifically, perpendicular to) part (specifically, one end) of the multiple gate structures 35. The first gate wiring 46A penetrates the interlayer insulating film 40 via the multiple contact openings 43 and is electrically connected to one end of the multiple gate structures 35.

[0119] The second gate wiring 46B is drawn out from the gate pad 45 toward the third side surface 5C and extends in a line along the periphery of the active region 10 so as to intersect (specifically, perpendicular to) part (specifically, the other end portions) of the multiple gate structures 35. The second gate wiring 46B penetrates the interlayer insulating film 40 via the multiple contact openings 43 and is electrically connected to the other end portions of the multiple gate structures 35.

[0120] The semiconductor device 1A includes a source pad 47 disposed on the interlayer insulating film 40 at a distance from the gate pad 45 and the gate wiring 46. The source pad 47 is an electrode to which a source potential is applied from the outside. The source pad 47 may also be referred to as a "source pad electrode," a "second pad electrode," or the like. The source pad 47 may have a layered structure including a Ti-based metal film and an Al-based metal film layered in this order from the interlayer insulating film 40 side.

[0121] The source pad 47 is disposed on a portion of the interlayer insulating film 40 that covers the active region 10. The source pad 47 may be disposed at an interval from the peripheral region 11 toward the active region 10. In this embodiment, the source pad 47 is formed in a polygonal shape having a recess that is recessed along the gate pad 45 in a plan view. Of course, the source pad 47 may also be formed in a quadrangular shape in a plan view.

[0122] The source pad 47 penetrates the interlayer insulating film 40 via the plurality of contact openings 43, and is electrically connected to the plurality of body regions 32, the plurality of source regions 33, and the plurality of contact regions 34. The source pad 47 is electrically connected to the plurality of first pillar regions 12 via the plurality of body regions 32.

[0123] 2 , the semiconductor device 1A includes a drain pad 48 covering the second main surface 4. The drain pad 48 is an electrode to which a drain potential is applied from the outside. The drain pad 48 may also be referred to as a "drain pad electrode," a "third pad electrode," or the like. The drain pad 48 forms an ohmic contact with the base layer 6 exposed from the second main surface 4. The drain pad 48 is electrically connected to the stacked portion 7 (the drift region 8 and the plurality of second pillar regions 13) via the base layer 6.

[0124] The drain pad 48 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. The drain pad 48 may cover the second main surface 4 at a distance inward from the periphery of the chip 2 so as to expose the periphery of the chip 2.

[0125] The breakdown voltage that can be applied between source pad 47 and drain pad 48 (between first main surface 3 and second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value that belongs to any one of the ranges of 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0126] 10 is a schematic diagram showing a wafer 50 used in the manufacture of the semiconductor device 1A. The wafer 50 is a substrate of the base layer 6 and contains SiC single crystal. The wafer 50 is formed in a flat disk shape. Of course, the wafer 50 may also be formed in a flat rectangular parallelepiped shape. The wafer 50 has a first wafer main surface 51 on one side, a second wafer main surface 52 on the other side, and a wafer side surface 53 connecting the first wafer main surface 51 and the second wafer main surface 52.

[0127] The first wafer main surface 51 corresponds to the upper end of the base layer 6, and the second wafer main surface 52 corresponds to the lower end of the base layer 6. The first wafer main surface 51 and the second wafer main surface 52 are formed by the c-plane of the SiC single crystal. The first wafer main surface 51 is formed by the silicon surface of the SiC single crystal, and the second wafer main surface 52 is formed by the carbon surface of the SiC single crystal.

[0128] The wafer 50 has a mark 54 on the wafer side surface 53 that indicates the crystal orientation of the SiC single crystal. The mark 54 may include either or both of an orientation flat and an orientation notch. The orientation flat is a cutout that is linearly cut out in a plan view. The orientation notch is a cutout that is concave (e.g., tapered) toward the center of the first wafer main surface 51 in a plan view.

[0129] The mark 54 may include either or both of a first orientation flat extending in the m-axis direction and a second orientation flat extending in the a-axis direction. The mark 54 may include either or both of an orientation notch recessed in the m-axis direction and an orientation notch recessed in the a-axis direction. Figure 10 shows an orientation flat extending in the m-axis direction in a plan view.

[0130] For example, a plurality of device regions 55 and a plurality of cutting lines 56 are set on the wafer 50 by alignment marks or the like. Each device region 55 corresponds to a semiconductor device 1A. Each of the plurality of device regions 55 is set to have a quadrangular shape in a plan view.

[0131] In this embodiment, the device regions 55 are set in a matrix along the first direction X and the second direction Y in a plan view. The device regions 55 are set at intervals inward from the periphery of the first wafer main surface 51 in a plan view. The cutting lines 56 are set in a grid pattern extending along the first direction X and the second direction Y to partition the device regions 55.

[0132] Fig. 11 is a flowchart showing an example of a method for manufacturing the semiconductor device 1A. Figs. 12A to 12C are cross-sectional perspective views showing an example of a method for manufacturing a superjunction structure using first pillar regions 12 and second pillar regions 13. Figs. 12A to 12C show cross-sectional views of a portion of the active region 10 of one device region 55.

[0133] First, referring to FIG. 12A, the above-described wafer 50 preparation step is carried out (step S1 in FIG. 11).

[0134] Next, referring to FIG. 12B , the step of forming the n-type stacked layer 7 is performed (step S2 in FIG. 11 ). The stacked layer 7 is formed starting from the first wafer main surface 51 (wafer 50) by epitaxial growth while adding n-type impurity ions. The impurity ions used are at least one pentavalent element, preferably nitrogen. At this point, the entire stacked layer 7 (active region 10 and peripheral region 11) has been formed as the drift region 8.

[0135] 12C , a step of forming a first mask 60 having a predetermined pattern is performed (step S3 in FIG. 11 ). The first mask 60 is preferably an organic mask (resist mask). The first mask 60 is disposed on the first main surface 3 of the stacked layer 7 and has a plurality of first openings 61 that expose regions of the stacked layer 7 where a plurality of first pillar regions 12 are to be formed. The plurality of first openings 61 are formed at intervals in the first direction X and are each partitioned into strips extending in the second direction Y.

[0136] Next, a step of forming a plurality of first pillar regions 12 is performed (step S4 in FIG. 11 ). The step of forming the plurality of first pillar regions 12 includes a step of ion implantation of a trivalent element (p-type impurity) into the stacked portion 7. The impurity ions used are at least one type of trivalent element, preferably aluminum. The ion implantation step can be performed by, for example, random implantation, channeling implantation, or the like. As a result, a plurality of first pillar regions 12 are formed in the drift region 8 exposed from the first opening 61. Accordingly, a second pillar region 13 is formed in a region sandwiched between the plurality of first pillar regions 12. The first pillar regions 12 may be formed by a multi-epitaxial method or the like in addition to the method shown in FIG. 12C .

[0137] Thereafter, the MIS structure 31 (body region 32, source region 33, contact region 34, gate structure 35, etc.), a plurality of field regions 38, interlayer insulating film 40, gate pad 45, gate wiring 46, source pad 47, drain pad 48, etc. are formed (step S5 in FIG. 11). Then, the wafer 50 is cut along a plurality of cutting lines 56. In this way, a plurality of semiconductor devices 1A are manufactured from one wafer 50.

[0138] 8 , according to the semiconductor device 1A, a plurality of first pillar regions 12 (pillar main body portions 71) overlap one body region 32 in a one-to-many correspondence. The plurality of first pillar regions 12 are connected to the body region 32 of a common unit cell 14, extend in the depth direction of the chip 2 from the first main surface 3 toward the second main surface 4, and are physically separated and independent from one another. This makes it possible to narrow the first pitch P1 of the first pillar regions 12 and the second pitch P2 of the second pillar regions 13 compared to a configuration in which the first pillar regions 12 are provided in a one-to-one correspondence with the body region 32.

[0139] 13 is a graph showing the relationship between the withstand voltage and on-resistance of a SiC device having a superjunction structure SJ for each pitch. In FIG. 13, examples of pitches PA, PB, PC, and PD are shown as pitches (p-pillar width + n-pillar width) of a superjunction structure SJ formed by a combination of p-pillars 74 and n-pillars 75. The magnitude relationship between these pitches is pitch PD > pitch PC > pitch PB > pitch PA. Pitch PD is the widest, and pitch PA is the narrowest.

[0140] 13 shows that the narrower the pitch of the superjunction structure SJ, the lower the on-resistance can be for the same withstand voltage. The narrower the pitch, the shorter the distance between one pn junction 76A and the other pn junction 76B in the superjunction structure SJ. This makes it easy to achieve a superjunction structure SJ in a charge-balanced state. The charge-balanced state refers to a state in which the depletion layer extending from one pn junction 76A and the depletion layer extending from the other pn junction 76B are connected within multiple n-type pillars 75.

[0141] Therefore, in the semiconductor device 1A, a charge balance state can be maintained even if the impurity concentrations are increased in the first pillar region 12 and the second pillar region 13. As a result, by appropriately designing the impurity concentrations, it is possible to reduce the on-resistance of the current path (first portion 29 of the second pillar region 13) in the chip 2 while maintaining the breakdown voltage.

[0142] 14 to 17 are diagrams showing first to fourth modified examples of the superjunction structure according to the first embodiment. The semiconductor device 1A may include at least one of the superjunction structures according to the first to fourth modified examples. The semiconductor device 1A may simultaneously include at least two of the superjunction structure of FIG. 8 and the superjunction structures according to the first to fourth modified examples in the same cross-sectional region or different cross-sectional regions.

[0143] Referring to FIG. 14 (first modified example), first lower end 12 a of first pillar region 12 may be aligned with the lower end of stacked portion 7 and connected to base layer 6 .

[0144] 15 (second modified example), first lower end 12a of first pillar region 12 may have an extension 77 that crosses the boundary between base layer 6 and stack portion 7 and is located within base layer 6. In this case, the thickness of extension 77 of first lower end 12a, based on the upper end of base layer 6, may be greater than 0 μm and less than 2 μm. The thickness of extension 77 of first lower end 12a may have a value that belongs to any one of the ranges of greater than 0 μm and less than 0.5 μm, 0.5 μm or more to 1 μm or less, 1 μm or more to 1.5 μm or less, and 1.5 μm or more to 2 μm or less.

[0145] 16 (third modified example), each of the plurality of first pillar regions 12 has a stacked structure including a first region 18 and a second region 19 in the thickness direction of the stacked portion 7. In this embodiment, the first region 18 and the second region 19 are arranged at intervals from each other in the thickness direction of the stacked portion 7.

[0146] A portion of the stack 7 (drift region 8) is interposed between the first region 18 and the second region 19. The portion of the drift region 8 provides an n-type intermediate region 25 that physically separates the first region 18 and the second region 19. The intermediate region 25 may be located at the center of the thickness direction of the stack 7, or at the upper end or lower end relative to the center position. The first region 18 and the second region 19 may be connected to each other at a position (not shown) in the depth direction of the stripes of the first region 18 and the second region 19. That is, in the first pillar region 12, the first region 18 and the second region 19 may be integrated at a first position in the depth direction of the first pillar region 12, and may be physically separated at a second position in the depth direction.

[0147] 17 (fourth modification), a clear step S may be formed between the body side portion 32 a and the first side portion 12 c. As a result, the first side portion 12 c may be disposed more inward than the side portion (source side portion 33 a) of the source region 33.

[0148] FIG. 18 is a cross-sectional perspective view showing a superjunction structure according to the second embodiment.

[0149] In the superjunction structure according to the first embodiment, a pair of first pillar regions 12 are connected to one body region 32, but as shown in FIG. 18 , three first pillar regions 12 may be connected to one body region 32.

[0150] As a result, the drift region 8 below the body region 32 of each unit cell 14 is divided by the multiple first pillar regions 12 to provide multiple second pillar regions 13. In the region below the body region 32 of each unit cell 14, the multiple first pillar regions 12 and the multiple second pillar regions 13 are arranged alternately in the first direction X. A central first pillar region 12 among the multiple first pillar regions 12 may face the contact region 34 with the corresponding body region 32 interposed therebetween.

[0151] 19 to 21 are diagrams showing first to third modified examples of the superjunction structure according to the second embodiment. The semiconductor device 1A may include at least one of the superjunction structures according to the first to third modified examples. The semiconductor device 1A may simultaneously include at least two of the superjunction structure of FIG. 18 and the superjunction structures according to the first to third modified examples in the same cross-sectional region or different cross-sectional regions.

[0152] Referring to FIG. 19 (first modified example), first lower end 12 a of first pillar region 12 may be aligned with the lower end of stacked portion 7 and connected to base layer 6 .

[0153] 20 (second modified example), first lower end 12a of first pillar region 12 may have an extension 77 that crosses the boundary between base layer 6 and stack portion 7 and is located within base layer 6. In this case, the thickness of extension 77 of first lower end 12a, based on the upper end of base layer 6, may be greater than 0 μm and less than 2 μm. The thickness of extension 77 of first lower end 12a may have a value that belongs to any one of the ranges of greater than 0 μm and less than 0.5 μm, 0.5 μm or more to 1 μm or less, 1 μm or more to 1.5 μm or less, and 1.5 μm or more to 2 μm or less.

[0154] 21 (third modified example), each of the plurality of first pillar regions 12 has a stacked structure including a first region 18 and a second region 19 in the thickness direction of the stacked portion 7. In this embodiment, the first region 18 and the second region 19 are arranged at intervals from each other in the thickness direction of the stacked portion 7.

[0155] A portion of the stack 7 (drift region 8) is interposed between the first region 18 and the second region 19. The portion of the drift region 8 provides an n-type intermediate region 25 that physically separates the first region 18 and the second region 19. The intermediate region 25 may be located at the center of the thickness direction of the stack 7, or at the upper end or lower end relative to the center position. The first region 18 and the second region 19 may be connected to each other at a position (not shown) in the depth direction of the stripes of the first region 18 and the second region 19. That is, in the first pillar region 12, the first region 18 and the second region 19 may be integrated at a first position in the depth direction of the first pillar region 12, and may be physically separated at a second position in the depth direction.

[0156] Although not shown, in the super junction structure according to the second embodiment, a clear step S may be formed between the body side portion 32a and the first side portion 12c, as shown in FIG. 17 .

[0157] FIG. 22 is a cross-sectional perspective view showing a superjunction structure according to the third embodiment.

[0158] In the superjunction structure according to the first embodiment, a pair of first pillar regions 12 are connected to one body region 32, but as shown in FIG. 22 , four first pillar regions 12 may be connected to one body region 32.

[0159] As a result, the drift region 8 below the body region 32 of the unit cell 14 is divided by the multiple first pillar regions 12 to provide multiple second pillar regions 13. In the region below the body region 32 of each unit cell 14, the multiple first pillar regions 12 and the multiple second pillar regions 13 are arranged alternately in the first direction X. A central first pillar region 12 among the multiple first pillar regions 12 may face the contact region 34 with the corresponding body region 32 interposed therebetween.

[0160] 23 to 25 are diagrams showing first to third modified examples of the superjunction structure according to the third embodiment. The semiconductor device 1A may include at least one of the superjunction structures according to the first to third modified examples. The semiconductor device 1A may simultaneously include at least two of the superjunction structure of FIG. 22 and the superjunction structures according to the first to third modified examples in the same cross-sectional region or different cross-sectional regions.

[0161] Referring to FIG. 23 (first modified example), first lower end 12 a of first pillar region 12 may be aligned with the lower end of stacked portion 7 and connected to base layer 6 .

[0162] 24 (second modified example), first lower end 12a of first pillar region 12 may have an extension 77 that crosses the boundary between base layer 6 and stack portion 7 and is located within base layer 6. In this case, the thickness of extension 77 of first lower end 12a, based on the upper end of base layer 6, may be greater than 0 μm and less than 2 μm. The thickness of extension 77 of first lower end 12a may have a value that belongs to any one of the ranges of greater than 0 μm and less than 0.5 μm, 0.5 μm or more to 1 μm or less, 1 μm or more to 1.5 μm or less, and 1.5 μm or more to 2 μm or less.

[0163] 25 (third modified example), each of the plurality of first pillar regions 12 has a stacked structure including a first region 18 and a second region 19 in the thickness direction of the stacked portion 7. In this embodiment, the first region 18 and the second region 19 are arranged at intervals from each other in the thickness direction of the stacked portion 7.

[0164] A portion of the stack 7 (drift region 8) is interposed between the first region 18 and the second region 19. The portion of the drift region 8 provides an n-type intermediate region 25 that physically separates the first region 18 and the second region 19. The intermediate region 25 may be located at the center of the thickness direction of the stack 7, or at the upper end or lower end relative to the center position. The first region 18 and the second region 19 may be connected to each other at a position (not shown) in the depth direction of the stripes of the first region 18 and the second region 19. That is, in the first pillar region 12, the first region 18 and the second region 19 may be integrated at a first position in the depth direction of the first pillar region 12, and may be physically separated at a second position in the depth direction.

[0165] Although not shown, in the super junction structure according to the third embodiment, a clear step S may be formed between the body side portion 32a and the first side portion 12c, as shown in FIG. 17 .

[0166] Fig. 26 is a cross-sectional perspective view showing a superjunction structure according to the fourth embodiment, and Fig. 27 is an enlarged cross-sectional view of the region surrounded by the two-dot chain line XXVII in Fig. 26.

[0167] In the superjunction structure according to the fourth embodiment, the impurity concentration of the first portion 29 of the second pillar region 13 varies from one region to another. In Fig. 27, the boundaries between the regions with different impurity concentrations are indicated by dashed lines. In this embodiment, multiple regions having different impurity regions are provided at different depths in the chip 2.

[0168] More specifically, the first portion 29 includes a first concentration portion C1, a second concentration portion C2, and a third concentration portion C3, while the second portion 30 has a constant impurity concentration in the depth direction of the chip 2, and the entire second portion 30 may be a fourth concentration portion C4.

[0169] The first concentration region C1 is provided by the first pillar adjacent region 29a. The second concentration region C2 is provided by the cell adjacent region 29b. The third concentration region C3 is provided by the first protruding region 29c. The fourth concentration region C4 is provided by the second pillar adjacent region 30a and the second protruding region 30c.

[0170] In terms of the concentration magnitude relationship, the first concentration section C1 is the highest, followed by the second concentration section C2. The third concentration section C3 and the fourth concentration section C4 are lower than the second concentration section C2. The third concentration section C3 and the fourth concentration section C4 may have the same concentration, or one may be higher than the other. Therefore, the order may be first concentration section C1 > second concentration section C2 > third concentration section C3 = fourth concentration section C4, first concentration section C1 > second concentration section C2 > third concentration section C3 > fourth concentration section C4, or first concentration section C1 > second concentration section C2 > fourth concentration section C4 > third concentration section C3.

[0171] For example, the impurity concentration of the first concentration portion C1 is 1×10 １７ cm －３ 1x10 or more １９ cm －３ The impurity concentration of the second concentration portion C2 may be 5×10 １６ cm －３ 1x10 or more １７ cm －３ The impurity concentrations of the third concentration portion C3 and the fourth concentration portion C4 may be 1×10 or less. １６ cm －３ 1x10 or more １７ cm －３ It may be the following:

[0172] The first concentration section C1, the second concentration section C2, the third concentration section C3, and the fourth concentration section C4 are all adjusted in concentration by a pentavalent element. The first concentration section C1 may be adjusted in concentration by a pentavalent element different from the second concentration section C2, the third concentration section C3, and the fourth concentration section C4. More preferably, the first concentration section C1 is adjusted in concentration by phosphorus (P), and the second concentration section C2 is adjusted in concentration by phosphorus (P) or nitrogen (N). It is preferable that the third concentration section C3 and the fourth concentration section C4 do not contain phosphorus (P) as an impurity and are adjusted in concentration by nitrogen (N).

[0173] As described above, the first protrusion 29c, the second protrusion 30c, and the drift region 8 below the first pillar region 12 may be collectively referred to as an n-type base region 39. The base region 39 has a constant impurity concentration along the lateral direction along the first main surface 3. The base region 39 may also be referred to as a fifth concentration portion C5. The fifth concentration portion C5 has the same concentration as the third concentration portion C3 and the fourth concentration portion C4. The impurity concentration of the fifth concentration portion C5 is 1×10 １６ cm －３ 1x10 or more １７ cm －３ It may be the following:

[0174] Fig. 28 is a flowchart showing an example of a method for manufacturing a superjunction structure according to the fourth embodiment. Fig. 29A to Fig. 29E are cross-sectional perspective views showing an example of a method for manufacturing a superjunction structure according to the fourth embodiment.

[0175] First, referring to FIG. 29A, the above-described wafer 50 preparation step is carried out (step S1 in FIG. 28).

[0176] Next, referring to FIG. 29B , the step of forming the n-type stacked layer 7 is performed (step S2 in FIG. 28 ). The stacked layer 7 is formed starting from the first wafer main surface 51 (wafer 50) by epitaxial growth while adding n-type impurity ions. The impurity ions used are at least one pentavalent element, preferably nitrogen. At this point, the entire stacked layer 7 (active region 10 and peripheral region 11) has been formed as the drift region 8.

[0177] Next, referring to FIG. 29C , a step of forming a first mask 80 having a predetermined pattern is performed (step S3 in FIG. 28 ). The first mask 80 is preferably an organic mask (resist mask). The first mask 80 is disposed on the first main surface 3 of the stacked layer 7 and has a plurality of first openings 81 that expose regions of the stacked layer 7 where a plurality of second pillar regions 13 (first concentration portions C1) are to be formed. The plurality of first openings 81 are formed at intervals in the first direction X and are each partitioned into strips extending in the second direction Y.

[0178] Next, a process for forming a plurality of second pillar regions 13 (first concentration portions C1) is performed (step S4 in FIG. 28 ). The process for forming the plurality of second pillar regions 13 includes a process for ion implantation of a pentavalent element (n-type impurity) into the stacked layer 7. The impurity ions used are at least one type of pentavalent element, preferably phosphorus (P). For example, random implantation, channeling implantation, or the like can be applied as the ion implantation process. As a result, a plurality of second pillar regions 13 (first concentration portions C1) are selectively formed in the drift region 8 exposed from the first opening 81.

[0179] 29D , a step of forming a second mask 82 having a predetermined pattern is performed (step S5 in FIG. 28 ). The second mask 82 is preferably an organic mask (resist mask). The second mask 82 is disposed on the first main surface 3 of the stacked layer 7 and has a plurality of second openings 83 that expose regions of the stacked layer 7 where the plurality of first pillar regions 12 are to be formed. The second openings 83 are formed at intervals in the first direction X and are each partitioned into strips extending in the second direction Y.

[0180] Next, a step of forming a plurality of first pillar regions 12 is performed (step S6 in FIG. 28 ). The step of forming the plurality of first pillar regions 12 includes a step of ion implantation of a trivalent element (p-type impurity) into the stacked portion 7. The impurity ions used are at least one type of trivalent element, preferably aluminum. The ion implantation step can be performed by, for example, random implantation, channeling implantation, or the like. As a result, a plurality of first pillar regions 12 are formed in the drift region 8 exposed from the second opening 83. Accordingly, a second pillar region 13 is formed in a region sandwiched between the plurality of first pillar regions 12. The first pillar regions 12 may be formed by a multi-epitaxial method or the like in addition to the method shown in FIG. 29D .

[0181] Next, referring to FIG. 29E , the step of forming the second stacked layer 84 is performed (step S7 in FIG. 28 ). The second stacked layer 84 is formed starting from the first wafer main surface 51 of the stacked layer 7 by epitaxial growth while adding n-type impurity ions. The impurity ions used are at least one pentavalent element, preferably nitrogen. The second stacked layer 84 is the base of the second concentration portion C2 (cell adjacent portion 29 b) of the multiple second pillar regions 13.

[0182] Thereafter, the MIS structure 31 (body region 32, source region 33, contact region 34, gate structure 35, etc.), a plurality of field regions 38, interlayer insulating film 40, gate pad 45, gate wiring 46, source pad 47, drain pad 48, etc. are formed (step S8 in FIG. 28). Then, the wafer 50 is cut along a plurality of cutting lines 56. In this way, a plurality of semiconductor devices 1A having the super junction structure according to the fourth embodiment are manufactured from one wafer 50.

[0183] 30 to 33 are diagrams showing first to fourth modified examples of the superjunction structure according to the fourth embodiment. The semiconductor device 1A may include at least one of the superjunction structures according to the first to fourth modified examples. The semiconductor device 1A may simultaneously include at least two of the superjunction structure of FIG. 27 and the superjunction structures according to the first to fourth modified examples in the same cross-sectional region or different cross-sectional regions.

[0184] Referring to FIG. 30 (first modified example), first lower end 12 a of first pillar region 12 may be aligned with the lower end of stacked portion 7 and connected to base layer 6 .

[0185] 31 (second modified example), first lower end 12a of first pillar region 12 may have an extension 77 that crosses the boundary between base layer 6 and stack portion 7 and is located within base layer 6. In this case, the thickness of extension 77 of first lower end 12a, based on the upper end of base layer 6, may be greater than 0 μm and less than 2 μm. The thickness of extension 77 of first lower end 12a may have a value that belongs to any one of the ranges of greater than 0 μm and less than 0.5 μm, 0.5 μm or more to 1 μm or less, 1 μm or more to 1.5 μm or less, and 1.5 μm or more to 2 μm or less.

[0186] 32 (third modified example), each of the plurality of first pillar regions 12 has a stacked structure including a first region 18 and a second region 19 in the thickness direction of the stacked portion 7. In this embodiment, the first region 18 and the second region 19 are arranged at intervals from each other in the thickness direction of the stacked portion 7.

[0187] A part of the stacked layer 7 (drift region 8) is interposed between the first region 18 and the second region 19. The part of the drift region 8 provides an n-type intermediate region 25 that physically separates the first region 18 and the second region 19. The intermediate region 25 may be located at the center of the stacked layer 7 in the thickness direction, or at the upper or lower end side relative to the center position.

[0188] 33 (fourth modification), a clear step S may be formed between the body side portion 32 a and the first side portion 12 c. As a result, the first side portion 12 c may be disposed more inward than the side portion (source side portion 33 a) of the source region 33.

[0189] Next, variations in the planar layout of the superjunction structure will be mainly described with reference to FIGS.

[0190] Fig. 34 is a plan view showing a superjunction structure according to a fifth embodiment. Fig. 35 is a sectional perspective view showing a superjunction structure according to the fifth embodiment. Fig. 36 is a plan view showing a superjunction structure according to a sixth embodiment. Fig. 37 is a plan view showing a superjunction structure according to a seventh embodiment. Fig. 38 is a plan view showing a superjunction structure according to an eighth embodiment. Fig. 39 is a plan view showing a superjunction structure according to a ninth embodiment.

[0191] 34 and 35, the first pillar regions 12 may be arranged at intervals along the extension direction of the body regions 32, and may be arranged in a stripe pattern extending parallel to each other along a direction intersecting the extension direction of the body regions 32.

[0192] The extension direction of the multiple first pillar regions 12 may coincide with the extension direction of the multiple unit cells 14 (multiple body regions 32) as shown in the above-described embodiment (for example, FIG. 5 ), or may coincide with a direction intersecting the extension direction of the multiple unit cells 14 (multiple body regions 32).

[0193] 34 and 35 , in a cross-sectional view along the extension direction of the plurality of body regions 32 (second direction Y in this embodiment), a plurality of first pillar regions 12 (pillar main body portions 71) overlap one body region 32 in a one-to-many correspondence. As a result, a plurality of first pillar regions 12 and a plurality of second pillar regions 13 (second portions 30) are alternately arranged in the region below each body region 32. The plurality of second portions 30 are sandwiched between a plurality of first pillar regions 12 in the extension direction of the plurality of body regions 32.

[0194] 36 , the multiple first pillar regions 12 in the lower region of the body region 32 do not need to be connected at their ends via pillar connection portions 72 (see FIG. 5 ), and may be completely physically separated from one another and connected to a common body region 32 (pillar main body portion 71). In this embodiment, the pillar connection portions 72 ( FIG. 5 ) are omitted, and multiple band-shaped first pillar regions 12 extending along the extension direction of the body region 32 are arranged in a stripe pattern along a direction intersecting the extension direction of the body region 32. An end 85 of each band-shaped first pillar region 12 may coincide with an end 86 of a line 27 between adjacent body regions 32.

[0195] Referring to FIG. 37 , an end 85 of each strip-shaped first pillar region 12 may be formed as a protrusion that protrudes outward beyond an end 86 of a line 27 between adjacent body regions 32 .

[0196] Referring to Figure 38, when multiple first pillar regions 12 are connected at their ends via pillar connection portions 72, the pillar connection portions 72 may be positioned outside the ends 86 of the lines 27 between adjacent body regions 32.

[0197] 39, the planar layout of the plurality of first pillar regions 12 may be a combination of the layout of Fig. 5 and the layout of Fig. 34. The extending direction of the plurality of first pillar regions 12 may coincide with the extending direction of the plurality of unit cells 14 (plurality of body regions 32) and may coincide with a direction intersecting the extending direction of the plurality of unit cells 14 (plurality of body regions 32).

[0198] In this embodiment, the first pillar region 12 integrally includes a plurality of pillar body portions 71 extending in parallel along the stripe direction of the unit cells 14 in the region below each body region 32, and a plurality of pillar connecting portions 78 arranged along the stripe direction of the unit cells 14 in the same region below the body region 32 and connecting between the plurality of pillar body portions 71. The first pillar region 12 may be formed in a ladder shape in a plan view in the region below each body region 32.

[0199] The second portion 30 of the second pillar region 13 may be surrounded by the first pillar region 12 in a plan view.

[0200] The above-described embodiments can be implemented in other forms. For example, in each of the above-described embodiments, the base layer 6 and the stacked portion 7 each include a SiC single crystal. However, at least one of the base layer 6 and the stacked portion 7 or all of the base layer 6 and the stacked portion 7 may include a single crystal of a wide bandgap semiconductor other than a SiC single crystal.

[0201] Wide bandgap semiconductors are semiconductors that have a bandgap larger than that of silicon. Wide bandgap semiconductor single crystals include silicon carbide (SiC), gallium nitride (GaN), diamond (C), and gallium oxide (Ga ２ O ３ The base layer 6 and the laminated portion 7 may be made of the same type of single crystal, or may be made of different types of single crystal.

[0202] In the above-described embodiments, an n-type base layer 6 has been described. However, a p-type base layer 6 may be employed. In this case, an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure. In this case, in the above description, the "source" of the MISFET structure is replaced with the "emitter" of the IGBT structure, and the "drain" of the MISFET structure is replaced with the "collector" of the IGBT structure. The p-type base layer 6 may be a p-type region containing a trivalent element introduced into the surface layer of the second main surface 4 of the chip 2 by ion implantation.

[0203] Below, examples of features extracted from this specification and the drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiments. The "semiconductor device" in the following items may be replaced with "semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier device," "MISFET device," "IGBT device," "diode device," etc., as necessary.

[0204] [Supplementary Note 1-1] A SiC chip (2) having a first main surface (3) and a second main surface (4); a first region (8) of a first conductivity type formed in a surface layer portion of the first main surface (3) of the SiC chip (2); a plurality of second regions (32) of a second conductivity type formed in a surface layer portion of the first region (8), the second regions (32) providing a plurality of unit cells (14) in the SiC chip (2); a third region (33) of the first conductivity type formed in a surface layer portion of the second region (32) in each of the unit cells (14); and a planar gate structure (35) facing a channel region (73) in the second region (32) of each of the unit cells (14) and controlling channel conduction between the first region (8) and the third region (33). a plurality of first pillar regions (12) of a second conductivity type connected to the second region (32) of the common unit cell (14), extending in a depth direction of the SiC chip (2) from the first main surface (3) toward the second main surface (4), and physically separated and independent from one another in a cross-sectional view; and a second pillar region (13) of the first conductivity type adjacent to the first pillar region (12) within the SiC chip (2) and extending in the depth direction.

[0205] [Supplementary Note 1-2] The semiconductor device (1A) according to Supplementary Note 1-1, wherein the plurality of second regions (32) are arranged in a stripe pattern, and the plurality of first pillar regions (12) are arranged at intervals in a direction intersecting a direction in which the plurality of second regions (32) extend.

[0206] [Supplementary Note 1-3] The semiconductor device (1A) according to Supplementary Note 1-2, wherein the plurality of first pillar regions (12) are arranged in stripes extending side by side along the extension direction.

[0207] [Supplementary Note 1-4] The semiconductor device (1A) according to Supplementary Note 1-2 or Supplementary Note 1-3, wherein the first pillar regions (12) and the second pillar regions (13) are alternately arranged in the intersecting direction within a region below the second region (32) of each of the unit cells (14).

[0208] [Appendix 1-5] The semiconductor device (1A) according to any one of Appendices 1-1 to 1-4, wherein a pitch (P1) of the plurality of first pillar regions (12) is narrower than a pitch (PCL) of the plurality of unit cells (14).

[0209] [Appendix 1-6] The semiconductor device (1A) according to appendix 1-5, wherein the pitch (PCL) of the plurality of unit cells (14) is 3 μm or more and 6 μm or less, and the pitch (P1) of the plurality of first pillar regions (12) is 0.5 μm or more and 2 μm or less.

[0210] [Supplementary Note 1-7] The semiconductor device (1A) according to any one of Supplementary Note 1-1 to Supplementary Note 1-6, wherein the second pillar region (13) includes a first portion (29) extending in the depth direction from a region sandwiched between the plurality of unit cells (14) in the first region (8), and a second portion (30) sandwiched between the plurality of first pillar regions (12) in a region below the second region (32) of each of the unit cells (14), and the first portion (29) of the second pillar region (13) includes a first concentration portion (C1) having an impurity concentration relatively higher than that of the second portion (30) of the second pillar region (13).

[0211] [Supplementary Note 1-8] The semiconductor device (1A) according to Supplementary Note 1-7, wherein the first concentration portion (C1) is a pillar adjacent portion (29a) arranged in contact with the first pillar region (12) in a lateral direction along the first main surface (3), and the first portion (29) of the second pillar region (13) is a cell adjacent portion (29b) arranged in a region sandwiched between the plurality of unit cells (14) in the lateral direction, and further includes a second concentration portion (C2) having an impurity concentration lower than that of the pillar adjacent portion (29a).

[0212] [Supplementary Note 1-9] The semiconductor device (1A) according to Supplementary Note 1-8, wherein the impurity concentration of the second concentration portion (C2) is higher than the impurity concentration of the second portion (30) of the second pillar region (13).

[0213] [Additional Note 1-10] The impurity concentration of the first concentration portion (C1) is 1×10 １７ cm －３ 1x10 or more １９ cm －３The impurity concentration of the second concentration portion (C2) is 5×10 or less. １６ cm －３ 1x10 or more １７ cm －３ The impurity concentration of the second portion (30) of the second pillar region (13) is 1×10 or less. １６ cm －３ 1x10 or more １７ cm －３ The semiconductor device (1A) according to Supplementary Note 1-8 or Supplementary Note 1-9 is as follows:

[0214] [Supplementary Note 1-11] The semiconductor device (1A) according to any one of Supplementary Note 1-8 to Supplementary Note 1-10, wherein the SiC chip (2) includes a substrate (6) and an epitaxial layer (7) formed on the substrate (6) and providing the first pillar region (12) and the second pillar region (13), and the first portion (29) of the second pillar region (13) further includes a third concentration portion (C3) that is arranged on the substrate (6) side with respect to the pillar adjacent portion (29 a) and has an impurity concentration lower than that of the cell adjacent portion (29 b).

[0215] [Appendix 1-12] The semiconductor device (1A) according to any one of Appendices 1-7 to 1-11, wherein the first concentration portion (C1) has a concentration adjusted by phosphorus (P), and the second portion (30) of the second pillar region (13) does not contain phosphorus (P) and has a concentration adjusted by nitrogen (N).

[0216] [Appendix 1-13] The semiconductor device (1A) according to any one of Appendices 1-2 to 1-4, wherein the plurality of first pillar regions (12) are arranged in a region that is more inward than an outer edge portion (32 a) of each of the second regions (32) in the intersecting direction.

[0217] [Appendix 1-14] The semiconductor device (1A) according to any one of Appendices 1-1 to 1-13, wherein the plurality of first pillar regions (12) face the third region (33) across the common second region (32).

[0218] [Supplementary Note 1-15] The semiconductor device (1A) according to any one of Supplementary Note 1-1 to Supplementary Note 1-14, further including a fourth region (34) of a second conductivity type connected to the second region (32) from the first main surface (3) via the third region (33) and having a higher impurity concentration than the second region (32), wherein the plurality of first pillar regions (12) face the fourth region (34) across the common second region (32).

[0219] [Supplementary Note 1-16] The semiconductor device (1A) according to Supplementary Note 1-1, wherein the second regions (32) are arranged in a stripe pattern, the first pillar regions (12) are spaced apart in a direction intersecting an extension direction of the second regions (32) and extend parallel to one another along the extension direction in a stripe pattern, and the first region (8) below the second region (32) of each unit cell (14) is divided by the first pillar regions (12) to provide the second pillar regions (13).

[0220] [Appendix 1-17] The semiconductor device (1A) according to appendix 1-16, wherein a first pitch (P1) of the plurality of first pillar regions (12) and a second pitch (P2) of the plurality of second pillar regions (13) are equal.

[0221] [Appendix 1-18] The semiconductor device (1A) according to appendix 1-17, wherein the first pitch (P1) and the second pitch (P2) are narrower than a pitch (PCL) of the plurality of unit cells (14) and are 0.5 μm or more and 2 μm or less.

[0222] [Appendix 1-19] The semiconductor device (1A) according to any one of Appendices 1-16 to 1-18, wherein a first width (W1) of the plurality of first pillar regions (12) and a second width (W2) of the plurality of second pillar regions (13) are equal.

[0223] [Appendix 1-20] The semiconductor device (1A) according to any one of Appendices 1-16 to 1-19, wherein the first pillar regions (12) at both ends in the intersecting direction among the plurality of first pillar regions (12) have pillar side portions (12c) that extend continuously in the depth direction from side portions (32a) of the second regions (32).

[0224] [Supplementary Note 2-1] A SiC chip (2) having a first main surface (3) and a second main surface (4); a first region (8) of a first conductivity type formed in a surface layer portion of the first main surface (3) of the SiC chip (2); a plurality of second regions (32) of a second conductivity type formed in a surface layer portion of the first region (8), the second regions (32) providing a plurality of unit cells (14) in the SiC chip (2); a third region (33) of the first conductivity type formed in a surface layer portion of the second region (32) in each of the unit cells (14); and a planar gate structure (35) facing a channel region (73) in the second region (32) of each of the unit cells (14) and controlling conduction of a channel between the first region (8) and the third region (33). the first pillar regions (12) of a second conductivity type are connected to the second region (32) of a common unit cell (14), extend in a depth direction of the SiC chip (2) from the first main surface (3) toward the second main surface (4), and are physically separated and independent from each other in a cross-sectional view; and a second pillar region (13) of the first conductivity type is adjacent to the first pillar regions (12) in the SiC chip (2) and extends in the depth direction, the second pillar region (13) including a first portion (29) extending in the depth direction from a region sandwiched between the plurality of unit cells (14) in the first region (8), and a second portion (30) sandwiched between the plurality of first pillar regions (12) in a region below the second region (32) of each unit cell (14), The semiconductor device (1A), wherein the first portion (29) of the second pillar region (13) includes a first concentration portion (C1) having a relatively higher impurity concentration than the second portion (30) of the second pillar region (13).

[0225] [Supplementary Note 2-2] The semiconductor device (1A) according to Supplementary Note 2-1, wherein the first concentration portion (C1) is a pillar adjacent portion (29a) arranged in contact with the first pillar region (12) in a lateral direction along the first main surface (3), and the first portion (29) of the second pillar region (13) is a cell adjacent portion (29b) arranged in a region sandwiched between the plurality of unit cells (14) in the lateral direction, and further includes a second concentration portion (C2) having an impurity concentration lower than that of the pillar adjacent portion (29a).

[0226] [Supplementary Note 2-3] The semiconductor device (1A) according to Supplementary Note 2-2, wherein the impurity concentration of the second concentration portion (C2) is higher than the impurity concentration of the second portion (30) of the second pillar region (13).

[0227] [Note 2-4] The impurity concentration of the first concentration portion (C1) is 1×10 １７ cm －３ 1x10 or more １９ cm －３ The impurity concentration of the second concentration portion (C2) is 5×10 or less. １６ cm －３ 1x10 or more １７ cm －３ The impurity concentration of the second portion (30) of the second pillar region (13) is 1×10 or less. １６ cm －３ 1x10 or more １７ cm －３ A semiconductor device (1A) according to Supplementary Note 2-2 or Supplementary Note 2-3, which is as follows:

[0228] [Supplementary Note 2-5] The semiconductor device (1A) according to any one of Supplementary Note 2-2 to Supplementary Note 2-4, wherein the SiC chip (2) includes a substrate (6) and an epitaxial layer (7) formed on the substrate (6) and providing the first pillar region (12) and the second pillar region (13), and the first portion (29) of the second pillar region (13) further includes a third concentration portion (C3) that is arranged on the substrate (6) side with respect to the pillar adjacent portion (29 a) and has an impurity concentration lower than that of the cell adjacent portion (29 b).

[0229] [Appendix 2-6] The semiconductor device (1A) according to any one of Appendices 2-1 to 2-5, wherein the first concentration portion (C1) has a concentration adjusted by phosphorus (P), and the second portion (30) of the second pillar region (13) does not contain phosphorus (P) and has a concentration adjusted by nitrogen (N).

[0230] [Supplementary Note 2-7] The semiconductor device (1A) according to any one of Supplementary Note 2-2 to Supplementary Note 2-4, wherein the SiC chip (2) includes a substrate (6) and an epitaxial layer (7) formed on the substrate (6) and providing the first pillar region (12) and the second pillar region (13), wherein a bottom of the first pillar region (12) is disposed away from the substrate (6) toward the first main surface (3), and further includes a first conductivity type base region (39) extending across bottoms of the plurality of first pillar regions (12), bottoms of the pillar-adjacent portions (29 a), and the second portion (30) of the second pillar region (13) along the first main surface (3), and having a lower impurity concentration than the cell-adjacent portion (29 b).

[0231] [Supplementary Note 2-8] The semiconductor device (1A) according to Supplementary Note 2-7, wherein the base region (39) provides a boundary with the substrate (6) over the entire in-plane direction of the SiC chip (2).

[0232] [Appendix 2-9] The semiconductor device (1A) according to Appendix 2-7 or Appendix 2-8, wherein the base region (39) has the same impurity concentration as the second portion (30) of the second pillar region (13) and is integrally connected to the second portion (30) of the second pillar region (13).

[0233] [Supplementary Note 2-10] The semiconductor device (1A) according to any one of Supplementary Note 2-2 to Supplementary Note 2-4, wherein the SiC chip (2) includes a substrate (6) and an epitaxial layer (7) formed on the substrate (6) to provide the first pillar region (12) and the second pillar region (13), and a bottom of the first pillar region (12) is connected to the substrate (6).

[0234] DESCRIPTION OF SYMBOLS 1A: Semiconductor device 2: Chip 3: First main surface 4: Second main surface 5A: First side surface 5B: Second side surface 5C: Third side surface 5D: Fourth side surface 6: Base layer 7: Stacked portion 8: Drift region 10: Active region 11: Peripheral region 12: First pillar region 12a: First lower end portion 12b: First upper end portion 12c: First side portion 13: Second pillar region 14: Unit cell 18: First region 19: Second region 25: Intermediate region 27: Line 28: Connection region 29: First portion 29a: First pillar-adjacent portion 29b: Cell-adjacent portion 29c: First protrusion portion 30: Second portion 30a: Second pillar-adjacent portion 30c: Second protrusion 31: MIS structure 32: Body region 32a: Body side 33: Source region 33a: Source side 34: Contact region 35: Gate structure 36: Gate insulating film 37: Gate electrode 38: Field region 39: Base region 40: Interlayer insulating film 41: First insulating film 42: Second insulating film 43: Contact opening 45: Gate pad 46: Gate wiring 46A: First gate wiring 46B: Second gate wiring 47: Source pad 48: Drain pad 50: Wafer 51: First wafer main surface 52: Second wafer main surface 53: Wafer side surface 54: Mark 55: Device region 56: Cutting line 60: First mask 61: First opening 71 : Pillar main body 72 : Pillar connecting portion 73 : Channel region 74 : P-type pillar 75 : N-type pillar 76A : pn junction portion 76B : pn junction portion 77 : Extension portion 78 : Pillar connecting portion 80 : First mask 81 : First opening 82 : Second mask 83 : Second opening 84 : Second stacked portion 85 : End portion 86 : End portionC1: 1st concentration area C2: 2nd concentration area C3: 3rd concentration area C4: 4th concentration area C5: 5th concentration area

Claims

a first region of a first conductivity type formed in a surface layer portion of the first main surface of the SiC chip; a plurality of second regions of a second conductivity type formed in a surface layer portion of the first region, the second regions providing a plurality of unit cells in the SiC chip; a third region of the first conductivity type formed in a surface layer portion of the second region in each of the unit cells; a planar gate structure facing a channel region in the second region of each of the unit cells and controlling channel conduction between the first region and the third region; a plurality of first pillar regions of a second conductivity type connected to the second region of a common unit cell, extending in a depth direction of the SiC chip from the first main surface toward the second main surface, and being physically separated and independent from each other; and a second pillar region of the first conductivity type adjacent to the first pillar region within the SiC chip and extending in the depth direction.

2. The semiconductor device according to claim 1, wherein the second regions are arranged in a striped pattern, and the first pillar regions are arranged at intervals in a direction intersecting the direction in which the second regions extend.

3. The semiconductor device according to claim 2, wherein the plurality of first pillar regions extend side by side in the extension direction and are arranged in a stripe pattern.

4. The semiconductor device according to claim 2 or 3, wherein the first pillar regions and the second pillar regions are alternately arranged in the intersecting direction within a region below the second region of each of the unit cells.

5. The semiconductor device according to any one of claims 1 to 4, wherein the pitch between the first pillar regions is narrower than the pitch between the unit cells.

6. The semiconductor device according to claim 5, wherein the pitch between the plurality of unit cells is 3 μm or more and 6 μm or less, and the pitch between the plurality of first pillar regions is 0.5 μm or more and 2 μm or less.

7. The semiconductor device according to any one of claims 1 to 6, wherein the second pillar region includes a first portion extending in the depth direction from a region in the first region that is sandwiched between the plurality of unit cells, and a second portion that is sandwiched between the plurality of first pillar regions in a region below the second region of each of the unit cells, and the first portion of the second pillar region includes a first concentration portion that has a relatively higher impurity concentration than the second portion of the second pillar region.

8. The semiconductor device described in claim 7, wherein the first concentration portion is a pillar adjacent portion arranged adjacent to the first pillar region in the horizontal direction along the first main surface, and the first portion of the second pillar region is a cell adjacent portion arranged in a region sandwiched between the plurality of unit cells in the horizontal direction, and further includes a second concentration portion having an impurity concentration lower than that of the pillar adjacent portion.

9. The semiconductor device according to claim 8, wherein the impurity concentration of the second concentration portion is higher than the impurity concentration of the second portion of the second pillar region.

10. The impurity concentration of the first concentration portion is 1×10 １７ cm －３ 1x10 or more １９ cm －３ the impurity concentration of the second concentration portion is 5×10 or less １６ cm －３ 1x10 or more １７ cm －３ the impurity concentration of the second portion of the second pillar region is 1×10 １６ cm －３ 1x10 or more １７ cm －３ 10. The semiconductor device according to claim 8, wherein:

11. The semiconductor device according to any one of claims 8 to 10, wherein the SiC chip includes a substrate and an epitaxial layer formed on the substrate to provide the first pillar region and the second pillar region, and the first portion of the second pillar region further includes a third concentration portion that is disposed on the substrate side with respect to the pillar-adjacent portion and has an impurity concentration lower than that of the cell-adjacent portion.

12. A semiconductor device according to any one of claims 7 to 11, wherein the first concentration portion is concentration-adjusted with phosphorus (P), and the second portion of the second pillar region does not contain phosphorus (P) and is concentration-adjusted with nitrogen (N).

13. The semiconductor device according to any one of claims 2 to 4, wherein the plurality of first pillar regions are arranged in a region that is more inward than the outer edge of each of the second regions in the intersecting direction.

14. The semiconductor device according to any one of claims 1 to 13, wherein the plurality of first pillar regions face the third region across the common second region.

15. The semiconductor device according to any one of claims 1 to 14, further comprising a fourth region of the second conductivity type connected from the first main surface to the second region via the third region and having a higher impurity concentration than the second region, wherein the plurality of first pillar regions face the fourth region across the common second region.

16. The semiconductor device described in claim 1, wherein the second regions are arranged in a stripe pattern, the first pillar regions are spaced apart in a direction intersecting the extension direction of the second regions, and extend parallel to one another along the extension direction in a stripe pattern, and the first region below the second region of each unit cell is divided by the first pillar regions to provide the second pillar regions.

17. The semiconductor device according to claim 16, wherein a first pitch between the plurality of first pillar regions and a second pitch between the plurality of second pillar regions are equal.

18. The semiconductor device according to claim 17, wherein the first pitch and the second pitch are narrower than the pitch of the plurality of unit cells and are not less than 0.5 μm and not more than 2 μm.

19. The semiconductor device according to any one of claims 16 to 18, wherein the first width of the plurality of first pillar regions is equal to the second width of the plurality of second pillar regions.

20. A semiconductor device according to any one of claims 16 to 19, wherein the first pillar regions at both ends in the intersecting direction among the plurality of first pillar regions have pillar sides that extend continuously in the depth direction from the sides of the second region.

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