Display panel and display device

Abstract

A display panel and a display device, relating to the technical field of display. The display panel comprises a display area and a plurality of frame areas surrounding the display area; and the plurality of frame areas include a first frame area, a second frame area, a third frame area and a fourth frame area. The display panel further comprises a GOA circuit in the frame areas; the GOA circuit comprises a plurality of first GOA units and a plurality of second GOA units; the plurality of first GOA units are arranged in the first frame area and the second frame area; and the plurality of second GOA units are arranged in the third frame area. The display panel comprises a plurality of rows of pixel units in the display area; and in a first direction, at least one second GOA unit among the plurality of second GOA units is located on the side of a first row of pixel units among the plurality of rows of pixel units away from the fourth frame area. The display panel and the display device provided in embodiments of the present application can keep a high resolution and reduce the frame size of the display panel, thereby improving user experience.

Description

Display panel and display device Technical Field

[0001] The embodiments of the present application relate to the field of display technology, and more specifically, to a display panel and a display device. Background Art

[0002] As display product resolution continues to increase, higher requirements are placed on the overall driving capabilities of these products. Especially for current full-HD display products, this increase in resolution requires the gate drive array (GOA) circuits of these products to have corresponding driving capabilities. However, this also requires an increase in the area (border area) where the GOA circuits are located. This increases the size of the display product's borders, impacting the user experience.

[0003] Summary of the Invention

[0004] The embodiments of the present application provide a display panel and a display device, aiming to reduce the frame size of the display panel while maintaining high resolution, thereby improving the user experience.

[0005] According to a first aspect of an embodiment of the present application, a display panel is provided, comprising:

[0006] a display area and a plurality of frame areas surrounding the display area, the plurality of frame areas including a first frame area, a second frame area, a third frame area, and a fourth frame area, the first frame area and the second frame area being arranged opposite to each other along a first direction, and the third frame area and the fourth frame area being arranged opposite to each other along a second direction;

[0007] The display panel further includes a GOA circuit in the frame area;

[0008] The GOA circuit includes a plurality of first GOA units and a plurality of second GOA units, wherein the plurality of first GOA units are arranged in the first border area and the second border area, and the plurality of second GOA units are arranged in the third border area;

[0009] The display panel includes a plurality of rows of pixel units in the display area;

[0010] In the first direction, at least one of the plurality of second GOA units is located on a side of a first row of pixel units in the plurality of rows of pixel units away from the fourth border area;

[0011] The first direction and the second direction are perpendicular to each other.

[0012] Optionally, a size of the second GOA unit in the first direction is different from a size of the first GOA unit in the first direction, and a size of the second GOA unit in the second direction is different from a size of the first GOA unit in the second direction.

[0013] Optionally, a size of the second GOA unit in the first direction is larger than a size of the first GOA unit in the first direction, and a size of the second GOA unit in the second direction is smaller than a size of the first GOA unit in the second direction.

[0014] Optionally, the output line of the second GOA unit is located between the second GOA unit and the display area.

[0015] Optionally, the third border area includes a first area, a second area, and a third area arranged along the second direction, and the second area is located between the first area and the third area;

[0016] A plurality of the second GOA units are located in the first region and the third region.

[0017] Optionally, the second area includes an ambient light detection area and a common electrode bus, and the common electrode bus is arranged on a side of the ambient light detection area away from the display area.

[0018] Optionally, the second area includes an ambient light detection area and an electrostatic release unit, and the electrostatic release unit is arranged on a side of the ambient light detection area close to the display area.

[0019] Optionally, the display panel includes in the ambient light detection area:

[0020] substrate;

[0021] a device layer, disposed on the substrate, the device layer comprising an ambient light sensor;

[0022] a liquid crystal layer, disposed on a side of the device layer facing away from the substrate;

[0023] a black matrix layer, disposed on a side of the liquid crystal layer away from the device layer, the black matrix layer being provided with a plurality of filling grooves, the filling grooves being filled with a color resist material;

[0024] a color filter substrate, disposed on a side of the black matrix layer facing away from the liquid crystal layer;

[0025] The orthographic projection of the color resist material on the base substrate at least partially overlaps with the orthographic projection of the ambient light sensor on the base substrate.

[0026] Optionally, the color resist material includes: a plurality of color resists of different colors, and the color resists of different colors are respectively located in different filling grooves;

[0027] The ambient light sensor includes: a plurality of sensor units, and orthographic projections of different sensor units on the base substrate overlap with orthographic projections of color resists of different colors on the base substrate.

[0028] Optionally, the ambient light sensor further includes a control circuit, and the plurality of sensor units are connected to the same control circuit.

[0029] Optionally, the ambient light sensor further includes multiple groups of control circuits, the multiple sensor units are divided into multiple sensor unit groups, the sensor unit groups include at least one sensor unit, and different sensor unit groups are connected to different control circuits.

[0030] Optionally, the ambient light sensor includes a transistor, and the control circuit includes a gate signal line, a source signal line, and a drain signal line;

[0031] The gate of the transistor is connected to the gate signal line, the source of the transistor is connected to the source signal line, and the drain of the transistor is connected to the drain signal line.

[0032] Optionally, a plurality of the sensor units are evenly spaced and arranged along the second direction.

[0033] Optionally, the device layer further includes a redundant gate line, and the redundant gate line is arranged on a side of the electrostatic release unit electrode close to the display area.

[0034] Optionally, part of the second GOA units are located between a first row of pixel units in the multiple rows of pixel units and an outer edge of the third border area.

[0035] Optionally, the GOA circuit further includes a plurality of third GOA units, wherein the plurality of third GOA units are located at corners of the third border area, and the plurality of third GOA units are adjacent to both the first GOA unit and the second GOA unit.

[0036] The size of the third GOA unit in the first direction is different from the size of the first GOA unit in the first direction, and the size of the third GOA unit in the second direction is different from the size of the first GOA unit in the second direction.

[0037] Optionally, the size of the third GOA unit in the first direction is larger than the size of the first GOA unit in the first direction, and the size of the third GOA unit in the second direction is smaller than the size of the first GOA unit in the second direction.

[0038] Optionally, the display panel includes in the fourth border area:

[0039] A binding terminal connected to the GOA circuit.

[0040] A second aspect of the embodiments of the present application provides a display device, comprising the display panel provided in the first aspect of the embodiments of the present application.

[0041] Optionally, the display device includes:

[0042] A flexible circuit board is bound and connected to the binding terminals of the display panel. Beneficial effects:

[0043] The present application provides a display panel and a display device, which are provided with a display area and multiple frame areas surrounding the display area, wherein the multiple frame areas include a first frame area, a second frame area, a third frame area and a fourth frame area, the first frame area and the second frame area are arranged relative to each other along a first direction, and the third frame area and the fourth frame area are arranged relative to each other along a second direction. The display panel also includes a GOA circuit, the GOA circuit includes multiple first GOA units and multiple second GOA units, the multiple first GOA units are located in the first frame area and the second frame area, the multiple second GOA units are located in the third frame area, and at least one second GOA unit of the multiple second GOA units is located on a side of a first row of pixel units in multiple rows of pixel units away from the fourth frame area; in this way, by placing some GOA units in the GOA circuit in the third frame area, the number of GOA units can be increased without increasing or reducing the area of ​​the first frame area and the second frame area, so that the GOA circuit can drive the display product to achieve high resolution, thereby achieving a narrow frame of the high-resolution display product and improving the user experience.

[0044] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0046] FIG1 is a schematic diagram of a planar structure of a display panel proposed in an embodiment of the present application;

[0047] FIG2 is a schematic structural diagram of the CC' section in FIG1;

[0048] FIG3 is a schematic structural diagram of a first GOA unit in a display panel according to an embodiment of the present application;

[0049] FIG4 is a schematic structural diagram of a second GOA unit in a display panel according to an embodiment of the present application;

[0050] FIG5 is a schematic diagram of a partial planar structure of a display panel with rounded corners according to an embodiment of the present application;

[0051] FIG6 is a schematic structural diagram of a third GOA unit in a display panel according to an embodiment of the present application;

[0052] FIG7 is a schematic diagram of a cascade structure of a first GOA unit (lower) and a third GOA unit (upper) in a display panel proposed in one embodiment of the present application;

[0053] FIG8 is a schematic diagram of a partial structure of a device in a third border area of ​​a display panel according to an embodiment of the present application;

[0054] FIG9 is a schematic structural diagram of a sensor unit of an ambient light sensor in a display panel according to an embodiment of the present application;

[0055] FIG10 is a schematic structural diagram of a second region in a display panel according to an embodiment of the present application;

[0056] FIG11 is a schematic structural diagram of the DD' section in FIG1;

[0057] FIG12 is a schematic structural diagram of a display panel in which multiple sensor units are connected to the same control circuit according to an embodiment of the present application;

[0058] FIG13 is a schematic structural diagram of a display panel in which multiple sensor unit groups are connected to different control circuits according to an embodiment of the present application;

[0059] FIG14 is a schematic structural diagram of a first sensor unit group in a display panel according to an embodiment of the present application;

[0060] FIG. 15 is a flow chart of steps of a method for manufacturing a display panel according to an embodiment of the present application.

[0061] Explanation of reference numerals: 10, base substrate; 11, driving circuit layer; 12, light-emitting layer; 20, device layer; 21, ambient light sensor; 211, sensor unit; 2110, first sensor unit group; 2111, first sensor unit; 2112, second sensor unit; 2113, third sensor unit; 2114, fourth sensor unit; 212, control circuit; 2121, first control circuit; 2122, second control circuit; 22, common electrode bus; 23, electrostatic discharge unit; 24, redundant gate line; 30, liquid crystal layer; 40, black matrix layer; 401, filling groove; 402, pixel color resistance; 50, color filter substrate; 61, first GOA unit; 611, first input signal line; 61 2. First transistor; 613. First cascade line; 62. Second GOA unit; 621. Output line; 622. Second input signal line; 623. Second transistor; 624. Second cascade line; 63. Third GOA unit; 631. Third input signal line; 632. Third transistor; 633. Third cascade line; 80. Sealing layer; 90. First row pixel unit; 91. Binding terminal; A. Display area; B1. First border area; B2. Second border area; B3. Third border area; B31. First area; B32. Second area; B321. Ambient light detection area; B33. Third area; B4. Fourth border area; X, first direction; Y, second direction; D1 / D2, drain; G, gate; S, source. Specific embodiments

[0062] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0063] In the related art, the GOA circuit is usually located on the left and right sides of the display area of ​​the display panel, which can also be understood as the left and right border areas of the display panel. When the resolution of the display panel is improved, the pixel density in the corresponding display panel will also increase. Therefore, the number of drive rows of the GOA circuit and the panel load will increase accordingly. This not only compresses the output line space of a single GOA unit, but also increases the output capacity of the GOA circuit. The impact is the lateral widening of the GOA circuit, which leads to an increase in the width of the left and right borders of the display panel. In addition, for the lower border, the increase in the number of drive columns will increase the number of signal line routings, and the required wiring space and the number of electrostatic release units will increase significantly, which will also affect the size of the lower border.

[0064] In view of this, an embodiment of the present application proposes a display panel and a display device, which provide a display area and multiple border areas surrounding the display area, wherein the multiple border areas include a first border area, a second border area, a third border area and a fourth border area, the first border area and the second border area are arranged relative to each other along a first direction, and the third border area and the fourth border area are arranged relative to each other along a second direction. The display panel also includes a GOA circuit, the GOA circuit includes multiple first GOA units and multiple second GOA units, the multiple first GOA units are located in the first border area and the second border area, the multiple second GOA units are located in the third border area, and at least one second GOA unit of the multiple second GOA units is located on the side of the first row of pixel units in the multiple rows of pixel units away from the fourth border area; in this way, by placing some of the GOA units in the GOA circuit in the third border area, the number of GOA units can be increased without increasing or reducing the area of ​​the first border area and the second border area, so that the GOA circuit can drive the realization of high resolution of the display product, thereby realizing a narrow border of the high-resolution display product and improving the user experience.

[0065] 1 , a display panel according to an embodiment of the present application is shown. The display panel includes a display area A and a plurality of frame areas surrounding the display area A.

[0066] Specifically, display area A is the area where the display panel emits light; that is, image content can be displayed within display area A. As shown in Figure 2 , the display panel in display area A may include a base substrate 10, a drive circuit layer 11, a light-emitting layer 12, and the like disposed on base substrate 10. Base substrate 10 may be made of either a rigid or flexible material. If the display panel requires rigidity, base substrate 10 may be made of a rigid material, such as glass. If the display panel requires foldability or bendability, base substrate 10 may be made of a flexible material, such as polyimide.

[0067] The driving circuit layer 11 may include a thin film transistor, which may include an active layer, a gate insulating layer, a gate, an interlayer dielectric layer, a source electrode, and a drain electrode, etc., stacked on the base substrate 10; wherein the gate insulating layer is formed on the side of the active layer facing away from the base substrate 10, the gate is formed on the side of the gate insulating layer facing away from the active layer, the interlayer dielectric layer is formed on the side of the gate away from the gate insulating layer, and the source and drain electrodes are formed on the side of the interlayer dielectric layer away from the gate, and the source and drain electrodes are connected to the active layer through vias penetrating the interlayer dielectric layer and the gate insulating layer. It is understood that the thin film transistor may have a top-gate structure or a bottom-gate structure.

[0068] The light-emitting layer 12 has different structures depending on the type of display panel. For example, the display panel may include an OLED (Organic Electroluminescence Display) or a QLED (Quantum Dot Light Emitting Diode) display panel. When the display panel is an OLED display panel, the light-emitting layer 12 may include all or part of a hole injection layer, a hole transport layer, an electron blocking layer, a luminescent material layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0069] As shown in Figure 1, in the embodiment of the present application, the multiple border areas include a first border area B1, a second border area B2, a third border area B3 and a fourth border area B4. The first border area B1 and the second border area B2 are arranged relative to each other along the first direction X, and the third border area B3 and the fourth border area B4 are arranged relative to each other along the second direction Y. It can be understood that in the embodiment of the present application, the overall shape of the display panel is roughly rectangular, wherein the first direction X is the length direction of the display panel, and the second direction Y is the width direction of the display panel. Therefore, the first border area B1 and the second border area B2 can also be understood as the left border area and the right border area of ​​the display panel, respectively, and the third border area B3 and the fourth border area B4 can also be understood as the upper border area and the lower border area of ​​the display panel, respectively.

[0070] As shown in Figure 1, the display panel also includes a GOA circuit in the border area. The GOA circuit includes multiple first GOA units 61 and multiple second GOA units 62. The multiple first GOA units 61 are arranged in the first border area B1 and the second border area B2, and the multiple second GOA units 62 are arranged in the third border area B3.

[0071] Specifically, a plurality of first GOA units 61 are in a cascade relationship, a plurality of second GOA units 62 are in a cascade relationship, and adjacent first GOA units 61 and second GOA units 62 are in a cascade relationship. For example, among the plurality of first GOA units 61, the first GOA units 61 in the previous row can be cascade-connected to the first GOA units 61 in the next row; and among the plurality of second GOA units 62, the second GOA units 62 in the previous row can be cascade-connected to the second GOA units 62 in the next row.

[0072] It can be understood that in the embodiment of the present application, the general structure of the first GOA unit 61 and the second GOA unit 62 are the same. For example, the effective circuit schematics of the first GOA unit 61 and the second GOA unit 62 are the same.

[0073] In addition, in some embodiments, the second GOA unit 62 may also include at least one dummy GOA unit, which is not directly connected to the gate line of the display panel.

[0074] As shown in Figure 1, at the same time, in the embodiment of the present application, the size of the second GOA unit 62 in the first direction X is different from the size of the first GOA unit 61 in the first direction X, and the size of the second GOA unit 62 in the second direction Y is different from the size of the first GOA unit 61 in the second direction Y.

[0075] Specifically, with reference to Figure 3, taking the first GOA unit 61 in the first border area B1 as an example, the first GOA unit 61 includes a first transistor 612 and signal lines located on both sides of the first transistor 612 in the second direction Y, and the signal lines on both sides extend along the first direction X. Among them, the signal line located on the left side of the first transistor 612 may include the first input signal lines 611 such as CLK, STV, and GCH, and the signal line located on the right side of the first transistor 612 is the first cascade line 613 of the first GOA unit 61. The size of the first GOA unit 61 in the first direction X is also the size of the first transistor 612 in the first direction X. The size of the first GOA unit 61 in the second direction Y is the boundary line of the signal line farthest from the display area A in the first input signal line 611, and the boundary line of the cascade line 613 closest to the display area A in the first cascade line, and the straight-line distance between the two boundary lines.

[0076] For the first GOA unit 61 located in the second border area B2, the signal lines on the right side of the first transistor 612 may include the first input signal lines 611 such as CLK, STV, and GCH, and the signal line on the left side of the first transistor 612 is the first cascade line 613 of the first GOA unit 61.

[0077] 4 , the second GOA unit 62 includes a second transistor 623 and signal lines located around the second transistor 623, wherein the signal lines located on the upper side of the second transistor 623 may include second input signal lines 622 such as CLK, STV, and GCH, and the signal lines located on the left, right, and bottom of the second transistor 623 are second cascade lines 624 of the second GOA unit 62. The size of the second GOA unit 62 in the first direction X is the straight-line distance between the boundary line of the cascade line closest to the display area A in the second cascade lines 624 located below the second transistor 623 and the boundary line of the signal line farthest from the display area A in the second input signal lines 622 located above the second transistor 623; the size of the second GOA unit 62 in the second direction Y is the distance between the boundary line of the cascade line farthest from the second transistor 623 in the second cascade lines 624 located on the left side of the second transistor 62 and the boundary line of the cascade line farthest from the second transistor 623 in the second cascade lines 624 on the right side of the second transistor 623. It should be noted that the second cascade line 624 has a bent portion in the first direction X. For the second cascade line 624 with a bent portion, the cascade line farthest from the second transistor is also the cascade line with the largest relative distance from the second transistor.

[0078] It can be understood that the size of the first GOA unit 61 and the second GOA unit 62 in the first direction X is also the size of the area occupied by a single first GOA unit (including the first transistor 612 and the signal line around the first transistor 612) 61 and a single second GOA unit 62 (including the second transistor 623 and the signal line around the second transistor 623) on the display panel in the first direction X, and the size of the first GOA unit 61 and the second GOA unit 62 in the second direction Y is also the size of the area occupied by a single first GOA unit 61 and a single second GOA unit 62 on the display panel in the second direction Y. Therefore, the sizes of the first GOA unit 61 and the second GOA unit 62 in the first direction X and the second direction Y can be understood as the length and width of the area, respectively.

[0079] It can be understood that in order to make part of the GOA unit located in the third border area B3, in the embodiment of the present application, it is necessary to adjust the size of this part of the GOA unit (i.e., the second GOA unit 62), so this part of the GOA unit has a certain difference in size from the original part of the GOA unit (i.e., the first GOA unit 61).

[0080] 3 and 4 , for example, in an embodiment of the present application, the size of the second GOA unit 62 in the first direction X is larger than the size of the first GOA unit 61 in the first direction X, and the size of the second GOA unit 62 in the second direction Y is smaller than the size of the first GOA unit 61 in the second direction Y, that is, the length of the second GOA unit 62 is increased relative to the length of the first GOA unit 61, and the width of the second GOA unit 62 is reduced relative to the width of the first GOA unit 61. In this way, the second GOA unit 62 can be arranged in the third border area B3 (the size of the third border area B3 in the first direction X is relatively sufficient, so the length of the second GOA unit 62 can be made relatively longer).

[0081] The size of the second GOA unit 62 in the first direction X is greater than or equal to 390 μm and less than or equal to 410 μm. For example, the size of the second GOA unit 62 in the first direction X can be 390 μm, 395 μm, 400 μm, 405 μm, 410 μm, etc., and those skilled in the art can set it according to actual needs.

[0082] The size of the second GOA unit 62 in the second direction Y is greater than or equal to 505 μm and less than or equal to 525 μm. For example, the size of the second GOA unit 62 in the first direction X can be 505 μm, 510 μm, 515 μm, 520 μm, 525 μm, etc., and those skilled in the art can set it according to actual needs.

[0083] Through the display panel provided in the embodiment of the present application, some GOA units in the GOA circuit are placed in the third border area B3, so that the number of GOA units can be increased without increasing or decreasing the areas of the first border area B1 and the second border area B2, so that the GOA circuit can drive the display product to achieve high resolution, thereby realizing a narrow border of a high-resolution display product and improving the user experience.

[0084] With reference to Figure 8, in addition, it should be noted that, since the second GOA unit 62 is placed in the third frame area B3, there is no one-to-one correspondence between the GOA unit and the pixel unit of the display panel. In other words, the GOA unit corresponding to the pixel unit of the first row is not in the position corresponding to the first row pixel unit, but is located on the upper side of the first row pixel unit, that is, at least one second GOA unit 62 in a plurality of second GOA units 62 is located on the side of the first row pixel unit 90 away from the fourth frame area B4. Wherein, the first row pixel unit 90 refers to a row of pixel units adjacent to the third frame area B3 in the multi-row pixel units (arranged along the first direction X and extended along the second direction Y) included in the display panel, and the first row pixel unit 90 is a row of pixel units that can be effectively displayed. For this reason, the length of the output line 621 of the second GOA unit 62 needs to be adaptively increased. In the embodiment of the present application, the output line 621 of the second GOA unit 62 is located between the second GOA unit 62 and the display area A, and the output line 621 extends along the second direction Y, and most of the output line 621 is located in the third frame area B3. At the same time, in some embodiments, the output line length of the first GOA unit 61 can also be adaptively increased, so that the lengths of the output lines connecting multiple GOA units and corresponding pixel units can be roughly the same, avoiding the influence of RC delay on the gate line transmission signal.

[0085] In the embodiment of the present application, in the first direction X, at least a portion of the second GOA unit 62 is located between the first row of pixel units 90 of the display panel and the outer edge of the third border area B3.

[0086] 5 , in one embodiment, due to the setting of the curved corners (R corners) at the corners of the display panel, the size of the GOA units at the corners within the third frame area B3 is also changed to a certain extent.

[0087] Specifically, the GOA circuit further includes a third GOA unit 63, which is located at a corner position within the third border area B3 and is adjacent to the first GOA unit 61 and the second GOA unit 62. The size of the third GOA unit 63 in the first direction X is different from the size of the first GOA unit in the first direction X, and the size of the third GOA unit 63 in the second direction Y is also different from the size of the first GOA unit in the second direction Y.

[0088] 6 , taking the third GOA unit 63 in the same column as the first border area B1 as an example, the third GOA unit 63 includes a third transistor 632 and a signal line located on both sides of the third transistor 632 in the second direction, and the signal lines on both sides extend along the first direction X. Among them, the signal line located on the left side of the third transistor 632 may include third input signal lines 631 such as CLK, STV, and GCH, and the signal line located on the right side of the third transistor 632 is the third cascade line 633 of the third GOA unit 63. The size of the third GOA unit 63 in the first direction X is also the size of the third transistor 632 in the first direction X. The size of the third GOA unit 63 in the second direction Y is the boundary line of the signal line farthest from the display area A in the third input signal line 631, and the boundary line of the cascade line closest to the display area A in the third cascade line 633, and the straight-line distance between the two boundary lines.

[0089] For example, referring to Figures 3 and 6, the size of the third GOA unit 63 in the first direction X is larger than the size of the first GOA unit in the first direction X, and the size of the third GOA unit 63 in the second direction Y is smaller than the size of the first GOA unit in the second direction Y. That is, the length of the third GOA unit 63 is increased relative to the length of the first GOA unit 61, and the width of the third GOA unit 63 is reduced relative to the width of the first GOA unit 61.

[0090] Figure 7 shows a partial structure of the GOA circuit in the first border area B1 of the display panel entering the corner position. It can also be seen from Figure 7 that the size of the first GOA unit 61 in the first border area B1 or the second border area B2 of the display panel in the first direction X is smaller than the size of the third GOA unit 63 in the corner position in the first direction X, and the size of the first GOA unit 61 in the second direction Y is larger than the size of the third GOA unit 63 in the second direction Y.

[0091] In the third border area B3 , in addition to the second GOA unit 62 , other devices, such as the common electrode bus 22 , need to be placed.

[0092] Specifically, as shown in Figure 1, in an embodiment of the present application, the third border area B3 includes a first area B31, a second area B32 and a third area B33 arranged along the second direction Y, and the second area B32 is located between the first area B31 and the third area B33. Among them, a plurality of second GOA units 62 are located in the first area B31 and the third area B33. It can be understood that the first area B31, the second area B32 and the third area B33 are all virtual areas. Since most of the GOA circuits are located in the first border area B1 and the second border area B2, and different GOA units adopt a cascade design, the second GOA unit 62 arranged upwards will naturally be closer to the first border area B1 and the second border area B2, that is, located in the first area B31 and the third area B33.

[0093] 10 , other devices can be placed in the second area B32 . In the embodiment of the present application, the second area B32 includes an ambient light detection area B321 , a common electrode bus 22 , an electrostatic discharge unit 23 , and redundant gate lines 24 .

[0094] Specifically, the common electrode bus 22 is arranged on the side of the ambient light detection area B321 away from the display area A, the electrostatic release unit 23 is arranged on the side of the ambient light detection area B321 close to the display area A, and the redundant gate line 24 is arranged on the side of the electrostatic release unit 23 close to the display area A. As shown in Figure 8, the common electrode bus 22 has different positions and width designs in different areas. For example, on the side of the second GOA unit 62 close to the display area A, the width of the common electrode bus 22 is relatively narrow (linear); on the side of the ambient light detection area B321 away from the sensor unit 211, the width of the common electrode bus 22 is relatively wide (grid-shaped).

[0095] In practical applications, the redundant gate lines 24 can be formed by adding several rows of gate lines at the beginning and end of the display area A of the display panel, and connecting these gate lines to some of the second GOA units. It can be understood that these gate lines are not connected to valid pixel units, and some of the second GOA units connected to these gate lines are not connected to valid pixel units. These second GOA units serve as the first few GOA units cascaded in the GOA circuit.

[0096] In related art, the electrostatic discharge unit 23 is generally placed in the fourth border area B4. Due to the increase in the number of wiring in the high-resolution display panel, if the electrostatic discharge unit 23 is placed in the fourth border area B4, the size of the fourth border area B4 will also increase accordingly.

[0097] To this end, the embodiment of the present application adjusts the width and / or position of part of the common electrode bus 22, thereby forming redundant wiring space in the third border area B3, and places part of the GOA unit (the second GOA unit 62) and the electrostatic release unit 23 in these spaces, so that the size of the fourth border area B4 can also remain unchanged or decrease, thereby achieving a narrow border of a high-resolution display panel and improving the user experience.

[0098] Therefore, in the display panel of the embodiment of the present application, the second region B32 of the third border area B3 includes the common electrode bus 22 , the electrostatic discharge unit 23 and the redundant gate line 24 .

[0099] The size of the electrostatic discharge unit 23 in the first direction X is greater than or equal to 85 μm and less than or equal to 95 μm. For example, the size of the electrostatic discharge unit 23 in the first direction X can be 85 μm, 87 μm, 90 μm, 92 μm, 95 μm, etc., and those skilled in the art can set it according to actual needs.

[0100] The redundant gate line 24 has a size greater than or equal to 45 μm and less than or equal to 55 μm in the first direction X. For example, the electrostatic discharge unit 23 may have a size of 45 μm, 47 μm, 50 μm, 52 μm, 55 μm, etc. in the first direction X, and those skilled in the art may set the size according to actual needs.

[0101] 10 and 11 , to enhance the functionality of the display panel, in this embodiment, the second region B32 further includes an ambient light detection region B321. The display panel includes a stacked base substrate 10, a device layer 20, a liquid crystal layer 30, a black matrix layer 40, and a color filter substrate 50 in the ambient light detection region B321.

[0102] Specifically, the base substrate 10 is the same base substrate 10 as the base substrate 10 within the display area A. A device layer 20 is disposed on the base substrate 10, and the device layer 20 includes an ambient light sensor 21. A liquid crystal layer 30 is disposed on the side of the device layer 20 facing away from the base substrate 10. A black matrix layer 40 is disposed on the side of the liquid crystal layer 30 facing away from the device layer 20. A color filter substrate 50 is disposed on the side of the black matrix layer 40 facing away from the liquid crystal layer 30. It will be appreciated that a sealing layer 80 is also disposed between the base substrate 10 and the color filter substrate 50. The sealing layer 80 encloses the device layer 20, the liquid crystal layer 30, and the black matrix layer 40, thereby achieving a sealed display panel.

[0103] As shown in Figure 11 , a plurality of filling slots 401 are defined in the black matrix layer 40, each of which is filled with a color resist material 402. Furthermore, the orthographic projection of the color resist material 402 on the base substrate 10 at least partially overlaps with the orthographic projection of the ambient light sensor 21 on the base substrate 10. Utilizing the ambient light sensor 21 and the color resist material 402 allows the display panel to perform color temperature compensation based on different ambient light sensing requirements, thereby achieving adjustable color temperature for the display panel.

[0104] In an embodiment of the present application, the color resist material 402 includes a plurality of color resists of different colors. For example, the color resist material 402 may include red color resist, blue color resist, green color resist, white color resist, and the like. Moreover, the color resists of different colors are respectively located in different filling grooves 401. That is to say, the color resist material 402 of the embodiment of the present application is not arranged in the ambient light detection area B321 in the manner of a plurality of pixel arrays, but is independently arranged in the ambient light detection area B321, that is, the color resist material 402 of a single color is located in one filling groove 401. It should be noted that the color resist material 402 can be made of the same layer and material as the pixel color resist in the display area A of the display panel, or the color resist material 402 can also be made of a different layer from the pixel color resist in the display area A of the display panel.

[0105] At the same time, the ambient light sensor 21 includes multiple sensor units 211, and the orthographic projections of different sensor units 211 on the base substrate 10 overlap with the orthographic projections of different color resists on the base substrate 10. In this way, different sensor units 211 can be used to achieve independent control of different color resists. In this embodiment of the present application, the multiple sensor units 211 are evenly spaced along the second direction Y, that is, the distance between any two sensor units 211 is the same.

[0106] 12 , in one embodiment, the ambient light sensor 21 further includes a control circuit 212 , and the plurality of sensor units 211 are connected to the same control circuit 212 .

[0107] Specifically, as shown in FIG9 , the sensor unit 211 may include at least one transistor having a gate G, a source S, and a drain D. The control circuit 212 includes a gate signal line, a source signal line, and a drain signal line, wherein the gate signal line is connected to the gate G of the transistor, the source signal line is connected to the source S of the transistor, and the drain signal line is connected to the drain D of the transistor. Furthermore, the gate G, source S, and drain D of the transistor of each sensor unit 211 are respectively connected to the gate signal line, source signal line, and drain signal line in the control circuit 212. The control circuit 212 is connected to the control chip of the display panel via wiring, so that the sensing signal generated by the sensor unit 211 can be transmitted to the control chip, and the color temperature compensation of the display panel can be achieved based on the sensing signal.

[0108] 13 and 14 , in one embodiment, the ambient light sensor 21 further includes multiple groups of control circuits 212 , and multiple sensor units 211 are divided into multiple sensor unit groups, and each sensor unit group includes at least one sensor unit 211 , and different sensor unit groups are connected to different control circuits 212 .

[0109] Exemplarily, the multiple sensor units 211 include a first sensor unit 2111, a second sensor unit 2112, a third sensor unit 2113 and a fourth sensor unit 2114, wherein the first sensor unit 2111 and the second sensor unit 2112 are divided into a first sensor unit group 2110, and the third sensor unit 2113 and the fourth sensor unit 2114 are divided into a second sensor unit group. At the same time, the ambient light sensor 21 includes a first control circuit 2121 and a second control circuit 2122, the first sensor unit group 2110 is connected to the first control circuit 2121, and the second sensor unit group is connected to the second control circuit 2122.

[0110] In addition, each sensor unit 211 may include at least one transistor having a gate, a source and a drain, and each control circuit 212 includes a gate signal line, a source signal line and a drain signal line, wherein the gate signal line is connected to the gate of the transistor, the source signal line is connected to the source of the transistor, and the drain signal line is connected to the drain of the transistor.

[0111] The gates, sources, and drains of the transistors in the first sensor unit 2111 and the second sensor unit 2112 are connected to the gate signal line, source signal line, and drain signal line, respectively, in the first control circuit 2121. The gates, sources, and drains of the transistors in the third sensor unit 2113 and the fourth sensor unit 2114 are connected to the gate signal line, source signal line, and drain signal line, respectively, in the second control circuit 2122. By using independent control circuits 212 to control different groups of sensor units, the stability of the sensor units 211 can be improved, which helps to enhance the accuracy of ambient light sensing.

[0112] As shown in Figure 13, the first sensor unit group 2110 includes a first sensor unit 2111 and a second sensor unit 2112. It can be seen that the gate G of the transistors in the first sensor unit 2111 and the second sensor unit 2112 are connected to the source S. Similarly, the gate and source of the transistors in the third sensor unit 2113 and the fourth sensor unit 2114 included in the second sensor unit group are connected. However, the first sensor unit group 2110 and the second sensor unit group are controlled independently.

[0113] As shown in Figure 1, the fourth frame area B4 of the display panel includes a binding terminal 91, which is connected to the GOA circuit through a wiring to transmit the sensing signal to the flexible circuit board connected to the binding terminal 91, and then to the control chip of the display panel.

[0114] FIG15 is a flowchart showing the steps of a method for manufacturing a display panel. Referring to FIG15 , an embodiment of the present application discloses a method for manufacturing a display panel, the method comprising:

[0115] Step S01: providing a base substrate 10 .

[0116] Specifically, the base substrate 10 can be a rigid material or a flexible material. When the display panel has rigidity requirements, the base substrate 10 can be made of a rigid material, such as glass, etc.; when the display panel has foldable or bendable requirements, the base substrate 10 can be made of a flexible material, such as polyimide, etc.

[0117] Step S02 : forming a driving circuit layer 11 and a light emitting layer 12 at a position corresponding to the display area A on the base substrate 10 , and forming a GOA circuit at a position corresponding to the frame area on the base substrate 10 .

[0118] Specifically, the driving circuit layer 11 may include a thin film transistor, which may include an active layer, a gate insulating layer, a gate, an interlayer dielectric layer, a source electrode, and a drain electrode, etc., stacked on the base substrate 10; wherein the gate insulating layer is formed on the side of the active layer facing away from the base substrate 10, the gate is formed on the side of the gate insulating layer facing away from the active layer, the interlayer dielectric layer is formed on the side of the gate away from the gate insulating layer, the source electrode and the drain electrode are formed on the side of the interlayer dielectric layer away from the gate, and the source electrode and the drain electrode are connected to the active layer through vias penetrating the interlayer dielectric layer and the gate insulating layer. It is understood that the thin film transistor may have a top gate structure or a bottom gate structure.

[0119] The light-emitting layer 12 has different structures depending on the type of display panel. For example, the display panel may include an OLED (Organic Electroluminescence Display) or a QLED (Quantum Dot Light Emitting Diode) display panel. When the display panel is an OLED display panel, the light-emitting layer 12 may include all or part of a hole injection layer, a hole transport layer, an electron blocking layer, a luminescent material layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0120] The display panel has multiple border areas. In the embodiment of the present application, the multiple border areas include a first border area B1, a second border area B2, a third border area B3, and a fourth border area B4. The first border area B1 and the second border area B2 are arranged relative to each other along a first direction X, and the third border area B3 and the fourth border area B4 are arranged relative to each other along a second direction Y.

[0121] The GOA circuit includes a plurality of first GOA units 61 and a plurality of second GOA units 62 . The plurality of first GOA units 61 are arranged in the first frame area B1 and the second frame area B2 , and the plurality of second GOA units 62 are arranged in the third frame area B3 .

[0122] Moreover, in the embodiment of the present application, the size of the second GOA unit 62 in the first direction X is smaller than the size of the first GOA unit 61 in the first direction X, and the size of the second GOA unit 62 in the second direction Y is larger than the size of the first GOA unit 61 in the second direction Y, that is, the length of the second GOA unit 62 is increased relative to the length of the first GOA unit 61, and the width of the second GOA unit 62 is reduced relative to the width of the first GOA unit 61.

[0123] By using the display panel prepared in the embodiment of the present application, some of the GOA units in the GOA circuit are placed in the third border area B3, so that the number of GOA units can be increased without increasing or decreasing the areas of the first border area B1 and the second border area B2, so that the GOA circuit can drive the display product to achieve high resolution, thereby realizing a narrow border of a high-resolution display product and improving the user experience.

[0124] Based on the same inventive concept, an embodiment of the present application discloses a display device, comprising any display panel as described above in the embodiment of the present application.

[0125] Specifically, the display device may include a computer monitor, a television, a billboard, a laser printer with display function, a telephone, a mobile phone, a personal digital assistant (PDA), a laptop computer, a digital camera, a camcorder, a viewfinder, a vehicle, a large-area wall, a theater screen or a stadium sign, etc.

[0126] At the same time, the display device includes a flexible circuit board, one end of which is connected to the binding terminal 91 of the display panel, and the other end is connected to the control chip, so that the control chip can be used to realize the light emission of the pixel.

[0127] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0128] References herein to "one embodiment," "an embodiment," or "one or more embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Furthermore, please note that instances of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0129] In the description provided herein, a large number of specific details are described. However, it is understood that the embodiments of the present application can be practiced without these specific details. In some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of this description.

[0130] In the claims, any reference signs placed between brackets shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in the claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present application may be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The use of the words first, second, and third etc. does not indicate any order. These words may be interpreted as names.

[0131] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, wherein: The display device includes a display area and a plurality of frame areas surrounding the display area, wherein the plurality of frame areas include a first frame area, a second frame area, a third frame area, and a fourth frame area, wherein the first frame area and the second frame area are arranged opposite to each other along a first direction, and the third frame area and the fourth frame area are arranged opposite to each other along a second direction; The display panel further includes a GOA circuit in the frame area; The GOA circuit includes a plurality of first GOA units and a plurality of second GOA units, wherein the plurality of first GOA units are arranged in the first border area and the second border area, and the plurality of second GOA units are arranged in the third border area; The display panel includes a plurality of rows of pixel units in the display area; In the first direction, at least one of the plurality of second GOA units is located on a side of a first row of pixel units in the plurality of rows of pixel units away from the fourth border area; The first direction and the second direction are perpendicular to each other.

2. The display panel according to claim 1, wherein The size of the second GOA unit in the first direction is different from the size of the first GOA unit in the first direction, and the size of the second GOA unit in the second direction is different from the size of the first GOA unit in the second direction.

3. The display panel according to claim 2, wherein: The size of the second GOA unit in the first direction is larger than the size of the first GOA unit in the first direction, and the size of the second GOA unit in the second direction is smaller than the size of the first GOA unit in the second direction.

4. The display panel according to claim 1, wherein: The output line of the second GOA unit is located between the second GOA unit and the display area.

5. The display panel according to any one of claims 1 to 4, wherein: The third border area includes a first area, a second area, and a third area arranged along the second direction, and the second area is located between the first area and the third area; A plurality of the second GOA units are located in the first region and the third region. The display panel according to claim 5 , wherein: The second area includes an ambient light detection area and a common electrode bus. The common electrode bus is arranged on a side of the ambient light detection area away from the display area.

7. The display panel according to claim 5, wherein: The second area includes an ambient light detection area and an electrostatic release unit, and the electrostatic release unit is arranged on a side of the ambient light detection area close to the display area.

8. The display panel according to claim 6 or 7, wherein: The display panel includes in the ambient light detection area: substrate; a device layer, disposed on the substrate, the device layer comprising an ambient light sensor; a liquid crystal layer, disposed on a side of the device layer facing away from the substrate; a black matrix layer, disposed on a side of the liquid crystal layer away from the device layer, the black matrix layer being provided with a plurality of filling grooves, the filling grooves being filled with a color resist material; a color filter substrate, disposed on a side of the black matrix layer facing away from the liquid crystal layer; The orthographic projection of the color resist material on the base substrate at least partially overlaps with the orthographic projection of the ambient light sensor on the base substrate.

9. The display panel according to claim 8, wherein: The color resist material includes: a plurality of color resists of different colors, wherein the color resists of different colors are respectively located in different filling grooves; The ambient light sensor includes: a plurality of sensor units, and orthographic projections of different sensor units on the base substrate overlap with orthographic projections of color resists of different colors on the base substrate.

10. The display panel according to claim 9, wherein: The ambient light sensor further includes a control circuit, and the plurality of sensor units are connected to the same control circuit.

11. The display panel according to claim 9, wherein: The ambient light sensor further includes multiple groups of control circuits. The multiple sensor units are divided into multiple sensor unit groups. Each sensor unit group includes at least one sensor unit. Different sensor unit groups are connected to different control circuits.

12. The display panel according to claim 10 or 11, wherein: The ambient light sensor includes a transistor, and the control circuit includes a gate signal line, a source signal line, and a drain signal line; The gate of the transistor is connected to the gate signal line, the source of the transistor is connected to the source signal line, and the drain of the transistor is connected to the drain signal line.

13. The display panel according to claim 9, wherein: The plurality of sensor units are evenly spaced and arranged along the second direction.

14. The display panel according to claim 7, wherein: The device layer further includes a redundant gate line, and the redundant gate line is arranged on a side of the electrostatic discharge unit electrode close to the display area.

15. The display panel according to any one of claims 1 to 4, wherein: In the first direction, part of the second GOA units is located between a first row of pixel units in the multiple rows of pixel units and an outer edge of the third border area.

16. The display panel according to any one of claims 1 to 4, wherein: The GOA circuit further includes a plurality of third GOA units, wherein the plurality of third GOA units are located at corners of the third border area, and the plurality of third GOA units are adjacent to the first GOA unit and the second GOA unit at the same time; The size of the third GOA unit in the first direction is different from the size of the first GOA unit in the first direction, and the size of the third GOA unit in the second direction is different from the size of the first GOA unit in the second direction.

17. The display panel according to claim 16, wherein: The size of the third GOA unit in the first direction is larger than the size of the first GOA unit in the first direction, and the size of the third GOA unit in the second direction is smaller than the size of the first GOA unit in the second direction.

18. The display panel according to any one of claims 1 to 4, wherein: The display panel includes, in the fourth frame area: A binding terminal connected to the GOA circuit.

19. A display device, wherein: The display panel comprises the display panel according to any one of claims 1 to 18.

20. The display device according to claim 19, wherein The display device includes: A flexible circuit board is bound and connected to the binding terminals of the display panel.

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