Resource allocation method, processor and electronic device

Abstract

A resource allocation method, a processor, and an electronic device. The resource allocation method is applied to a processor, the processor is configured to concurrently execute a plurality of threads, and the processor comprises a micro-instruction cache. The method comprises: acquiring hit information of micro-instructions of a plurality of threads in a sampling window hitting a micro-instruction cache (S201); determining a control strategy on the basis of the hit information (S202); and on the basis of the control strategy, controlling the allocation of resources of the micro-instruction cache (S203). The method can at least partially solve the problem of low utilization rate of resources of a micro-instruction cache caused by mutual contention of the resources of the micro-instruction cache among a plurality of threads, thereby improving the utilization rate of the resources of the micro-instruction cache.

Description

Resource allocation method, processor, and electronic device

[0001] This application claims priority to Chinese Patent Application No. 202410260546.4 filed on March 7, 2024, and the contents of the above-mentioned Chinese patent application disclosure are hereby incorporated by reference in their entirety as a part of this application. Technical Field

[0002] Embodiments of the present disclosure relate to a resource allocation method, a processor, and an electronic device. Background Art

[0003] Traditional processors (CPUs) can only process one instruction sequence at a time, commonly called a thread. During this thread, the CPU's processing unit must continuously load instructions and data for processing. As CPU technology advances, CPU clock speed and performance continue to increase, requiring an ever-increasing speed at which instructions and data must be loaded. Unfortunately, memory technology has not kept pace with CPU development, and memory often cannot provide enough instructions and data for the CPU to process.

[0004] To improve the utilization of the CPU processing unit, thread-level parallelism has been proposed. This means that more than one instruction sequence can be executed in the CPU core. For the operating system, one physical processor is equivalent to multiple logical processors, implementing multi-threading technology.

[0005] Summary of the Invention

[0006] At least one embodiment of the present disclosure provides a resource allocation method applied to a processor, wherein the processor is configured to execute multiple threads concurrently, and the processor includes a microinstruction cache. The method includes: obtaining hit information of microinstructions of the multiple threads within a sampling window hitting the microinstruction cache; determining a regulation strategy based on the hit information; and controlling the allocation of resources of the microinstruction cache based on the regulation strategy.

[0007] For example, in the resource allocation method provided in an embodiment of the present disclosure, a regulation strategy is generated based on the hit information, including: calculating the microinstruction cache hit rate of each of the multiple threads based on the hit information, the microinstruction cache hit rate indicating the proportion of microinstructions in each thread that hit the microinstruction cache to all microinstructions of each thread within the sampling window; calculating the total microinstruction cache hit rate of the multiple threads based on the hit information, the total microinstruction cache hit rate indicating the proportion of microinstructions in the multiple threads that hit the microinstruction cache to all microinstructions of the multiple threads within the sampling window; and generating the regulation strategy based on the microinstruction cache hit rate of each of the multiple threads and the total microinstruction cache hit rate.

[0008] For example, in the resource allocation method provided in an embodiment of the present disclosure, the control strategy is determined based on the microinstruction cache hit rate of each of the multiple threads and the total hit rate of the microinstruction cache, including: in response to the total hit rate of the microinstruction cache being higher than or equal to the hit rate threshold, determining that the control strategy includes storing the target microinstructions in the microinstructions of each of the multiple threads into the microinstruction cache; in response to the total hit rate of the microinstruction cache being lower than the hit rate threshold, determining the control strategy according to the microinstruction cache hit rate of each of the multiple threads and the hit rate threshold.

[0009] For example, in the resource allocation method provided in an embodiment of the present disclosure, in response to the total microinstruction cache hit rate being lower than the hit rate threshold, the regulation strategy is determined based on the microinstruction cache hit rate of each of the multiple threads and the hit rate threshold, including: in response to the total microinstruction cache hit rate being lower than the hit rate threshold, selecting a target thread whose microinstruction cache hit rate meets the conditions from the microinstruction cache hit rate of each of the multiple threads; and determining that the regulation strategy includes writing the microinstructions of the target thread into the microinstruction cache, and not writing the microinstructions of the remaining threads of the multiple threads except the target thread into the microinstruction cache.

[0010] For example, in a resource allocation method provided in an embodiment of the present disclosure, in response to the total microinstruction cache hit rate being lower than the hit rate threshold, selecting a target thread whose microinstruction cache hit rate meets the condition from the microinstruction cache hit rate of each of the multiple threads includes:

[0011] In response to the total microinstruction cache hit rate being lower than the hit rate threshold, the target thread is obtained by excluding the object thread having the lowest microinstruction cache hit rate among the multiple threads.

[0012] For example, in a resource allocation method provided in an embodiment of the present disclosure, in response to the total microinstruction cache hit rate being lower than the hit rate threshold, a target thread whose microinstruction cache hit rate meets the conditions is selected based on the microinstruction cache hit rate of each of the multiple threads, including: sorting the multiple threads according to the microinstruction cache hit rate of each of the multiple threads, preferentially excluding the object thread with the lowest microinstruction cache hit rate among the multiple threads, and calculating the total microinstruction cache hit rate of the remaining threads after excluding the object thread, until the total microinstruction cache hit rate of the remaining threads is higher than or equal to the hit rate threshold; and taking the remaining threads corresponding to the case where the total microinstruction cache hit rate of the remaining threads is higher than or equal to the hit rate threshold as the target threads.

[0013] For example, in the resource allocation method provided in an embodiment of the present disclosure, obtaining the hit information of the microinstructions of the multiple threads within the sampling window hitting the microinstruction cache includes: monitoring a first number of microinstructions from the decoder and a second number of microinstructions from the microinstruction cache for each of the multiple threads, the first number and the second number serving as the hit information.

[0014] For example, in the resource allocation method provided in an embodiment of the present disclosure, the sampling window includes a number of clock cycles within a preset range.

[0015] For example, in the resource allocation method provided in an embodiment of the present disclosure, the allocation of resources of the microinstruction cache is controlled according to the regulation strategy, including: within the regulation window after the end of the sampling window, the allocation of resources of the microinstruction cache is controlled according to the regulation strategy.

[0016] For example, in the resource allocation method provided by an embodiment of the present disclosure, within the sampling window, the target microinstructions in the microinstructions of each of the multiple threads are stored in the microinstruction cache.

[0017] For example, in the resource allocation method provided in an embodiment of the present disclosure, the sampling window and the control window serve as a control cycle, and the method further includes: at the end of a control cycle, recounting the number of cycles of the clock cycle.

[0018] For example, in the resource allocation method provided in an embodiment of the present disclosure, the time length of the control window is the same as the time length of the sampling window.

[0019] For example, in the resource allocation method provided in one embodiment of the present disclosure, the target microinstructions are obtained by decoding the core instructions of each thread, and each thread includes the core instructions and non-core instructions, and the importance of the core instructions is greater than that of the non-core instructions.

[0020] At least one embodiment of the present disclosure provides a processor configured to concurrently execute multiple threads, the processor comprising: a microinstruction cache; a monitor; and a controller. The monitor is coupled to the microinstruction cache and configured to obtain hit information of microinstructions of the multiple threads hitting the microinstruction cache within a sampling window, and to determine a control strategy based on the hit information; and the controller is coupled to the microinstruction cache and the monitor and configured to obtain the control strategy provided by the monitor and control the allocation of resources of the microinstruction cache based on the control strategy.

[0021] For example, the processor provided in one embodiment of the present disclosure further includes: a decoder, coupled to the monitor, and configured to decode the instructions of each thread to obtain microinstructions of each thread; the monitor is configured to obtain a first number of microinstructions from the decoder and a second number of microinstructions from the microinstruction cache for each of the multiple threads, and the first number and the second number are used as the hit information.

[0022] For example, the processor provided in one embodiment of the present disclosure further includes: a buffer, the input end of the buffer is coupled to the output end of the controller, the output end of the buffer is coupled to the microinstruction cache, the buffer includes multiple buffers, the multiple buffers correspond one-to-one to the microinstructions of the multiple threads, and are configured to store the microinstructions of the multiple threads, the buffer is configured to write the microinstructions in the buffer into the microinstruction cache, the decoder is also coupled to the input end of the controller, and the controller is configured to: control whether the microinstructions of the current thread among the multiple threads provided by the decoder are written into the buffer corresponding to the current thread according to the control strategy.

[0023] At least one embodiment of the present disclosure provides an electronic device, including the processor provided by any embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0025] FIG1 shows a flowchart of a CPU working in SMT mode;

[0026] FIG2 shows a flow chart of a resource allocation method provided by at least one embodiment of the present disclosure;

[0027] FIG3 shows a flowchart of a method of step S20 in FIG2 provided by at least one embodiment of the present disclosure;

[0028] FIG4 shows a flowchart of another resource allocation method provided by at least one embodiment of the present disclosure;

[0029] FIG5 shows a schematic diagram of a processor provided by at least one embodiment of the present disclosure;

[0030] FIG6 shows a schematic diagram of a microstructure of a processor provided by at least one embodiment of the present disclosure;

[0031] FIG7 is a schematic block diagram of an electronic device provided by some embodiments of the present disclosure; and

[0032] FIG8 is a schematic block diagram of another electronic device provided by some embodiments of the present disclosure. DETAILED DESCRIPTION

[0033] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0034] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0035] Multithreading technologies, such as Simulated Multi-Threading (SMT), also known as Hyper-Threading, can make a single physical CPU core behave like two or more independent processors. This allows the processor to handle multiple tasks simultaneously, significantly improving CPU efficiency. SMT is a key technology for improving overall CPU performance. It leverages the multi-issue and out-of-order execution mechanisms of high-performance CPU cores to simultaneously execute instructions from multiple threads. This allows a physical CPU core to appear to software and the operating system as multiple virtual CPU cores. When executing a single thread, the multiple execution units and hardware resources within a modern multi-issue high-performance CPU core are often underutilized. When the thread stalls due to some reason (such as a L2 cache miss), the hardware execution units are forced to idle, wasting hardware resources and reducing performance-to-power ratio. In SMT mode, when one thread stalls, other threads can continue to run, improving hardware resource utilization and boosting the CPU core's multi-threaded throughput, overall performance, and performance-to-power ratio. Depending on the maximum number of active threads supported, SMT can be called SMT2 (up to two active threads), SMT4 (up to four active threads), and so on.

[0036] The CPU core includes multiple pipeline stages, such as branch prediction, instruction fetch, instruction decoding, instruction dispatch and rename, instruction execution, and instruction retirement.

[0037] Modern high-performance CPUs often have an instruction cache (IC) and a micro-operation cache (OC). The IC is used to cache undecoded instructions, and the OC is used to cache micro-instructions. Micro-instructions are one or more micro-instructions that are decoded into instructions and can be passed to subsequent pipelines for execution. When the instruction fetch pipeline finds that an instruction exists in the IC or OC based on the results of the branch prediction pipeline, it can directly obtain the undecoded instructions or micro-instructions (decoded instructions) from these two caches to avoid the high latency caused by accessing the lower-level storage area. In addition, obtaining micro-instructions directly from the OC can reduce the process of fetching undecoded instructions from the IC and decoding them, which can achieve higher instruction issuance bandwidth and faster running speed, thereby improving CPU core performance and effectively reducing power consumption.

[0038] The OC is a crucial component of modern high-performance CPU cores. Using it effectively reduces CPU core pipeline front-end latency, lowers power consumption, and increases access bandwidth, significantly impacting CPU core performance and power consumption. When the branch prediction unit provides new instruction segment information and finds the corresponding instruction segment in the OC, it eliminates the need to fetch and decode the instruction from the instruction cache (IC). Instead, it retrieves the corresponding micro-operation segment directly from the OC and provides it to the back-end pipeline.

[0039] FIG1 shows a flowchart of a CPU operation in SMT mode.

[0040] As shown in FIG1 , the operation of the CPU in the SMT mode includes steps S101 to S109 .

[0041] Step S101: The branch predictor performs thread arbitration and selects the thread (thread 0 or thread 1) on the pipeline of the current clock cycle to the branch prediction pipeline for branch prediction, thereby obtaining a branch prediction result. Branch prediction is used to predict the target address of the branch instruction. The branch prediction result includes, for example, branch prediction information (Branch Prediction Info, BPI), that is, the prediction information output by the branch predictor, including the target address of the instruction, thread tag, starting position of the storage space, etc. A BPI may include one or more consecutive instructions. For example, the SMT mode includes two active threads, thread 0 and thread 1. For example, the branch predictor performs arbitration according to polling or other methods to select the thread on the pipeline of the current clock cycle.

[0042] Step S102: Write the BPI to the branch prediction result acquisition queue of the corresponding thread. For example, if the branch predictor selects thread 0 for branch prediction in step S101, the BPI is written to the branch prediction result acquisition queue of thread 0. If the branch predictor selects thread 1 for branch prediction in step S101, the BPI is written to the branch prediction result acquisition queue of thread 1.

[0043] Step S103: The instruction cache performs thread arbitration, selects the thread on the pipeline for the current clock cycle (thread 0 or thread 1), and sequentially retrieves the BPI from the branch prediction result acquisition queue corresponding to that thread. If the thread selected by the instruction cache during thread arbitration is not cached in the microinstruction cache 110, the BPI is sent to the instruction cache pipeline. The instruction cache pipeline is responsible for retrieving undecoded instructions from the instruction cache and providing the retrieved undecoded instructions to the decoder. For example, if the instruction cache selects thread 1 as the thread on the pipeline for the current clock cycle, the BPI is sequentially retrieved from thread 1's branch prediction result acquisition queue and sent to the instruction cache pipeline. This retrieves thread 1's undecoded instructions from the instruction cache and provides them to the decoder. Similarly, the thread selected by the instruction cache for the pipeline for the current clock cycle may also be thread 0. For example, the instruction cache selects the thread on the pipeline of the current clock cycle by arbitration in a round-robin manner or other manner. If the BPI obtained by the thread selected by the instruction cache through thread arbitration is cached in the microinstruction cache 110, the process jumps to the subsequent step S108.

[0044] Step S104: The decoder decodes the undecoded instruction into a microinstruction (UOP) and sends the decoded UOP to the microinstruction queue corresponding to the thread for backend execution. For example, the decoder decodes the undecoded instruction of thread 0 and obtains the UOP of thread 0. The decoder then sends the UOP of thread 0 to the microinstruction queue of thread 0, so that the UOP of thread 0 enters the microinstruction queue of thread 0.

[0045] Step S105: The decoder simultaneously provides UOPs to the buffer. For example, the buffer includes multiple buffers, each corresponding to a plurality of threads, and each buffer is used to store the UOPs of a thread. In step S105, the decoder performs arbitration and selects the buffer corresponding to the thread in the buffer to which the UOPs decoded by the decoder are written. For example, if the decoder obtains the UOP of thread 0, the decoder arbitrates and writes the UOP provided by the decoder into the buffer of thread 0.

[0046] For example, while the decoder provides the UOP of a certain thread to the microinstruction queue of the thread, it also performs decoder arbitration and writes the UOP of the thread into the buffer corresponding to the thread.

[0047] Step S106: The UOP of each thread accumulates multiple instructions in the buffer to form a microinstruction entry.

[0048] Step S107: The pipeline of the microinstruction cache performs thread arbitration, selects the thread of the pipeline in the current clock cycle, removes the microinstruction cache entry already formed by the thread from the buffer, and writes it to the microinstruction cache 110. For example, if the thread of the pipeline in the current clock cycle selected by the pipeline of the microinstruction cache 110 through thread arbitration is thread 1, the microinstruction cache entry already formed by thread 1 is removed from the buffer and written to the microinstruction cache 110.

[0049] Step S108: The microinstruction fetch queue stores the BPI provided by the instruction cache. For example, if the BPI obtained by the thread selected after instruction cache arbitration from the branch prediction result fetch queue is already cached in the microinstruction cache 110, the BPI of this thread will no longer be sent to the instruction cache pipeline and decoder, but will be sent directly to the microinstruction fetch queue of the corresponding thread.

[0050] For example, the BPI of thread 1 selected after instruction cache arbitration has been cached in the microinstruction cache 110. Then, the BPI of thread 1 is no longer provided to the instruction cache pipeline and decoder, but is provided to the microinstruction fetch queue of thread 1, so that the microinstruction fetch queue of thread 1 stores the BPI of thread 1.

[0051] Step S109: The pipeline of the microinstruction cache performs thread arbitration, selects the thread of the pipeline of the current clock cycle, obtains BPI information from the microinstruction acquisition queue of the thread, searches for the corresponding UOP in the microinstruction cache, and sends the UOP to the corresponding microinstruction queue for use in back-end execution.

[0052] For example, the pipeline of the microinstruction cache 110 performs thread arbitration and selects the thread of the pipeline in the current clock cycle as thread 0. Then, the BPI information is obtained from the microinstruction acquisition queue of thread 0, the corresponding UOP is found, and the UOP is sent to the corresponding microinstruction queue for use in back-end execution.

[0053] In this workflow, the microinstructions in the microinstruction queue of each thread may come from the decoder or the microinstruction cache.

[0054] As described above, when filling the microinstruction cache, multiple threads share the entire microinstruction cache space, which means that multiple threads compete with each other for microinstruction cache resources. Since different threads of the processor run different program codes, different threads have different requirements for microinstruction cache resources.

[0055] Since the capacity of the microinstruction cache is limited, in the case of limited microinstruction cache capacity, this multi-threaded competition for microinstruction cache resources may cause multiple threads to be unable to achieve a relatively high microinstruction cache hit rate, resulting in low utilization of the microinstruction cache.

[0056] To address the issue of reduced microinstruction cache utilization caused by competition for microinstruction cache resources among multiple threads in current processors, the present disclosure provides a resource allocation method that monitors the microinstruction cache utilization of multiple threads from the perspective of the entire CPU core. Based on the monitoring results, a feedback mechanism is formed to dynamically control the microinstruction cache resource usage of different threads, thereby improving the overall microinstruction cache hit rate.

[0057] This resource allocation method is applied to a processor. The processor is configured to execute multiple threads concurrently, and the processor includes a microinstruction cache. The method includes: obtaining hit information of microinstructions of multiple threads hitting the microinstruction cache within a sampling window; determining a regulation strategy based on the hit information; and controlling the allocation of resources of the microinstruction cache based on the regulation strategy. The embodiments of the present disclosure at least partially solve the problem of multiple threads competing for OC resources, resulting in a low overall OC hit rate. This not only accelerates the operating speed of the entire CPU, but also saves power.

[0058] FIG2 shows a flowchart of a resource allocation method provided by at least one embodiment of the present disclosure.

[0059] As shown in FIG2 , the resource allocation method includes steps S201 to S203 . The resource allocation method is applied to a processor configured to concurrently execute multiple threads, such as a processor concurrently executing multiple threads in SMT mode. The processor includes a microinstruction cache. The microinstruction cache includes multiple cached microinstructions.

[0060] Step S201: Obtain hit information of microinstructions of multiple threads within a sampling window hitting the microinstruction cache.

[0061] Step S202: Determine a control strategy based on the hit information.

[0062] Step S203: Control the allocation of microinstruction cache resources according to the regulation strategy.

[0063] In step S201, a microinstruction hitting the microinstruction cache means that the microinstruction has already been cached in the microinstruction cache. For example, as described in FIG1 , whether the microinstruction has been cached in the microinstruction cache can be determined based on the BPI. If the microinstruction has already been cached in the microinstruction cache, the microinstruction is directly provided by the microinstruction cache entry microinstruction queue, without passing through the decoder to provide the microinstruction to the microinstruction queue.

[0064] For example, within the adoption window, a first number of microinstructions from the decoder and a second number of microinstructions from the microinstruction cache of each of the multiple threads are monitored, and the first number and the second number are used as hit information. For example, in the example of FIG1 , within the adoption window, the microinstructions in the respective microinstruction queues of thread 0 and thread 1 are monitored to determine which microinstructions are from the decoder and which are from the microinstruction cache, and the number of microinstructions from the decoder and the number of microinstructions from the microinstruction cache in the microinstruction queue of thread 0 and the microinstruction queue of thread 1 are counted, respectively.

[0065] In some embodiments of the present disclosure, a sampling window is set to collect hit information of each thread's microinstructions hitting the microinstruction cache within the sampling window. The sampling window, for example, includes a number of clock cycles within a preset range. For example, the sampling window includes a preset number of clock cycles. In this example, the preset number is an example of a preset range. For example, every 500 clock cycles is used as a sampling window, that is, the number of clock cycles in [0,499] is used as a sampling window. In other embodiments, the sampling window can also be a preset number of instructions.

[0066] For example, 1000 clock cycles are used as a sampling window, and hit information for microinstructions from multiple threads hitting the microinstruction cache is collected during the 1000 clock cycles. Another example is 50,000 instructions as a sampling window, i.e., the preset number of instructions is 50,000. After collecting a total of 50,000 microinstructions from multiple threads, the number of microinstructions from the decoder and the number of microinstructions in the microinstruction cache are counted, as well as the thread to which each microinstruction belongs.

[0067] For step S202, the control strategy may include, for example, whether to store microinstructions of multiple threads in the microinstruction cache, or which threads' microinstructions are to be stored in the microinstruction cache. For example, based on the hit information, a target thread is selected from the multiple threads, and the control strategy is to store only the microinstructions of the target thread in the microinstruction cache.

[0068] For step S203, the resources of the microinstruction cache include the storage space of the microinstruction cache. For example, if the control strategy is to store only the microinstructions of the target thread in the microinstruction cache, the storage space of the microinstruction cache is controlled to store only the microinstructions of the target thread.

[0069] For example, if the number of core instructions of one thread among the multiple threads is large, the microinstructions of the thread may not be stored in the microinstruction cache.

[0070] FIG3 shows a flowchart of a method of step S20 in FIG2 provided by at least one embodiment of the present disclosure.

[0071] As shown in FIG3 , the method includes steps S212 to S232 .

[0072] Step S212: Calculate the microinstruction cache hit rate of each of the multiple threads based on the hit information. The microinstruction cache hit rate indicates the proportion of microinstructions that hit the microinstruction cache in each thread to all microinstructions of each thread in the sampling window.

[0073] Step S222: Calculate the total microinstruction cache hit rate of the multiple threads based on the hit information. The total microinstruction cache hit rate indicates the proportion of microinstructions that hit the microinstruction cache in the multiple threads to all microinstructions in the multiple threads within the sampling window.

[0074] Step S232: Generate a control strategy based on the microinstruction cache hit rate of each of the multiple threads and the total microinstruction cache hit rate.

[0075] This method dynamically controls the occupancy of microinstruction cache resources by different threads according to the microinstruction cache hit rate of each thread and the total microinstruction cache hit rate, thereby improving the overall hit rate of the microinstruction cache.

[0076] Regarding step S212 , for example, in the SMT mode, including concurrently executed threads 0 and 1 , the microinstruction cache hit rate of thread 0 and the microinstruction cache hit rate of thread 1 are calculated based on the hit information.

[0077] The microinstruction cache hit rate is, for example, the ratio of the number of microinstructions that hit the microinstruction cache among all microinstructions of the thread (e.g., thread 0 or thread 1) obtained within a sampling window to the total number of microinstructions of the thread. For example, if P1 microinstructions of a thread are obtained within a sampling window, and m1 of them hit the microinstruction cache, then the microinstruction cache hit rate of the thread is Y1 = m1 / P1.

[0078] For example, if 1000 microinstructions are obtained for thread 0 within the sampling window, and 200 of them hit the microinstruction cache, the microinstruction cache hit rate of thread 0 is 20%. For example, if 1500 microinstructions are obtained for thread 1 within the sampling window, and 450 of them hit the microinstruction cache, the microinstruction cache hit rate of thread 1 is 30%.

[0079] In step S222, the total microinstruction cache hit rate for multiple threads refers to the percentage of microinstructions in the multiple threads as a whole that hit the microinstruction cache. For example, if a total of P microinstructions are obtained from multiple threads in the sampling window, and m of the P microinstructions hit the microinstruction cache, then the total microinstruction cache hit rate Y = m / P.

[0080] For example, in the sampling window, a total of 1000 microinstructions of thread 0 and 2000 microinstructions of thread 1 are obtained, so the total number of microinstructions is 3000. Among these 3000 microinstructions, a total of 650 microinstructions (200 microinstructions of thread 0 and 450 microinstructions of thread 1) hit the microinstruction cache, and the total microinstruction cache hit rate is 650 / 3000≈21.67%.

[0081] For step S232 , a control strategy is generated based on the microinstruction cache hit rate and the total microinstruction cache hit rate.

[0082] For example, a control strategy is generated according to the microinstruction cache hit rate Y1 of each of the multiple threads and the total microinstruction cache hit rate Y.

[0083] The control policy is used, for example, to indicate which threads' microinstructions are to be written into (also referred to as "filled") the microinstruction cache and which threads' microinstructions are not to be written into the microinstruction cache.

[0084] For example, based on the microinstruction cache hit rate Y1 of each of the multiple threads and the total microinstruction cache hit rate Y, threads with lower microinstruction cache hit rates are selected, and the target thread is obtained after excluding these threads. The control strategy in this case is, for example, to write the microinstructions of the specified target thread into the microinstruction cache.

[0085] In some embodiments of the present disclosure, step S232 includes: in response to the total hit rate of the microinstruction cache being higher than or equal to a hit rate threshold, determining a control strategy including storing the target microinstructions in the microinstructions of each of the multiple threads into the microinstruction cache; in response to the total hit rate of the microinstruction cache being lower than the hit rate threshold, determining a control strategy based on the microinstruction cache hit rate of each of the multiple threads.

[0086] For example, if the total hit rate Y of the microinstruction cache is greater than or equal to the hit rate threshold Y0, the control strategy includes storing the target microinstructions in the microinstructions of each of the multiple threads into the microinstruction cache, that is, each of the multiple threads is used as a target thread, and the target microinstructions of the target thread are stored into the microinstruction cache.

[0087] In some embodiments of the present disclosure, the target micro-instructions are obtained by decoding the core instructions of each thread. Each thread includes core instructions and non-core instructions, and the importance level of the core instructions is greater than that of the non-core instructions. Only storing the micro-instructions obtained by decoding the core instructions of the target thread into the micro-instruction cache instead of storing all the micro-instructions of the target thread into the micro-instruction cache can save the storage space of the micro-instruction cache for other threads to use. The importance level of an instruction is characterized, for example, by the number of times the instruction is executed during the complete execution of the program. The more times an instruction is executed, the higher the importance level of the instruction. For example, a program often includes a loop body, and the instructions in the loop body are often executed multiple times, so the importance level of the instructions in the loop body is higher than that of the instructions outside the loop body. In some embodiments of the present disclosure, the core instructions are, for example, the instructions (i.e., loop instructions) in the loop body, and the non-core instructions are the instructions outside the loop body. Or, the core instructions are, for example, the instructions that are executed more than once during the complete execution of the program, and the non-core instructions are the instructions that are only executed once during the complete execution of the program.

[0088] For example, if the overall hit rate Y of the micro-instruction cache is less than Y0, a regulation strategy is determined based on the micro-instruction cache hit rates and the hit rate threshold of each of the multiple threads.

[0089] For example, each micro-instruction cache hit rate Y1 is compared with the hit rate threshold Y0 to determine the micro-instruction cache hit rate Y1 that is greater than the hit rate threshold Y0. The threads with Y1 > Y0 are used as target threads, and the regulation strategy includes storing the target micro-instructions of these target threads into the micro-instruction cache.

[0090] In some embodiments of the present disclosure, in response to the overall hit rate Y of the micro-instruction cache being lower than the hit rate threshold Y0, target threads are selected from the micro-instruction cache hit rates Y1 of each of the multiple threads where the micro-instruction cache hit rate Y1 meets the conditions; and it is determined that the regulation strategy includes writing the micro-instructions of the target threads into the micro-instruction cache, and not writing the micro-instructions of the remaining threads other than the target threads among the multiple threads into the micro-instruction cache.

[0091] The target threads where the micro-instruction cache hit rate Y1 meets the conditions are, for example, the target threads where the micro-instruction cache hit rate Y1 is lower than the preset hit rate. The preset hit rate can be set by those skilled in the art. Or, the multiple micro-instruction cache hit rates Y1 are sorted from smallest to largest, and the threads after the preset position in the sorting are the target threads that meet the conditions.

[0092] In some embodiments of the present disclosure, for example, in response to the overall hit rate Y of the micro-instruction cache being lower than the hit rate threshold Y0, the object thread with the lowest micro-instruction cache hit rate Y1 among the multiple threads is excluded to obtain the target threads.

[0093] In some other embodiments of the present disclosure, for example, multiple threads are sorted according to the micro-instruction cache hit rate of each thread, and the target thread with the lowest micro-instruction cache hit rate among the multiple threads is preferentially excluded in sequence, and the total micro-instruction cache hit rate of the remaining threads after excluding the target thread is calculated until the total micro-instruction cache hit rate of the remaining threads is higher than or equal to the hit rate threshold; and the remaining threads corresponding to the case where the total micro-instruction cache hit rate of the remaining threads is higher than or equal to the hit rate threshold are used as target threads.

[0094] For example, the processor concurrently executes 4 threads, namely thread 1, thread 2, thread 3, and thread 0; the micro-instruction cache hit rates of these 4 threads are Y11, Y12, Y13, and Y10 respectively, and the total micro-instruction cache hit rate of these 4 threads is Y. If Y < Y0, then the threads 1, 2, 3, and 0 are sorted according to the magnitudes of Y11, Y12, Y13, and Y10. For example, the sorting result in ascending order is thread 1, thread 2, thread 0, and thread 3. After removing the front-ranked thread 1, the total micro-instruction cache hit rate Y' of the remaining threads (thread 2, thread 0, and thread 3) is calculated. If Y' < Y0, then thread 2 is continued to be removed, and the total micro-instruction cache hit rate Y'' of the remaining threads (thread 0 and thread 3) is calculated. If Y'' ≥ Y0, then thread 0 and thread 3 are used as target threads. If Y'' < Y0, then thread 0 is continued to be removed until the total micro-instruction cache hit rate of the remaining threads is greater than or equal to the hit rate threshold.

[0095] In the embodiments of the present disclosure, those skilled in the art can set the hit rate threshold according to actual needs, and the present disclosure does not specifically limit the hit rate threshold. For example, the hit rate threshold can be 50%.

[0096] In some embodiments of the present disclosure, step S203 in FIG. 2 includes: within the regulation window after the end of the sampling window, controlling the allocation of resources of the micro-instruction cache according to the regulation strategy. In some embodiments of the present disclosure, the size of the regulation window and the size of the sampling window can be the same. For example, if the number of clock cycles of the sampling window is within a preset range, then the time length of the regulation window is the same as the time length of the sampling window.

[0097] In some other embodiments of the present disclosure, the size of the regulation window and the size of the sampling window can be different.

[0098] In some embodiments of the present disclosure, within the sampling window, the target micro-instructions in the micro-instructions of each of the multiple threads are all stored in the micro-instruction cache.

[0099] In some embodiments of the present disclosure, the sampling window and the regulation window are used as a regulation period, and the method further includes: at the end of one regulation period, the number of clock cycles is re-counted.

[0100] The following describes an embodiment of resource allocation according to the present disclosure with reference to FIG4 .

[0101] FIG4 shows a flowchart of another resource allocation method provided by at least one embodiment of the present disclosure.

[0102] As shown in FIG4 , the resource allocation method includes steps S401 to S412 .

[0103] Step S401: Count the clock cycles, and increase the count value by a preset step size for each clock cycle. The preset step size is, for example, 1. Of course, the preset step size can also be other positive integers such as 2 or 3.

[0104] Step S402: Compare the current count value with the clock threshold. The clock threshold determines the sampling window. For example, if the clock threshold is 500, the sampling window is the clock period with a count value of [0, 500]. For example, compare the current count value with 500. If the count value is less than or equal to the clock threshold, proceed to step S404. If the clock threshold is less than or equal to the count value and less than 2 × the clock threshold, proceed to step S403. If the count value is equal to or equal to the clock threshold, proceed to step S405.

[0105] Step S403: The count value is reset to 0 and the next sampling window is restarted. If the clock threshold < the count value < 2 × the clock threshold, the count value is reset to 0, meaning that the control window and the sampling window have the same length, 500 clock cycles. At the end of a control cycle, the number of clock cycles is reset.

[0106] Step S404: Both thread 0 and thread 1 are populated into the microinstruction cache. Specifically, when the count value does not reach the clock threshold, the microinstructions of each thread are populated into the microinstruction cache. In other words, within the sampling window, the target microinstructions in the microinstructions of each of the multiple threads are stored in the microinstruction cache, and the multiple threads compete for resources. After executing step S404, the process proceeds directly to step S412.

[0107] Step S405: When the count value is equal to the clock threshold, obtain the microinstruction cache hit rate Y10 of thread 0, the microinstruction cache hit rate Y11 of thread 1, and the total microinstruction cache hit rate Y to generate a control strategy based on the above hit rates.

[0108] It should be noted that, in this embodiment, the concurrent execution of two threads (thread 0 and thread 1) is taken as an example to illustrate the implementation method, but this has no limiting effect on the present disclosure.

[0109] In the above embodiment, as shown in the algorithm, 1 is added to each clock cycle. When the count value is less than the clock threshold, all threads are normally filled into the microinstruction cache, and everyone competes for resources; at the same time, the hit information of each overall microinstruction cache within the sampling window of the clock threshold is monitored. When the count value is equal to the clock threshold, a decision is made based on the hit information. That is, within the control window after the end of the sampling window, the allocation of resources of the microinstruction cache is controlled according to the control strategy, and within the sampling window, the target microinstructions in the microinstructions of each of the multiple threads are stored in the microinstruction cache. In the above example,

[0110] Step S406: Determine whether the total microinstruction cache hit rate Y is less than the hit rate threshold. If the total microinstruction cache hit rate Y is less than the hit rate threshold, execute step S407; if the total microinstruction cache hit rate Y is not less than the hit rate threshold, execute step S410.

[0111] Step S407: Compare the microinstruction cache hit rate Y10 of thread 0 with the microinstruction cache hit rate Y11 of thread 1. If Y10>Y11, execute step S409; if Y10≤Y11, execute step S408.

[0112] Step S408: Fill the microinstructions of thread 1 into the microinstruction cache.

[0113] Step S409: Fill the microinstructions of thread 0 into the microinstruction cache.

[0114] Step S410: Fill the microinstructions of thread 0 and thread 1 into the microinstruction cache.

[0115] Step S411: Generate a control strategy. The control strategy, for example, includes the results obtained in steps S408 to S410.

[0116] Step S412: Control the resource allocation of the microinstruction cache according to the regulation strategy.

[0117] In the example of Figure 4, if the overall microinstruction cache hit rate (i.e., the total microinstruction cache hit rate Y) is higher than the hit rate threshold, the control strategy is to continue to fill the microinstructions of all threads into the microinstruction cache at the same time; if the overall microinstruction cache hit rate is lower than the hit rate threshold, a control strategy decision is generated based on the microinstruction cache hit rate of each thread. The control strategy is, for example, to stop filling the thread with the lowest microinstruction cache hit rate into the microinstruction cache.

[0118] The disclosed embodiments propose a method for allocating microinstruction cache resources in a concurrent multithreaded mode, addressing the problem of multiple threads competing for microinstruction cache resources, resulting in a low overall microinstruction cache hit rate. This not only speeds up the entire CPU but also saves power.

[0119] Another aspect of the present disclosure provides a processor configured to execute multiple threads concurrently. The processor includes: a microinstruction cache, a monitor, and a controller. The monitor is coupled to the microinstruction cache and configured to obtain hit information of the microinstructions of multiple threads hitting the microinstruction cache within a sampling window, and to determine a control strategy based on the hit information; the controller is coupled to the microinstruction cache and the monitor and configured to obtain the control strategy provided by the monitor, and to control the allocation of resources of the microinstruction cache based on the control strategy. The processor can at least partially solve the problem that the overall microinstruction cache hit rate is not high due to multiple threads competing for microinstruction cache resources, which can not only accelerate the operating speed of the entire CPU, but also save power consumption.

[0120] Embodiments of the present disclosure provide a processor for allocating microinstruction cache resources in a concurrent multithreaded mode. For example, the processor may include a monitor before the microinstruction queue and a controller before the microinstruction cache. The monitor generates a control policy based on hit information, and the controller controls the allocation of microinstruction cache resources based on the control policy.

[0121] It should be noted that although the embodiments of the present disclosure illustrate the disclosed implementation methods by executing two threads (thread 0 and thread 1) in parallel, this does not limit the present disclosure. The resource allocation method provided by the present disclosure can be applied to the concurrent execution of any number of threads.

[0122] FIG5 shows a schematic diagram of a processor 500 provided by at least one embodiment of the present disclosure.

[0123] As shown in FIG. 5 , the processor 500 includes a microinstruction cache 501 , a controller 502 , and a monitor 503 .

[0124] The monitor 503 is coupled to the microinstruction cache 501 and configured to obtain hit information of microinstructions of multiple threads hitting the microinstruction cache within a sampling window and determine a control strategy based on the hit information. The monitor 503 is used to execute steps S201 and S202 in Figure 2, for example.

[0125] The controller 502 is coupled to the microinstruction cache 501 and the monitor 503 and is configured to obtain a control policy provided by the monitor 503 and control the allocation of microinstruction cache resources according to the control policy. The controller 502 is used to execute step S203 in FIG2 , for example.

[0126] Please refer to the above description for the microinstruction cache 501. The controller 502 and the monitor 503 can be hardware, software, firmware, or any feasible combination thereof. For example, the controller 502 and the monitor 503 can be dedicated or general-purpose circuits, chips, or devices, etc. The embodiments of the present disclosure do not limit the specific implementation form of the above-mentioned each unit. The controller 502 and the monitor 503 correspond to the various steps of the aforementioned resource allocation method. For the specific functions of the controller 502 and the monitor 503, please refer to the relevant description of the resource allocation method, which will not be repeated here.

[0127] FIG6 shows a schematic diagram of a microstructure of a processor provided by at least one embodiment of the present disclosure.

[0128] As shown in FIG6 , the processor includes a decoder 603 in addition to a microinstruction cache 601 , a controller 602 and a monitor 605 .

[0129] The microinstruction cache 601, the controller 602, and the monitor 605 are similar to the microinstruction cache 501, the controller 502, and the monitor 503 in Figure 5 above. The microinstruction cache 601 is also similar to the microinstruction cache 110 in Figure 1.

[0130] The decoder 603 is coupled to the monitor 605 and is configured to decode the instructions of each thread to obtain the microinstructions of each thread; the monitor 605 is configured to obtain a first number of microinstructions from the decoder 603 and a second number of microinstructions from the microinstruction cache 601 for each of the multiple threads, and the first number and the second number are used as hit information.

[0131] As shown in FIG. 6 , the processor may further include a buffer 604 .

[0132] The input end of the buffer 604 is coupled to the output end of the controller 602, and the output end of the buffer 604 is coupled to the microinstruction cache 601. The buffer includes multiple buffers, and the multiple buffers correspond one-to-one to the microinstructions of multiple threads. The buffer is configured to store the microinstructions of multiple threads, and the buffer is configured to write the microinstructions in the buffer into the microinstruction cache.

[0133] The decoder 603 is further coupled to an input terminal of the controller 602 . The controller is configured to control whether the microinstructions of the current thread among the multiple threads provided by the decoder 603 are written into a buffer corresponding to the current thread according to a control strategy.

[0134] In this embodiment, the controller 602 first writes the target microinstructions of the target thread into the buffer corresponding to the target thread in the buffer 604 according to the control strategy. After a certain number of microinstruction cache items are accumulated in the buffer, they are taken out from the buffer according to the arbitration of the microinstruction cache 601 and stored in the microinstruction cache 601.

[0135] For example, the controller 602 obtains the microinstructions of thread 0 from the decoder 603 and determines, based on the control policy, whether the microinstructions of thread 0 are stored in the buffer corresponding to thread 0. If the microinstructions of thread 0 are stored in the buffer corresponding to thread 0, step S601 is executed, i.e., the controller 602 arbitrates and stores thread 0 in the buffer corresponding to thread 0.

[0136] As shown in FIG6 , the microstructure of the processor is similar to that of FIG1 , except that the microstructure includes a controller 602 and a monitor 605 outlined by an oval dotted line, and the arbitration of step S601 is performed by the controller.

[0137] The components and structures of the processor shown in FIG5 and FIG6 are merely exemplary and non-limiting. The processor may further include other components and structures as needed.

[0138] The specific implementation forms of the above-mentioned units can be hardware, software, firmware, or any feasible combination thereof, which is not limited in the embodiments of the present disclosure.

[0139] It should be noted that the embodiments of the present disclosure are not only applicable to the SMT mode, but also to other modes of concurrently executing multiple threads. As long as the processor executes multiple threads concurrently, the resource allocation method provided by the embodiments of the present disclosure can be used.

[0140] Another aspect of the present disclosure provides an electronic device, which includes the process provided by any embodiment of the present disclosure.

[0141] Figure 7 is a schematic block diagram of an electronic device provided in some embodiments of the present disclosure. As shown in Figure 7, the electronic device 700 includes a processor 710 and a memory 720. The memory 720 is used to store non-transitory computer-readable instructions (e.g., one or more computer program modules). The processor 710 is used to execute non-transitory computer-readable instructions, and when the non-transitory computer-readable instructions are executed by the processor 710, one or more steps in the resource allocation method described above can be executed. The memory 720 and the processor 710 can be interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0142] The processor 701 may be the processor provided by any embodiment of the present disclosure. For example, the microstructure of the processor 701 is similar to the microstructure of the processor in FIG. 6 .

[0143] For example, the processor 710 may be a central processing unit (CPU), a graphics processing unit (GPU), or other processing units with data processing capabilities and / or program execution capabilities. For example, the central processing unit (CPU) may be an X86 or ARM architecture. The processor 710 may be a general-purpose processor or a dedicated processor, and may control other components in the electronic device 700 to perform desired functions.

[0144] For example, the memory 720 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a USB memory, a flash memory, etc. One or more computer program modules may be stored on the computer-readable storage medium, and the processor 710 may execute one or more computer program modules to implement various functions of the electronic device 700. Various applications and various data, as well as various data used and / or generated by the applications, may also be stored in the computer-readable storage medium.

[0145] It should be noted that, in the embodiment of the present disclosure, the specific functions and technical effects of the electronic device 700 can be referred to the above description of the resource allocation method, which will not be repeated here.

[0146] Figure 8 is a schematic block diagram of another electronic device provided in some embodiments of the present disclosure. This electronic device 800 is, for example, suitable for implementing the resource allocation method provided in embodiments of the present disclosure. The electronic device 800 may be a terminal device, etc. It should be noted that the electronic device 800 shown in Figure 8 is merely an example and does not impose any limitations on the functionality or scope of use of the embodiments of the present disclosure.

[0147] As shown in FIG8 , electronic device 800 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 810, which may perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 820 or a program loaded from a storage device 880 into a random access memory (RAM) 830. Processing device 810 may be, for example, the processor provided in any embodiment of the present disclosure, and, for example, the microstructure of processor 810 may be similar to the microstructure of the processor in FIG6 .

[0148] Various programs and data required for the operation of the electronic device 800 are also stored in the RAM 830. The processing device 810, the ROM 820, and the RAM 830 are connected to each other via a bus 840. An input / output (I / O) interface 850 is also connected to the bus 840.

[0149] Typically, the following devices may be connected to the I / O interface 850: an input device 860 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 870 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 880 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 890. The communication device 890 may allow the electronic device 800 to communicate with other electronic devices wirelessly or by wire to exchange data. Although FIG8 shows the electronic device 800 with various devices, it should be understood that it is not required to implement or have all of the devices shown, and the electronic device 800 may alternatively implement or have more or fewer devices.

[0150] There are a few points to note:

[0151] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0152] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0153] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A resource allocation method, applied to a processor, wherein: The processor is configured to execute multiple threads concurrently, the processor includes a microinstruction cache, and the method includes: Obtaining hit information of microinstructions of the plurality of threads within a sampling window hitting the microinstruction cache; Determining a regulatory strategy based on the hit information; and According to the regulation strategy, the allocation of resources of the microinstruction cache is controlled.

2. The method according to claim 1, wherein Generate a control strategy based on the hit information, including: Calculating a microinstruction cache hit rate for each of the plurality of threads based on the hit information, wherein the microinstruction cache hit rate indicates a proportion of microinstructions in each thread that hit the microinstruction cache relative to all microinstructions of each thread within the sampling window; Calculating a total microinstruction cache hit rate of the multiple threads based on the hit information, wherein the total microinstruction cache hit rate indicates a ratio of microinstructions of the multiple threads that hit the microinstruction cache to all microinstructions of the multiple threads within the sampling window; and The regulation strategy is generated based on the microinstruction cache hit rate of each of the multiple threads and the total microinstruction cache hit rate.

3. The method according to claim 2, wherein: Determining the control strategy based on the microinstruction cache hit rate of each of the multiple threads and the total microinstruction cache hit rate includes: In response to the total hit rate of the microinstruction cache being higher than or equal to a hit rate threshold, determining that the regulation strategy includes storing a target microinstruction among the microinstructions of each of the plurality of threads into the microinstruction cache; In response to the total microinstruction cache hit rate being lower than the hit rate threshold, the regulation strategy is determined according to the microinstruction cache hit rate of each of the plurality of threads and the hit rate threshold.

4. The method according to claim 3, wherein: In response to the total microinstruction cache hit rate being lower than the hit rate threshold, determining the regulation strategy according to the microinstruction cache hit rate of each of the plurality of threads and the hit rate threshold, including: In response to the total microinstruction cache hit rate being lower than the hit rate threshold, selecting a target thread whose microinstruction cache hit rate meets the condition from the microinstruction cache hit rate of each of the multiple threads; Mark thread; and Determining the regulation strategy includes writing the microinstructions of the target thread into the microinstruction cache, and not writing the microinstructions of the remaining threads of the plurality of threads except the target thread into the microinstruction cache.

5. The method according to claim 4, wherein In response to the total microinstruction cache hit rate being lower than the hit rate threshold, selecting a target thread whose microinstruction cache hit rate meets the condition from the microinstruction cache hit rate of each of the multiple threads, comprising: In response to the total microinstruction cache hit rate being lower than the hit rate threshold, the target thread is obtained by excluding the object thread having the lowest microinstruction cache hit rate among the multiple threads.

6. The method according to claim 4 or 5, wherein: In response to the total microinstruction cache hit rate being lower than the hit rate threshold, selecting a target thread whose microinstruction cache hit rate meets the condition according to the microinstruction cache hit rate of each of the multiple threads, including: sorting the plurality of threads according to a microinstruction cache hit rate of each of the plurality of threads, sequentially and preferentially excluding a target thread having the lowest microinstruction cache hit rate among the plurality of threads, and calculating a total microinstruction cache hit rate of the remaining threads after excluding the target thread, until the total microinstruction cache hit rate of the remaining threads is higher than or equal to the hit rate threshold; and The remaining threads corresponding to the remaining threads whose total microinstruction cache hit rates are higher than or equal to the hit rate threshold are used as the target threads.

7. The method according to any one of claims 1 to 6, wherein: Obtaining hit information of the microinstructions of the multiple threads within a sampling window hitting the microinstruction cache, including: monitoring a first number of microinstructions from a decoder and a second number of microinstructions from a microinstruction cache for each of the plurality of threads, The first number and the second number serve as the hit information.

8. The method according to any one of claims 1 to 7, wherein: The sampling window includes a number of clock cycles within a preset range.

9. The method according to claim 8, wherein Controlling allocation of resources of the microinstruction cache according to the regulation strategy includes: In a control window after the sampling window ends, allocation of resources of the microinstruction cache is controlled according to the control strategy.

10. The method according to claim 9, wherein: Within the sampling window, target microinstructions in the microinstructions of each of the multiple threads are stored in the microinstruction cache.

11. The method according to claim 9 or 10, wherein: The sampling window and the control window serve as a control cycle, and the method further includes: At the end of a regulation cycle, the number of cycles of the clock cycle is re-counted.

12. The method according to claim 9 or 10, wherein: The time length of the control window is the same as the time length of the sampling window.

13. The method according to any one of claims 3 to 6, wherein: The target microinstructions are obtained by decoding the core instructions of each thread, wherein each thread includes the core instructions and non-core instructions, and the importance of the core instructions is greater than that of the non-core instructions.

14. A processor configured to execute multiple threads concurrently, wherein: The processor includes: microinstruction cache; a monitor coupled to the microinstruction cache and configured to obtain hit information of microinstructions of the plurality of threads hitting the microinstruction cache within a sampling window, and determine a control strategy based on the hit information; and The controller is coupled to the microinstruction cache and the monitor, and is configured to obtain the regulation policy provided by the monitor and control allocation of resources of the microinstruction cache according to the regulation policy.

15. The processor of claim 14, further comprising: a decoder coupled to the monitor and configured to decode the instructions of each thread to obtain microinstructions of each thread; The monitor is configured to obtain a first number of microinstructions from a decoder and a second number of microinstructions from a microinstruction cache for each of the multiple threads, wherein the first number and the second number serve as the hit information.

16. The processor of claim 15, further comprising: a buffer, wherein an input end of the buffer is coupled to an output end of the controller, an output end of the buffer is coupled to the microinstruction cache, the buffer comprising a plurality of buffers, the plurality of buffers corresponding one-to-one to the microinstructions of the plurality of threads, and configured to store the microinstructions of the plurality of threads, and the buffer is configured to write the microinstructions in the buffers into the microinstruction cache, The decoder is also coupled to the input terminal of the controller. Wherein, the controller is configured to: according to the control strategy, control the decoder to provide Whether the microinstructions of the current thread among the multiple threads are written into the buffer corresponding to the current thread.

17. An electronic device comprising: The processor according to any one of claims 14 to 16.

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