Display panel and display device

Abstract

A display panel, comprising: a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of gate driver circuits, a first group of data fan-out lines, a second group of data fan-out lines, a first group of control signal lines, a second group of control signal lines, a first group of electrostatic discharge circuits and a second group of electrostatic discharge circuits. The orthographic projections of the first group of data fan-out lines and the first group of control signal lines on the substrate overlap, and the orthographic projections of the second group of data fan-out lines and the second group of control signal lines on the substrate overlap. The first group of electrostatic discharge circuits are connected to the first group of control signal lines, and the second group of electrostatic discharge circuits are connected to the second group of control signal lines. The first group of electrostatic discharge circuits and the second group of electrostatic discharge circuits are located between the first group of data fan-out lines and the second group of data fan-out lines, the first group of electrostatic discharge circuits are located on the side of the first group of control signal lines away from a bending area, and the second group of electrostatic discharge circuits are located on the side of the second group of control signal lines away from the bending area.

Description

Display panel and display device

[0001] This application claims priority to the Chinese patent application filed on March 5, 2024, with application number 202410251827.3 and invention name “Display Panel and Display Device”, the content of which should be understood as incorporated into this application by reference. Technical Field

[0002] This article relates to but is not limited to the field of display technology, and in particular to a display panel and a display device. Background Art

[0003] Organic light-emitting diodes (OLEDs) and quantum-dot light-emitting diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, displays using OLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field. Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] Embodiments of the present application provide a display panel and a display device.

[0006] In one aspect, this embodiment provides a display panel comprising: a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of gate driver circuits, a plurality of data fan-out lines, a plurality of control signals, and a plurality of first electrostatic discharge circuits. The substrate comprises a display area and a frame area surrounding the display area. The frame area comprises a first frame area and a second frame area, the first frame area and the second frame area being connected. The first frame area comprises a first fan-out area, a bend area, and a second fan-out area, arranged sequentially away from the display area. A plurality of sub-pixels are located in the display area and on one side of the substrate. A plurality of data lines are located in the display area, the plurality of sub-pixels being electrically connected to the plurality of data lines, and the plurality of data lines being configured to provide data signals to the plurality of sub-pixels. A plurality of gate driver circuits are located in the second frame area and electrically connected to the plurality of sub-pixels, and the plurality of gate driver circuits being configured to provide a plurality of pixel control signals to the plurality of sub-pixels. A plurality of data fan-out lines and a plurality of control signal lines are located in the first frame area; the plurality of data fan-out lines are electrically connected to the plurality of data lines, and a portion of the plurality of control signal lines are electrically connected to the plurality of gate driver circuits. The plurality of data fan-out lines include a first group of data fan-out lines and a second group of data fan-out lines. The plurality of control signal lines include a first group of control signal lines and a second group of control signal lines. The first group of data fan-out lines overlaps with the first group of control signal lines in their orthographic projections on the substrate, and the second group of data fan-out lines overlaps with the second group of control signal lines in their orthographic projections on the substrate. A plurality of first electrostatic discharge circuits are located in the first border region. The plurality of first electrostatic discharge circuits include a first group of electrostatic discharge circuits and a second group of electrostatic discharge circuits located in the second fan-out region. The first group of electrostatic discharge circuits is connected to the first group of control signal lines, and the second group of electrostatic discharge circuits is connected to the second group of control signal lines. The first and second groups of electrostatic discharge circuits are located between the first and second groups of data fan-out lines, the first group of electrostatic discharge circuits being adjacent to the first group of data fan-out lines, and the second group of electrostatic discharge circuits being adjacent to the second group of data fan-out lines. The first group of electrostatic discharge circuits is located on a side of the first group of control signal lines away from the bending region, and the second group of electrostatic discharge circuits is located on a side of the second group of control signal lines away from the bending region.

[0007] In some exemplary embodiments, the display panel further includes: a first power fan-out line located in the second fan-out region; the first power fan-out line includes a fan-out main portion and a first fan-out extension portion, the fan-out main portion extending along a first direction; the first fan-out extension portion is connected to the fan-out main portion, is located on a side of the fan-out main portion away from the bending region, and extends along a second direction, the first direction intersecting the second direction; and the first and second groups of electrostatic discharge circuits are located on either side of the first fan-out extension portion along the first direction.

[0008] In some exemplary embodiments, the plurality of first electrostatic discharge circuits further include: a third group of electrostatic discharge circuits and a fourth group of electrostatic discharge circuits located in the second fan-out region; the third group of electrostatic discharge circuits is connected to the first group of control signal lines, and the fourth group of electrostatic discharge circuits is connected to the second group of control signal lines. The first power fan-out line further includes: a second fan-out extension and a third fan-out extension, each of which is connected to the fan-out main body and located on either side of the first fan-out extension along the first direction. The third group of electrostatic discharge circuits is located on a side of the first group of data fan-out lines away from the second group of data fan-out lines and is surrounded by the first group of control signal lines, the first group of data fan-out lines, and the second fan-out extension. The fourth group of electrostatic discharge circuits is located on a side of the second group of data fan-out lines away from the first group of data fan-out lines and is surrounded by the second group of control signal lines, the second group of data fan-out lines, and the third fan-out extension.

[0009] In some exemplary embodiments, the plurality of first electrostatic discharge circuits further include: a fifth group of electrostatic discharge circuits and a sixth group of electrostatic discharge circuits located in the second fan-out region; the fifth group of electrostatic discharge circuits is connected to the first group of control signal lines, and the sixth group of electrostatic discharge circuits is connected to the second group of control signal lines. The fifth group of electrostatic discharge circuits is located on a side of the first group of data fan-out lines away from the second group of data fan-out lines, and on a side of the first group of control signal lines away from the bending region; the sixth group of electrostatic discharge circuits is located on a side of the second group of data fan-out lines away from the first group of data fan-out lines, and on a side of the second group of control signal lines away from the bending region.

[0010] In some exemplary embodiments, the plurality of gate drive circuits include: a first group of gate drive circuits and a second group of gate drive circuits; the first group of gate drive circuits and the second group of gate circuits are located on both sides of the display area. The display panel further includes: a plurality of second electrostatic discharge circuits located in the second border area. The plurality of second electrostatic discharge circuits include: a seventh group of electrostatic discharge circuits and an eighth group of electrostatic discharge circuits; the seventh group of electrostatic discharge circuits is connected to a portion of the control signal lines in the first group of control signal lines and is adjacent to the starting position of the first group of gate drive circuits; the eighth group of electrostatic discharge circuits is connected to a portion of the control signal lines in the second group of control signal lines and is adjacent to the starting position of the second group of gate drive circuits.

[0011] In some exemplary embodiments, the display panel further includes: a plurality of multiplexing circuits located in the border area and arranged adjacent to the display area; the plurality of control signal lines further include: a plurality of control signal lines for providing multiplexing control signals to the plurality of multiplexing circuits; each multiplexing circuit includes a plurality of multiplexing control transistors, and the plurality of multiplexing control transistors within the plurality of multiplexing circuits are arranged in the same manner.

[0012] In some exemplary embodiments, the plurality of multiplexing control transistors of each multiplexing circuit are arranged sequentially along the first direction.

[0013] In some exemplary embodiments, the second border region includes: a first corner region and a second corner region located on both sides of the first fan-out region. The plurality of multiplexing circuits include: a first group of multiplexing circuits located in the first fan-out region and a plurality of second groups of multiplexing circuits located in the first corner region and the second corner region of the second border region; the plurality of second groups of multiplexing circuits are arranged in a stair-like manner along an edge of the display region.

[0014] In some exemplary embodiments, the display panel further includes: a first peripheral power line located in the first fan-out area, and a first power fan-out line located in the second fan-out area; the first peripheral power line is electrically connected to the first power fan-out line; and the first peripheral power line is located on a side of the first group of multiplexing circuits away from the display area.

[0015] In some exemplary embodiments, the display panel further includes: a plurality of peripheral touch lines located in the first fan-out area; the plurality of peripheral touch lines are located on a side of the first peripheral power line away from the substrate, and the orthographic projection of the plurality of peripheral touch lines on the substrate at least partially overlaps with the orthographic projection of the first peripheral power line on the substrate.

[0016] In some exemplary embodiments, the display panel further includes: a plurality of peripheral control lines located in the first fan-out region, at least one of the plurality of peripheral control lines including: a first peripheral line segment and a second peripheral line segment connected to each other, the first peripheral line segment being located on a side of the first peripheral power line closer to the substrate, and the orthographic projection of the first peripheral line segment on the substrate partially overlapping the orthographic projection of the first peripheral power line on the substrate; and the orthographic projection of the second peripheral line segment on the substrate not overlapping the orthographic projection of the first peripheral power line on the substrate. The bending region is provided with a plurality of control bending lines, the first peripheral line segment being connected to at least one control bending line. The plurality of control bending lines are electrically connected to the plurality of control signal lines.

[0017] In some exemplary embodiments, the first peripheral line segment includes: a first routing line and a second routing line located in different conductive layers, wherein the orthographic projection of the first routing line on the substrate overlaps the orthographic projection of the second routing line on the substrate. The first routing line and the second routing line are connected to the at least one control bending line via a first connecting electrode; the first connecting electrode is located on a side of the first routing line and the second routing line away from the substrate, and the at least one control bending line is located on a side of the first connecting electrode away from the substrate.

[0018] In some exemplary embodiments, the first routing line is located in a first gate metal layer, the second routing line is located in a second gate metal layer, the first connecting electrode is located in a first source / drain metal layer, and the at least one control bending line is located in a second source / drain metal layer.

[0019] In some exemplary embodiments, the bending region is further provided with four groups of first power bending lines, a first group of data bending lines, and a second group of data bending lines; the four groups of first power bending lines include: a first group of first power bending lines, a second group of first power bending lines, a third group of first power bending lines, and a fourth group of first power bending lines arranged along a first direction. The plurality of control bending lines are located between the second group of first power bending lines and the third group of first power bending lines, and are connected to the first group of control signal lines and the second group of control signal lines. The first group of data bending lines is located on a side of the first group of first power bending lines away from the second group of first power bending lines, and is connected to the first group of data fan-out lines. The second group of data bending lines is located on a side of the fourth group of first power bending lines away from the third group of first power bending lines, and is connected to the second group of data fan-out lines.

[0020] On the other hand, this embodiment provides a display device, including the display panel as described above.

[0021] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. Other advantages of the present application can be realized and obtained by the solutions described in the description and the drawings.

[0022] Summary of the Figures

[0023] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0024] FIG1 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure;

[0025] FIG2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0026] FIG3 is a partial cross-sectional schematic diagram of a display area according to at least one embodiment of the present disclosure;

[0027] FIG4 is a diagram illustrating an exemplary configuration of a gate drive circuit according to at least one embodiment of the present disclosure;

[0028] FIG5 is a partial plan view of a first frame region according to at least one embodiment of the present disclosure;

[0029] FIG6 is an equivalent circuit diagram of a multiplexing circuit according to at least one embodiment of the present disclosure;

[0030] FIG7A is a partial enlarged schematic diagram of area SS1 in FIG5 ;

[0031] FIG7B is a schematic diagram of the multiplexing circuit after forming the second gate metal layer in FIG7A ;

[0032] FIG8A is a partial enlarged schematic diagram of area SS2 in FIG5 ;

[0033] FIG8B is a schematic diagram of the first peripheral power line in FIG8A ;

[0034] FIG9A is another partially enlarged schematic diagram of the area SS2 in FIG5 ;

[0035] 9B is a schematic diagram of the first gate metal layer, the second gate metal layer, and the first source and drain metal layer in FIG. 9A ;

[0036] FIG9C is a schematic diagram of the second gate metal layer in FIG9A ;

[0037] FIG9D is a schematic diagram of the first gate metal layer in FIG9A ;

[0038] FIG10 is an equivalent circuit diagram of a first electrostatic discharge circuit according to at least one embodiment of the present disclosure;

[0039] 11 and 12 are schematic diagrams of the first set of electrostatic discharge circuits in FIG. 5 ;

[0040] 13 and 14 are schematic diagrams of the second set of electrostatic discharge circuits in FIG. 5 ;

[0041] FIG. 15 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0042] Details

[0043] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0044] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0045] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. "Multiple" in this disclosure means two or more.

[0046] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0047] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, removable connections, or integral connections; they can refer to mechanical connections or connections; they can refer to direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the circumstances.

[0048] In this specification, a transistor refers to a device that includes at least three terminals: a gate (gate electrode), a drain, and a source. A transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source. In this specification, the channel region refers to the region through which current primarily flows.

[0049] In this specification, the first electrode can be a drain and the second electrode can be a source, or the first electrode can be a source and the second electrode can be a drain. Furthermore, the gate electrode can also be referred to as a control electrode. The functions of "source" and "drain" are sometimes interchangeable when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source" and "drain" can be interchangeable.

[0050] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with multiple functions.

[0051] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0052] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.

[0053] In this specification, "about" and "substantially" are used without strict limits and allow for process and measurement errors. In this disclosure, "substantially the same" means that the numerical values ​​differ by less than 10%.

[0054] In this specification, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. Throughout this specification, "A extends along direction B" means "the main portion of A extends along direction B."

[0055] As used herein, "A and B are in the same layer" means that A and B are formed simultaneously through the same patterning process. "Same layer" does not always mean that the thickness or height of the layer is the same in a cross-sectional view. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection of A, or that the orthographic projection of A covers the orthographic projection of B.

[0056] To better meet people's needs for various functions and a better screen experience (for example, displays with an ultra-high screen-to-body ratio), narrow-border display designs are gradually becoming the mainstream form factor of display devices. However, in some implementations, the layout of some signal lines and circuits in the border area of ​​the display panel is not conducive to achieving a narrow border on the display panel.

[0057] This embodiment provides a display panel comprising: a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of gate driver circuits, a plurality of data fan-out lines, a plurality of control signal lines, and a plurality of first electrostatic discharge circuits. The substrate comprises a display area and a frame area surrounding the display area. The frame area comprises a first frame area and a second frame area, the first frame area and the second frame area being connected. The first frame area comprises a first fan-out area, a bend area, and a second fan-out area, arranged sequentially away from the display area. The plurality of sub-pixels are located in the display area and on one side of the substrate. The plurality of data lines are located in the display area, the plurality of sub-pixels being electrically connected to the plurality of data lines, and the plurality of data lines being configured to provide data signals to the plurality of sub-pixels. The plurality of gate driver circuits are located in the second frame area and electrically connected to the plurality of sub-pixels, and the plurality of gate driver circuits being configured to provide a plurality of pixel control signals to the plurality of sub-pixels. The plurality of data fan-out lines and the plurality of control signal lines are located in the first frame area; the plurality of data fan-out lines are electrically connected to the plurality of data lines, and a portion of the plurality of control signal lines are electrically connected to the plurality of gate driver circuits. The plurality of data fan-out lines include a first group of data fan-out lines and a second group of data fan-out lines, and the plurality of control signal lines include a first group of control signal lines and a second group of control signal lines. The orthographic projections of the first group of data fan-out lines and the first group of control signal lines on the substrate overlap, and the orthographic projections of the second group of data fan-out lines and the second group of control signal lines on the substrate overlap. The plurality of first electrostatic discharge circuits are located in the first border region; the plurality of first electrostatic discharge circuits include a first group of electrostatic discharge circuits and a second group of electrostatic discharge circuits located in the second fan-out region; the first group of electrostatic discharge circuits is connected to the first group of control signal lines, and the second group of electrostatic discharge circuits is connected to the second group of control signal lines. The first group of electrostatic discharge circuits and the second group of electrostatic discharge circuits are located between the first group of data fan-out lines and the second group of data fan-out lines, the first group of electrostatic discharge circuits is adjacent to the first group of data fan-out lines, and the second group of electrostatic discharge circuits is adjacent to the second group of data fan-out lines. The first group of electrostatic discharge circuits is located on the side of the first group of control signal lines away from the bending region, and the second group of electrostatic discharge circuits is located on the side of the second group of control signal lines away from the bending region.

[0058] In this example, A and B being adjacent means that A and B are close to each other and there is no other circuit structure between them.

[0059] The display panel provided in this embodiment can optimize the arrangement of the first electrostatic release circuit in the first frame area by setting the first electrostatic release circuit in the second fan-out area, which is beneficial to optimizing the wiring space in the first frame area and thus conducive to narrow frame design.

[0060] In some exemplary embodiments, the display panel may further include: a first power fan-out line located in the second fan-out area. The first power fan-out line may include: a fan-out main body and a first fan-out extension, the fan-out main body may extend along a first direction, the first fan-out extension is connected to the fan-out main body, is located on a side of the fan-out main body away from the bending area, and extends along a second direction, the first direction intersecting the second direction. For example, the first direction may be perpendicular to the second direction. The first group of electrostatic release circuits and the second group of electrostatic release circuits may be located on both sides of the first fan-out extension along the first direction. This example can optimize the arrangement of the first electrostatic release circuit in the first border area, which is conducive to optimizing the wiring space of the first border area.

[0061] In some exemplary embodiments, the plurality of first electrostatic discharge circuits may further include: a third group of electrostatic discharge circuits and a fourth group of electrostatic discharge circuits located in the second fan-out area. The third group of electrostatic discharge circuits is connected to the first group of control signal lines, and the fourth group of electrostatic discharge circuits is connected to the second group of control signal lines. The first power fan-out line may further include: a second fan-out extension and a third fan-out extension, the second fan-out extension and the third fan-out extension being connected to the fan-out main body and being located on both sides of the first fan-out extension along the first direction. The third group of electrostatic discharge circuits may be located on a side of the first group of data fan-out lines away from the second group of data fan-out lines, and be surrounded by the first group of control signal lines, the first group of data fan-out lines, and the second fan-out extension. The fourth group of electrostatic discharge circuits may be located on a side of the second group of data fan-out lines away from the first group of data fan-out lines, and be surrounded by the second group of control signal lines, the second group of data fan-out lines, and the third fan-out extension. This example can make full use of the vacant space in the second fan-out area to increase the number of first electrostatic discharge circuits.

[0062] In some exemplary embodiments, the plurality of first electrostatic discharge circuits may further include: a fifth group of electrostatic discharge circuits and a sixth group of electrostatic discharge circuits located in the second fan-out area; the fifth group of electrostatic discharge circuits is connected to the first group of control signal lines, and the sixth group of electrostatic discharge circuits is connected to the second group of control signal lines. The fifth group of electrostatic discharge circuits may be located on a side of the first group of data fan-out lines away from the second group of data fan-out lines, and on a side of the first group of control signal lines away from the bending area. The sixth group of electrostatic discharge circuits may be located on a side of the second group of data fan-out lines away from the first group of data fan-out lines, and on a side of the second group of control signal lines away from the bending area. This example can make full use of the vacant space in the second fan-out area to increase the number of first electrostatic discharge circuits.

[0063] In some exemplary embodiments, the display panel may further include: a plurality of multiplexing circuits located in the border region and disposed adjacent to the display region. The plurality of control signal lines may further include: a plurality of control signal lines that provide multiplexing control signals to the plurality of multiplexing circuits. Each multiplexing circuit may include a plurality of multiplexing transistors, and the plurality of multiplexing transistors within the plurality of multiplexing circuits may be arranged in the same manner. In this example, by providing a plurality of multiplexing circuits with the same arrangement, the parasitic capacitance consistency between the signals may be ensured, thereby reducing interference caused by the parasitic capacitance.

[0064] In some exemplary embodiments, the display panel may further include: a first peripheral power line located in the first fan-out area, and a first power fan-out line located in the second fan-out area; the first peripheral power line is electrically connected to the first power fan-out line. The first peripheral power line may be located on a side of the first group of multiplexing circuits away from the display area. In some examples, the display panel may further include: a plurality of peripheral touch lines located in the first fan-out area; the plurality of peripheral touch lines may be located on a side of the first peripheral power line away from the substrate, and the orthographic projections of the plurality of peripheral touch lines on the substrate may at least partially overlap with the orthographic projection of the first peripheral power line on the substrate. In this example, the first peripheral power line may be used in the first fan-out area to shield the peripheral touch lines to prevent the peripheral touch lines from being interfered with by signals from the display structure layer.

[0065] The solution of this embodiment is illustrated below through some examples.

[0066] FIG1 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure. In some examples, as shown in FIG1 , the display panel may include: a display area AA and a border area BB located around the display area AA. The border area BB may include: a first border area B1 located on one side of the display area AA and a second border area B2 located on the remaining sides of the display area AA. The first border area B1 may be located on one side of the display area AA along the second direction Y. The first border area B1 may be connected to the second border area B2. For example, the first border area B1 may be the lower border area of ​​the display panel; the second border area B2 may include: a left border area, a right border area, and a top border area of ​​the display panel.

[0067] In some examples, as shown in FIG1 , the display area AA may be a flat area including a plurality of sub-pixels P constituting a pixel array, and the plurality of sub-pixels P may be configured to display a dynamic image or a still image. The display area AA may be referred to as an active area. In some examples, the display area AA may be circular or elliptical. However, this embodiment is not limited thereto. For example, the display area may be other shapes such as a rectangle. In some examples, the display panel may be a flexible panel, and thus the display panel may be deformable, such as being curled, bent, folded, or rolled up.

[0068] In some examples, as shown in FIG1 , the display area AA may include: a display structure layer provided on a substrate, or may include a display structure layer and a touch structure layer provided in sequence on a substrate. For example, the display panel may integrate a touch structure to form a structure in which the touch structure is on a thin film package (Touch on Thin Film Encapsulation, referred to as Touch on TFE). The Touch on TFE structure mainly includes a Flexible Multi-Layer On Cell (FMLOC) structure and a Flexible Single-Layer On Cell (FSLOC) structure. The FMLOC structure is based on the working principle of mutual capacitance detection. Generally, two layers of metal are used to form the driving (Tx) electrode and the sensing (Rx) electrode. The driving chip (IC) realizes the touch action by detecting the mutual capacitance between the driving electrode and the sensing electrode. The FSLOC structure is based on the working principle of self-capacitance (or voltage) detection. Generally, a single layer of metal is used to form the touch electrode. The integrated circuit realizes the touch action by detecting the self-capacitance (or voltage) of the touch electrode.

[0069] In some examples, the display structure layer may include a plurality of sub-pixels P, a plurality of gate lines GL, and a plurality of data lines DL. The plurality of gate lines GL may extend along a first direction X, and the plurality of data lines DL may extend along a second direction Y. The orthographic projections of the plurality of gate lines GL and the plurality of data lines DL on the substrate may intersect to form a plurality of sub-pixel regions. One sub-pixel P may be arranged in one sub-pixel region. The plurality of data lines DL may be electrically connected to the plurality of sub-pixels P, and the plurality of data lines DL may be configured to provide data signals to the plurality of sub-pixels P. The plurality of gate lines GL may be electrically connected to the plurality of sub-pixels P, and the plurality of gate lines GL may be configured to provide pixel control signals to the plurality of sub-pixels P. For example, the pixel control signal may include a scan signal, or may include a scan signal and a light-emitting control signal, or may include a scan signal, a reset control signal, and a light-emitting control signal.

[0070] In some examples, as shown in FIG1 , the first direction X may be an extending direction (e.g., a row direction) of the gate lines GL in the display area AA, and the second direction Y may be an extending direction (e.g., a column direction) of the data lines DL in the display area AA. The first direction X and the second direction Y may intersect each other, for example, may be perpendicular to each other.

[0071] In some examples, a pixel unit of the display area AA may include three sub-pixels, and the three sub-pixels may be a first sub-pixel emitting a first color light (e.g., red light), a second sub-pixel emitting a second color light (e.g., green light), and a third sub-pixel emitting a third color light (e.g., blue light). However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, and the four sub-pixels may be a sub-pixel emitting red light, a sub-pixel emitting green light, a sub-pixel emitting blue light, and a sub-pixel emitting white light. For another example, a pixel unit may include four sub-pixels, and the four sub-pixels may include a sub-pixel emitting red light, a sub-pixel emitting blue light, and two sub-pixels emitting green light.

[0072] In some examples, a sub-pixel may include: a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. In the above circuit structure, T refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors. In other examples, the multiple transistors in the pixel circuit may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield.

[0073] In some examples, the shape of the light-emitting elements of a sub-pixel can be rectangular, rhombus, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels can be arranged horizontally, vertically, or in a triangular pattern; when a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged horizontally, vertically, or in a square pattern. However, this embodiment is not limited to this.

[0074] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, which may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as needed. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0075] Figure 2 is an equivalent circuit diagram of a pixel circuit of at least one embodiment of the present disclosure. The pixel circuit of this example is illustrated using an 8T1C structure as an example. In some examples, as shown in Figure 2, the pixel circuit of this example may include eight transistors (i.e., a first transistor T1 to an eighth transistor T8) and a storage capacitor Cst. The first transistor T1 may also be referred to as a first reset transistor, the second transistor T2 may also be referred to as a threshold compensation transistor, the third transistor T3 may also be referred to as a drive transistor, the fourth transistor T4 may also be referred to as a data write transistor, the fifth transistor T5 may also be referred to as a first light-emitting control transistor, the sixth transistor T6 may also be referred to as a second light-emitting control transistor, the seventh transistor T7 may also be referred to as a second reset transistor, and the eighth transistor T8 may also be referred to as a third reset transistor. The light-emitting element EL may include an anode, a cathode, and an organic light-emitting layer disposed between the anode and the cathode.

[0076] In some examples, the first transistor T1 and the third transistor T3 to the eighth transistor T8 may be first-type transistors, such as P-type transistors, and the second transistor T2 may be a second-type transistor, such as N-type transistors. However, this embodiment is not limited to this. For example, the plurality of transistors in the pixel circuit may all be P-type transistors, or may all be N-type transistors.

[0077] In some examples, the first type of transistor of the pixel circuit (for example, including the first transistor T1, the third transistor T3 to the eighth transistor T8) can be a low-temperature polysilicon thin film transistor, and the second type of transistor of the pixel circuit (for example, including the second transistor T2) can be an oxide thin film transistor. The active layer of the low-temperature polysilicon thin film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, while oxide thin film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin film transistors and oxide thin film transistors on a display panel to form a low-temperature polycrystalline oxide (LTPS+Oxide) display panel can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0078] In some examples, as shown in FIG2 , the pixel circuit can be electrically connected to a first scan line GL1, a second scan line GL2, a data line DL, a first power line PL1, a second power line PL2, an emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a third initial signal line INIT3, a first reset control line RST1, and a second reset control line RST2. The first power line PL1 can be configured to provide a constant first voltage signal VDD to the pixel circuit, and the second power line PL2 can be configured to provide a constant second voltage signal VSS to the pixel circuit, with the first voltage signal VDD being greater than the second voltage signal VSS. The first scan line GL1 can be configured to provide a first scan signal SCAN1 to the pixel circuit. The second scan line GL2 can be configured to provide a second scan signal SCAN2 to the pixel circuit. The data line DL can be configured to provide a data signal to the pixel circuit. The emission control line EML can be configured to provide an emission control signal EM to the pixel circuit. The first reset control line RST1 can be configured to provide a first reset control signal RESET1 to the pixel circuit. The second reset control line may be configured to provide a second reset control signal RESET2 to the pixel circuit.

[0079] In some examples, as shown in FIG2 , the gate of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The gate of the fourth transistor T4 is electrically connected to the first scan line GL1, the first electrode of the fourth transistor T4 is electrically connected to the data line DL, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2. The gate of the second transistor T2 is electrically connected to the second scan line GL2, the first electrode of the second transistor T2 is electrically connected to the third node N3, and the second electrode of the second transistor T2 is electrically connected to the first node N1. The gate of the fifth transistor T5 is electrically connected to the emission control line EML, the first electrode of the fifth transistor T5 is electrically connected to the first power line PL1, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2. The gate of the sixth transistor T6 is electrically connected to the emission control line EML, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. The gate of the first transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the third node N3. The first transistor T1 can be configured to reset the third node N3. The gate of the seventh transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. The seventh transistor T7 can be configured to reset the fourth node N4. The gate of the eighth transistor T8 is electrically connected to the second reset control line RST2, the first electrode of the eighth transistor T8 is electrically connected to the third initial signal line INIT3, and the second electrode of the eighth transistor T8 is electrically connected to the second node N2. The eighth transistor T8 can be configured to reset the second node N2. The first electrode of the storage capacitor Cst is electrically connected to the first node N1, and the second electrode of the storage capacitor Cst is electrically connected to the first power line PL1.

[0080] In this example, the first node N1 is the connection point of the storage capacitor Cst, the second transistor T2 and the third transistor T3, the second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4, the eighth transistor T8 and the third transistor T3, the third node N3 is the connection point of the first transistor T1, the third transistor T3, the second transistor T2 and the sixth transistor T6, and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7 and the light emitting element EL.

[0081] The operation process of the pixel circuit shown in Figure 2 is described below. In the pixel circuit, the first transistor T1, the third transistor T3 to the eighth transistor T8 are P-type transistors, and the second transistor T2 is an N-type transistor.

[0082] In some examples, during a frame display period, the operation process of the pixel circuit may include at least: a first stage, a second stage, a third stage, and a fourth stage.

[0083] The first stage is called the first reset stage. The second reset control signal RESET2 provided by the second reset control line RST2 is a low-level signal, turning on the seventh transistor T7 and the eighth transistor T8. The second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, turning on the second transistor T2. The eighth transistor T8 is turned on, allowing the third initial signal provided by the third initial signal line INIT3 to be supplied to the second node N2. The seventh transistor T7 is turned on, allowing the second initial signal provided by the second initial signal line INIT2 to be supplied to the fourth node N4, initializing the fourth node N4. The first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, the first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, and the emission control signal EM provided by the emission control line EML is a high-level signal, turning off the fourth transistor T4, the first transistor T1, the fifth transistor T5, and the sixth transistor T6. During this stage, the light-emitting element EL does not emit light.

[0084] The second phase is called the second reset phase. The first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, turning on the first transistor T1; the second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, turning on the second transistor T2. The first and second transistors T1 and T2 are turned on, causing the first initial signal line provided by the first initial signal line INIT1 to be supplied to the first node N1, initializing the first node N1. The second reset control signal RESET2 provided by the second reset control line RST2 is a high-level signal, the first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, and the emission control signal EM provided by the emission control line EML is a high-level signal, turning off the seventh transistor T7, the eighth transistor T8, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. During this phase, the light-emitting element EL does not emit light.

[0085] The third stage is called the data writing stage or the threshold compensation stage. The first scan signal SCAN1 provided by the first scan line GL1 is a low-level signal, and the fourth transistor T4 is turned on; the second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, and the second transistor T2 is turned on. During this stage, the first electrode of the storage capacitor Cst is at a low level, and the third transistor T3 is turned on. The second transistor T2, the fourth transistor T4, and the third transistor T3 are turned on, so that the data voltage Vdata output by the data line DL is provided to the first node N1 through the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage Vdata output by the data line DL and the threshold voltage of the third transistor T3 is charged into the storage capacitor Cst. The voltage of the first electrode of the storage capacitor Cst (i.e., the first node N1) is Vdata-|Vth|, where Vdata is the data voltage output by the data line DL and Vth is the threshold voltage of the third transistor T3. The first reset control signal RESET1 provided by the first reset control line RST1 is a high level signal, the second reset control signal RESET2 provided by the second reset control line RST2 is a high level signal, and the light-emitting control signal EM provided by the light-emitting control line EML is a high level signal, so that the first transistor T1, the seventh transistor T7, the eighth transistor T8, the fifth transistor T5 and the sixth transistor T6 are disconnected.

[0086] In the fourth stage, the emission control signal EM provided by the emission control line EML can be switched from a high-level signal to a low-level signal, turning on the fifth transistor T5 and the sixth transistor T6. The second scan signal SCAN2 provided by the second scan line GL2 is a low-level signal, turning off the second transistor T2. The first scan signal SCAN1 provided by the first scan line GL1, the first reset control signal RESET1 provided by the first reset control line RST1, and the second reset control signal RESET2 provided by the second reset control line RST2 are high-level signals, turning off the fourth transistor T4, the first transistor T1, the seventh transistor T7, and the eighth transistor T8. The first voltage signal VDD output by the first power line PL1 can provide a driving voltage to the anode of the light-emitting element EL through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, driving the light-emitting element EL to emit light.

[0087] During the driving process of the pixel circuit, the driving current flowing through the third transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is: I=K×(Vgs-Vth) 2 =K×[(VDD-Vdata+|Vth|)-Vth] 2 =K×[VDD-Vdata]2 ;

[0088] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light-emitting element, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data line DL, and VDD is the first voltage signal output by the first power line PL1.

[0089] From the above equation, it can be seen that the current flowing through the light-emitting element is independent of the threshold voltage of the third transistor T3. Therefore, the pixel circuit of this embodiment can effectively compensate for the threshold voltage of the third transistor T3. Moreover, the pixel circuit provided by this embodiment can improve the display quality caused by low frequency and enhance the display effect of the light-emitting element.

[0090] FIG3 is a partial cross-sectional schematic diagram of a display region according to at least one embodiment of the present disclosure. FIG3 illustrates the structure of a sub-pixel in the display region as an example. In this example, the pixel circuit shown in FIG2 includes a low-temperature polysilicon thin-film transistor and an oxide thin-film transistor.

[0091] In some examples, as shown in FIG3 , in a direction perpendicular to the display panel, the display area of ​​the display panel may include at least: a substrate 10, and a circuit structure layer 12, a light-emitting structure layer 13, an encapsulation structure layer 14, and a touch structure layer 15 sequentially disposed on the substrate 10. The display structure layer may include at least the circuit structure layer 12 and the light-emitting structure layer 13. The circuit structure layer 12 may include at least: pixel circuits for multiple sub-pixels, each of which may include multiple transistors and at least one capacitor. The light-emitting structure layer 13 may include at least: light-emitting elements for multiple sub-pixels.

[0092] In some examples, FIG3 illustrates an example of each sub-pixel including a first-type transistor 21, a second-type transistor 22, and a capacitor 23. The first-type transistor 21 may be a low-temperature polysilicon thin-film transistor, and the second-type transistor 22 may be an oxide thin-film transistor.

[0093] In some examples, the circuit structure layer 12 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source / drain metal layer, and a second source / drain metal layer, disposed on the substrate 10. A first insulating layer 101 may be disposed between the first semiconductor layer and the first gate metal layer, and a second insulating layer 102 may be disposed between the first gate metal layer and the second gate metal layer; a third insulating layer 103 may be disposed between the second gate metal layer and the second semiconductor layer; a fourth insulating layer 104 may be disposed between the second semiconductor layer and the third gate metal layer; a fifth insulating layer 105 may be disposed between the third gate metal layer and the first source / drain metal layer; a sixth insulating layer 106 (also referred to as a passivation layer) and a seventh insulating layer 107 (also referred to as a first planarizing layer) may be disposed between the first source / drain metal layer and the second source / drain metal layer; the seventh insulating layer 107 may be located on a side of the sixth insulating layer 106 away from the substrate 10; and an eighth insulating layer 108 (also referred to as a second planarizing layer) may be disposed on a side of the second source / drain metal layer away from the substrate 10. Among them, the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, the fifth insulating layer 105 and the sixth insulating layer 106 can be inorganic insulating layers, and the seventh insulating layer 107 and the eighth insulating layer 108 can be organic insulating layers. However, this embodiment is not limited to this. In other examples, a buffer layer can be further provided on the side of the first semiconductor layer close to the substrate. The buffer layer can prevent harmful substances in the substrate from invading the interior of the display panel and can also increase the adhesion of the film layer in the display panel to the substrate. In other examples, a bottom shielding metal layer (BSM) can be further provided on the side of the buffer layer close to the substrate. The bottom shielding metal layer can be configured to at least partially cover the active layer of the transistor of the pixel circuit to prevent external light from affecting the performance of the transistor. In other examples, the sixth insulating layer can be omitted between the first source and drain metal layer and the second source and drain metal layer, and only the seventh insulating layer can be provided between the first source and drain metal layer and the second source and drain metal layer.

[0094] In some examples, as shown in FIG3 , the first semiconductor layer in the display area may include at least a first active layer 210 of the first-type transistor 21. The first active layer 210 of the first-type transistor 21 may include a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least a first gate 213 of the first-type transistor 21 and a first plate 231 of the capacitor 23. The orthographic projection of the first gate 213 of the first-type transistor 21 on the substrate 10 may overlap the orthographic projection of the channel region 2100 of the first active layer 210 on the substrate 10. The second gate metal layer may include at least a second plate 232 of the capacitor 23 and a third gate 224 of the second-type transistor 22. The orthographic projections of the second plate 232 and the first plate 231 of the capacitor 23 on the substrate 10 may at least partially overlap, for example, they may overlap. The second semiconductor layer may include at least a second active layer 220 of the second-type transistor 22. The third gate metal layer may include at least a second gate 223 of the second-type transistor 22. The orthographic projection of the second gate 223 of the second-type transistor 22 on the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 on the substrate 10. The orthographic projection of the third gate 224 of the second-type transistor 22 on the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 on the substrate 10. The third gate 224 may be the bottom gate of the second-type transistor 22, and the second gate 223 may be the top gate of the second-type transistor 22.

[0095] In some examples, as shown in FIG3 , the first source-drain metal layer in the display area may include at least: a first source 211 and a first drain 212 of the first-type transistor 21, and a second source 221 and a second drain 222 of the second-type transistor 22. The fifth insulating layer 105 may have a plurality of pixel vias (e.g., including a first pixel via, a second pixel via, a third pixel via, and a fourth pixel via) in the display area. The fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 within the first pixel via may be removed to expose at least a portion of the surface of the first region 2101 of the first active layer 210. The fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 within the second pixel via may be removed to expose at least a portion of the surface of the second region 2102 of the first active layer 210. The fifth insulating layer 105, fourth insulating layer 104, and third insulating layer 103 within the third and fourth pixel vias can be removed, exposing at least portions of the surfaces of both ends of the second active layer 220. The first source 211 of the first-type transistor 21 can be electrically connected to the first region 2101 of the first active layer 210 through the first pixel via, and the first drain 212 can be electrically connected to the second region 2102 of the first active layer 210 through the second pixel via. The second source 221 of the second-type transistor 22 can be electrically connected to one end of the second active layer 220 through the third pixel via, and the second drain 222 of the second-type transistor 22 can be electrically connected to the other end of the second active layer 220 through the fourth pixel via. The second source-drain metal layer can include at least a first connecting electrode 241. The first connecting electrode 241 can be electrically connected to the first drain 212 of the first-type transistor 21 of the pixel circuit through a fifth pixel via defined between the sixth and seventh insulating layers 106 and 107. In this example, the first switching electrode 241 can be used to achieve electrical connection between the pixel circuit and the light-emitting element.

[0096] In some examples, the gate lines of the display area may be located in the first gate metal layer and the third gate metal layer, the data lines of the display area may be located in the second source / drain metal layer, and the high-potential power lines of the display area may be located in the second source / drain metal layer. This embodiment is not limited to this.

[0097] In some examples, as shown in FIG3 , the light-emitting structure layer 13 may include a pixel definition layer 134 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 131, an organic light-emitting layer 132, and a second electrode 133. The first electrode 131 of the light-emitting element may be an anode. The first electrode 131 may be disposed on the eighth insulating layer 108 and electrically connected to the first transfer electrode 241 through a sixth pixel via provided in the eighth insulating layer 108. The pixel definition layer 134 is disposed on the first electrode 131 and the eighth insulating layer 108. The pixel definition layer 134 may have multiple pixel openings, each of which may expose at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light-emitting layer 132 may be disposed within a pixel opening and connected to the corresponding first electrode 131. The second electrode 133 may be disposed on and connected to the organic light-emitting layer 132. Driven by the first electrode 131 and the second electrode 133, the organic light-emitting layer 132 may emit light of a corresponding color.

[0098] In some examples, the organic light-emitting layer 132 of the light-emitting element may include an emitting layer (EML), and at least one of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole blocking layer (HBL), an electron blocking layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Driven by the voltage of the first electrode 131 and the second electrode 133, the light-emitting properties of the organic material can be utilized to emit light according to the required grayscale.

[0099] In some examples, the light-emitting layers of light-emitting elements of different colors may be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. In order to reduce the difficulty of the process and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer may adopt a common layer, and the electron injection layer and the electron transport layer on the other side of the light-emitting layer may adopt a common layer. In some examples, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer can be made by a one-time process (a one-time evaporation process or a one-time inkjet printing process), and isolation is achieved by means of a surface step difference of the formed film layer or by surface treatment. For example, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by evaporation using a fine metal mask (FMM) or an open mask (Open Mask), or by inkjet technology.

[0100] In some examples, as shown in FIG3 , the encapsulation structure layer 14 may include a stacked first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143. The first encapsulation layer 141 and the third encapsulation layer 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density and can prevent the intrusion of water, oxygen, and the like. The second encapsulation layer 142 may be disposed between the first and third encapsulation layers 141, 143 to prevent external moisture from entering the light-emitting element. The second encapsulation layer 142 may be made of an organic material, such as a polymer material containing a desiccant or a polymer material that can block moisture, or a polymer resin to planarize the surface of the display panel and relieve stress on the first and third encapsulation layers 141, 143. It may also include a desiccant or other absorbent material to absorb intrusive water, oxygen, and other substances. However, this embodiment is not limited to this. For example, the encapsulation structure layer may have a five-layer stacked structure: inorganic / organic / inorganic / organic / inorganic / inorganic.

[0101] In some examples, the touch structure layer of the display area may include: a plurality of first touch electrodes, a plurality of first connecting portions, a plurality of second touch electrodes, and a plurality of second connecting portions. The plurality of first touch electrodes may be arranged in the same layer, and adjacent first touch electrodes may be connected via the first connecting portions. The plurality of second touch electrodes may be arranged in the same layer, and adjacent second touch electrodes may be connected via the second connecting portions.

[0102] In some examples, as shown in FIG3 , in a direction perpendicular to the display panel, the touch structure layer 15 of the display area may include: a touch buffer layer (TBL) 150, a first touch conductive layer 151, a touch interlayer insulating layer (TLD) 153, a second touch conductive layer 152, and a protective layer 154, which are arranged in sequence. The touch buffer layer 150 and the touch interlayer insulating layer 153 may be inorganic insulating layers, and the protective layer 154 may be an organic insulating layer. For example, the first touch conductive layer 151 may include a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of first connecting portions. The first touch electrodes and the first connecting portions may be an integrated structure connected to each other. The second touch conductive layer 152 may include a plurality of second connecting portions. The second connecting portions may be connected to adjacent second touch electrodes through vias provided in the touch interlayer insulating layer. However, this embodiment is not limited to this. In other examples, the first touch conductive layer may include: a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of second connecting portions, wherein the second touch electrodes and the second connecting portions may be an interconnected integral structure; the second touch conductive layer may include a plurality of first connecting portions, wherein the first connecting portions may be interconnected with adjacent first touch electrodes via vias defined in the touch interlayer insulating layer. In some examples, the first touch electrodes may be drive (Tx) electrodes, and the second touch electrodes may be sense (Rx) electrodes. Alternatively, the first touch electrodes may be sense (Rx) electrodes, and the second touch electrodes may be drive (Tx) electrodes. This embodiment is not limited to this.

[0103] In some examples, the first touch electrode and the second touch electrode may have a rhombus shape, such as a regular rhombus, a horizontally elongated rhombus, or a vertically elongated rhombus. In other examples, the first touch electrode and the second touch electrode may have any one or more of a triangle, a square, a trapezoid, a parallelogram, a pentagon, a hexagon, and other polygonal shapes, which are not limited in the embodiments of the present disclosure.

[0104] In some examples, the first and second touch electrodes may be transparent conductive electrodes. In other examples, the first and second touch electrodes may be in the form of a metal mesh. The metal mesh may be formed by interweaving multiple metal wires. The metal mesh may include multiple mesh patterns, and the mesh pattern may be a polygon formed by multiple metal wires. The metal mesh-type first and second touch electrodes have advantages such as low resistance, small thickness, and fast response speed.

[0105] FIG4 is a diagram illustrating an example of a gate drive circuit configuration according to at least one embodiment of the present disclosure. In some examples, as shown in FIG1 and FIG4 , multiple gate drive circuits may be provided in the second border region B2 of the display panel. The multiple gate drive circuits may be electrically connected to the multiple sub-pixels P within the display region AA via multiple gate lines. The multiple gate drive circuits may be configured to provide multiple pixel control signals to the multiple sub-pixels P. In some examples, using the pixel circuit shown in FIG2 as an example, the multiple pixel control signals may include: a first scan signal, a second scan signal, a light emission control signal, a first reset control signal, and a second reset control signal.

[0106] In some examples, the multiple gate drive circuits may include: a first scan drive circuit 261, a second scan drive circuit 262, a light emitting drive circuit 251, a first reset drive circuit 252, and a second reset drive circuit 253. The first scan drive circuit 261 can be configured to provide a first scan signal to multiple rows of pixel circuits in the display area AA. The second scan drive circuit 262 can be configured to provide a second scan signal to multiple rows of pixel circuits in the display area AA. The light emitting drive circuit 251 can be configured to provide a light emitting control signal to multiple rows of pixel circuits in the display area AA. The first reset drive circuit 252 can be configured to provide a first reset control signal to multiple rows of pixel circuits in the display area AA. The second reset drive circuit 253 can be configured to provide a second reset control signal to multiple rows of pixel circuits in the display area AA. Each gate drive circuit may include multiple cascaded drive units.

[0107] In some examples, the multiple gate drive circuits may include: a first group of gate drive circuits and a second group of gate drive circuits; the first group of gate drive circuits may be located on a side of the display area AA opposite to the first direction X, and the second group of gate drive circuits may be located on a side of the display area AA in the first direction X. For example, the first group of gate drive circuits may be located in the left border area of ​​the second border area B2, and the second group of gate drive circuits may be located in the right border area of ​​the second border area B2. In some examples, the first group of gate drive circuits may include the following three gate drive circuits: a light-emitting drive circuit 251, a first reset drive circuit 252, and a second reset drive circuit 253; and the second group of gate drive circuits may include the following two gate drive circuits: a first scan drive circuit 261 and a second scan drive circuit 262. For example, in the left border area of ​​the second border area B2, the light-emitting drive circuit 251, the first reset drive circuit 252, and the second reset drive circuit 253 may be arranged sequentially in the first direction X in a direction away from the display area AA; in the right border area of ​​the second border area B2, the first scan drive circuit 261 and the second scan drive circuit 262 may be arranged sequentially in the first direction X in a direction away from the display area AA. However, this embodiment is not limited to this.

[0108] In some examples, the first scan driving circuit 261 may include a plurality of cascaded first scan driving units (e.g., GP(1) to GP(4)). Each stage of the first scan driving unit may be configured to provide a first scan signal to a row of pixel circuits in the display area AA. For example, the first stage of the first scan driving unit GP(1) may be configured to provide a first scan signal to the first row of pixel circuits in the display area AA.

[0109] In some examples, the second scan driving circuit 262 may include a plurality of cascaded second scan driving units (e.g., GN(1) to GN(4)). Each stage of the second scan driving unit may be configured to provide a second scan signal to at least one row of pixel circuits in the display area AA. For example, the first stage of the second scan driving unit GN(1) may be configured to provide a second scan signal to the first row or the first and second rows of pixel circuits in the display area AA.

[0110] In some examples, the light-emitting driving circuit 251 may include a plurality of cascaded light-emitting driving units (e.g., EM(1) to EM(4)). Each level of light-emitting driving units may be configured to provide a light-emitting control signal to at least one row of pixel circuits in the display area AA. For example, the first level of light-emitting driving unit EM(1) may be configured to provide a light-emitting control signal to the first row or the first and second rows of pixel circuits in the display area AA.

[0111] In some examples, the first reset driver circuit 252 can include a plurality of cascaded first reset driver units (e.g., RP(1) to RP(4)). Each stage of the first reset driver unit can be configured to provide a first reset control signal to at least one row of pixel circuits in the display area AA. For example, the first stage of the first reset driver unit RP(1) can be configured to provide a first reset control signal to the first row or the first and second rows of pixel circuits in the display area AA.

[0112] In some examples, the second reset driving circuit 253 may include a plurality of cascaded second reset driving units (e.g., RH(1) to RH(4)). Each stage of the second reset driving unit may be configured to provide a second reset control signal to at least one row of pixel circuits in the display area AA. For example, the first stage of the second reset driving unit RH(1) may be configured to provide a second reset control signal to the first row or the first and second rows of pixel circuits in the display area AA.

[0113] In some examples, as shown in FIG1 , the first bezel area B1 may include: a first fan-out area B11, a bending area B12, a second fan-out area B13, a first signal access area B14, and a second signal access area B15, arranged sequentially in a direction away from the display area AA. The first fan-out area B11 may be connected to the second bezel area B2 and to the display area AA; the bending area B12 may be connected to the first fan-out area B11 and the second fan-out area B13. The bending area B12 may be configured to bend the second fan-out area B13, the first signal access area B14, and the second signal access area B15 toward the back of the display area AA.

[0114] In some examples, the pixel circuit shown in FIG2 requires a relatively large number of gate drive circuits, which increases the number of border traces provided in the first border region B1 of the display panel, hindering the narrow-border design of the display panel. The display panel of this example optimizes the circuits and traces within the first border region B1 to optimize circuit and wiring space, thereby facilitating the realization of a narrow-border display panel while ensuring circuit functionality.

[0115] Figure 5 is a partial plan view of the first border region of at least one embodiment of the present disclosure. Figure 5 provides an overall diagram of the multiplexed data lines in the first fan-out region B11, the bend lines in the bend region B12, and the multiple data fan-out lines in the second fan-out region B13. This embodiment does not limit the number of various types of routing lines.

[0116] In some examples, as shown in Figures 1 and 5, the second border area B2 may be provided with a plurality of gate drive circuits, and the plurality of gate drive circuits may include: a first group of gate drive circuits 25 (for example, including a light-emitting drive circuit 251, a first reset drive circuit 252, and a second reset drive circuit 253) and a second group of gate drive circuits 26 (for example, including a first scan drive circuit 261 and a second scan drive circuit 262). The second border area B2 may include: a first corner area and a second corner area, and the first corner area and the second corner area may be located on both sides of the first fan-out area B11 along the first direction X and connected to the first fan-out area B11. The first group of gate drive circuits 25 may be arranged starting from the connection position between the first corner area and the first fan-out area B11, and the second group of gate drive circuits 26 may be arranged starting from the connection position between the second corner area and the first fan-out area B11. The multiple gate driving circuits within the first group of gate driving circuits 25 can be arranged in sequence along a direction away from the display area AA, and the multiple driving units of each gate driving circuit can be arranged in sequence along the edge shape of the display area AA; the multiple gate driving circuits within the second group of gate driving circuits 26 can be arranged in sequence along a direction away from the display area AA, and the multiple driving units of each gate driving circuit can be arranged in sequence along the edge shape of the display area AA.

[0117] In some examples, as shown in Figure 5, the border area BB may be provided with a plurality of multiplexing circuits arranged adjacent to the display area AA. The plurality of multiplexing circuits may include: a first group of multiplexing circuits 31a located in the first fan-out area B11, and a plurality of second groups of multiplexing circuits 31b located in the first corner area and the second corner area of ​​the second border area B2. The first group of multiplexing circuits 31a may include a plurality of multiplexing circuits arranged along the first direction X, and the second group of multiplexing circuits 31b may include at least one multiplexing circuit or may include a plurality of multiplexing circuits arranged along the first direction X. The number of multiplexing circuits within the first group of multiplexing circuits 31a may be greater than the number of multiplexing circuits within a single second group of multiplexing circuits 31b.

[0118] In some examples, as shown in FIG5 , multiple second multiplexing circuits 31 b can be arranged in a stair-like manner along the edge of the display area AA. Each multiplexing circuit can include multiple multiplexing control transistors, and the multiple multiplexing control transistors within the multiple multiplexing circuits can be arranged in the same manner. For example, the multiple multiplexing control transistors within each multiplexing circuit can be arranged sequentially along the first direction X. In this example, the multiplexing control transistors within the first multiplexing circuit 31 a and the second multiplexing circuit 31 b are arranged in the same manner, which can facilitate routing and ensure consistency in parasitic capacitance between signals.

[0119] FIG6 is an equivalent circuit diagram of a multiplexing circuit of at least one embodiment of the present disclosure. FIG6 is a diagram illustrating a multiplexing circuit 311 as an example. In some examples, as shown in FIG6 , a multiplexing circuit 311 can be electrically connected to nine multiplexing control lines, a multiplexing data line 411, and multiple data lines (e.g., the first data line DL1 to the ninth data line DL9). The multiplexing circuit 311 of this example can transmit the data signal provided by a multiplexing data line 411 to nine data lines. However, this embodiment is not limited to this. In other examples, a multiplexing circuit can transmit the data signal provided by a multiplexing data line to three or six data lines.

[0120] In some examples, the first multiplexing control line 422a is configured to transmit a first multiplexing control signal, the second multiplexing control line 422b is configured to transmit a second multiplexing control signal, the third multiplexing control line 422c is configured to transmit a third multiplexing control signal, the fourth multiplexing control line 422d is configured to transmit a fourth multiplexing control signal, the fifth multiplexing control line 422e is configured to transmit a fifth multiplexing control signal, the sixth multiplexing control line 422f is configured to transmit a sixth multiplexing control signal, the seventh multiplexing control line 422g is configured to transmit a seventh multiplexing control signal, the eighth multiplexing control line 422h is configured to transmit an eighth multiplexing control signal, and the ninth multiplexing control line 422i is configured to transmit a ninth multiplexing control signal.

[0121] In some examples, the multiplexing circuit 311 may include nine multiplexing control transistors (i.e., a first multiplexing control transistor M1 to a ninth multiplexing control transistor M9). The gates of the nine multiplexing control transistors may be connected to different multiplexing control lines, i.e., the gate of the first multiplexing control transistor M1 is connected to the first multiplexing control line 422a, the gate of the second multiplexing control transistor M2 is connected to the second multiplexing control line 422b, the gate of the third multiplexing control transistor M3 is connected to the third multiplexing control line 422c, the gate of the fourth multiplexing control transistor M4 is connected to the fourth multiplexing control line 422d, the gate of the fifth multiplexing control transistor M5 is connected to the fifth multiplexing control line 422e, the gate of the sixth multiplexing control transistor M6 is connected to the sixth multiplexing control line 422f, the gate of the seventh multiplexing control transistor M7 is connected to the seventh multiplexing control line 422g, the gate of the eighth multiplexing control transistor M8 is connected to the eighth multiplexing control line 422h, and the gate of the ninth multiplexing control transistor M9 is connected to the ninth multiplexing control line 422i.

[0122] In some examples, the first electrodes of the nine multiplexing control transistors can all be connected to the same multiplexing data line 411. The second electrodes of the nine multiplexing transistors are respectively connected to different data lines of the display area. For example, the second electrode of the first multiplexing control transistor M1 is connected to the first data line DL1, the second electrode of the second multiplexing control transistor M2 is connected to the second data line DL2, the second electrode of the third multiplexing control transistor M3 is connected to the third data line DL3, the second electrode of the fourth multiplexing control transistor M4 is connected to the fourth data line DL4, the second electrode of the fifth multiplexing control transistor M5 is connected to the fifth data line DL5, the second electrode of the sixth multiplexing control transistor M6 is connected to the sixth data line DL6, the second electrode of the seventh multiplexing control transistor M7 is connected to the seventh data line DL7, the second electrode of the eighth multiplexing control transistor M8 is connected to the eighth data line DL8, and the second electrode of the ninth multiplexing control transistor M9 is connected to the ninth data line DL9. Each data line can be connected to at least one column of pixel circuits PX.

[0123] Figure 7A is a partially enlarged schematic diagram of region SS1 in Figure 5 . Figure 7B is a schematic diagram of the multiplexing circuit after the second gate metal layer is formed in Figure 7A . Figures 7A and 7B primarily illustrate the locations of some of the multiplexing control transistors within the two second groups of multiplexing circuits, briefly illustrate the structure of the pixel circuit PX, and omit the traces extending along the first direction X to which the pixel circuit PX is connected.

[0124] In some examples, as shown in Figures 5, 7A, and 7B, one second multiplexing circuit 31b may correspond to a row of pixel circuits PX. The multiple multiplexing circuits within the second multiplexing circuit 31b may be arranged sequentially along the first direction X, and the multiplexing control transistors within each multiplexing circuit may be arranged sequentially along the first direction X.

[0125] The following describes the film layer structure of the multiplexing control transistor using the multiplexing control transistor M1 as an example. The multiplexing control transistor M1 may include: an active layer M10, a gate electrode M13, a first electrode M11, and a second electrode M12. The active layer M10 of the multiplexing control transistor M1 may be located in the first semiconductor layer, and its orthographic projection on the substrate may be rectangular. The gate electrode M11 of the multiplexing control transistor M1 may be located in the first gate metal layer, for example, and may extend at least along the second direction Y. The orthographic projection of the gate electrode M11 on the substrate overlaps with the orthographic projection of the active layer M10 on the substrate. For example, the orthographic projection of the gate electrode M11 on the substrate may pass through the midline of the active layer M10 along the first direction X. The first electrode M11 may be connected to the first region of the active layer M10, and the second electrode M12 may be connected to the second region of the active layer M10. The first electrode M11 and the second electrode M12 may be located on either side of the gate electrode M13 in the first direction X. The first electrode M11 and the second electrode M12 may be located in the first source / drain metal layer. The first electrode M11 may be connected to the data line DL located in the second source / drain metal layer.

[0126] In some examples, the active layers of multiple multiplexing control transistors within each group of multiplexing circuits can be aligned along the first direction X. The first electrodes of the nine multiplexing control transistors of a multiplexing circuit can be an integrated structure that is interconnected and can be located on the side of the multiple multiplexing control lines close to the display area AA. The integrated structure of the first electrodes of the nine multiplexing control transistors of the multiplexing circuit can be connected to the multiplexed data line 411. The multiplexed data line 411 can be located, for example, in the second gate metal layer, or can be located in the first gate metal layer. For example, a plurality of multiplexed data lines can be alternately arranged in the first gate metal layer and the second gate metal layer, and the orthographic projections of the plurality of multiplexed data lines on the substrate may not overlap. The setting method of this example can save the gap between adjacent multiplexed data lines, which is conducive to optimizing the arrangement space of the multiplexed data lines.

[0127] In some examples, the multiplexing control lines can be located on a side of the multiplexing circuit away from the display area AA. The multiplexing control lines (e.g., including the first multiplexing control line 422a to the ninth multiplexing control line 422i) can be arranged sequentially along a direction away from the display area AA. For example, the multiplexing control lines can be located in the first source-drain metal layer. The gate electrodes of the nine multiplexing control transistors of the multiplexing circuit can be connected to the corresponding multiplexing control lines.

[0128] The arrangement of the multiplexing control transistors in the first multiplexing circuit is similar to the arrangement of the multiplexing control transistors in the second multiplexing circuit, and therefore will not be described in detail here.

[0129] The multiplexing circuit of this example is arranged in a staircase pattern next to the display area. This prevents the data line connected to the second electrode of the multiplexing control transistor from overlapping with the remaining signal lines. This reduces the risk of interference from the remaining signal lines due to parasitic capacitance on the data line, and ensures the consistency of the parasitic capacitance between the multiplexed data lines and multiplexed control lines connected to the multiple multiplexing control transistors and the remaining alternating signals. Furthermore, the multiple multiplexing control transistors of the multiplexing circuit of this example utilize a unified layout design, ensuring the consistency of parasitic capacitance between the signals and improving the display effect.

[0130] In some examples, as shown in FIG5 , the first fan-out region B11 is further provided with a first peripheral power line 43 and second peripheral power lines 44 a and 44 b. The first peripheral power line 43 can be located on a side of the first group of multiplexing circuits 31 a away from the display area AA. Within the first fan-out region B11, the second peripheral power lines 44 a and 44 b can be located on either side of the first peripheral power line 43 along the first direction X. For example, the first peripheral power line 43 and the second peripheral power lines 44 a and 44 b can be located on the first source / drain metal layer.

[0131] In some examples, as shown in FIG5 , the first peripheral power line 43 may include a peripheral main portion 430 , a first peripheral extension portion 431 , and a second peripheral extension portion 432 . The peripheral main portion 430 may extend generally along the first direction X. A first end of the peripheral main portion 430 may be connected to the first peripheral extension portion 431 , and a second end may extend from the second peripheral extension portion 432 . The first peripheral extension portion 431 may extend toward the left side of the second border area B2 , and the second peripheral extension portion 432 may extend toward the right side of the second border area B2 .

[0132] In some examples, as shown in FIG5 , the first peripheral power line 43 may further include four first peripheral connection portions connected to the peripheral body portion 430 . The four first peripheral connection portions may be located on a side of the peripheral body portion 430 near the bending region B12 . The four first peripheral connection portions may be connected in a one-to-one correspondence with the four groups of first power bending lines in the bending region B12 .

[0133] In some examples, as shown in Figure 5, the second peripheral power line 44a can extend toward the left border area of ​​the second border area B2 and be located on the side of the first group of gate drive circuits 25 away from the display area AA; the second peripheral power line 44b can extend toward the right border area of ​​the second border area B2 and be located on the side of the second group of gate drive circuits 26 away from the display area AA.

[0134] In some examples, as shown in FIG5 , the first fan-out area B11 may also be provided with a plurality of multiplexed data lines. The plurality of multiplexed data lines may include: a first group of multiplexed data lines 41a and a second group of multiplexed data lines 41b. The first group of multiplexed data lines 41a may be connected to the multiplexing circuit within the first corner area of ​​the second border area B2 and part of the multiplexing circuit within the first fan-out area B11; the second group of multiplexed data lines 41b may be connected to the multiplexing circuit within the second corner area of ​​the second border area B2 and another part of the multiplexing circuit within the first fan-out area B11. The first group of multiplexed data lines 41a may be located on the side of the second peripheral power line 44a close to the first peripheral power line 43, and the second group of multiplexed data lines 44b may be located on the side of the second peripheral power line 44b close to the first peripheral power line 43.

[0135] In some examples, as shown in FIG5 , the first fan-out area B11 may further be provided with a plurality of peripheral control lines. The plurality of peripheral control lines may include a first group of peripheral control lines 42 a and a second group of peripheral control lines 42 b. The first group of peripheral control lines 42 a and the second group of peripheral control lines 42 b may be adjacent to each other in the first fan-out area B11 near the bend area B12. The first group of peripheral control lines 42 a may extend toward a first corner area of ​​the second border area B2, and the second group of peripheral control lines 42 b may extend toward a second corner area of ​​the second border area B2.

[0136] In some examples, the plurality of peripheral control lines may include: a plurality of drive control lines (e.g., including a start signal line, a clock signal line, a voltage line, etc. connected to a gate drive circuit) and a plurality of multiplexing control lines. The plurality of drive control lines within the first group of peripheral control lines 42a may be connected to the first group of gate drive circuits 25, and the plurality of multiplexing control lines within the first group of peripheral control lines 42a may be connected to the multiplexing circuit within the first corner region and a portion of the multiplexing circuit within the first fan-out region B11. The plurality of drive control lines within the second group of peripheral control lines 42b may be connected to the second group of gate drive circuits 26, and the plurality of multiplexing control lines within the second group of peripheral control lines 42b may be connected to the multiplexing circuit within the second corner region and another portion of the multiplexing circuit within the first fan-out region B11. For example, the orthographic projections of the first group of peripheral control lines 42a and the first group of multiplexing data lines 41a on the substrate may overlap. The orthographic projections of the second group of peripheral control lines 42b and the second group of multiplexing data lines 41b on the substrate may overlap. The multiplexed control lines in each group of peripheral control lines may be located on a side of the multiple drive control lines close to the display area AA, which may be beneficial for optimizing routing paths and reducing routing overlaps.

[0137] FIG8A is a partially enlarged schematic diagram of area SS2 in FIG5 . FIG8B is a schematic diagram of the first peripheral power line in FIG8A . In some examples, as shown in FIG8A and FIG8B , the first fan-out area B11 is further provided with a plurality of peripheral touch traces, and the plurality of peripheral touch traces may include a first group of peripheral touch traces 45a and a second group of peripheral touch traces 45b. The orthographic projections of the plurality of peripheral touch traces on the substrate may overlap with the orthographic projections of the first peripheral power line 43 on the substrate. The plurality of peripheral touch traces may be located on the side of the first peripheral power line 43 away from the substrate. The plurality of peripheral touch traces may be located in a touch structure layer, for example, in the first touch conductive layer or the second touch conductive layer, or may be arranged alternately in the first touch conductive layer and the second touch conductive layer.

[0138] In some examples, as shown in Figures 8A and 8B , the peripheral body 430 of the first peripheral power line 43 includes a first portion 430-1 and a second portion 430-2 interconnected along the second direction Y. The second portion 430-2 can be located on a side of the first portion 430-1 away from the display area AA, and the first portion 430-1 can be connected to the first peripheral extension 431 and the second peripheral extension 432. The length of the second portion 430-2 along the first direction X can be greater than the length of the first portion 430-1 along the first direction X, thereby increasing the overlap area between the peripheral body 430 of the first peripheral power line 43 and the multiple peripheral touch traces. In this example, by positioning the first peripheral power line 43 at the periphery of the multiplexing circuit away from the display area AA and overlapping the first peripheral power line 43 with the multiple peripheral touch traces in the first fan-out area, the peripheral touch traces in the first fan-out area B11 can be shielded from interference from the signal traces of the display structure layer, thereby preventing mutual interference between the peripheral traces of the display structure layer and the touch structure layer.

[0139] Figure 9A is another partially enlarged schematic diagram of region SS2 in Figure 5. Figure 9B is a schematic diagram of the first gate metal layer, the second gate metal layer, and the first source and drain metal layer in Figure 9A. Figure 9C is a schematic diagram of the second gate metal layer in Figure 9A.

[0140] Figure 9D is a schematic diagram of the first gate metal layer in Figure 9 A. Figure 9A takes the partially overlapping area of ​​the first peripheral power line 43 and the plurality of peripheral control lines as an example.

[0141] In some examples, as shown in Figures 9A to 9D , at least one peripheral control line 42 among the plurality of peripheral control lines (e.g., a clock signal line connected to a gate drive circuit) may include a first peripheral line segment 421 and a second peripheral line segment 422 that are connected to each other. The first peripheral line segment 421 may be located on a side of the first peripheral power line 43 that is close to the substrate, and the orthographic projection of the first peripheral line segment 421 on the substrate may partially overlap with the orthographic projection of the first peripheral power line 43 on the substrate, while the orthographic projection of the second peripheral line segment 422 on the substrate may not overlap with the orthographic projection of the first peripheral power line 43 on the substrate.

[0142] In some examples, as shown in Figures 9A to 9D , the first peripheral line segment 421 may include a first trace 4211 and a second trace 4212 located in different conductive layers. For example, the first trace 4211 may be located in the first gate metal layer, and the second trace 4212 may be located in the second gate metal layer. The orthographic projection of the first trace 4211 on the substrate may overlap the orthographic projection of the second trace 4212 on the substrate. The first trace 4211 and the second trace 4212 may be connected to the control bending line 520 of the bending region B12 via the first connecting electrode 521. The first trace 4211 and the second trace 4212 may also be connected to the second peripheral line segment 422. Alternatively, the first trace 4211 and the second trace 4212 may be connected to the second peripheral line segment 422 via the second connecting electrode 522.

[0143] In some examples, the first connection trace 521 and the second connection electrode 522 may be located in the first source / drain metal layer, the second peripheral line segment 422 may be located in the second source / drain metal layer, and the control bending line 520 may be located in the second source / drain metal layer.

[0144] In this example, the peripheral control line can be arranged in the first gate metal layer and the second gate metal layer in the overlapping area with the first peripheral power line, which can reduce interference with the peripheral touch wiring.

[0145] In some examples, as shown in FIG5 , the bending region B12 may include multiple bending lines. The multiple bending lines may include: four groups of first power bending lines 53a, 53b, 53c, and 53d, two groups of second power bending lines 54a and 54b, a first group of data bending lines 51a, a second group of data bending lines 51b, a group of control bending lines 52, a first group of touch bending lines 55a, a second group of touch bending lines 55b, a first group of detection bending lines 56a, and a second group of detection bending lines 56b. The first group of second power bending lines 54a, the first group of detection bending lines 56a, the first group of data bending lines 51a, the first group of first power bending lines 53a, the first group of touch bending lines 55a, the second group of first power bending lines 53b, a group of control bending lines 52, the third group of first power bending lines 53c, the second group of touch bending lines 55b, the fourth group of first power bending lines 53d, the second group of data bending lines 51b, the second group of detection bending lines 56b, and the second group of second power bending lines 54b can be arranged sequentially along the first direction X. The multiple bending lines in the bending area B12 can be arranged in the same layer, for example, in the second source and drain metal layer.

[0146] In some examples, as shown in FIG5 , the second fan-out area B13 may be provided with at least a first power fan-out line 63, second power fan-out lines 64a and 64b, multiple data fan-out lines (for example, including a first group of data fan-out lines 61a and a second group of data fan-out lines 61b), and multiple control signal lines (for example, including a first group of control signal lines 62a and a second group of control signal lines 62b).

[0147] In some examples, as shown in FIG5 , the first power fan-out line 63 may include a fan-out main portion 630, a first fan-out extension portion 631, a second fan-out extension portion 632, and a third fan-out extension portion 633. The fan-out main portion 630 may extend along the first direction X. Four fan-out connection portions are provided on a side of the fan-out main portion 630 near the bending region B12. The four fan-out connection portions may be electrically connected to the four groups of first power bending lines 53a, 53b, 53c, and 53d in the bending region B12 in a one-to-one correspondence, thereby achieving connection with the first peripheral power lines 43 in the first fan-out region B11.

[0148] In some examples, the first fan-out extension 631, the second fan-out extension 632, and the third fan-out extension 633 are all connected to the fan-out main body 630, and the second fan-out extension 632 and the third fan-out extension 633 can be located on both sides of the first fan-out extension 631 along the first direction X. For example, the second fan-out extension 632 can be located on a side of the first fan-out extension 631 opposite to the first direction X, and the third fan-out extension 633 can be located on a side of the first fan-out extension 631 in the first direction X. The first fan-out extension 631 can extend along the second direction Y. The second fan-out extension 632 can extend along a third direction F3, and the third fan-out extension 633 can extend along a fourth direction F4. The third direction F3 intersects the first direction X, the second direction Y, and the fourth direction F4. The second fan-out extension 632 can bypass the first signal access area B14 from the left to extend to connect with the contact pad in the second signal access area B15, and the third fan-out extension 633 can bypass the first signal access area B14 from the right to extend to connect with the contact pad in the second signal access area B15.

[0149] In some examples, the first fan-out extension 631, the second fan-out extension 632, and the third fan-out extension 633 can be located on a side of the fan-out main body 630 away from the bending region B12. The fan-out main body 630, the first fan-out extension 631, the second fan-out extension 632, and the third fan-out extension 633 of the first power fan-out line 63 are interconnected as an integrated structure, and can be located, for example, on the first source / drain metal layer, or on the second source / drain metal layer, or employ a dual-layer routing structure located on both the first source / drain metal layer and the second source / drain metal layer.

[0150] In some examples, the second power fan-out line 64a can be connected to the second peripheral power line 44a in the first fan-out area B11 via the second power bend line 54a in the bend area B12, and the second power fan-out line 64b can be connected to the second peripheral power line 44b in the first fan-out area B11 via the second power bend line 54b in the bend area B12. The second power fan-out line 64a can be located on the side opposite to the first power fan-out line 63 along the first direction X, and the second power fan-out line 64b can be located on the side of the first power fan-out line 63 along the first direction X. The second power fan-out lines 64a and 64b can both be located in the first source and drain metal layer, or can both be located in the second source and drain metal layer, or can adopt a double-layer routing structure arranged in the first source and drain metal layer and the second source and drain metal layer. The second power fan-out line 64a can bypass the first signal access area B14 from the left to extend to connect to the contact pad in the second signal access area B15. The second power fan-out line 64 b may extend from the right side around the first signal access area B14 to connect with the contact pad in the second signal access area B15 .

[0151] In some examples, as shown in FIG5 , the second fan-out area B13 may be provided with a plurality of data fan-out lines. The plurality of data fan-out lines may extend approximately along the second direction Y toward the first signal access area B14. The plurality of data fan-out lines may include a first group of data fan-out lines 61a and a second group of data fan-out lines 61b. The first group of data fan-out lines 61a may be located on a side of the second power fan-out lines 64b away from the edge of the display panel, and the second group of data fan-out lines 61b may be located on a side of the second power fan-out lines 64b away from the edge of the display panel. The plurality of data fan-out lines within the first group of data fan-out lines 61a may be connected to the first group of multiplexed data lines 41a within the first fan-out area B11 via the first group of data bend lines 51a within the bend area B12; the plurality of data fan-out lines within the second group of data fan-out lines 61b may be connected to the second group of multiplexed data lines 41b within the first fan-out area B11 via the second group of data bend lines 51b within the bend area B12. For example, the first group of data fan-out lines 61a can be configured to provide data signals to sub-pixels in the left half of display area AA, and the second group of data fan-out lines 61b can be configured to provide data signals to sub-pixels in the right half of display area AA. The number of data fan-out lines in the first group of data fan-out lines 61a and the number of data fan-out lines in the second group of data fan-out lines 61b can be the same. For example, the multiple data fan-out lines can be located in the first gate metal layer, or in the second gate metal layer, or can be arranged alternately in the first gate metal layer and the second gate metal layer.

[0152] In some examples, based on the differences in transmission signals, the multiple control signal lines within the second fan-out region B13 may include: multiple first control signal lines and multiple second control signal lines. The multiple first control signal lines can be configured to provide start signals, clock signals, voltage signals, etc. to multiple gate drive circuits. The multiple second control signal lines can be configured to provide multiplexed control signals to multiple multiplexing control circuits. For example, the multiple first control signal lines can be connected to the multiple drive control lines within the first fan-out region B11 via multiple control bend lines within the bend region, and the multiple second control signal lines can be connected to the multiple multiplexing control lines within the first fan-out region B11 via multiple control bend lines within the bend region.

[0153] In some examples, as shown in FIG5 , the arrangement of the multiple control signal lines may include a first group of control signal lines 62a and a second group of control signal lines 62b. Each group of control signal lines may include multiple first control signal lines and multiple second control signal lines. Each control signal line within the second fan-out area B13 may include a first control line segment and a second control line segment connected to each other. The first group of control signal lines 62a may include a first group of first control line segments 621a and a first group of second control line segments 622a connected to each other; the second group of control signal lines 62b may include a second group of first control line segments 621b and a second group of second control line segments 622b connected to each other. The first group of first control line segments 621a and the second group of first control line segments 621b may be connected to multiple peripheral control lines (including the first group of peripheral control lines 42a and the second group of peripheral control lines 42b) within the first fan-out area B11 via a set of control bend lines 52 within the bend area B12. The orthographic projection of the first group of first control line segments 621a and the second group of first control line segments 621b onto the substrate can be roughly an inverted Y-shape. The orthographic projection of the first group of first control line segments 621a and the second group of first control line segments 621b onto the substrate can overlap with the orthographic projection of the fan-out body 630 of the first power fan-out line 63 onto the substrate. The first group of first control line segments 621a and the second group of first control line segments 621b can be located, for example, in the second gate metal layer, or in the first gate metal layer, or can employ a dual-layer routing structure with the first and second gate metal layers.

[0154] In some examples, the first group of second control line segments 622a and the second group of second control line segments 622b can be located on a side of the fan-out body 630 of the first power fan-out line 63 away from the bending region B12. The orthographic projection of the first group of second control line segments 622a on the substrate can overlap with the orthographic projection of the first group of data fan-out lines 61a on the substrate, and the orthographic projection of the second group of second control line segments 622b on the substrate can overlap with the orthographic projection of the second group of data fan-out lines 61b on the substrate. The first group of second control line segments 622a can access the first signal access area B14 and bypass the first signal access area B14 from the left to extend to the second signal access area B15, where they can connect to contact pads within the second signal access area B15. The second group of second control line segments 622b can access the second signal access area B14 and bypass the first signal access area B14 from the right to extend to the second signal access area B15, where they can connect to contact pads within the second signal access area B15.

[0155] In some examples, the first group of second control line segments 622 a and the second group of second control line segments 622 b may be located in the first source-drain metal layer.

[0156] In some examples, the second fan-out area B13 may also be provided with a plurality of touch fan-out lines (for example, including a first group of touch fan-out lines and a second group of touch fan-out lines) located in the touch structure layer. The first group of touch fan-out lines may be connected to the first group of peripheral touch traces (for example, the first group of peripheral touch traces 45a shown in FIG8A ) through the first group of touch bending lines 55a, and the second group of touch fan-out lines may be connected to the second group of peripheral touch traces (for example, the second group of peripheral touch traces 45b shown in FIG8A ) through the second group of touch bending lines 55b. The orthographic projections of the first group of touch fan-out lines and the second group of touch fan-out lines on the substrate may overlap with the orthographic projections of the first fan-out extension 631 of the first power fan-out line 63 on the substrate, and the first group of touch fan-out lines and the second group of touch fan-out lines may extend to the first signal access area B14 and be connected to the contact pads within the first signal access area B14.

[0157] In some examples, the second fan-out region B13 may further be provided with a plurality of first electrostatic discharge circuits. The plurality of first electrostatic discharge circuits may include a first group of electrostatic discharge circuits 321 and a second group of electrostatic discharge circuits 322. The first group of electrostatic discharge circuits 321 may be connected to the first group of second control line segments 622a, and the second group of electrostatic discharge circuits 322 may be connected to the second group of second control line segments 622b.

[0158] In some examples, the first and second electrostatic discharge circuits 321, 322 can be located between the first and second data fan-out lines 61a, 61b. The first and second electrostatic discharge circuits 321 can be adjacent to the first and second data fan-out lines 61a, and the second and second electrostatic discharge circuits 322 can be adjacent to the second and second data fan-out lines 61b. The first and second electrostatic discharge circuits 321, 322 can be located on the side of the first and second control line segments 622a away from the bending region B12, and the second and second electrostatic discharge circuits 322 can be located on the side of the second and second control line segments 622b away from the bending region B12. The first and second electrostatic discharge circuits 321, 322 can be located on either side of the first fan-out extension 631 along the first direction X. In this example, the first set of electrostatic discharge circuits 321 can be surrounded by the first set of data fan-out lines 61a, the first set of second control line segments 622a, and the first fan-out extension 631; and the second set of electrostatic discharge circuits 322 can be surrounded by the second set of data fan-out lines 61b, the second set of second control line segments 622b, and the first fan-out extension 631. The arrangement of the first electrostatic discharge circuits in this example is conducive to optimizing the wiring space in the first border area.

[0159] In some examples, as shown in FIG5 , the first signal access area B14 can be configured to house a driver chip (IC). For example, the driver chip housed in the first signal access area B14 can be a display driver chip or a touch and display driver integrated circuit (TDDI). The first signal access area B14 can also be referred to as a driver chip placement area. The driver chip can be configured to generate data signals required to drive the sub-pixels and provide the data signals to the data lines of the display area.

[0160] In some examples, the first signal access area B14 may be provided with a plurality of first contact pads, which may include: a first group of first contact pads 71 ​​and a second group of first contact pads 72. The second group of first contact pads 72 may be located on a side of the first group of first contact pads 71 ​​away from the bending area B12. The plurality of first contact pads within the first group of first contact pads 71 ​​may be arranged in at least one row along the first direction X. A plurality of data fan-out lines may be connected to the plurality of first contact pads within the first group of first contact pads 71 ​​within the first signal access area B14 to receive data signals from a driver chip; a plurality of touch fan-out lines may be connected to the plurality of first contact pads within the first group of first contact pads 71 ​​within the first signal access area B14 to receive touch signals from the driver chip. The plurality of first contact pads within the second group of first contact pads 72 may be arranged in a row along the first direction X.

[0161] In some examples, the second signal access area B15 may be provided with a plurality of second contact pads. The plurality of second contact pads may be configured to bind a flexible printed circuit (FPC) so that a plurality of signal lines (for example, including a plurality of control signal lines, a first power fan-out line and a second power fan-out line, etc.) are connected to an external control device through a plurality of second contact pads. The second signal access area B15 may also be referred to as a circuit binding area. The second group of first contact pads 72 within the first signal access area B14 may be electrically connected to the plurality of second contact pads within the second signal access area B15 through a plurality of pin connection lines.

[0162] FIG10 is an equivalent circuit diagram of a first electrostatic discharge circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG10 , the first electrostatic discharge circuit can be connected to a control signal line 62 and configured to discharge static electricity from the control signal line 62 to which it is connected. The first electrostatic discharge circuit can include: first to fourth release transistors ST1 to ST4. The first electrode of the first release transistor ST1 is electrically connected to the fourth power line VGL, the gate and second electrode of the first release transistor ST1 are electrically connected to the first electrode of the second release transistor ST2, the gate and second electrode of the second release transistor ST2 are electrically connected to the control signal line 62 corresponding to the first electrostatic discharge circuit, the first electrode of the third release transistor ST3 is electrically connected to the control signal line 62 corresponding to the first electrostatic discharge circuit, the gate and second electrode of the third release transistor ST3 are electrically connected to the first electrode of the fourth release transistor ST4, and the gate and second electrode of the fourth release transistor ST4 are electrically connected to the third power line VGH.

[0163] In one example, providing a first electrostatic discharge circuit can prevent static electricity accumulation in the control signal line from causing discharge breakdown and resulting in damage, thereby releasing the static electricity accumulated in the control signal line and protecting the control signal line.

[0164] In another example, the first electrostatic discharge circuit may include two discharge transistors, each with one electrode connected to its own gate, forming an equivalent diode connection. The signal line to be protected is connected between the two "diodes," and the other two ends of the two "diodes" are connected to the third power line VGH and the fourth power line VGL, respectively. Thus, when a transient high voltage (e.g., 100V) appears in the signal line due to accumulated positive charge, one of the "diodes" conducts, releasing the positive charge in the signal line. When a transient low voltage (e.g., -100V) appears in the signal line due to accumulated negative charge, the other "diode" conducts, releasing the negative charge in the signal line.

[0165] In some examples, the multiple first electrostatic discharge circuits in the first group of electrostatic discharge circuits 321 may be arranged in one or two rows. The multiple first electrostatic discharge circuits in the second group of electrostatic discharge circuits 322 may be arranged in one or two rows. This embodiment is not limited to this.

[0166] Figures 11 and 12 are schematic diagrams of the first group of electrostatic discharge circuits in Figure 5. In some examples, as shown in Figures 11 and 12, the first group of electrostatic discharge circuits 321 may include: a plurality of first electrostatic discharge circuits (e.g., fourteen first electrostatic discharge circuits 731 to 744). A plurality of first electrostatic discharge circuits may be arranged in three rows. For example, five first electrostatic discharge circuits 731, 732, 733, 734, and 735 may be arranged in the first row, five first electrostatic discharge circuits 736, 737, 738, 739, and 740 may be arranged in the second row, and four first electrostatic discharge circuits 741, 742, 743, and 744 may be arranged in the third row. The first row, the second row, and the third row may be arranged in a direction away from the bending area. The first electrostatic release circuits 731 and 735 can be arranged in the same column, the first electrostatic release circuits 732, 737 and 741 can be arranged in the same column, the first electrostatic release circuits 733, 738 and 742 can be arranged in the same column, the first electrostatic release circuits 734, 739 and 743 can be arranged in the same column, and the first electrostatic release circuits 735, 740 and 744 can be arranged in the same column.

[0167] In some examples, the four release transistors in adjacent first electrostatic discharge circuits in the same row are arranged in the opposite order. For example, the first to fourth release transistors in the first electrostatic discharge circuit 731 can be arranged along the first direction X, the first to fourth release transistors in the first electrostatic discharge circuit 732 can be arranged in the opposite direction of the first direction X, and the first to fourth release transistors in the first electrostatic discharge circuit 733 can be arranged along the first direction X.

[0168] In some examples, the active layers of the release transistors of multiple first electrostatic discharge circuits in the same row may be interconnected and integrated. For example, the active layers of the release transistors may be located in the first semiconductor layer, the gates of the release transistors may be located in the first gate metal layer, and the first and second electrodes of the release transistors may be located in the first source / drain metal layer.

[0169] In some examples, the first group of control signal lines 62a may include: multiple first control signal lines (for example, including first control signal lines 811, 815, 835, 8341, 8331, 8321, 8311, 8411, 8421, 8431, 8441, 845, 8511, 8521, 8531, 8541 and 855), and multiple second control signal lines (for example, including second control signal lines 423a and 423b).

[0170] In some examples, the first electrostatic discharge circuit 731 can be connected to a connection line 8343 located in the first source / drain metal layer, the connection line 8343 can be connected to a connection line 8342 located in the first gate metal layer, and the connection line 8342 can be connected to a first control signal line 8341 located in the first source / drain metal layer. The first control signal line 8341 can be configured to provide a third clock signal HCX to the second reset driver circuit.

[0171] In some examples, the first electrostatic discharge circuit 732 can be connected to a connection line 8333 located in the first source / drain metal layer, the connection line 8333 can be connected to a connection line 8332 located in the first gate metal layer, and the connection line 8332 can be connected to a first control signal line 8331 located in the first source / drain metal layer. The first control signal line 8331 can be configured to provide a first clock signal HCK to the second reset driver circuit.

[0172] In some examples, the first electrostatic discharge circuit 733 can be connected to a connection line 8323 located in the first source / drain metal layer, the connection line 8323 can be connected to a connection line 8322 located in the first gate metal layer, and the connection line 8322 can be connected to a first control signal line 8321 located in the first source / drain metal layer. The first control signal line 8321 can be configured to provide a second clock signal HCB to the second reset driver circuit.

[0173] In some examples, the first electrostatic discharge circuit 734 can be connected to a connection line 8313 located in the first source / drain metal layer, the connection line 8313 can be connected to a connection line 8312 located in the first gate metal layer, and the connection line 8312 can be connected to a first control signal line 8311 located in the first source / drain metal layer. The first control signal line 8311 can be configured to provide a start signal HSTV to the second reset driver circuit.

[0174] In some examples, the first electrostatic discharge circuit 735 can be connected to a connection line 8413 located in the first source / drain metal layer, the connection line 8413 can be connected to a connection line 8412 located in the first gate metal layer, and the connection line 8412 can be connected to a first control signal line 8411 located in the first source / drain metal layer. The first control signal line 8411 can be configured to provide a start signal PSTV to the first reset driver circuit.

[0175] In some examples, the first electrostatic discharge circuit 736 can be connected to a connection line 8423 located in the first source / drain metal layer, the connection line 8423 can be connected to a connection line 8422 located in the first gate metal layer, and the connection line 8422 can be connected to a first control signal line 8421 located in the first source / drain metal layer. The first control signal line 8421 can be configured to provide a first clock signal PCK to the first reset driver circuit.

[0176] In some examples, the first electrostatic discharge circuit 737 can be connected to a connection line 8433 located on the first source / drain metal layer, the connection line 8433 can be connected to a connection line 8432 located on the first gate metal layer, and the connection line 8432 can be connected to a first control signal line 8431 located on the first source / drain metal layer. The first control signal line 8431 can be configured to provide a second clock signal PCB to the first reset driver circuit.

[0177] In some examples, the first electrostatic discharge circuit 738 can be connected to a connection line 8443 located in the first source / drain metal layer, the connection line 8443 can be connected to a connection line 8442 located in the first gate metal layer, and the connection line 8442 can be connected to a first control signal line 8441 located in the first source / drain metal layer. The first control signal line 8441 can be configured to provide a third clock signal PCX to the first reset driver circuit.

[0178] In some examples, the first electrostatic discharge circuit 739 can be connected to a connection line 8513 located in the first source / drain metal layer, the connection line 8513 can be connected to a connection line 8512 located in the first gate metal layer, and the connection line 8512 can be connected to a first control signal line 8511 located in the first source / drain metal layer. The first control signal line 8511 can be configured to provide a start signal ESTV to the light emitting driving circuit.

[0179] In some examples, the first electrostatic discharge circuit 740 can be connected to a connection line 8523 located in the first source / drain metal layer, the connection line 8523 can be connected to a connection line 8522 located in the first gate metal layer, and the connection line 8522 can be connected to a first control signal line 8521 located in the first source / drain metal layer. The first control signal line 8521 can be configured to provide a first clock signal ECK to the light emitting driving circuit.

[0180] In some examples, the first electrostatic discharge circuit 741 can be connected to a connection line 8533 located in the first source / drain metal layer, the connection line 8533 can be connected to a connection line 8532 located in the first gate metal layer, and the connection line 8532 can be connected to a first control signal line 8531 located in the first source / drain metal layer. The first control signal line 8531 can be configured to provide a second clock signal ECB to the light emitting driving circuit.

[0181] In some examples, the first electrostatic discharge circuit 742 can be connected to a connection line 8543 located in the first source / drain metal layer, the connection line 8543 can be connected to a connection line 8542 located in the first gate metal layer, and the connection line 8542 can be connected to a first control signal line 8541 located in the first source / drain metal layer. The first control signal line 8541 can be configured to provide a third clock signal ECX to the light emitting driving circuit.

[0182] In some examples, the first electrostatic discharge circuit 743 can be connected to a connection line 4242 located in the first source / drain metal layer, the connection line 4242 can be connected to a connection line 4241 located in the first gate metal layer, and the connection line 4241 can be connected to a second control signal line 423a located in the first source / drain metal layer. The second control signal line 423a can be configured to provide a first multiplexing control signal MUX1 to the multiplexing circuit.

[0183] In some examples, the first electrostatic discharge circuit 744 can be connected to a connection line 4244 located in the first source / drain metal layer, the connection line 4244 can be connected to a connection line 4243 located in the first gate metal layer, and the connection line 4243 can be connected to a second control signal line 423b located in the first source / drain metal layer. The second control signal line 423b can be configured to provide a second multiplexing control signal MUX2 to the multiplexing circuit.

[0184] In some examples, the first electrostatic discharge circuits 731 to 744 are connected to the connection line 812 located in the first gate metal layer via the connection line located in the first source / drain metal layer, and the connection line 812 can be connected to the power line 811 located in the first source / drain metal layer. The first electrostatic discharge circuits 731 to 744 can also be connected to the connection line 816 located in the first gate metal layer via the connection line located in the first source / drain metal layer, and the connection line 816 can be connected to the power line 815 located in the first source / drain metal layer. The power line 811 is configured to transmit a low-level signal, and the power line 815 is configured to transmit a high-level signal.

[0185] In some examples, a line 804 transmitting a third initial signal and a first control signal line 805 can be provided between power line 811 and power line 815. The first control signal line 805 can be configured to provide a voltage signal to the gate drive circuit. A line 802 transmitting a first initial signal, a line 801 transmitting a second initial signal, and a first control signal line 803 can be provided on the side of power line 811 away from power line 815. The first control signal line 803 can be configured to provide a voltage signal to the gate drive circuit. The voltage signal provided by the first control signal line 803 can be lower than the voltage signal provided by the first control signal line 805.

[0186] In some examples, the first control signal line 835 can be configured to transmit the output signal HOUT of the second reset driving circuit, the first control signal line 845 can be configured to transmit the output signal POUT of the first reset driving circuit, and the first control signal line 855 can be configured to transmit the output signal EOUT of the light-emitting driving circuit.

[0187] Figures 13 and 14 are schematic diagrams of the second group of electrostatic discharge circuits in Figure 5. In some examples, as shown in Figures 13 and 14, the second group of electrostatic discharge circuits 322 may include: a plurality of first electrostatic discharge circuits (e.g., fourteen first electrostatic discharge circuits 751 to 764). A plurality of first electrostatic discharge circuits may be arranged in four rows. For example, five first electrostatic discharge circuits 751, 752, 753, 754, and 755 may be arranged in the first row, four first electrostatic discharge circuits 756, 757, 758, and 759 may be arranged in the second row, four first electrostatic discharge circuits 760, 761, 762, and 763 may be arranged in the third row, and the first electrostatic discharge circuit 764 may be arranged in the fourth row. The first row, the second row, the third row, and the fourth row may be arranged in a direction away from the bending region. The first electrostatic discharge circuits 752, 756, 760 and 764 can be arranged in the same column, the first electrostatic discharge circuits 753, 757 and 761 can be arranged in the same column, the first electrostatic discharge circuits 754, 758 and 762 can be arranged in the same column, and the first electrostatic discharge circuits 755, 759 and 753 can be arranged in the same column.

[0188] In some examples, the second group of control signal lines 62b may include: multiple first control signal lines (for example, including first control signal lines 8611, 8621, 8631, 864, 8711, 8721, 8731, 8741, 875), and multiple second control signal lines (for example, including second control signal lines 423c, 423d, 423e, 423f, 423g, 423h and 423i).

[0189] In some examples, the first electrostatic discharge circuit 751 can be connected to a connection line 8743 located in the first source / drain metal layer, the connection line 8743 can be connected to a connection line 8742 located in the first gate metal layer, and the connection line 8742 can be connected to a first control signal line 8741 located in the first source / drain metal layer. The first control signal line 8741 can be configured to provide a third clock signal NCX to the second scan driving circuit.

[0190] In some examples, the first electrostatic discharge circuit 752 can be connected to a connection line 8613 located in the first source / drain metal layer, the connection line 8613 can be connected to a connection line 8612 located in the first gate metal layer, and the connection line 8612 can be connected to a first control signal line 8611 located in the first source / drain metal layer. The first control signal line 8611 can be configured to provide a start signal GSTV to the first scan driving circuit.

[0191] In some examples, the first electrostatic discharge circuit 753 can be connected to a connection line 8733 located in the first source / drain metal layer, the connection line 8733 can be connected to a connection line 8732 located in the first gate metal layer, and the connection line 8732 can be connected to a first control signal line 8731 located in the first source / drain metal layer. The first control signal line 8731 can be configured to provide a second clock signal NCB to the second scan driving circuit.

[0192] In some examples, the first electrostatic discharge circuit 754 can be connected to a connection line 8723 located in the first source / drain metal layer, the connection line 8723 can be connected to a connection line 8722 located in the first gate metal layer, and the connection line 8722 can be connected to a first control signal line 8721 located in the first source / drain metal layer. The first control signal line 8721 can be configured to provide a first clock signal NCK to the second scan driving circuit.

[0193] In some examples, the first electrostatic discharge circuit 755 can be connected to a connection line 8713 located in the first source / drain metal layer, the connection line 8713 can be connected to a connection line 8712 located in the first gate metal layer, and the connection line 8712 can be connected to a first control signal line 8711 located in the first source / drain metal layer. The first control signal line 8711 can be configured to provide a start signal NSTV to the second scan driving circuit.

[0194] In some examples, the first electrostatic discharge circuit 758 can be connected to a connection line 8633 located in the first source / drain metal layer, the connection line 8633 can be connected to a connection line 8632 located in the first gate metal layer, and the connection line 8632 can be connected to a first control signal line 8631 located in the first source / drain metal layer. The first control signal line 8631 can be configured to provide a first clock signal GCK to the first scan driving circuit.

[0195] In some examples, the first electrostatic discharge circuit 759 can be connected to a connection line 8623 located in the first source / drain metal layer, the connection line 8623 can be connected to a connection line 8622 located in the first gate metal layer, and the connection line 8622 can be connected to a first control signal line 8621 located in the first source / drain metal layer. The first control signal line 8621 can be configured to provide a second clock signal GCB to the first scan driving circuit.

[0196] In some examples, the first electrostatic discharge circuit 756 can be connected to a connection line 4256 located in the first source / drain metal layer, the connection line 4256 can be connected to a connection line 4255 located in the first gate metal layer, and the connection line 4255 can be connected to a second control signal line 423h located in the first source / drain metal layer. The second control signal line 423h can be configured to provide an eighth multiplexing control signal MUX8 to the multiplexing circuit.

[0197] In some examples, the first electrostatic discharge circuit 757 can be connected to a connection line 4258 located in the first source / drain metal layer, the connection line 4258 can be connected to a connection line 4257 located in the first gate metal layer, and the connection line 4257 can be connected to a second control signal line 423i located in the first source / drain metal layer. The second control signal line 423i can be configured to provide a ninth multiplexing control signal MUX9 to the multiplexing circuit.

[0198] In some examples, the first electrostatic discharge circuit 760 can be connected to the connection line 4248 located in the first source-drain metal layer, the connection line 4248 can be connected to the connection line 4247 located in the first gate metal layer, and the connection line 4247 can be connected to the second control signal line 423d located in the first source-drain metal layer. The second control signal line 423d can be configured to provide a fourth multiplexing control signal MUX4 to the multiplexing circuit.

[0199] In some examples, the first electrostatic discharge circuit 761 can be connected to a connection line 4250 located in the first source / drain metal layer, the connection line 4250 can be connected to a connection line 4249 located in the first gate metal layer, and the connection line 4249 can be connected to a second control signal line 423e located in the first source / drain metal layer. The second control signal line 423e can be configured to provide a fifth multiplexing control signal MUX5 to the multiplexing circuit.

[0200] In some examples, the first electrostatic discharge circuit 762 can be connected to a connection line 4252 located in the first source / drain metal layer, the connection line 4252 can be connected to a connection line 4251 located in the first gate metal layer, and the connection line 4251 can be connected to a second control signal line 423f located in the first source / drain metal layer. The second control signal line 423f can be configured to provide a sixth multiplexing control signal MUX6 to the multiplexing circuit.

[0201] In some examples, the first electrostatic discharge circuit 763 can be connected to the connection line 4254 located in the first source-drain metal layer, the connection line 4254 can be connected to the connection line 4253 located in the first gate metal layer, and the connection line 4253 can be connected to the second control signal line 423g located in the first source-drain metal layer. The second control signal line 423g can be configured to provide the seventh multiplexing control signal MUX7 to the multiplexing circuit.

[0202] In some examples, the first electrostatic discharge circuit 764 can be connected to a connection line 4246 located in the first source / drain metal layer, the connection line 4246 can be connected to a connection line 4245 located in the first gate metal layer, and the connection line 4245 can be connected to a second control signal line 423c located in the first source / drain metal layer. The second control signal line 423c can be configured to provide a third multiplexing control signal MUX3 to the multiplexing circuit.

[0203] In some examples, the first electrostatic discharge circuits 751 to 764 are connected to the connection line 814 located in the first gate metal layer via the connection line located in the first source / drain metal layer, and the connection line 814 can be connected to the power line 813 located in the first source / drain metal layer. The first electrostatic discharge circuits 751 to 764 can also be connected to the connection line 818 located in the first gate metal layer via the connection line located in the first source / drain metal layer, and the connection line 818 can be connected to the power line 817 located in the first source / drain metal layer. The power line 813 and the power line 811 are configured to transmit the same signal, and the power lines 817 and 815 are configured to transmit the same signal.

[0204] In some examples, a line 809 transmitting a third initial signal and a first control signal line 810 may be provided between power line 813 and power line 817. The first control signal line 810 may be configured to provide a voltage signal to the gate drive circuit. A line 807 transmitting a first initial signal, a line 806 transmitting a second initial signal, and a first control signal line 808 may be provided on the side of power line 813 away from power line 817. The first control signal line 808 may be configured to provide a voltage signal to the gate drive circuit. The voltage signal provided by the first control signal line 808 may be lower than the voltage signal provided by the first control signal line 810.

[0205] In some examples, the first control signal line 864 can be configured to transmit the output signal GOUT of the first scan driving circuit, and the first control signal line 875 can be configured to transmit the output signal NOUT of the second scan driving circuit.

[0206] The remaining structures of the second electrostatic discharge circuit can refer to the description of the first electrostatic discharge circuit, so they will not be described again here.

[0207] In other examples, as shown in FIG5 , the plurality of first electrostatic discharge circuits within the second fan-out region B13 may further include a third group of electrostatic discharge circuits 323 and a fourth group of electrostatic discharge circuits 324. The third group of electrostatic discharge circuits 323 may be connected to the first group of second control line segments 622a of the first group of control signal lines 62a, and the fourth group of electrostatic discharge circuits 324 may be connected to the second group of second control line segments 622b of the second group of control signal lines 62b. For example, each second control line segment within the first group of second control line segments 622a may be simultaneously connected to the first group of electrostatic discharge circuits 321 and the third group of electrostatic discharge circuits 323; or, a portion of the second control line segments within the first group of second control line segments 622a may be connected to the first group of electrostatic discharge circuits 321, while another portion of the second control line segments may be connected to the third group of electrostatic discharge circuits 323.

[0208] In some examples, the third set of electrostatic discharge circuits 323 can be located on a side of the first set of data fan-out lines 61a away from the first fan-out extension 631 of the second set of data fan-out lines 61b and the first power fan-out lines 63. The third set of electrostatic discharge circuits 323 can be surrounded by the first set of second control line segments 622a, the first set of data fan-out lines 61a, and the second fan-out extension 632 of the first power fan-out lines 63. The fourth set of electrostatic discharge circuits 324 can be located on a side of the second set of data fan-out lines 61b away from the first fan-out extension 631 of the first set of data fan-out lines 61a and the first power fan-out lines 63. The fourth set of electrostatic discharge circuits 324 can be surrounded by the second set of second control line segments 622b, the second set of data fan-out lines 61b, and the third fan-out extension 633 of the first power fan-out lines 63. In this example, the addition of the third and fourth sets of electrostatic discharge circuits can improve the electrostatic discharge effect of the control signal lines.

[0209] In other examples, as shown in FIG5 , the plurality of first electrostatic discharge circuits within the second fan-out region B13 may further include: a fifth group of electrostatic discharge circuits 325 and a sixth group of electrostatic discharge circuits 326. The fifth group of electrostatic discharge circuits 325 may be connected to the first group of second control line segments 622a of the first group of control signal lines 62a, and the sixth group of electrostatic discharge circuits 326 may be connected to the second group of second control line segments 622b of the second group of control signal lines 62b. For example, each second control line segment within the first group of second control line segments 622a may be simultaneously connected to the first group of electrostatic discharge circuits 321 and the fifth group of electrostatic discharge circuits 325; or, a portion of the second control line segments within the first group of second control line segments 622a may be connected to the first group of electrostatic discharge circuits 321, while another portion of the second control line segments may be connected to the fifth group of electrostatic discharge circuits 325.

[0210] In some examples, the fifth set of electrostatic discharge circuits 325 can be located on a side of the first set of data fan-out lines 61a away from the second set of data fan-out lines 61b, and on a side of the second set of second control line segments 622a of the first set of control signal lines 62a away from the bending region B12. The sixth set of electrostatic discharge circuits 326 can be located on a side of the second set of data fan-out lines 61b away from the first set of data fan-out lines 61a, and on a side of the second set of second control line segments 622b of the second set of control signal lines 62b away from the bending region B12. The fifth set of electrostatic discharge circuits 325 can be surrounded by the first set of data fan-out lines 61a and the second set of second control line segments 622a, and the sixth set of electrostatic discharge circuits 326 can be surrounded by the second set of data fan-out lines 61b and the second set of second control line segments 622b. In this example, the addition of the fifth and sixth sets of electrostatic discharge circuits can improve the electrostatic discharge effect of the control signal lines.

[0211] In other examples, each second control line segment in the first group of second control line segments in the second fan-out region can be simultaneously connected to the first group of electrostatic discharge circuits 321, the third electrostatic discharge circuit 323, and the fifth electrostatic discharge circuit 325. Alternatively, each second control line segment in the second fan-out region can be connected to one or two of the first group of electrostatic discharge circuits 321, the third electrostatic discharge circuit 323, and the fifth electrostatic discharge circuit 325. The connection method between the second group of second control line segments and the electrostatic discharge circuits is similar and will not be further described here.

[0212] In other examples, as shown in Figure 5, the display panel may further include: a plurality of second electrostatic discharge circuits located in the second frame area B2. The plurality of second electrostatic discharge circuits may include: a seventh group of electrostatic discharge circuits 327 located in the first corner area of ​​the second frame area B2 and an eighth group of electrostatic discharge circuits 328 located in the second corner area of ​​the second frame area B2. The seventh group of electrostatic discharge circuits 327 may be connected to the wiring (for example, including a plurality of drive control lines) connected to the first group of gate drive circuits 25 and adjacent to the starting position of the first group of gate drive circuits 25. The eighth group of electrostatic discharge circuits 328 may be connected to the wiring (for example, including a plurality of drive control lines) connected to the second group of gate drive circuits 26 and adjacent to the starting position of the second group of gate drive circuits 26. This example can effectively utilize the extra space to arrange the electrostatic discharge circuit by arranging the second electrostatic discharge circuit near the starting position of the gate drive circuit, which is beneficial to optimizing the wiring space of the frame area. The structure of the second electrostatic discharge circuit can refer to the structure of the first electrostatic discharge circuit, so it will not be repeated here.

[0213] The display panel provided in this example can reduce the space occupied in the first fan-out area by setting the electrostatic discharge circuit in the second fan-out area, or in the second fan-out area and the second frame area, and can meet the wiring space requirements of the first fan-out area caused by the increase in the frame wiring by using the pixel circuit shown in Figure 2, which is conducive to realizing a display panel with a narrow frame. Moreover, the multiplexing circuit of this example is arranged in a stepped manner close to the display area, which can reduce the interference of the data signal and help ensure the consistency of the parasitic capacitance between signals. In addition, the first peripheral power line in the first fan-out area can shield the wiring of the touch structure layer and the display structure layer, which can reduce mutual interference between signals.

[0214] Figure 15 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in Figure 15 , this embodiment provides a display device 91 comprising a display panel 910 according to the aforementioned embodiment. In some examples, display panel 910 may be an OLED display panel, such as an OLED display panel with an integrated touchscreen structure. Display device 91 may be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, or may be a product or component with both touchscreen and display functions.

[0215] In some examples, the display device 91 may be a wearable display device, for example, a display device that can be worn on a human body in some manner. For example, the display device 91 may be a smart watch, a smart bracelet, etc. However, this embodiment is not limited to this.

[0216] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example" or "some examples" and the like mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and features of different embodiments or examples, unless they are mutually inconsistent.

[0217] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A display panel, comprising: A substrate comprising: a display area and a frame area surrounding the display area, the frame area comprising a first frame area and a second frame area, the first frame area and the second frame area being connected, the first frame area comprising: a first fan-out area, a bending area, and a second fan-out area sequentially arranged in a direction away from the display area; a plurality of sub-pixels located in the display area and on one side of the substrate; a plurality of data lines located in the display area, the plurality of sub-pixels being electrically connected to the plurality of data lines, the plurality of data lines being configured to provide data signals to the plurality of sub-pixels; a plurality of gate driving circuits located in the second frame area and electrically connected to the plurality of sub-pixels, the plurality of gate driving circuits being configured to provide a plurality of pixel control signals to the plurality of sub-pixels; A plurality of data fan-out lines and a plurality of control signal lines are located in the first border area; the plurality of data fan-out lines are electrically connected to the plurality of data lines, and a portion of the plurality of control signal lines are electrically connected to the plurality of gate drive circuits, the plurality of data fan-out lines include a first group of data fan-out lines and a second group of data fan-out lines, and the plurality of control signal lines include a first group of control signal lines and a second group of control signal lines; the first group of data fan-out lines and the first group of control signal lines overlap in orthographic projection on the substrate, and the second group of data fan-out lines and the second group of control signal lines overlap in orthographic projection on the substrate; a plurality of first electrostatic release circuits located in the first border region; the plurality of first electrostatic release circuits including: a first group of electrostatic release circuits and a second group of electrostatic release circuits located in the second fan-out region; the first group of electrostatic release circuits being connected to the first group of control signal lines, and the second group of electrostatic release circuits being connected to the second group of control signal lines; The first group of electrostatic release circuits and the second group of electrostatic release circuits are located between the first group of data fan-out lines and the second group of data fan-out lines, the first group of electrostatic release circuits are adjacent to the first group of data fan-out lines, and the second group of electrostatic release circuits are adjacent to the second group of data fan-out lines. The first group of electrostatic release circuits is located on the side of the first group of control signal lines away from the bending area, and the second group of electrostatic release circuits is located on the side of the second group of control signal lines away from the bending area.

2. The display panel according to claim 1, further comprising: a first power fan-out line located in the second fan-out area; The first power fan-out line includes: a fan-out main portion and a first fan-out extension portion, the fan-out main portion extending along a first direction, the first fan-out extension portion connected to the fan-out main portion, located on a side of the fan-out main portion away from the bending area, and extending along a second direction, the first direction intersecting the second direction; The first group of electrostatic discharge circuits and the second group of electrostatic discharge circuits are located on both sides of the first fan-out extension along the first direction.

3. The display panel according to claim 2, wherein: The plurality of first electrostatic discharge circuits further include: a third group of electrostatic discharge circuits and a fourth group of electrostatic discharge circuits located in the second fan-out area; the third group of electrostatic discharge circuits is connected to the first group of control signal lines, and the fourth group of electrostatic discharge circuits is connected to the second group of control signal lines; The first power fan-out line further includes: a second fan-out extension portion and a third fan-out extension portion, wherein the second fan-out extension portion and the third fan-out extension portion are both connected to the fan-out main portion and are located on both sides of the first fan-out extension portion along the first direction; The third group of electrostatic discharge circuits is located on a side of the first group of data fan-out lines away from the second group of data fan-out lines, and is surrounded by the first group of control signal lines, the first group of data fan-out lines and the second fan-out extension; The fourth group of electrostatic discharge circuits is located on a side of the second group of data fan-out lines away from the first group of data fan-out lines, and is surrounded by the second group of control signal lines, the second group of data fan-out lines, and the third fan-out extension.

4. The display panel according to claim 1, wherein: The plurality of first electrostatic discharge circuits further include: a fifth group of electrostatic discharge circuits and a sixth group of electrostatic discharge circuits located in the second fan-out area; the fifth group of electrostatic discharge circuits is connected to the first group of control signal lines, and the sixth group of electrostatic discharge circuits is connected to the second group of control signal lines; The fifth set of electrostatic discharge circuits is located on a side of the first set of data fan-out lines away from the second set of data fan-out lines, and is located on a side of the first set of control signal lines away from the bending area; The sixth set of electrostatic discharge circuits is located on a side of the second set of data fan-out lines away from the first set of data fan-out lines, and is also located on a side of the second set of control signal lines away from the bending region.

5. The display panel according to claim 1, wherein: The plurality of gate driving circuits include: a first group of gate driving circuits and a second group of gate driving circuits; the first group of gate driving circuits and the second group of gate circuits are located on both sides of the display area; The display panel further includes: a plurality of second electrostatic discharge circuits located in the second frame area, The multiple second electrostatic release circuits include: a seventh group of electrostatic release circuits and an eighth group of electrostatic release circuits; the seventh group of electrostatic release circuits is connected to a part of the control signal lines in the first group of control signal lines, and is adjacent to the starting position of the first group of gate drive circuits; the eighth group of electrostatic release circuits is connected to a part of the control signal lines in the second group of control signal lines, and is adjacent to the starting position of the second group of gate drive circuits.

6. The display panel according to claim 1, further comprising: a plurality of multiplexing circuits located in the frame area and disposed adjacent to the display area; The plurality of control signal lines further include: a plurality of control signal lines for providing multiplexing control signals to the plurality of multiplexing circuits; Each multiplexing circuit includes a plurality of multiplexing control transistors, and the plurality of multiplexing control transistors in the plurality of multiplexing circuits are arranged in the same manner.

7. The display panel according to claim 6, wherein: The multiplexing control transistors of each multiplexing circuit are arranged in sequence along a first direction.

8. The display panel according to claim 6, wherein: The second border area includes: a first corner area and a second corner area located on both sides of the first fan-out area; The multiple multiplexing circuits include: a first group of multiplexing circuits located in the first fan-out area and a plurality of second groups of multiplexing circuits located in the first corner area and the second corner area of ​​the second border area; the plurality of second groups of multiplexing circuits are arranged in a stepped manner along the edge of the display area.

9. The display panel according to claim 8, further comprising: a first peripheral power line located in the first fan-out area and a first power fan-out line located in the second fan-out area; The first peripheral power line is electrically connected to the first power fan-out line; the first peripheral power line is located on a side of the first group of multiplexing circuits away from the display area.

10. The display panel according to claim 9, further comprising: A plurality of peripheral touch lines are located in the first fan-out area; the plurality of peripheral touch lines are located on a side of the first peripheral power line away from the substrate, and an orthographic projection of the plurality of peripheral touch lines on the substrate at least partially overlaps with an orthographic projection of the first peripheral power line on the substrate.

11. The display panel according to claim 9, further comprising: a plurality of peripheral control lines located in the first fan-out region, at least one of the plurality of peripheral control lines comprising: a first peripheral line segment and a second peripheral line segment connected to each other, the first peripheral line segment being located on a side of the first peripheral power line close to the substrate, and an orthographic projection of the first peripheral line segment on the substrate partially overlapping an orthographic projection of the first peripheral power line on the substrate; and an orthographic projection of the second peripheral line segment on the substrate not overlapping an orthographic projection of the first peripheral power line on the substrate; The bending area is provided with a plurality of control bending lines, and the first peripheral line segment is connected to at least one control bending line; The plurality of control bending lines are electrically connected to the plurality of control signal lines.

12. The display panel according to claim 11, wherein: The first peripheral line segment includes: a first routing line and a second routing line located in different conductive layers, wherein the orthographic projection of the first routing line on the substrate covers the orthographic projection of the second routing line on the substrate; The first routing line and the second routing line are connected to the at least one control bending line through a first connecting electrode; the first connecting electrode is located on a side of the first routing line and the second routing line away from the substrate, and the at least one control bending line is located on a side of the first connecting electrode away from the substrate.

13. The display panel according to claim 12, wherein: The first wiring is located in the first gate metal layer, the second wiring is located in the second gate metal layer, the first connecting electrode is located in the first source-drain metal layer, and the at least one control bending line is located in the second source-drain metal layer.

14. The display panel according to claim 11, wherein: The bending area is further provided with four groups of first power bending lines, a first group of data bending lines and a second group of data bending lines; The four groups of first power bending lines include: a first group of first power bending lines, a second group of first power bending lines, a third group of first power bending lines and a fourth group of first power bending lines arranged along the first direction; The plurality of control bending lines are located between the second group of first power bending lines and the third group of first power bending lines, and are connected to the first group of control signal lines and the second group of control signal lines; The first group of data bending lines is located on a side of the first group of first power bending lines away from the second group of first power bending lines, and is connected to the first group of data fan-out lines; The second group of data bending lines is located on a side of the fourth group of first power bending lines away from the third group of first power bending lines and is connected to the second group of data fan-out lines.

15. A display device comprising the display panel according to any one of claims 1 to 14.

Images