Data processing method and transmission device

Abstract

Disclosed in embodiments of the present application is a data processing method applicable to a high-speed optical transport network. The method comprises the following steps: on the basis of first bit data having a bit number of din, acquiring second bit data, wherein the second bit data comprises din bits in the first bit data, dCRC check bits, and / or dPAD padding bits; scrambling the second bit data to obtain third bit data, wherein the bit number of the third bit data is that dscr=din+dCP, and dCP=dCRC+dPAD; then performing probabilistic constellation shaping (PCS) processing on a first bit subset in a first bit set having a bit number of m, so as to obtain a second bit subset, wherein the first bit set is acquired from the third bit data; and performing FEC coding and interleaving processing on the second bit subset and a third bit subset other than the first bit subset in the first bit set to obtain a second bit set. The present application provides different values of din, m, and dCP, achieving the compatibility with existing 400 G networks, good performance, and low costs.

Description

Data processing method and transmission device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on March 8, 2024, with application number 202410269781.8 and application name “A Data Processing Method and Transmission Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of communication technology, and in particular to a data processing method and a transmission device. Background Art

[0003] Driven by 5G, cloud computing, big data, and artificial intelligence, high-speed optical transmission networks are developing towards large capacity, packetization, and intelligence. Coherent optical communication systems use the amplitude, phase, polarization, and frequency of light waves to carry information. To combat optical signal distortion caused by dispersion, polarization-related impairments, noise, nonlinear effects, and other factors during transmission and maintain long-distance transmission, coherent optical communication systems typically require the use of efficient forward error correction (FEC) codes to combat optical impairments during optical transmission and maintain a sufficiently low bit error rate over long distances. For example, the open FEC code (OpenFEC), also referred to as OFEC code, currently adopted by 400ZR+ and 800ZR, has an overhead (OH) of 15.3%. When soft-decision decoding is used, the performance is approximately 2.0E-2 before correction.

[0004] To improve spectrum efficiency, multi-level Quadrature Amplitude Modulation (QAM) is often used, such as 16QAM, 32QAM, 64QAM, and even higher-order QAM. In traditional QAM modulation, each constellation point on the signal constellation diagram appears with the same probability. Probabilistic Constellation Shaping (PCS) processing technology changes the probability of constellation points appearing while maintaining their positions, making them non-uniformly distributed, thereby improving system transmission performance. As a modulation format optimization technology, PCS processing technology has the advantages of approaching the Shannon limit and being flexible and adaptable, and has been widely researched and applied.

[0005] For existing 400G long-haul transmission solutions using OFEC encoding, quadrature phase shift keying (QPSK) modulation is typically used, requiring devices that support baud rate generations of 120GBaud to 140GBaud. For example, in the case of optical transport network (OTN) data transmission using a Flexible Optical Transport Network (FlexO) that transmits 400G bits per second (FlexO-4 for short), the corresponding baud rate is approximately 124.102GBaud; in the case of FlexO-4e data transmission with Ethernet services as the payload, the corresponding baud rate is approximately 118.203GBaud. In this case, the channel spacing (also known as grid spacing) is typically 150GHz. However, the 400G data center and metropolitan area coherent transmission solutions used in existing networks use channel spacings of approximately 75GHz, 100GHz, or 112.5GHz. In other words, the 400G long-distance transmission solution using OFEC coding and QPSK modulation is difficult to be compatible with existing 400G data centers and metropolitan area networks, which is an urgent problem that needs to be solved. Summary of the Invention

[0006] The embodiments of the present application provide a data processing method, device, and system that adopt FEC coding and combine PCS technology to meet longer transmission distances and make the overall data processing operation simpler, less complex, and lower in power consumption; while ensuring overall performance, it can be compatible with existing 400G data centers and metropolitan area networks.

[0007] In a first aspect, the present application provides a data processing method, which comprises the following steps: in The first bit data is obtained, and the second bit data is obtained, wherein the second bit data includes d in bits in the first bit data, d CRC parity bits and / or d PAD Filling bits, d CRC is an integer greater than or equal to 0, d PAD is an integer greater than or equal to 0; the second bit data is scrambled to obtain a third bit data, the number of bits of the third bit data is d scr =d in +d CP , d CP =d CRC +d PAD; Performing probabilistic constellation shaping PCS processing on a first bit subset in a first bit set having a bit number m to obtain a second bit subset, wherein the first bit set is obtained from the third bit data, m is an integer greater than 1, and d scr is an integer multiple of m; performing forward error correction FEC encoding and interleaving on the second bit subset and a third bit subset of the first bit set excluding the first bit subset to obtain a second bit set, wherein d in , m and d CP The value of is any one of the following sets:

[0008] In this embodiment, for future metropolitan area telecommunication transmission and metropolitan area DCI interconnection scenarios, FEC coding will be adopted in combination with PCS technology to meet longer transmission distances. The introduction of PCS processing means that the data processing granularity for "PCS processing and FEC coding" (i.e., the first sub-processing in the specification) is no longer 3552, but a smaller value m. At this time, it is necessary to redesign the number of rows for obtaining data from the data frame, the number of CRC checks and the number of padding bits to be inserted, so as to make the overall data processing operation simpler, less complex, and less power-consuming. Moreover, when the first bit of data is FlexO-4e or 400G-ZR frame data, the corresponding baud rate is less than 100GBaud, which is better compatible with existing 400G data centers and metropolitan area network solutions.

[0009] In some possible implementations, d scr =336×m. In the embodiment of the present application, the number of bits is d in After the first bit of data is processed (including the "first data processing" and "second data processing" in the specification), a DSP frame is obtained. At this time, d scr =d in +d CP =L×m=336×m, which makes the proposed data processing method have lower implementation complexity and lower power consumption.

[0010] In some possible implementations, the number of bits in the first bit subset is an integer multiple of 16 or 32, the second bit subset includes 2048 bits, the third bit subset includes 1504 bits, and the second bit set includes 4096 bits.

[0011] In some possible implementations, the first bit data includes r rows and q columns of bits, d in =r×q, r is an integer greater than 1, q=2056 or 10280.

[0012] In some possible implementations, the number of bits is d in The method comprises: performing a cyclic redundancy check (CRC) on the first bit data and / or inserting padding bits to obtain the second bit data; wherein performing CRC on the first bit data comprises: performing a CRC-32 check on a total of r / p×q bits in each r / p row of the first bit data, adding a check bit with a length of 32 bits, and d CRC =32×p, r is divisible by p, and p is an integer greater than 1;

[0013] Alternatively, a CRC-32 check is performed on each r0 row of the first r0×(p-1) rows of the first bit data, totaling q×r0 bits, to add a check bit with a length of 32 bits, and a CRC-32 check is performed on the last r1 row of the first data, totaling q×r1 bits, to add a check bit with a length of 32 bits, wherein d CRC =32×p, r cannot be divided by p, p is an integer greater than 1, r0×(p-1)+r1=r, the integer r0 is greater than the integer r1.

[0014] In some possible implementations, q=2056, r, m, d CP , the values ​​of p and r1 are any of the following sets:

[0015] The data processing method provided in this embodiment requires CRC checking to detect data errors and reuses existing 800G-ZR CRC technology, simplifying implementation. Furthermore, when the first bit of data is FlexO-4e or 400G-ZR frame data, the corresponding baud rate is guaranteed to be less than 100GBaud, ensuring good compatibility with existing 400G data center and metropolitan area network solutions.

[0016] In some possible implementations, m is an integer multiple of 32, q=2056; r, m, d CP , the values ​​of p and r1 are any of the following sets:

[0017] The parameters provided in the embodiment of the present application can ensure the performance of FEC while simplifying the hardware implementation and reducing the complexity. In some possible implementations, q = 10280, r, m, d CP , the values ​​of p and r1 are any of the following sets:

[0018] The data processing method provided in this embodiment requires CRC checking to detect data errors and reuses existing 800G-ZR CRC technology, simplifying implementation. Furthermore, when the first bit of data is FlexO-4e or 400G-ZR frame data, the corresponding baud rate is guaranteed to be less than 100GBaud, ensuring good compatibility with existing 400G data center and metropolitan area network solutions.

[0019] In some possible implementations, m is an integer multiple of 32, q=10280, r, m, d CP , the values ​​of p and r1 are any of the following sets:

[0020] The parameters provided in the embodiments of the present application can ensure FEC performance while simplifying hardware implementation and reducing complexity.

[0021] In some possible implementations, the third bit subset includes 1504 bits, and the first bit subset includes m-1504 bits; performing probabilistic constellation shaping (PCS) processing on the first bit subset in the first bit set having m bits to obtain the second bit subset includes: dividing the first bit subset into 16 groups of sequences, each group of sequences including (m-1504) / 16 bits; performing PCS sub-processing on the 16 groups of sequences respectively to obtain 16 groups of output sequences corresponding to the 16 groups of sequences, wherein each group of output sequences includes 128 bits, and the 16 groups of output sequences constitute the second bit subset.

[0022] In some possible implementations, the third bit subset includes 1504 bits, and the first bit subset includes m-1504 bits; performing probabilistic constellation shaping (PCS) processing on the first bit subset in the first bit set with a bit number m to obtain the second bit subset includes: dividing the first bit subset into 32 groups of sequences, each group of sequences including (m-1504) / 32 bits; performing PCS sub-processing on the 32 groups of sequences respectively to obtain 32 groups of output sequences corresponding to the 32 groups of sequences, wherein each group of output sequences includes 64 bits, and the 32 groups of output sequences constitute the second bit subset.

[0023] In some possible embodiments, after obtaining the second bit set, the method further includes: performing symbol mapping and polarization division on the fourth bit data to obtain a dual-polarization symbol sequence, wherein the symbol mapping and the polarization division map 8 bits into 1 dual-polarization DP-16QAM symbol, and the fourth bit data includes multiple of the second bit sets; performing digital signal processing (DSP) framing on the dual-polarization symbol sequence to obtain a DSP frame (also called a superframe).

[0024] In some possible implementations, performing DSP framing on the dual-polarization symbol sequence includes: performing DSP framing processing on every 172032 dual-polarization DP-16QAM symbols to obtain a DSP frame.

[0025] In the second aspect, the present application provides a data processing device, comprising: a first processing unit, a scrambling unit, a probabilistic constellation shaping PCS unit and a forward error correction FEC encoding and interleaving unit; the first processing unit is used to: according to the number of bits d in The first bit data is obtained, and the second bit data is obtained, wherein the second bit data includes d in bits in the first bit data, d CRC parity bits and / or d PAD Filling bits, d CRC is an integer greater than or equal to 0, d PAD is an integer greater than or equal to 0; the scrambling unit is used to: scramble the second bit data to obtain a third bit data, the number of bits of the third bit data is d scr =r×q+d CP , d CP =d CRC +d PAD The PCS unit is configured to perform PCS processing on a first bit subset in a first bit set having a bit number m to obtain a second bit subset, wherein the first bit set is obtained from the third bit data, m is an integer greater than 1, and d scr is an integer multiple of m; the FEC encoding and interleaving unit is used to: perform FEC encoding and interleaving on the second bit subset and the third bit subset of the first bit set excluding the first bit subset to obtain a second bit set, wherein d in , m and d CP The value of is any one of the following sets:

[0026] In this embodiment, for future metropolitan area telecommunication transmission and metropolitan area DCI interconnection scenarios, FEC coding will be adopted in combination with PCS technology to meet longer transmission distances. The introduction of PCS processing means that the data processing granularity for "PCS processing and FEC coding" (i.e., the first sub-processing in the specification) is no longer 3552, but a smaller value m. At this time, it is necessary to redesign the number of rows for obtaining data from the data frame, the number of CRC checks and the number of padding bits to be inserted, so as to make the overall data processing operation simpler, less complex, and less power-consuming. Moreover, when the first bit of data is FlexO-4e or 400G-ZR frame data, the corresponding baud rate is less than 100GBaud, which is better compatible with existing 400G data centers and metropolitan area network solutions.

[0027] In some possible implementations, d scr =336×m. In the embodiment of the present application, the number of bits is d in After the first bit of data is processed (including the "first data processing" and "second data processing" in the specification), a DSP frame is obtained. At this time, d scr =d in +d CP =L×m=336×m, which makes the proposed data processing method have lower implementation complexity and lower power consumption.

[0028] In some possible implementations, the number of bits in the first bit subset is an integer multiple of 16 or 32, the second bit subset includes 2048 bits, the third bit subset includes 1504 bits, and the second bit set includes 4096 bits.

[0029] In some possible implementations, the first bit data includes r rows and q columns of bits, d in =r×q, r is an integer greater than 1, q=2056 or 10280.

[0030] In some possible implementations, the processing unit is specifically configured to: perform a CRC-32 check on a total of r / p×q bits in each r / p row of the first bit data, add a check bit with a length of 32 bits, and CRC =32×p, r is divisible by p, and p is an integer greater than 1;

[0031] Alternatively, a CRC-32 check is performed on each r0 row of the first r0×(p-1) rows of the first bit data, totaling q×r0 bits, to add a check bit with a length of 32 bits, and a CRC-32 check is performed on the last r1 row of the first data, totaling q×r1 bits, to add a check bit with a length of 32 bits, wherein d CRC=32×p, r cannot be divided by p, p is an integer greater than 1, r0×(p-1)+r1=r, the integer r0 is greater than the integer r1.

[0032] In some possible implementations, q=2056, r, m, d CP , the values ​​of p and r1 are any of the following sets:

[0033] The data processing method provided in this embodiment requires CRC checking to detect data errors and reuses existing 800G-ZR CRC technology, simplifying implementation. Furthermore, when the first bit of data is FlexO-4e or 400G-ZR frame data, the corresponding baud rate is guaranteed to be less than 100GBaud, ensuring good compatibility with existing 400G data center and metropolitan area network solutions.

[0034] In some possible implementations, m is an integer multiple of 32, q=2056; r, m, d CP , the values ​​of p and r1 are any of the following sets:

[0035] The parameters provided in the embodiments of the present application can ensure FEC performance while simplifying hardware implementation and reducing complexity.

[0036] In some possible implementations, q=10280, r, m, d CP , the values ​​of p and r1 are any of the following sets:

[0037] The data processing method provided in this embodiment requires CRC checking to detect data errors and reuses existing 800G-ZR CRC technology, simplifying implementation. Furthermore, when the first bit of data is FlexO-4e or 400G-ZR frame data, the corresponding baud rate is guaranteed to be less than 100GBaud, ensuring good compatibility with existing 400G data center and metropolitan area network solutions.

[0038] In some possible implementations, m is an integer multiple of 32, q=10280, r, m, d CP , the values ​​of p and r1 are any of the following sets:

[0039] The parameters provided in the embodiments of the present application can ensure FEC performance while simplifying hardware implementation and reducing complexity.

[0040] In some possible implementations, the third bit subset includes 1504 bits, and the first bit subset includes m-1504 bits; the PCS unit is used to: divide the first bit subset into 16 groups of sequences, each group of sequences includes (m-1504) / 16 bits; perform PCS sub-processing on the 16 groups of sequences respectively to obtain 16 groups of output sequences corresponding to the 16 groups of sequences, wherein each group of output sequences includes 128 bits, and the 16 groups of output sequences constitute the second bit subset.

[0041] In some possible implementations, the third bit subset includes 1504 bits, and the first bit subset includes m-1504 bits; performing probabilistic constellation shaping (PCS) processing on the first bit subset in the first bit set with a bit number m to obtain the second bit subset includes: dividing the first bit subset into 32 groups of sequences, each group of sequences including (m-1504) / 32 bits; performing PCS sub-processing on the 32 groups of sequences respectively to obtain 32 groups of output sequences corresponding to the 32 groups of sequences, wherein each group of output sequences includes 64 bits, and the 32 groups of output sequences constitute the second bit subset.

[0042] In some possible embodiments, the data processing device also includes a second processing unit and a digital signal processing (DSP) framing unit; the second processing unit is used to perform symbol mapping and polarization division on the fourth bit data to obtain a dual-polarization symbol sequence, wherein the symbol mapping and the polarization division map 8 bits into 1 dual-polarization DP-16QAM symbol, and the fourth bit data includes multiple sets of the second bits; the DSP framing unit is used to perform DSP framing on the dual-polarization symbol sequence to obtain a DSP frame (also called a superframe).

[0043] In some possible implementations, the DSP framing unit is configured to perform framing processing on every 172032 dual-polarization DP-16QAM symbols to obtain a DSP frame.

[0044] In a third aspect, the present application provides a chip comprising a processor configured to execute the method described in any embodiment of the first aspect.

[0045] In a fourth aspect, embodiments of the present application provide an optical module. The optical module includes a processor and an interface, wherein the processor is configured to execute the method described in any embodiment of the first aspect and to send signals through the interface. For example, the interface is configured to send signals from the processor or transmit received signals to the processor.

[0046] In some possible implementations, the interface is specifically an electrical interface, and the processor is configured to send electrical signals via the interface. For example, the processor executes the method described in any implementation of the first aspect and performs data processing on the second bit set to obtain a DSP frame, and then sends the DSP frame via the interface. The data processing herein includes symbol mapping, polarization division, and DSP framing.

[0047] In some possible implementations, the interface is specifically an optical interface, and the optical module further includes a modulator. For example, the processor executes the method described in any implementation of the first aspect and performs data processing on the second bit set to obtain a DSP frame. The modulator then performs signal processing such as electro-optical conversion based on the DSP frame to obtain an optical signal, which is then transmitted via the interface. The data processing herein includes symbol mapping, polarization division, and DSP framing.

[0048] In a fifth aspect, an embodiment of the present application provides a sending device, which includes a host-side device and an optical module as described in any embodiment of the fourth aspect, wherein the optical module is configured to generate an optical signal based on data from the host-side device and send the optical signal.

[0049] In a sixth aspect, an embodiment of the present application provides a communication system, which includes the sending device and receiving device introduced in the fifth aspect, and the sending device is used to send an optical signal to the receiving device.

[0050] In a seventh aspect, the present application provides a computer-readable storage medium having instructions stored thereon. When the instructions are executed by a computer, the method described in any embodiment of the first aspect is implemented.

[0051] In an eighth aspect, the present application provides a computer program product, which includes program instructions. When the computer program product is executed, it is used to implement the method introduced in any embodiment of the first aspect above. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] FIG1 is a schematic diagram of a communication system used in an embodiment of the present application;

[0053] FIG2 is a schematic diagram of the structure of a data frame;

[0054] FIG3 is a schematic diagram of an embodiment of data processing in an embodiment of the present application;

[0055] FIG4 is a schematic diagram of an embodiment of the first sub-process in the embodiment of the present application;

[0056] FIG5( a ) is a schematic diagram of an embodiment of the second sub-process in an embodiment of the present application;

[0057] FIG5( b ) is a schematic diagram of another embodiment of the second sub-process in the embodiment of the present application;

[0058] FIG5( c ) is a schematic diagram of another embodiment of the second sub-processing in the embodiment of the present application;

[0059] FIG6 is a schematic diagram of an implementation method of performing CRC on data in an embodiment of the present application;

[0060] FIG7 is a schematic diagram of another implementation method of performing CRC on data in an embodiment of the present application;

[0061] FIG8 is a schematic diagram of another implementation method of performing CRC on data in an embodiment of the present application;

[0062] FIG9 is a schematic structural diagram of a data processing device according to an embodiment of the present application;

[0063] FIG10 is another structural diagram of a data processing device according to an embodiment of the present application;

[0064] FIG11 is a schematic structural diagram of an optical module according to an embodiment of the present application;

[0065] FIG12 is a schematic structural diagram of a sending device in an embodiment of the present application. DETAILED DESCRIPTION

[0066] The embodiments of the present application provide a data processing method and a data processing device, which use FEC coding and combine it with PCS technology to reduce the baud rate required by the solution and make the overall data processing operation simpler, less complex, and with lower power consumption, meeting the needs of long-distance transmission scenarios.

[0067] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, rather than to limit a specific order or precedence. It should be understood that the above terms are interchangeable where appropriate so that the embodiments described in this application can be implemented in a sequence other than that described in this application. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0068] Figure 1 is a schematic diagram of a communication system used in an embodiment of the present application. As shown in Figure 1, at the transmitting end, the information source provides a data stream to be sent, and the transmitting end data processor receives the data stream. The transmitting end data processor first performs data processing including PCS processing, encoding, interleaving, symbol mapping, and DSP framing to obtain a symbol data stream, which is then sent to the transmitting end signal processor for signal processing, and then transmitted through the channel to the receiving device. After the receiving device receives the distorted signal caused by noise or other damage in the channel, it is sent to the receiving end signal processor for dispersion compensation, synchronization, phase recovery and other operations, and then sent to the receiving end data processor for operations including demodulation, deinterleaving, decoding processing, etc. to restore the original data, and then send the recovered data to the destination. In some specific applications, the transmitting end data processor can be implemented in an optical module. For example, the optical module can be a 400G long-haul (LH) module (400G-LH module, a coherent optical module).

[0069] It should be noted that some of the operation symbols appearing in the formulas involved in the embodiments of this application, Operation, which means rounding a down to an integer. For example, The b%c operation in the embodiments of the present application represents the modulus of b with respect to c. When b is non-negative, the value of b%c is the remainder of b divided by c. For example, 8%3=2, 2%3=2. When b is negative, the value of b%c is the modulus of b plus an integer multiple of c to obtain a positive integer. For example, -9%16=7, -10%3=2.

[0070] It should be noted that the concepts of bit sets and bit subsets in this specification and claims are merely introduced for ease of description. In practical applications, the data stream is a whole and not divided. Each bit set or bit subset can be considered as one or more bits in the data stream. It should be understood that bit sets and bit subsets can also be presented in the form of matrices, arrays, sequences, etc., which are not specifically limited here.

[0071] Figure 2 is a schematic diagram of the structure of a data frame. As shown in Figure 2, the data frame includes multiple rows of bits, and each row includes q bits. It should be understood that the present application does not limit the specific type of data frame. As an example, a 400G frame contains 256 rows, each row contains 10280 bits. As another example, in order to better adapt to PCS processing, a 400G frame contains 1280 rows, each row contains 2056 bits. In some specific applications, the integer q is an integer multiple of 257; typically, q is 10280, 8224, 5140, 4112, or 2056, etc.

[0072] It should be noted that the data processing method provided in this application can be divided into two parts, respectively referred to as "first data processing" and "second data processing", as shown in Figure 3. The following is a detailed introduction to the "first data processing" and "second data processing" respectively.

[0073] 1) First data processing

[0074] As shown in Figure 3, the first data processing includes adding cyclic redundancy check (CRC) and / or padding bits, and scrambling. In practical applications, at least one of adding CRC and inserting padding can be performed.

[0075] As an example, the first bit of data is d in =q×r bits. Then, according to the number of bits d in The first bit data can be obtained by adding CRC and / or padding bits to the first bit data to obtain the second bit data. CRC CRC check bits are inserted during the operation of adding padding bits. PAD Pad bits. scr =q×r+d CRC +d PAD The second bit data of bits is scrambled to obtain the number of bits d scr The third bit of data. CRC is an integer greater than or equal to 0, d PAD is an integer greater than or equal to 0, which can be expressed as d CP =d CRC +d PAD , at this time d scr =q×r+d CP In this case, the redundancy corresponding to the CRC checksum and inserted padding bits is OH CP =d scr / d in -1=(d CRC +d PAD ) / (q×r). It should be noted that, in some specific applications, the padding (Pad) bits are all 0 bits.

[0076] As an example, when d PAD =0, q×r+d after CRC check CRC As another example, in order to achieve lower latency and lower complexity, the CRC check is bypassed and replaced with padding bits, that is, dCRC =0.

[0077] It should be noted that in some specific application scenarios, CRC check uses CRC-32. As an example, a total of p CRC-32 operations are performed on the first bit of data, where p is an integer greater than 1 and the integer r is divisible by p, that is, r / p is an integer. At this time, d CRC =32×p. More specifically, for r rows of data obtained from the data frame, a CRC-32 operation is performed on each r / p row, totaling q×r / p bits, to add a 32-bit check bit. The CRC-32 operation is repeated p times to add a total of d CRC = 32 × p bits of CRC-32 check bits. It should be noted that in some specific implementations, q × r / p = 41120 is selected. In this case, the CRC-32 encoding and corresponding CRC check operations can directly use the CRC-32 operation in the existing 800G-ZR, where the CRC-32 operation is performed on 4 × 10280 = 41120 bits of data across 4 rows and 10280 columns. In some specific implementations, q = 2056 and r / p = 20.

[0078] It should be noted that in some other specific application scenarios, a total of p CRC-32 operations are performed on the first bit of data, where the number of CRC-32 operations p is an integer greater than 1 but the integer r cannot be divided by p, that is, r / p is not an integer. In this case, consider r0×(p-1)+r1=r, where the integer r0 is greater than the integer r1. In some specific implementations, the integer Integer r1=r-r0×(p-1), and r0>r1. A specific implementation method is given below. For the r lines of data obtained from the data frame, a CRC-32 check is performed on each r0 line of the first r0×(p-1) lines of the r lines of data, totaling q×r0 bits, and a check bit with a length of 32 bits is added, resulting in a total of 32×(p-1) CRC check bits; a CRC-32 operation is performed on the last r1 lines, totaling q×r1 bits, and a check bit with a length of 32 bits is added; a total of d CRC =32×(p-1)+32=32×p CRC-32 check bits. It should be noted that in some specific implementations, q×r0=41120 is selected. In this case, the CRC-32 encoding and corresponding CRC check operations can directly use the CRC-32 operation in the existing 800G-ZR, where the CRC-32 operation is performed on 4×10280=41120 bits of data across 4 rows and 10280 columns. In some specific implementations, q=2056 and r0=20.

[0079] 2) Second data processing

[0080] As shown in FIG3 , the second data processing includes a first sub-processing and a second sub-processing. The third bit data output by the first data processing includes L first bit sets, wherein the number of bits in each first bit set is m. At this time, d scr =q×r+d CP =L×m. The first sub-processing in the second data processing performs a process including PCS, interleaving and coding on each of the L first bit sets to obtain a second bit set, and a total of L second bit sets are obtained. The second sub-processing in the second data processing performs a data process including symbol mapping, polarization distribution and DSP framing on the fourth bit data containing the L second bit sets to obtain a DSP frame (also called a DSP superframe). At this time, the total d in =q×r bits of first bit data undergo the first data processing and the second data processing to obtain just one DSP frame, so that the proposed data processing method has lower implementation complexity and lower power consumption.

[0081] The following describes the detailed operations of the first sub-processing within the second data processing. As shown in Figure 4 , the first bit set consists of a first bit subset and a third bit subset; the first bit subset undergoes probabilistic constellation shaping (PCS) processing to obtain a second bit subset; and the second bit subset and the third bit subset undergo processing including interleaving and FEC encoding to obtain a second bit set.

[0082] It should be noted that, in one embodiment of the present application, the number of bits of the second bit set is 4096 bits, the number of bits of the second bit subset is 2048 bits, the number of bits of the third bit subset is 1504 bits, and the number of bits of the first bit subset is v=m-1504 bits. The encoding encodes a total of 2048+1504=3552 bits of the third bit subset and the second bit subset, and adds check bits to obtain 4096 encoded bits. More specifically, the 3552 bits are represented by a bit matrix of 32 rows and 111 columns, also known as an information bit matrix. The encoding encodes 111 bits in each row and adds 17 bits, resulting in 32 rows and 128 columns for a total of 4096 encoded bits. The bit matrix of 32 rows and 128 columns is also called a codeword bit matrix. The encoding uses spatial coupling coding, that is, when encoding 3552 bits at a current moment to obtain 4096 coded bits, the 4096 coded bits obtained at a previous moment are also used, for example, using oFEC coding, which is not specifically limited here. It should be understood that m<3552.

[0083] It should be noted that before performing FEC encoding, the 3552 bits may also be subjected to pre-coding interleaving, which is also called block mapping, pre-coding interleaving, or pre-FEC permutation. After performing FEC encoding, the 4096 coded bits may also be subjected to post-coding interleaving. Pre-coding interleaving and post-coding interleaving are collectively referred to as interleaving here, without specific limitation. It should be noted that the L second bit sets obtained by the first sub-processing may also be subjected to interleaving before the second sub-processing, which is not specifically limited here.

[0084] The second sub-processing in the second data processing is described below in detail. The second sub-processing includes symbol mapping, polarization distribution, and DSP framing, which can be understood by referring to Figure 5(a), Figure 5(b), or Figure 5(c).

[0085] As shown in Figure 5(a), the fourth bit data undergoes symbol mapping and polarization distribution to obtain a dual-polarization symbol sequence. The dual-polarization symbol sequence is also called a pre-framing symbol sequence. It should be noted that symbol mapping and polarization distribution can also be referred to as dual-polarization (DP) symbol mapping. For example, 16QAM symbol mapping and polarization distribution can be referred to as DP-16QAM symbol mapping or DP-16QAM mapping. The symbol mapping performs symbol mapping on every 4 bits in the fourth bit data into one symbol. Symbol mapping and polarization distribution (i.e., dual-polarization symbol mapping) maps every 8 bits in the fourth bit data into one dual-polarization symbol, where one dual-polarization symbol includes one X-polarization (X polarization) direction symbol and one Y-polarization (Y polarization) direction symbol. Then, the second sub-processing performs DSP framing operation on the dual-polarization symbol sequence (symbol sequence before framing). Specifically, a frame alignment word sequence (FAW sequence), a training symbol sequence, and at least one of a reserved symbol sequence and a pilot symbol sequence are inserted in the X and Y polarization directions, respectively, to obtain a dual-polarization symbol sequence to be transmitted, also known as a DSP frame. For example, the DSP framing operation performs DSP framing on every 172,032 dual-polarization symbols to obtain a DSP frame.

[0086] In some specific applications, the DSP framing operation performs DSP framing on every 172032 dual-polarization symbols (symbols before framing) to obtain a DSP frame containing 178176 dual-polarization symbols. The redundancy of the DSP framing is h DSP =178176 / 172032-1=1 / 28≈3.57%. In some other specific applications, the DSP framing operation performs DSP framing on every 172032 dual-polarization symbols (symbols before framing) to obtain a DSP frame containing 175104 dual-polarization symbols. The redundancy of the DSP framing is h DSP =175104 / 172032-1=1 / 56≈1.79%. In some embodiments, in the X polarization direction or the Y polarization direction, each N G A fixed symbol in the N symbols is a pilot symbol. G The first symbol among the symbols is the pilot symbol. Typically, NG =32 or 64 or 96 or 128, etc. In some specific applications, the symbol mapping is called 16QAM mapping.

[0087] It should be noted that the frame synchronization symbol is used for frame synchronization alignment, the training symbol is used for link training, the pilot symbol is used for carrier phase recovery, and the reserved symbol is used for future use and innovation. The value of the reserved symbol can be known and unchanged, or it can be randomized. The value of the reserved symbol can also be called a pattern. In some specific embodiments, the DSP frame includes multiple subframes, and the DSP frame can be called a super-frame. In other specific embodiments, the DSP frame can also be called a multi-frame, the reserved symbol can also be called fixed stuff (FS), and the frame synchronization symbol can also be called a multi-frame alignment signal (MFAS).

[0088] It should be noted that the DSP framing operation shown in Figure 5(a) is performed on symbols, that is, the DSP framing is performed after the symbol mapping operation. The DSP framing operation can also be performed on bits, as shown in Figures 5(b) and 5(c), where the DSP framing is performed before the symbol mapping operation. Figure 5(b) is a schematic diagram of another embodiment of the second sub-processing in the embodiment of the present application. As shown in Figure 5(b), the DSP framing operation is to insert the bits corresponding to the frame synchronization symbol sequence, training symbol sequence, reserved symbol sequence and pilot symbol sequence into the fourth bit data before symbol mapping, and then perform symbol mapping and polarization division to obtain the same DSP frame (also called superframe) as the operation in Figure 5(a). Figure 5(c) is a schematic diagram of another embodiment of the second sub-processing in the embodiment of the present application. As shown in Figure 5(c), the DSP framing operation is to insert the bits corresponding to the frame synchronization symbol sequence, training symbol sequence, reserved symbol sequence and pilot symbol sequence into the fourth bit data before symbol mapping, and then after polarization division and symbol mapping, the same DSP frame (also called superframe) as the operation in Figure 5(a) can be obtained; it should be understood that there are other framing operations that are not excluded and will not be described in detail in this application.

[0089] In this application, considering the DSP framing operation, every 172032 dual-polarization DP-16QAM symbols (pre-framing symbols) are subjected to DSP framing processing to obtain a DSP frame (also called a superframe). The number of bits of the fourth bit data containing L second bit sets is 172032×8=1376256. Considering that the number of bits of the second bit set is 4096 bits, L=1376256 / 4096=336. At this time, there is dscr =q×r+d CP =L×m=336×m.

[0090] It should be noted that the PCS process processes the input bits so that the probabilities of 0 and 1 appearing in the output bits are different. In some specific applications, the PCS process may also be referred to as a distribution matcher (DM). The PCS process can be implemented in various specific ways, such as using arithmetic coding (arithmetic coding), lookup tables (LUTs), trellis coding, etc.

[0091] To simplify the implementation of PCS processing, multiple PCS sub-processes are usually used to achieve the PCS processing effect. Each PCS sub-processing performs PCS sub-processing on k0 input bits to obtain n0 output bits, where n0>k0. It should be noted that the larger the value of n0, the better the performance of PCS processing, but the higher the complexity. In practical applications, a compromise between performance and complexity must be made. Typically, consider n0 = 128 or 64. In some specific applications, the PCS processing can be implemented using multiple lookup tables (LUTs), that is, each PCS sub-processing is implemented using a lookup table LUT processing. Each lookup table performs LUT mapping on the k0 input bits to obtain n0 output bits, where n0>k0. In this case, the PCS processing can also be called PCS LUT processing.

[0092] In some specific applications, the above-mentioned lookup table LUT processing can also be implemented using multiple sub-lookup tables to reduce complexity. In some specific implementations, the number of input bits of the multiple sub-lookup tables may be different, and the number of output bits may also be different. For example, each lookup table performs LUT mapping on the input k0 bits to obtain an output of n0=128 bits. The lookup table is composed of 12 sub-lookup tables, of which 4 sub-lookup tables have an output bit number of 10, and 8 sub-lookup tables have an output bit number of 11. The total output bits of the 12 sub-lookup tables are 4×10+8×11=128 as the n0=128 output bits of the lookup table.

[0093] In one embodiment, a first bit subset comprising v = m - 1504 bits is subjected to PCS processing to obtain a second bit subset comprising 2048 bits. In the embodiment of the present application, considering that n0 is specifically 128, 64, 32, or 16, the specific implementation of PCS processing can be facilitated and has lower complexity. In other words, v = m - 1504 is an integer multiple of 2048 / 128 = 16, 2048 / 64 = 32, 2048 / 32 = 64, or 2048 / 16 = 128. Here, we consider that v = m - 1504 is an integer multiple of 2048 / 128 = 16, and m < 3552. In this case, m is also an integer multiple of 16.

[0094] In some specific applications, performing probabilistic constellation shaping (PCS) processing on a first bit subset in a first bit set having a bit number m to obtain a second bit subset containing 2048 bits includes: dividing the first bit subset into 16 groups of sequences, each group of sequences including (m-1504) / 16 bits; performing PCS sub-processing on the 16 groups of sequences respectively to obtain 16 groups of output sequences corresponding to the 16 groups of sequences, wherein each group of output sequences includes 128 bits, and the 16 groups of output sequences constitute the second bit subset of 128×16=2048 bits.

[0095] In other specific applications, the performing probabilistic constellation shaping (PCS) processing on a first bit subset in a first bit set having a bit number m to obtain a second bit subset comprising 2048 bits includes: dividing the first bit subset into 32 groups of sequences, each group of sequences comprising (m-1504) / 32 bits; and performing PCS sub-processing on the 32 groups of sequences respectively to obtain 32 groups of output sequences corresponding to the 32 groups of sequences, wherein each group of output sequences comprises 64 bits, and the 32 groups of output sequences constitute the second bit subset comprising 64×32=2048 bits.

[0096] The first bit data contains r rows and q columns of bits, a total of d in =q×r bits. The following describes the two cases of q=2056 and q=10280 respectively.

[0097] First, consider the case where q = 2056

[0098] The number of bits of the third bit data is d scr =q×r+d CP = L × m = 336 × m. It should be understood that the number of bits d of the added CRC and / or padding bits CP The larger the value, the more redundant OH CP =d CP / (q×r) is larger. For transmission efficiency, we consider 0≤dCP <2×q=4112, which can ensure transmission performance and reduce redundancy. The following Table 1 gives the corresponding {d in , r, m, d CP} parameter combination.

[0099] Table 1

[0100] Table 1 also gives {r, m, d CP} parameter combination, the corresponding specific value of v / 16. It should be noted that v=m-1504 is an integer multiple of 16. When n0=128, k0=v / 16, that is, the PCS processing uses 16 PCS sub-processing to achieve the PCS processing effect, wherein each PCS sub-processing performs PCS sub-processing on the input k0=v / 16 bits to obtain an output n0=128 bits. In some specific applications, the 16 PCS sub-processing is implemented using 16 lookup tables LUTs. In other specific applications, the 16 PCS sub-processing is implemented using 16 trellis coding. It should be noted that in other specific embodiments, considering that v = m - 1504 is an integer multiple of 32, when n0 = 64, k0 = v / 32, that is, the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect, where each PCS sub-process performs PCS sub-processing on k0 = v / 32 bits of input to obtain n0 = 64 bits of output. In some specific applications, the 32 PCS sub-processes are implemented using 32 lookup tables (LUTs). In other specific applications, the 32 PCS sub-processes are implemented using 32 trellis coding.

[0101] It should be noted that in some specific applications, the first data processing includes adding a cyclic redundancy check CRC-32 operation. At this time, consider the following first constraint: when the number of rows r is an integer multiple of 20, the number of CRC-32 operations p = r / 20, d CRC =r / 20×32≤d CP , that is, CRC-32 operation is performed on every 20 rows of r rows of data, totaling 20×2056=41120 bits; when the number of rows r is not an integer multiple of 20, there are CRC-32 operation times in The operation means rounding a down, that is, r0=20, r1=r-20×(p-1), performing CRC-32 on each r0=20 rows of the first 20×(p-1) rows of r rows, totaling q×r0=41120 bits, and performing a CRC-32 operation on the last r1 rows, totaling q×r1 bits. Consider d PAD =d CP -d CRC Combining Table 1 and the first constraint above, the following Table 2 gives the corresponding {r, m, d CP d PAD , p} parameter combination. It should be noted that the last column of Table 2 also provides the specific value of parameter r1 when the number of rows r is not an integer multiple of 20. When the number of rows r is an integer multiple of 20, such as r = 540 in row 23 of Table 2, the corresponding parameter r1 is represented by a slash in the table, indicating that the parameter r1 does not exist.

[0102] Table 2

[0103] Table 2 also gives {r, m, d CP d PAD , p} parameter combination, the corresponding specific value of v / 16. It should be noted that v=m-1504 is an integer multiple of 16. When n0=128, k0=v / 16, that is, the PCS processing uses 16 PCS sub-processing to achieve the PCS processing effect, where each PCS sub-processing performs PCS sub-processing on the input k0=v / 16 bits to obtain an output n0=128 bits. In some specific applications, the 16 PCS sub-processing is implemented using 16 lookup tables (LUTs). In other specific applications, the 16 PCS sub-processing is implemented using 16 trellis coding. It should be noted that in other specific embodiments, considering that v = m - 1504 is an integer multiple of 32, when n0 = 64, k0 = v / 32, that is, the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect, where each PCS sub-process performs PCS sub-processing on k0 = v / 32 bits of input to obtain n0 = 64 bits of output. In some specific applications, the 32 PCS sub-processes are implemented using 32 lookup tables (LUTs). In other specific applications, the 32 PCS sub-processes are implemented using 32 trellis coding.

[0104] It should be noted that in other specific applications, a first bit set containing m bits is considered to be subjected to a first sub-processing including PCS, interleaving, and encoding to obtain a second bit set containing 4096 bits, wherein the ratio of the encoding input bit length to the encoding output bit length in the encoding operation is 3552:4096=111:128. Consider that the ratio of the input bit length m and the output bit length 4096 of the first sub-processing (including PCS processing, interleaving, and encoding) is m:4096=f1:f2, where the greatest common divisor of the integers f1 and f2 is 1. Typically, when the values ​​of f1 and f2 are smaller, the overall hardware implementation can be simpler, the complexity is lower, and the power consumption is lower. Therefore, considering the following second constraint, that is, m is an integer multiple of 32, the ratio of the input bit length m and the output bit length 4096 of the first sub-processing is m:4096=f:128, where the integer f=m / 32, which can be understood in conjunction with Figure 4. Combining Table 1 and the second constraint above, the following Table 3 gives the corresponding {r, m, d CP ,f} parameter combination.

[0105] Table 3

[0106] Table 3 also gives {r, m, d CP , f} parameter combination, the corresponding specific value of v / 16. It should be noted that v=m-1504 is an integer multiple of 16. When n0=128, k0=v / 16, that is, the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect, where each PCS sub-processing performs PCS sub-processing on the input k0=v / 16 bits to obtain an output n0=128 bits. In some specific applications, the 16 PCS sub-processes are implemented using 16 lookup tables (LUTs). In other specific applications, the 16 PCS sub-processes are implemented using 16 trellis coding. It should be noted that in other specific embodiments, considering that v = m - 1504 is an integer multiple of 32, when n0 = 64, k0 = v / 32, that is, the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect, where each PCS sub-process performs PCS sub-processing on k0 = v / 32 bits of input to obtain n0 = 64 bits of output. In some specific applications, the 32 PCS sub-processes are implemented using 32 lookup tables (LUTs). In other specific applications, the 32 PCS sub-processes are implemented using 32 trellis coding.

[0107] It should be noted that in some specific applications, the first and second constraints are considered. In this case, combined with Table 1 and the first and second constraints, the following Table 4 gives the corresponding {r, m, d CP d PAD , f, p} parameter combinations. It should be noted that the last column of Table 4 also provides the specific value of parameter r1 when the number of rows r is not an integer multiple of 20. When the number of rows r is an integer multiple of 20, such as r = 480 in row 28 of Table 4, the corresponding parameter r1 is represented by a slash in the table, indicating that the parameter r1 does not exist.

[0108] Table 4

[0109] Table 4 also gives {r, m, d CP d PAD , f, p} parameter combination, the corresponding specific value of v / 16. It should be noted that v=m-1504 is an integer multiple of 16. When n0=128, k0=v / 16, that is, the PCS processing uses 16 PCS sub-processing to achieve the PCS processing effect, wherein each PCS sub-processing performs PCS sub-processing on the input k0=v / 16 bits to obtain an output n0=128 bits. In some specific applications, the 16 PCS sub-processing is implemented using 16 lookup tables (LUTs). In other specific applications, the 16 PCS sub-processing is implemented using 16 trellis coding. It should be noted that in other specific embodiments, considering that v = m - 1504 is an integer multiple of 32, when n0 = 64, k0 = v / 32, that is, the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect, where each PCS sub-process performs PCS sub-processing on k0 = v / 32 bits of input to obtain n0 = 64 bits of output. In some specific applications, the 32 PCS sub-processes are implemented using 32 lookup tables (LUTs). In other specific applications, the 32 PCS sub-processes are implemented using 32 trellis coding.

[0110] It should be noted that, assuming the bit rate of the data frame is W0 Gbit / s, the corresponding bit rate after the first data processing is W0×(r×q+d CP ) / (r×q) Gbit / s, and the corresponding bit rate after the first sub-processing in the second data processing (i.e., PCS, interleaving and coding processing) is W1=W0×(r×q+d CP ) / (r×q)×(4096 / m). Considering the redundancy of DSP framing in the second data processing is h DSP, that is, the corresponding bit rate after the second data processing is W2=W1×(1+h DSP )=W0×(r×q+d CP ) / (r×q)×(4096 / m)×(1+h DSP ), the corresponding baud rate (i.e. symbol rate) is W s =W2 / 8=W0×(r×q+d CP ) / (r×q)×(4096 / m)×(1+h DSP ) / 8GBaud. Typically, considering the DSP framing redundancy is h DSP 1 / 28, or 1 / 56. It can be seen that for the parameter combinations given in Tables 1-4, when the input data for the first data processing (i.e., the first bit data) is FlexO-4e or 400G ZR frame data, the corresponding baud rates are all less than 100GBaud. It can be understood that the proposed data processing solution is highly compatible with existing 400G data centers and metropolitan area networks.

[0111] In the following, several specific embodiments are given in combination with the above introduction to the first data processing and the second data processing.

[0112] Example 1:

[0113] Consider that the input data of the first data processing (i.e., the first bit data) is FlexO-4e or 400G ZR frame data, and its nominal bit rate is W0≈402.489753310Gbit / s. It should be noted that the non-integer in the embodiment of the present application is only retained to 9 decimal places. In some specific applications, the description of the non-integer can be described in other forms, such as retaining 2 decimal places, etc. The description method is known to ordinary technicians in this field and will not be repeated here. The first bit data contains r rows, q=2056 columns, and a total of d in =q×r bits. After the first data processing, the corresponding bit rate is W0×(r×q+d CP ) / (r×q) Gbit / s, and the corresponding bit rate after the first sub-processing in the second data processing (i.e., PCS, interleaving and coding processing) is W1=W0×(r×q+d CP ) / (r×q)×(4096 / m).

[0114] In some specific applications, the redundancy of DSP framing in the second data processing is considered to be h DSP=1 / 28, each DSP frame (also called superframe or multiframe) contains 178176 dual-polarization symbols, of which 172032 dual-polarization symbols (i.e., symbols before framing) in each DSP frame are the fourth bit data obtained through symbol mapping and polarization division. At this time, the corresponding bit rate after the second data processing is W 2-28 =W1×(1+h DSP )=W0×(r×q+d CP ) / (r×q)×(4096 / m)×(29 / 28), the corresponding baud rate (i.e. symbol rate) is W s-28 =W 2-28 / 8=W0×(r×q+d CP ) / (r×q)×(4096 / m)×(29 / 28) / 8GBaud.

[0115] Table 5 below gives the corresponding {d in , r, m, d CP 、v / 16、W1、W 2-28 、W s-28} parameter combination.

[0116] Table 5

[0117] It should be noted that v = m - 1504 is an integer multiple of 16. In some specific implementations, considering n0 = 128, k0 = v / 16, that is, the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect, wherein each PCS sub-process performs PCS sub-processing on k0 = v / 16 input bits to obtain n0 = 128 output bits. In some specific applications, the 16 PCS sub-processes are implemented using 16 lookup tables (LUTs). In other specific applications, the 16 PCS sub-processes are implemented using 16 trellis coding. It should be noted that in other specific embodiments, considering v = m - 1504 is an integer multiple of 32, when n0 = 64, k0 = v / 32, that is, the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect, wherein each PCS sub-process performs PCS sub-processing on k0 = v / 32 input bits to obtain n0 = 64 output bits. In some specific applications, the 32 PCS sub-processes are implemented using 32 lookup tables (LUTs). In other specific applications, the 32 PCS sub-processes are implemented using 32 trellis codings.

[0118] It can be seen that the parameter combination given in this embodiment 1, when the input data of the first data processing (i.e., the first bit data) is FlexO-4e or 400G ZR frame data, the corresponding baud rate is less than 100GBaud; at this time, in the corresponding specific optical communication network transmission, the channel spacing that can be used is no more than 112.5GHz. It can be understood that the proposed data processing solution is well compatible with existing 400G data centers and metropolitan area networks. Moreover, it contains d in =q×r bits of first bit data undergo the first data processing and the second data processing to obtain just one DSP frame (also called a superframe or multi-frame), so that the proposed data processing method has lower implementation complexity and lower power consumption.

[0119] Example 2:

[0120] Based on Example 1, the first constraint and the second constraint are considered.

[0121] The first data processing includes adding a cyclic redundancy check CRC-32 operation. The CRC-32 encoding and the corresponding CRC check operation can directly use the CRC-32 operation in the existing 800G-ZR, which is easy to implement. That is, considering the first constraint as follows: when the number of rows r is an integer multiple of 20, there are CRC-32 operation times p = r / 20, d CRC =r / 20×32≤d CP , that is, CRC-32 operation is performed on every 20 rows of r rows of data, totaling 41120 bits; when the number of rows r is not an integer multiple of 20, there are CRC-32 operation times in The operation means rounding a down, that is, r0=20, r1=r-20×(p-1), performing CRC-32 on each r0=20 rows of the first 20×(p-1) rows of r rows, totaling q×r0=41120 bits, and performing a CRC-32 operation on the last r1 rows, totaling q×r1 bits. Consider d PAD =d CP -d CRC , you need to choose appropriate r, d CP Make d PAD ≥0.

[0122] Consider a first bit set containing m bits, and perform a first sub-processing including PCS, interleaving and encoding to obtain a second bit set containing 4096 bits, wherein the ratio of the encoding input bit length to the encoding output bit length in the encoding operation is 111:128. Consider that the ratio of the input bit length m and the output bit length 4096 of the first sub-processing (including PCS processing, interleaving and encoding) is m:4096=f1:f2, wherein the greatest common divisor of the integers f1 and f2 is 1. Typically, when the values ​​of f1 and f2 are smaller, the overall hardware implementation can be simpler, the complexity is lower, and the power consumption is lower. In order to facilitate the simplicity of hardware implementation, the following second constraint is considered, that is, m is an integer multiple of 32, so that the ratio of the input bit length m and the output bit length of the first sub-processing is f:128, wherein the integer f=m / 32.

[0123] In this embodiment 2, the redundancy of DSP framing in the second data processing is h DSP =1 / 28, each DSP frame (also called superframe or multiframe) contains 178176 dual-polarization symbols, of which 172032 dual-polarization symbols (i.e., symbols before framing) in each DSP frame are the fourth bit data obtained through symbol mapping and polarization division. At this time, the corresponding bit rate after the second data processing is W 2-28 =W1×(1+h DSP )=W0×(r×q+d CP ) / (r×q)×(4096 / m)×(29 / 28), the corresponding baud rate (i.e. symbol rate) is W s-28 =W 2-28 / 8=W0×(r×q+d CP ) / (r×q)×(4096 / m)×(29 / 28) / 8GBaud.

[0124] The following table 6 gives the corresponding {r, m, d CP d PAD ,f,p,v / 16,W1,W 2-28 、W s-28} parameter combination. It should be noted that Table 6 also provides the specific value of parameter r1 when the number of rows r is not an integer multiple of 20. When the number of rows r is an integer multiple of 20, such as r = 480 in row 28 of Table 6, the corresponding parameter r1 is represented by a slash in the table, indicating that the parameter r1 does not exist.

[0125] Table 6

[0126] It should be noted that v = m - 1504 is an integer multiple of 16. In some specific implementations, considering n0 = 128, k0 = v / 16, that is, the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect, wherein each PCS sub-process performs PCS sub-processing on k0 = v / 16 input bits to obtain n0 = 128 output bits. In some specific applications, the 16 PCS sub-processes are implemented using 16 lookup tables (LUTs). In other specific applications, the 16 PCS sub-processes are implemented using 16 trellis coding. It should be noted that in other specific embodiments, considering v = m - 1504 is an integer multiple of 32, when n0 = 64, k0 = v / 32, that is, the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect, wherein each PCS sub-process performs PCS sub-processing on k0 = v / 32 input bits to obtain n0 = 64 output bits. In some specific applications, the 32 PCS sub-processes are implemented using 32 lookup tables (LUTs). In other specific applications, the 32 PCS sub-processes are implemented using 32 trellis codings.

[0127] It can be seen that the parameter combination given in this embodiment 2, when the input data of the first data processing (i.e., the first bit data) is FlexO-4e or 400G ZR frame data, the corresponding baud rate is less than 100GBaud; at this time, in the corresponding specific optical communication network transmission, the channel spacing that can be used is no more than 112.5GHz. It can be understood that the proposed data processing solution is well compatible with existing 400G data centers and metropolitan area networks. Moreover, it contains d in =q×r bits of first-bit data undergo the first and second data processing to obtain a single DSP frame (also known as a superframe or multi-frame), resulting in the proposed data processing method having lower implementation complexity and lower power consumption. Furthermore, the CRC-32 operation included in the first data processing in this embodiment 2 utilizes the CRC-32 operation in the existing 800G-ZR, facilitating simple implementation. Furthermore, m is an integer multiple of 32, resulting in a ratio of the input bit length m to the output bit length of the first sub-processing to f:128, where the integer f = m / 32, simplifying hardware implementation.

[0128] Take some parameter combinations in Table 6 as an example, for example, the parameter combination in row 19, namely {r=506, m=3104, d CP =2608,d PAD =1776, f=97, p=26, r1=6, W1=532.451955840 (Gbit / s), W 2-28=551.468097120 (Gbit / s), W s-28 =68.933512140 (GBaud)}, the corresponding operation of adding cyclic redundancy check (CRC) and / or padding (Pad) bits can be understood with reference to FIG6. In this case, r0=20, and 1776b in FIG6 represents 1776 bits. It should be noted that in actual optical transmission applications, the channel spacing C grid GHz, its value is C grid (in G) is smaller than the baud rate value (in G), and C grid It is usually an integer multiple of 12.5. At this time, consider the baud rate corresponding to the parameter combination in line 21 is W s-28 = 68.933512140 (GBaud). In specific optical communication network transmission, the applicable channel spacing is 75 GHz. The proposed data processing solution is well compatible with existing 400G data centers and metropolitan area networks, such as OpenZR+, 400ZR, or 400ZR+ transmission networks using 75 GHz grid spacing.

[0129] For another example, the parameter combination in row 20 of Table 6, namely {r=501, m=3072, d CP =2136,d PAD =1304, f=96, p=26, r1=1, W1=537.765847615 (Gbit / s), W 2-28 =556.971770744 (Gbit / s), W s-28 =69.621471343 (GBaud)}. The corresponding addition of cyclic redundancy check (CRC) and / or padding bits can be understood with reference to Figure 7. In this case, r0 = 20, and 1304b in Figure 7 represents 1304 bits. In this case, a 75 GHz channel spacing can also be used in specific optical communication network transmission. The proposed data processing solution is highly compatible with existing 400G data centers and metropolitan area networks, such as OpenZR+, 400ZR, or 400ZR+ transmission networks using 75 GHz grid spacing.

[0130] Furthermore, consider the parameter combination in row 47 of Table 6, namely {r=412, m=2528, d CP =2336,d PAD =1664, f=79, p=21, r1=12, W1=653.933712755 (Gbit / s), W2-28 =677.288488210 (Gbit / s), W s-28 =84.661061026 (GBaud)}. In this case, in specific optical communication network transmission, the applicable channel spacing is 100 GHz. The proposed data processing solution is well compatible with existing 400G data centers and metropolitan area networks, such as OpenZR+, 400ZR, or 400ZR+ transmission networks that use 100 GHz grid spacing.

[0131] In other specific applications, the parameter combination in row 48 of Table 6 can be used, that is, {r=407, m=2496, d CP =1864,d PAD =1192, f=78, p=21, r1=7, W1=661.967296450 (Gbit / s), W 2-28 =685.608985608 (Gbit / s), W s-28 =85.701123201 (GBaud)}. In this case, in specific optical communication network transmission, the applicable channel spacing is 100 GHz. The proposed data processing solution is well compatible with existing 400G data centers and metropolitan area networks, such as OpenZR+, 400ZR, or 400ZR+ transmission networks using 100 GHz grid spacing.

[0132] In some specific applications, the parameter combination in row 49 of Table 6 can be used, that is, {r=406, m=2496, d CP =3920,d PAD =3248, f=78, p=21, r1=6, W1=663.597757771 (Gbit / s), W 2-28 =687.297677691(Gbit / s), W s-28 =85.912209711 (GBaud)}. In this case, in specific optical communication network transmission, the applicable channel spacing is 100 GHz. The proposed data processing solution is well compatible with existing 400G data centers and metropolitan area networks, such as OpenZR+, 400ZR, or 400ZR+ transmission networks with 100 GHz grid spacing.

[0133] For another example, consider the parameter combination in row 63 of Table 6, namely {r=365, m=2240, d CP =2200,d PAD=1592, f=70, p=19, r1=5, W1=738.138875767 (Gbit / s), W 2-28 =764.500978473 (Gbit / s), W s-28 =95.562622309 (GBaud)}. In this case, the applicable channel spacing in the corresponding optical communication network is 112.5 GHz. The proposed data processing solution is well compatible with existing 400G data centers and metropolitan area networks, such as high-performance metropolitan area transmission networks that use 112.5 GHz grid spacing.

[0134] In some specific applications, the parameter combination in row 64 of Table 6 can be used, that is, {r=360, m=2208, d CP =1728,d PAD =1152, f=69, p=18, W1=748.390804597 (Gbit / s), W 2-28 =775.119047618 (Gbit / s), W s-28 =96.889880952 (GBaud)}. The corresponding addition of cyclic redundancy check (CRC) and / or padding (Pad) bits can be understood with reference to Figure 8. In this case, r = 360 is divisible by p, r / p = 20, and 1152b in Figure 8 represents 1152 bits. In this case, the applicable channel spacing in the corresponding optical communication network is 112.5 GHz. The proposed data processing solution is highly compatible with existing 400G data centers and metropolitan area networks, such as high-performance metropolitan area transmission networks that utilize 112.5 GHz grid spacing.

[0135] Example 3:

[0136] Based on Example 1, the redundancy of DSP framing in the second data processing is considered to be h DSP =1 / 56, each DSP frame (also called superframe or multiframe) contains 175104 dual-polarization symbols, of which 172032 dual-polarization symbols (i.e., symbols before framing) in each DSP frame are the fourth bit data obtained through symbol mapping and polarization division. At this time, the corresponding bit rate after the second data processing is W 2-56 =W1×(1+h DSP )=W0×(r×q+d CP ) / (r×q)×(4096 / m)×(57 / 56), the corresponding baud rate (i.e. symbol rate) is W s-56 =W 2-56 / 8=W0×(r×q+dCP ) / (r×q)×(4096 / m)×(57 / 56) / 8GBaud.

[0137] Table 7 below gives the corresponding {d in , r, m, d CP 、v / 16、W1、W 2-56 、W s-56} parameter combination.

[0138] Table 7

[0139] It should be noted that v = m - 1504 is an integer multiple of 16. In some specific implementations, considering n0 = 128, k0 = v / 16, that is, the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect, wherein each PCS sub-process performs PCS sub-processing on k0 = v / 16 input bits to obtain n0 = 128 output bits. In some specific applications, the 16 PCS sub-processes are implemented using 16 lookup tables (LUTs). In other specific applications, the 16 PCS sub-processes are implemented using 16 trellis coding. It should be noted that in other specific embodiments, considering v = m - 1504 is an integer multiple of 32, when n0 = 64, k0 = v / 32, that is, the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect, wherein each PCS sub-process performs PCS sub-processing on k0 = v / 32 input bits to obtain n0 = 64 output bits. In some specific applications, the 32 PCS sub-processes are implemented using 32 lookup tables (LUTs). In other specific applications, the 32 PCS sub-processes are implemented using 32 trellis codings.

[0140] It can be seen that the parameter combination given in this embodiment 3, considering that the input data of the first data processing (i.e., the first bit data) is FlexO-4e or 400G-ZR frame data, the corresponding baud rate is less than 100GBaud; at this time, in the corresponding specific optical communication network transmission, the channel spacing that can be used is no more than 112.5GHz. It can be understood that the proposed data processing solution is well compatible with existing 400G data centers and metropolitan area networks. Moreover, it contains a total of d in =q×r bits of first bit data undergo the first data processing and the second data processing to obtain just one DSP frame (also called a superframe or multi-frame), so that the proposed data processing method has lower implementation complexity and lower power consumption.

[0141] Example 4:

[0142] Based on Example 3, the first constraint and the second constraint are considered.

[0143] The first data processing includes adding a cyclic redundancy check CRC-32 operation. The CRC-32 encoding and the corresponding CRC check operation can directly use the CRC-32 operation in the existing 800G-ZR, which is easy to implement. That is, considering the first constraint as follows: when the number of rows r is an integer multiple of 20, there are CRC-32 operation times p = r / 20, d CRC =r / 20×32≤d CP , that is, CRC-32 operation is performed on every 20 rows of r rows of data, totaling 41120 bits; when the number of rows r is not an integer multiple of 20, there are CRC-32 operation times in The operation means rounding a down, that is, r0=20, r1=r-20×(p-1), performing CRC-32 on each r0=20 rows of the first 20×(p-1) rows of r rows, totaling q×r0=41120 bits, and performing a CRC-32 operation on the last r1 rows, totaling q×r1 bits. Consider d PAD =d CP -d CRC , you need to choose appropriate r, d CP Make d PAD ≥0.

[0144] Consider a first bit set containing m bits, and perform a first sub-processing including PCS, interleaving and encoding to obtain a second bit set containing 4096 bits, wherein the ratio of the encoding input bit length to the encoding output bit length in the encoding operation is 111:128. Consider the ratio of the input bit length m and the output bit length 4096 of the first sub-processing (including PCS processing, interleaving and encoding) to be m:4096=f1:f2, wherein the greatest common divisor of the integers f1 and f2 is 1. Typically, when the values ​​of f1 and f2 are smaller, the overall hardware implementation can be simpler, the complexity is lower, and the power consumption is lower. In order to facilitate the simplicity of hardware implementation, the second constraint is considered, that is, m is an integer multiple of 32, so that the ratio of the input bit length m and the output bit length of the first sub-processing is f:128, wherein the integer f=m / 32.

[0145] In this embodiment 4, the redundancy of DSP framing in the second data processing is h DSP=56, each DSP frame (also called superframe or multiframe) contains 175104 dual-polarization symbols, of which 172032 dual-polarization symbols (i.e., pre-framing symbols) in each DSP frame are the fourth bit data obtained through symbol mapping and polarization division. At this time, the corresponding bit rate after the second data processing is W 2-56 =W1×(1+h DSP )=W0×(r×q+d CP ) / (r×q)×(4096 / m)×(57 / 56), the corresponding baud rate (i.e. symbol rate) is W s-56 =W 2-56 / 8=W0×(r×q+d CP ) / (r×q)×(4096 / m)×(57 / 56) / 8GBaud.

[0146] The following table 8 gives the corresponding {r, m, d CP d PAD ,f,p,W1,W 2-56 、W s-56} parameter combination. It should be noted that Table 8 also provides the specific value of parameter r1 when the number of rows r is not an integer multiple of 20. When the number of rows r is an integer multiple of 20, such as r = 480 in row 28 of Table 8, the corresponding parameter r1 is represented by a slash in the table, indicating that the parameter r1 does not exist.

[0147] Table 8

[0148] It should be noted that v = m - 1504 is an integer multiple of 16. In some specific implementations, considering n0 = 128, k0 = v / 16, that is, the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect, wherein each PCS sub-process performs PCS sub-processing on k0 = v / 16 input bits to obtain n0 = 128 output bits. In some specific applications, the 16 PCS sub-processes are implemented using 16 lookup tables (LUTs). In other specific applications, the 16 PCS sub-processes are implemented using 16 trellis coding. It should be noted that in other specific embodiments, considering v = m - 1504 is an integer multiple of 32, when n0 = 64, k0 = v / 32, that is, the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect, wherein each PCS sub-process performs PCS sub-processing on k0 = v / 32 input bits to obtain n0 = 64 output bits. In some specific applications, the 32 PCS sub-processes are implemented using 32 lookup tables (LUTs). In other specific applications, the 32 PCS sub-processes are implemented using 32 trellis codings.

[0149] It can be seen that the parameter combination given in this embodiment 4, when the input data of the first data processing (i.e., the first bit data) is FlexO-4e or 400G ZR frame data, the corresponding baud rate is less than 100GBaud; at this time, in the corresponding specific optical communication network transmission, the channel spacing that can be used is no more than 112.5GHz. It can be understood that the proposed data processing solution is well compatible with existing 400G data centers and metropolitan area networks. Moreover, it contains d in =q×r bits of first-bit data undergo the first and second data processing to obtain a single DSP frame (also known as a superframe or multi-frame), resulting in the proposed data processing method having lower implementation complexity and lower power consumption. Furthermore, the CRC-32 operation included in the first data processing in this embodiment 2 utilizes the CRC-32 operation in the existing 800G-ZR, facilitating simple implementation. Furthermore, m is an integer multiple of 32, resulting in a ratio of the input bit length m to the output bit length of the first sub-processing to f:128, where the integer f = m / 32, simplifying hardware implementation.

[0150] It should be noted that, under the same {r, m, d CP d PAD , f, p, W1} parameter combination, due to the DSP framing redundancy h used in this embodiment 4, DSP =1 / 56 is less than the framing redundancy in Example 2, and the bit rate W obtained after the second data processing 2-56And the corresponding baud rate W s-56 are respectively smaller than the bit rate W in Example 2 2-28 And the corresponding baud rate W s-28 .

[0151] Take some parameter combinations in Table 8 as an example, for example, the parameter combination in row 20 in Table 8, namely {r=496, m=3040, d CP =1664,d PAD =864, f=95, p=25, r1=16, W1=543.186874304 (Gbit / s), W 2-56 =552.886639917 (Gbit / s), W s-56 =69.110829990 (GBaud)}. In this case, the channel spacing used in the corresponding optical communication network transmission is 75 GHz. The proposed data processing solution is well compatible with existing 400G data centers and metropolitan area networks, such as OpenZR+, 400ZR, or 400ZR+ transmission networks using 75 GHz grid spacing.

[0152] Furthermore, for example, the parameter combination in row 50 in Table 8, namely {r=402, m=2464, d CP =1392,d PAD =720, f=77, p=21, r1=2, W1=670.200720535 (Gbit / s), W 2-56 =682.168590544 (Gbit / s), W s-56 =85.271073818 (GBaud)}. In this case, in a specific optical communication network, the channel spacing used is 100 GHz. The proposed data processing solution is well compatible with existing 400G data centers and metropolitan area networks, such as OpenZR+, 400ZR, or 400ZR+ transmission networks with 100 GHz grid spacing.

[0153] For another example, the parameter combination in row 66 in Table 8, namely {r=355, m=2176, d CP =1256,d PAD =680, f=68, p=18, r1=15, W1=758.931520155 (Gbit / s), W 2-56 =772.483868729 (Gbit / s), W s-56=96.560483591 (GBaud)}. In this case, the channel spacing used in specific optical communication network transmission is 112.5 GHz. The proposed data processing solution is well compatible with existing 400G data centers and metropolitan area networks, such as high-performance metropolitan area transmission networks that use 112.5 GHz grid spacing.

[0154] The first aspect mentioned above considers the case of q=2056, and the second aspect will be considered below, where q=10280.

[0155] The number of bits of the third bit data is d scr =q×r+d CP = L × m = 336 × m. It should be understood that the number of bits d of the added CRC and / or padding bits CP The larger the value, the more redundant OH CP =d CP / (q×r) is larger. For transmission efficiency, we consider 0≤d CP in , r, m, d CP} parameter combination.

[0156] Table 11

[0157] Table 11 also gives {r, m, d CP ​} parameter combination, the corresponding specific value of v / 16. It should be noted that v=m-1504 is an integer multiple of 16. When n0=128, k0=v / 16, that is, the PCS processing uses 16 PCS sub-processing to achieve the PCS processing effect, wherein each PCS sub-processing performs PCS sub-processing on the input k0=v / 16 bits to obtain an output n0=128 bits. In some specific applications, the 16 PCS sub-processing is implemented using 16 lookup tables LUTs. In other specific applications, the 16 PCS sub-processing is implemented using 16 trellis coding. It should be noted that in other specific embodiments, considering that v = m - 1504 is an integer multiple of 32, when n0 = 64, k0 = v / 32, that is, the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect, where each PCS sub-process performs PCS sub-processing on k0 = v / 32 bits of input to obtain n0 = 64 bits of output. In some specific applications, the 32 PCS sub-processes are implemented using 32 lookup tables (LUTs). In other specific applications, the 32 PCS sub-processes are implemented using 32 trellis coding.

[0158] It should be noted that in some specific applications, the first data processing includes adding a cyclic redundancy check CRC-32 operation. At this time, consider the following third constraint: when the number of rows r is an integer multiple of 4, the number of CRC-32 operations p = r / 4, d CRC =r / 4×32≤d CP , that is, CRC-32 operation is performed on every 4 rows of r rows of data, totaling 4×10280=41120 bits; when the number of rows r is not an integer multiple of 4, there are CRC-32 operation times in The operation means rounding a down to an integer, that is, r0=4, r1=r-4×(p-1), performing CRC-32 on each r0=4 row of the first 4×(p-1) rows of r rows, totaling q×r0=41120 bits, and performing a CRC-32 operation on the last r1 row, totaling q×r1 bits. Consider d PAD =d CP -d CRC Combining Table 11 and the third constraint above, the following Table 12 gives the corresponding {r, m, d CP d PAD , p} parameter combination. It should be noted that the last column of Table 12 also provides the specific value of parameter r1 when the number of rows r is not an integer multiple of 4. When the number of rows r is an integer multiple of 4, such as r = 112 in the second row of Table 12, the corresponding parameter r1 is represented by a slash in the table, indicating that the parameter r1 does not exist.

[0159] Table 12

[0160] It should be noted that, in some other specific applications, a first bit set containing m bits is considered to be subjected to a first sub-processing including PCS, interleaving and encoding to obtain a second bit set containing 4096 bits, wherein the ratio of the encoding input bit length to the encoding output bit length in the encoding operation is 111:128. In order to facilitate the simplicity of hardware implementation, the following fourth constraint is considered, that is, m is an integer multiple of 32, so that the ratio of the input bit length m to the output bit length of the first sub-processing is f:128, where the integer f = m / 32. Combining Table 11 and the above fourth constraint, the following Table 13 gives the corresponding {r, m, d CP ,f} parameter combination.

[0161] Table 13

[0162] Table 13 also gives {r, m, d CP , f} parameter combination, the corresponding specific value of v / 16. It should be noted that v=m-1504 is an integer multiple of 16. When n0=128, k0=v / 16, that is, the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect, where each PCS sub-processing performs PCS sub-processing on the input k0=v / 16 bits to obtain an output n0=128 bits. In some specific applications, the 16 PCS sub-processes are implemented using 16 lookup tables (LUTs). In other specific applications, the 16 PCS sub-processes are implemented using 16 trellis coding. It should be noted that in other specific embodiments, considering that v = m - 1504 is an integer multiple of 32, when n0 = 64, k0 = v / 32, that is, the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect, where each PCS sub-process performs PCS sub-processing on k0 = v / 32 bits of input to obtain n0 = 64 bits of output. In some specific applications, the 32 PCS sub-processes are implemented using 32 lookup tables (LUTs). In other specific applications, the 32 PCS sub-processes are implemented using 32 trellis coding.

[0163] It should be noted that in some specific applications, the third and fourth constraints mentioned above are considered. In this case, combined with Table 11 and the third and fourth constraints mentioned above, the following Table 14 gives the corresponding {r, m, d CP d PAD, f, p} parameter combinations. It should be noted that the last column of Table 14 also provides the specific value of parameter r1 when the number of rows r is not an integer multiple of 4. When the number of rows r is an integer multiple of 4, such as r = 100 in the second row of Table 14, the corresponding parameter r1 is represented by a slash in the table, indicating that the parameter r1 does not exist.

[0164] Table 14

[0165] Table 14 also gives {r, m, d CP d PAD , f, p} parameter combinations, and the corresponding specific value of v / 16. It should be noted that v = m - 1504 is an integer multiple of 16. When n0 = 128, k0 = v / 16, meaning the PCS process uses 16 PCS sub-processes to achieve the PCS processing effect, where each PCS sub-process performs PCS sub-processing on k0 = v / 16 input bits to produce n0 = 128 output bits.

[0166] It should be noted that, given that the bit rate of a data frame is W0 Gbit / s, the corresponding bit rate after the first data processing is W0×(r×q+d CP ) / (r×q) Gbit / s, and the corresponding bit rate after the first sub-processing in the second data processing (i.e., PCS, interleaving and coding processing) is W1=W0×(r×q+d CP ) / (r×q)×(4096 / m). Considering the redundancy of DSP framing in the second data processing is h DSP , that is, the corresponding bit rate after the second data processing is W2=W1×(1+h DSP )=W0×(r×q+d CP ) / (r×q)×(4096 / m)×(1+h DSP ), the corresponding baud rate (i.e. symbol rate) is W s =W2 / 8=W0×(r×q+d CP ) / (r×q)×(4096 / m)×(1+h DSP ) / 8GBaud. Typically, considering the DSP framing redundancy is h DSP 1 / 28, or 1 / 56. It can be seen that for the parameter combinations given in Tables 1-4, when the input data for the first data processing (i.e., the first bit data) is FlexO-4e or 400G ZR frame data, the corresponding baud rates are all less than 100GBaud. It can be understood that the proposed data processing solution is highly compatible with existing 400G data centers and metropolitan area networks.

[0167] In the following, several specific embodiments are given in combination with the above introduction to the first data processing and the second data processing.

[0168] Example 5:

[0169] Consider that the input data of the first data processing (i.e., the first bit data) is FlexO-4e or 400G ZR frame data, and its nominal bit rate is W0≈402.489753310Gbit / s. It should be noted that the non-integer in the embodiment of the present application is only retained to 9 decimal places. In some specific applications, the description of the non-integer can be described in other forms, such as retaining 2 decimal places, etc. The description method is known to ordinary technicians in this field and will not be repeated here. The first bit data contains r rows, q=10280 columns, and a total of d in =q×r bits. After the first data processing, the corresponding bit rate is W0×(r×q+d CP ) / (r×q) Gbit / s, and the corresponding bit rate after the first sub-processing in the second data processing (i.e., PCS, interleaving and coding processing) is W1=W0×(r×q+d CP ) / (r×q)×(4096 / m).

[0170] In some specific applications, the redundancy of DSP framing in the second data processing is considered to be h DSP =1 / 28, each DSP frame (also called superframe or multiframe) contains 178176 dual-polarization symbols, of which 172032 dual-polarization symbols (i.e., symbols before framing) in each DSP frame are the fourth bit data obtained through symbol mapping and polarization division. At this time, the corresponding bit rate after the second data processing is W 2-28 =W1×(1+h DSP )=W0×(r×q+d CP ) / (r×q)×(4096 / m)×(29 / 28), the corresponding baud rate (i.e. symbol rate) is W s-28 =W 2-28 / 8=W0×(r×q+d CP ) / (r×q)×(4096 / m)×(29 / 28) / 8GBaud.

[0171] Table 15 below gives the corresponding {d in , r, m, d CP 、v / 16、W1、W 2-28 、W s-28} parameter combination.

[0172] Table 15

[0173] It should be noted that v = m - 1504 is an integer multiple of 16. In some specific implementations, considering n0 = 128, k0 = v / 16, that is, the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect, wherein each PCS sub-process performs PCS sub-processing on k0 = v / 16 input bits to obtain n0 = 128 output bits. In some specific applications, the 16 PCS sub-processes are implemented using 16 lookup tables (LUTs). In other specific applications, the 16 PCS sub-processes are implemented using 16 trellis coding. It should be noted that in other specific embodiments, considering v = m - 1504 is an integer multiple of 32, when n0 = 64, k0 = v / 32, that is, the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect, wherein each PCS sub-process performs PCS sub-processing on k0 = v / 32 input bits to obtain n0 = 64 output bits. In some specific applications, the 32 PCS sub-processes are implemented using 32 lookup tables (LUTs). In other specific applications, the 32 PCS sub-processes are implemented using 32 trellis codings.

[0174] It can be seen that the parameter combination given in this embodiment, considering that the input data of the first data processing (i.e., the first bit data) is FlexO-4e or 400G ZR frame data, the corresponding baud rate is less than 100GBaud; at this time, in the corresponding specific optical communication network transmission, the channel spacing that can be used is no more than 112.5GHz. It can be understood that the proposed data processing solution is well compatible with existing 400G data centers and metropolitan area networks. Moreover, it contains d in =q×r bits of first bit data undergo the first data processing and the second data processing to obtain just one DSP frame (also called a superframe or multi-frame), so that the proposed data processing method has lower implementation complexity and lower power consumption.

[0175] Example 6:

[0176] Based on Example 5, the first constraint and the second constraint are considered.

[0177] The first data processing includes adding a cyclic redundancy check CRC-32 operation. The CRC-32 encoding and the corresponding CRC check operation can directly use the CRC-32 operation in the existing 800G-ZR, which is easy to implement. That is, considering the third constraint as follows: when the number of rows r is an integer multiple of 4, the number of CRC-32 operations p = r / 4, d CRC =r / 4×32≤d CP, that is, CRC-32 operation is performed on every 4 rows of r rows of data, totaling 41120 bits; when the number of rows r is not an integer multiple of 4, there are CRC-32 operation times in The operation means rounding a down to an integer, that is, r0=4, r1=r-4×(p-1), performing CRC-32 on each r0=4 row of the first 4×(p-1) rows of r rows, totaling q×r0=41120 bits, and performing a CRC-32 operation on the last r1 row, totaling q×r1 bits. Consider d PAD =d CP -d CRC .

[0178] Consider a first bit set consisting of m bits, and a first sub-process including PCS, interleaving, and encoding to obtain a second bit set consisting of 4096 bits. The ratio of the encoded input bit length to the encoded output bit length in the encoding operation is 111:128. To simplify hardware implementation, a fourth constraint is considered, namely, that m is an integer multiple of 32, so that the ratio of the input bit length m to the output bit length of the first sub-process is f:128, where the integer f = m / 32.

[0179] In this embodiment 12, the redundancy of DSP framing in the second data processing is considered to be h DSP =1 / 28, each DSP frame (also called superframe or multiframe) contains 178176 dual-polarization symbols, of which 172032 dual-polarization symbols (i.e., symbols before framing) in each DSP frame are the fourth bit data obtained through symbol mapping and polarization division. At this time, the corresponding bit rate after the second data processing is W 2-28 =W1×(1+h DSP )=W0×(r×q+d CP ) / (r×q)×(4096 / m)×(29 / 28), the corresponding baud rate (i.e. symbol rate) is W s-28 =W 2-28 / 8=W0×(r×q+d CP ) / (r×q)×(4096 / m)×(29 / 28) / 8GBaud.

[0180] Table 16 below gives the corresponding {r, m, d CP d PAD ,f,p,v / 16,W1,W 2-28 、W s-28} parameter combination. It should be noted that Table 16 also provides the specific value of parameter r1 when the number of rows r is not an integer multiple of 4. When the number of rows r is an integer multiple of 4, such as r = 100 in row 3 of Table 16, the corresponding parameter r1 is represented by a slash in the table, indicating that the parameter r1 does not exist.

[0181] Table 16

[0182] It should be noted that v = m - 1504 is an integer multiple of 16. In some specific implementations, considering n0 = 128, k0 = v / 16, that is, the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect, wherein each PCS sub-process performs PCS sub-processing on k0 = v / 16 input bits to obtain n0 = 128 output bits. In some specific applications, the 16 PCS sub-processes are implemented using 16 lookup tables (LUTs). In other specific applications, the 16 PCS sub-processes are implemented using 16 trellis coding. It should be noted that in other specific embodiments, considering v = m - 1504 is an integer multiple of 32, when n0 = 64, k0 = v / 32, that is, the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect, wherein each PCS sub-process performs PCS sub-processing on k0 = v / 32 input bits to obtain n0 = 64 output bits. In some specific applications, the 32 PCS sub-processes are implemented using 32 lookup tables (LUTs). In other specific applications, the 32 PCS sub-processes are implemented using 32 trellis codings.

[0183] It can be seen that the parameter combination given in this embodiment, considering that the input data of the first data processing (i.e., the first bit data) is FlexO-4e or 400G ZR frame data, the corresponding baud rate is less than 100GBaud; at this time, in the corresponding specific optical communication network transmission, the channel spacing that can be used is no more than 112.5GHz. It can be understood that the proposed data processing solution is well compatible with existing 400G data centers and metropolitan area networks. Moreover, it contains d in=q×r bits of first-bit data undergo the first and second data processing to obtain a single DSP frame (also known as a superframe or multi-frame), resulting in the proposed data processing method having lower implementation complexity and lower power consumption. Furthermore, the CRC-32 operation included in the first data processing in this embodiment 2 utilizes the CRC-32 operation in the existing 800G-ZR, facilitating simple implementation. Furthermore, m is an integer multiple of 32, resulting in a ratio of the input bit length m to the output bit length of the first sub-processing to f:128, where the integer f = m / 32, simplifying hardware implementation.

[0184] Take some parameter combinations in Table 16 as an example, for example, the parameter combination in the second row of Table 16, namely {r=101, m=3104, d CP =4664,d PAD =3832, f=97, p=26, r1=1, W1=533.506316148(Gbit / s), W 2-28 =552.560113154 (Gbit / s), W s-28 =69.070014144 (GBaud)}. In this case, the channel spacing used in specific optical communication network transmission is 75 GHz. The proposed data processing solution is well compatible with existing 400G data centers and metropolitan area networks, such as OpenZR+, 400ZR, or 400ZR+ transmission networks that use 75 GHz grid spacing.

[0185] For another example, the parameter combination in row 17 of Table 16, namely {r=73, m=2240, d CP =2200,d PAD =1592, f=70, p=19, r1=1, W1=738.138875767 (Gbit / s), W 2-28 =764.500978473 (Gbit / s), W s-28 =95.562622309 (GBaud)}. In this case, the applicable channel spacing in the corresponding optical communication network is 112.5 GHz. The proposed data processing solution is well compatible with existing 400G data centers and metropolitan area networks, such as high-performance metropolitan area transmission networks that use 112.5 GHz grid spacing.

[0186] Example 7:

[0187] Based on Example 5, the redundancy of DSP framing in the second data processing is considered to be h DSP=1 / 56, each DSP frame (also called superframe or multiframe) contains 175104 dual-polarization symbols, of which 172032 dual-polarization symbols (i.e., symbols before framing) in each DSP frame are the fourth bit data obtained through symbol mapping and polarization division. At this time, the corresponding bit rate after the second data processing is W 2-56 =W1×(1+h DSP )=W0×(r×q+d CP ) / (r×q)×(4096 / m)×(57 / 56), the corresponding baud rate (i.e. symbol rate) is W s-56 =W 2-56 / 8=W0×(r×q+d CP ) / (r×q)×(4096 / m)×(57 / 56) / 8GBaud.

[0188] Table 17 below gives the corresponding {d in , r, m, d CP 、v / 16、W1、W 2-56 、W s-56} parameter combination.

[0189] Table 17

[0190] It should be noted that v = m - 1504 is an integer multiple of 16. In some specific implementations, considering n0 = 128, k0 = v / 16, that is, the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect, wherein each PCS sub-process performs PCS sub-processing on k0 = v / 16 input bits to obtain n0 = 128 output bits. In some specific applications, the 16 PCS sub-processes are implemented using 16 lookup tables (LUTs). In other specific applications, the 16 PCS sub-processes are implemented using 16 trellis coding. It should be noted that in other specific embodiments, considering v = m - 1504 is an integer multiple of 32, when n0 = 64, k0 = v / 32, that is, the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect, wherein each PCS sub-process performs PCS sub-processing on k0 = v / 32 input bits to obtain n0 = 64 output bits. In some specific applications, the 32 PCS sub-processes are implemented using 32 lookup tables (LUTs). In other specific applications, the 32 PCS sub-processes are implemented using 32 trellis codings.

[0191] It can be seen that the parameter combination given in this embodiment, considering that the input data of the first data processing (i.e., the first bit data) is FlexO-4e or 400G-ZR frame data, the corresponding baud rate is less than 100GBaud; at this time, in the corresponding specific optical communication network transmission, the channel spacing that can be used is no more than 112.5GHz. It can be understood that the proposed data processing solution is well compatible with existing 400G data centers and metropolitan area networks. Moreover, it contains d in =q×r bits of first bit data undergo the first data processing and the second data processing to obtain just one DSP frame (also called a superframe or multi-frame), so that the proposed data processing method has lower implementation complexity and lower power consumption.

[0192] Example 8:

[0193] Based on Example 7, the first constraint and the second constraint are considered.

[0194] The first data processing includes adding a cyclic redundancy check CRC-32 operation. The CRC-32 encoding and the corresponding CRC check operation can directly use the CRC-32 operation in the existing 800G-ZR, which is easy to implement. That is, considering the first constraint as follows: when the number of rows r is an integer multiple of 4, there are CRC-32 operation times p = r / 4, d CRC =r / 4×32≤d CP , that is, CRC-32 operation is performed on every 4 rows of r rows of data, totaling 41120 bits; when the number of rows r is not an integer multiple of 4, there are CRC-32 operation times in The operation means rounding a down to an integer, that is, r0=4, r1=r-4×(p-1), performing CRC-32 on each r0=4 row of the first 4×(p-1) rows of r rows, totaling q×r0=41120 bits, and performing a CRC-32 operation on the last r1 row, totaling q×r1 bits. Consider d PAD =d CP -d CRC .

[0195] Consider a first bit set consisting of m bits, and perform a first sub-process including PCS, interleaving, and encoding to obtain a second bit set consisting of 4096 bits, wherein the ratio of the encoded input bit length to the encoded output bit length in the encoding operation is 111:128. To simplify hardware implementation, the fourth constraint, namely, that m is an integer multiple of 32, is considered, such that the ratio of the input bit length m to the output bit length of the first sub-process is f:128, where the integer f = m / 32.

[0196] In this embodiment 8, the redundancy of DSP framing in the second data processing is h DSP =56, each DSP frame (also called superframe or multiframe) contains 175104 dual-polarization symbols, of which 172032 dual-polarization symbols (i.e., pre-framing symbols) in each DSP frame are the fourth bit data obtained through symbol mapping and polarization division. At this time, the corresponding bit rate after the second data processing is W 2-56 =W1×(1+h DSP )=W0×(r×q+d CP ) / (r×q)×(4096 / m)×(57 / 56), the corresponding baud rate (i.e. symbol rate) is W s-56 =W 2-56 / 8=W0×(r×q+d CP ) / (r×q)×(4096 / m)×(57 / 56) / 8GBaud.

[0197] Table 18 below gives the corresponding {r, m, d CP d PAD ,f,p,W1,W 2-56 、W s-56} parameter combination. It should be noted that Table 18 also provides the specific value of parameter r1 when the number of rows r is not an integer multiple of 4. When the number of rows r is an integer multiple of 4, such as r = 100 in row 3 of Table 18, the corresponding parameter r1 is represented by a slash in the table, indicating that the parameter r1 does not exist.

[0198] Table 18

[0199] It should be noted that v = m - 1504 is an integer multiple of 16. In some specific implementations, considering n0 = 128, k0 = v / 16, that is, the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect, wherein each PCS sub-process performs PCS sub-processing on k0 = v / 16 input bits to obtain n0 = 128 output bits. In some specific applications, the 16 PCS sub-processes are implemented using 16 lookup tables (LUTs). In other specific applications, the 16 PCS sub-processes are implemented using 16 trellis coding. It should be noted that in other specific embodiments, considering v = m - 1504 is an integer multiple of 32, when n0 = 64, k0 = v / 32, that is, the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect, wherein each PCS sub-process performs PCS sub-processing on k0 = v / 32 input bits to obtain n0 = 64 output bits. In some specific applications, the 32 PCS sub-processes are implemented using 32 lookup tables (LUTs). In other specific applications, the 32 PCS sub-processes are implemented using 32 trellis codings.

[0200] It can be seen that the parameter combination given in this embodiment, considering that the input data of the first data processing (i.e., the first bit data) is FlexO-4e or 400G-ZR frame data, the corresponding baud rate is less than 100GBaud; at this time, in the corresponding specific optical communication network transmission, the channel spacing that can be used is no more than 112.5GHz. It can be understood that the proposed data processing solution is well compatible with existing 400G data centers and metropolitan area networks. Moreover, it contains d in =q×r bits of first-bit data undergo the first and second data processing to obtain a single DSP frame (also known as a superframe or multi-frame), resulting in the proposed data processing method having lower implementation complexity and lower power consumption. Furthermore, the CRC-32 operation included in the first data processing in this embodiment 2 utilizes the CRC-32 operation in the existing 800G-ZR, facilitating simple implementation. Furthermore, m is an integer multiple of 32, resulting in a ratio of the input bit length m to the output bit length of the first sub-processing to f:128, where the integer f = m / 32, simplifying hardware implementation.

[0201] It should be noted that the above embodiment considers that the input data for the first data processing (i.e., the first bit data) is FlexO-4e or 400G ZR frame data, whose nominal bit rate is W0 = 21845 / 25984×766×0.15625×4≈401.703640510×(512 / 511)≈402.489753310 Gbit / s. The parameter combination given in the above embodiment can also be applied to other data types, such as 400G FlexO-4 data, 600G FlexO-6e and FlexO-6 data, 800G FlexO-8e and FlexO-8 data, and future data at rates such as 1.2T and 1.6T. In some specific applications, the input data for the first data processing (i.e., the first bit data) is FlexO-4 data, whose nominal bit rate is W0 = 491384 / 462961×99.5328×4≈422.5740431 Gbit / s. In other specific applications, the input data for the first data processing (i.e., the first bit data) is FlexO-6e data, whose nominal bit rate is W0 = 21845 / 25984×766×0.15625×6≈603.73463 Gbit / s. In still other specific applications, the input data for the first data processing (i.e., the first bit data) is FlexO-6 data, whose nominal bit rate is W0 = 491384 / 462961×99.5328×6≈633.8611 Gbit / s. In some other specific applications, the input data of the first data processing (i.e., the first bit data) is FlexO-8 data, and its nominal rate is W0=491384 / 462961×99.5328×8≈845.14809 Gbit / s. In some other specific applications, the input data of the first data processing (i.e., the first bit data) is FlexO-8e data, and its nominal rate is W0=21845 / 25984×766×0.15625×8≈804.979507 Gbit / s. The corresponding bit rate after the second data processing can be calculated by W2=W1×(1+h DSP )=W0×(r×q+d CP ) / (r×q)×(4096 / m)×(1+h DSP ) is calculated, and the corresponding baud rate (i.e., symbol rate) is obtained by W s =W2 / 8=W0×(r×q+d CP ) / (r×q)×(4096 / m)×(1+h DSP ) / 8GBaud, the specific calculation of which is known to those skilled in the art and will not be described in detail here.

[0202] FIG9 is a schematic diagram of a structure of a data processing device according to an embodiment of the present application. As shown in FIG9 , the data processing device includes: a first processing unit 101, a scrambling unit 102, a PCS unit 103, and an FEC encoding and interleaving unit 104. The first processing unit 101 is specifically configured to process the data according to the number of bits d. in The first bit data is obtained, and the second bit data is obtained, wherein the second bit data includes d in bits in the first bit data, d CRC parity bits and / or d PAD Filling bits, d CRC is an integer greater than or equal to 0, d PAD is an integer greater than or equal to 0; specifically, it is used to perform a cyclic redundancy check (CRC) on the first bit of data and / or insert padding bits to obtain the second bit of data. The CRC check execution method has been specifically described in the previous method embodiment and will not be repeated in this embodiment. The scrambling unit 102 is used to perform the scrambling operation in the above embodiment. The PCS unit 103 is specifically used to perform the PCS processing operations in the above embodiment. The FEC encoding and interleaving unit 104 is specifically used to perform the FEC encoding and interleaving operations in the above embodiment.

[0203] In some possible implementations, the data processing device shown in FIG10 may further include: a second processing unit 105 and a digital signal processing (DSP) framing unit 106; the second processing unit 105 is configured to perform symbol mapping and polarization division (also referred to as dual-polarization symbol mapping) on ​​the fourth bit data to obtain a dual-polarization symbol sequence, wherein the symbol mapping and polarization division (also referred to as dual-polarization symbol mapping) map 8 bits into 1 dual-polarization DP-16QAM symbol, and the fourth bit data includes multiple sets of the second bit; the DSP framing unit 106 is configured to perform DSP framing on the dual-polarization symbol sequence to obtain a DSP frame (also referred to as a DSP superframe). The specific operations of the symbol mapping, polarization division, and DSP framing operations can be referred to the relevant description of the embodiments shown in FIG5(a)-5(c) above and will not be repeated here.

[0204] It should be understood that the data processing device provided in this application can also be implemented in other ways. For example, the unit division in the above-mentioned device is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system. In addition, the functional units in the various embodiments of the present application can be integrated into one processing unit, or they can be independent physical units, or two or more functional units can be integrated into one processing unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

[0205] Figure 11 is a structural diagram of an optical module in an embodiment of the present application. As shown in Figure 11, the optical module includes a processor 201 and an interface 202, and the processor 201 is used to perform the first data processing and second data processing operations described in the above embodiment. In one possible implementation, the processor 201 includes the first processing unit 101, the scrambling unit 102, the PCS unit 103, and the FEC encoding and interleaving unit 104 shown in Figure 9 above; it may also include the second processing unit 105 and the DSP framing unit 106 shown in Figure 10. The interface 202 can be a transceiver or an input / output interface, and the interface 202 is used to receive signals from other devices outside the optical module and transmit them to the processor 201, or send signals from the processor 201 to other devices outside the optical module. As an example, the processor 201 obtains a DSP frame after performing the above-mentioned first data processing and second data processing, and sends the DSP frame through the interface 202. In this example, the interface 202 specifically refers to an electrical interface. As another example, processor 201 performs the first and second data processing steps to obtain a DSP frame. A modulator in the optical module performs signal processing such as electro-optical conversion based on the DSP frame to obtain an optical signal, which is then transmitted via interface 202. In this example, interface 202 may specifically refer to an optical interface. Optionally, the optical module may further include a memory 203 for storing program instructions and / or data. The modulator may also be referred to as a signal driver.

[0206] Figure 12 is a structural diagram of a sending device in an embodiment of the present application. As shown in Figure 12, the sending device includes a host-side device 301 and an optical module 302. The host-side device 301 is used to send data to the optical module 302, and the optical module 302 generates an optical signal based on the data sent by the host-side device 301 and sends the optical signal through a channel. For example, the host-side device can specifically be a switch or a router. The sending device can be a communication device including the host-side device 301 and the optical module 302. It should also be understood that the sending device in the embodiment of the present application is named based on the direction of data flow, and does not limit the function of the device. For example, the sending device can also have a receiving function.

[0207] Embodiments of the present application also provide an optical transport network (OTN) device, which includes line-side equipment and client-side equipment. In some scenarios, the client-side equipment may also be referred to as branch-side equipment. The line-side equipment includes a processor and an interface, and the processor is configured to perform the first data processing and second data processing operations described in the above embodiments. The interface may be a transceiver or an input / output interface, and is configured to receive signals from devices other than the line-side equipment and transmit them to the processor, or to transmit signals from the processor to devices other than the line-side equipment.

[0208] The present application also provides a chip. This chip integrates circuitry and one or more interfaces for implementing the functions of the processor 201 described above. As an example, the chip integrates memory. As another example, if the chip does not integrate memory, it can be connected to an external memory via an interface. This chip can perform the method steps of any one or more of the aforementioned embodiments. Alternatively, the chip can implement the actions performed by the data processing device in the aforementioned embodiments based on program code stored in the memory.

[0209] An embodiment of the present application further provides a computer-readable storage medium, including a program or instructions. When the program or instructions are executed on a computer, the method executed by the processor 201 in the above method embodiment is executed.

[0210] It should be understood that the processors mentioned in the embodiments of the present application can be implemented by hardware or software. When implemented by hardware, the processor can be a logic circuit, an integrated circuit, etc. When implemented by software, the processor can be a general-purpose processor that is implemented by reading software code stored in a memory. The memory can exist independently and be connected to the processor, or the memory can be integrated with the processor.

[0211] As an example, the processor in the embodiments of the present application may be a central processing unit (CPU), or may be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor may be a microprocessor, or any conventional processor, or a processing circuit that implements a specific function.

[0212] In the embodiments of the present application, the memory may be a random access memory (RAM), a flash memory, a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a register, a hard disk, a mobile hard disk, a CD-ROM, or any other form of storage medium well known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium may also be an integral part of the processor. The processor and the storage medium may be located in an ASIC. In addition, the ASIC may be located in a network device or a terminal device. Of course, the processor and the storage medium may also exist in a network device or a terminal device as discrete components.

[0213] In the above embodiments, all or part of them can be implemented by software, hardware, firmware or any combination thereof.

[0214] When implemented using hardware, the data processing method provided in the embodiments of the present application may be implemented without reading software code or instructions. For example, it may be implemented by a CPU, DSP, ASIC, FPGA, other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0215] When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instruction is loaded and executed on a computer, the process or function described in the embodiment of the present application is executed in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, a network device, a terminal device, or other programmable device. The computer program or instruction may be stored in a computer-readable storage medium or transmitted via the computer-readable storage medium. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server that integrates one or more available media. The available medium may be a magnetic medium, such as a floppy disk, a hard disk, or a magnetic tape; it may also be an optical medium, such as a digital versatile disc (DVD); it may also be a semiconductor medium, such as a solid state disk (SSD).

[0216] Finally, it should be noted that the above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included within the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A data processing method, characterized in that: include: According to the number of bits d in The first bit data is obtained, and the second bit data is obtained, wherein the second bit data includes d in bits in the first bit data, d CRC parity bits and / or d PAD Filling bits, d CRC is an integer greater than or equal to 0, d PAD is an integer greater than or equal to 0; The second bit data is scrambled to obtain the third bit data, the number of bits of the third bit data is d scr =d in +d CP , d CP =d CRC +d PAD ; Performing probabilistic constellation shaping PCS processing on a first bit subset in a first bit set having a bit number m to obtain a second bit subset, wherein the first bit set is obtained from the third bit data, m is an integer greater than 1, and d scr is an integer multiple of m; Perform forward error correction (FEC) encoding and interleaving processing on the second bit subset and a third bit subset in the first bit set excluding the first bit subset to obtain a second bit set, wherein d in , m and d CP The value of is any one of the following sets:

2. The method according to claim 1, characterized in that d scr =336×m。 3. The method according to claim 1 or 2, characterized in that The number of bits in the first bit subset is an integer multiple of 16 or 32, the second bit subset includes 2048 bits, the third bit subset includes 1504 bits, and the second bit set includes 4096 bits.

4. The method according to any one of claims 1 to 3, characterized in that The first bit data includes r rows and q columns of bits, d in =r×q, r is an integer greater than 1, q=2056 or 10280.

5. The method according to claim 4, characterized in that The number of bits is d in The method of obtaining the second bit data from the first bit data specifically includes: performing a cyclic redundancy check (CRC) on the first bit data and / or inserting padding bits to obtain the second bit data; wherein performing the CRC on the first bit data includes: Perform CRC-32 check on a total of r×q / p bits in each r / p row of the first bit data, and add a check bit with a length of 32 bits. CRC =32×p, r is divisible by p, and p is an integer greater than 1; or, Perform a CRC-32 check on each r0 row of the first r0×(p-1) rows of the first bit data, totaling q×r0 bits, to add a check bit with a length of 32 bits, and perform a CRC-32 check on the last r1 row of the first data, totaling q×r1 bits, to add a check bit with a length of 32 bits, where d CRC =32×p, r cannot be divided by p, p is an integer greater than 1, r0×(p-1)+r1=r, the integer r0 is greater than the integer r1.

6. The method according to claim 5, characterized in that q=2056, r, m, d CP , the values ​​of p and r1 are any of the following sets:

7. The method according to claim 5, characterized in that m is an integer multiple of 32, q = 2056; r, m, d CP , the values ​​of p and r1 are any of the following sets:

8. The method according to claim 5, characterized in that q=10280,r,m,d CP , the values ​​of p and r1 are any of the following sets:

9. The method according to claim 5, characterized in that m is an integer multiple of 32, q = 10280, r, m, d CP , the values ​​of p and r1 are any of the following sets:

10. The method according to any one of claims 1 to 9, characterized in that The third bit subset includes 1504 bits, and the first bit subset includes m-1504 bits; and performing probabilistic constellation shaping (PCS) processing on the first bit subset in the first bit set having m bits to obtain the second bit subset includes: Dividing the first bit subset into 16 groups of sequences, each group of sequences including (m-1504) / 16 bits; performing PCS sub-processing on the 16 groups of sequences respectively to obtain 16 groups of output sequences corresponding to the 16 groups of sequences, wherein each group of output sequences includes 128 bits, and the 16 groups of output sequences constitute the second bit subset; Alternatively, performing probabilistic constellation shaping (PCS) processing on a first bit subset in a first bit set having a bit number m to obtain a second bit subset includes: Divide the first bit subset into 32 groups of sequences, each group of sequences including (m-1504) / 32 bits; Perform PCS sub-processing on the 32 groups of sequences respectively to obtain 32 groups of output sequences corresponding to the 32 groups of sequences, where each group of output sequences includes 64 bits, and the 32 groups of output sequences constitute the second bit subset.

11. The method according to any one of claims 1 to 10, characterized in that After obtaining the second bit set, the method further includes: performing symbol mapping and polarization division on the fourth bit data to obtain a dual-polarization symbol sequence, wherein the symbol mapping and the polarization division map 8 bits into one dual-polarization DP-16QAM symbol, and the fourth bit data includes a plurality of second bit sets; Digital signal processing (DSP) is performed on the dual-polarization symbol sequence to form a framing signal to obtain a DSP frame.

12. The method according to claim 11, characterized in that Performing DSP framing on the dual-polarization symbol sequence includes: Every 172032 dual-polarization DP-16QAM symbols are framed to obtain a DSP frame.

13. A data processing device, characterized in that: include: a first processing unit, a scrambling unit, a probabilistic constellation shaping PCS unit, and a forward error correction FEC encoding and interleaving unit; The first processing unit is configured to: in The first bit data is obtained, and the second bit data is obtained, wherein the second bit data includes d in bits in the first bit data, d CRC parity bits and / or d PAD Filling bits, d CRC is an integer greater than or equal to 0, d PAD is an integer greater than or equal to 0; The scrambling unit is used to scramble the second bit data to obtain the third bit data, the number of bits of the third bit data is d scr =r×q+d CP , d CP =d CRC +d PAD ; The PCS unit is configured to perform PCS processing on a first bit subset in a first bit set having a bit number m to obtain a second bit subset, wherein the first bit set is obtained from the third bit data, m is an integer greater than 1, and d scr is an integer multiple of m; The FEC encoding and interleaving unit is used to perform FEC encoding and interleaving on the second bit subset and a third bit subset in the first bit set excluding the first bit subset to obtain a second bit set, wherein d in , m and d CP The value of is any one of the following sets:

14. The device according to claim 13, characterized in that d scr =336×m。 15. The device according to claim 13 or 14, characterized in that The number of bits in the first bit subset is an integer multiple of 16 or 32, the second bit subset includes 2048 bits, the third bit subset includes 1504 bits, and the second bit set includes 4096 bits.

16. The device according to any one of claims 13 to 15, characterized in that The first bit data includes r rows and q columns of bits, d in =r×q, r is an integer greater than 1, q=2056 or 10280.

17. The device according to claim 16, characterized in that The processing unit is specifically configured to: Perform CRC-32 check on a total of r×q / p bits in each r / p row of the first bit data, and add a check bit with a length of 32 bits. CRC =32×p, r is divisible by p, and p is an integer greater than 1; or, Perform a CRC-32 check on each r0 row of the first r0×(p-1) rows of the first bit data, totaling q×r0 bits, to add a check bit with a length of 32 bits, and perform a CRC-32 check on the last r1 row of the first data, totaling q×r1 bits, to add a check bit with a length of 32 bits, where d CRC =32×p, r cannot be divided by p, p is an integer greater than 1, r0×(p-1)+r1=r, the integer r0 is greater than the integer r1.

18. The device according to claim 17, characterized in that q=2056, r, m, d CP , the values ​​of p and r1 are any of the following sets:

19. The device according to claim 17, characterized in that m is an integer multiple of 32, q = 2056; r, m, d CP , the values ​​of p and r1 are any of the following sets:

20. The device according to claim 17, wherein q=10280,r,m,d CP , the values ​​of p and r1 are any of the following sets:

21. The device according to claim 17, characterized in that m is an integer multiple of 32, q = 10280, r, m, d CP , the values ​​of p and r1 are any of the following sets:

22. The device according to any one of claims 13 to 21, characterized in that The third bit subset includes 1504 bits, the first bit subset includes m-1504 bits; and the PCS unit is configured to: Dividing the first bit subset into 16 groups of sequences, each group of sequences including (m-1504) / 16 bits; performing PCS sub-processing on the 16 groups of sequences respectively to obtain 16 groups of output sequences corresponding to the 16 groups of sequences, wherein each group of output sequences includes 128 bits, and the 16 groups of output sequences constitute the second bit subset; Alternatively, the PCS unit is configured to: Divide the first bit subset into 32 groups of sequences, each group of sequences including (m-1504) / 32 bits; Perform PCS sub-processing on the 32 groups of sequences respectively to obtain 32 groups of output sequences corresponding to the 32 groups of sequences, where each group of output sequences includes 64 bits, and the 32 groups of output sequences constitute the second bit subset.

23. The device according to any one of claims 13 to 22, characterized in that The data processing device also includes a second processing unit and a digital signal processing (DSP) framing unit. The second processing unit is configured to perform symbol mapping and polarization division on the fourth bit data to obtain a dual-polarization symbol sequence, wherein the symbol mapping and the polarization division map 8 bits into one dual-polarization DP-16QAM symbol, and the fourth bit data includes a plurality of second bit sets; The DSP framing unit is configured to perform DSP framing on the dual-polarization symbol sequence to obtain a DSP frame.

24. The device according to claim 23, characterized in that The DSP framing unit is used to perform framing processing on every 172032 dual-polarization DP-16QAM symbols to obtain a DSP frame.

25. A chip, characterized in that: The chip comprises a processor configured to execute the method according to any one of claims 1 to 12.

26. An optical module, characterized in that: The optical module includes a processor and an interface, wherein the processor is configured to execute the method according to any one of claims 1 to 12 and send a signal through the interface.

27. The optical module according to claim 26, wherein: The processor is configured to perform data processing on the second bit set to obtain a DSP frame, and send the DSP frame through the interface.

28. The optical module according to claim 26, wherein: The optical module further includes a modulator. The processor is configured to perform data processing on the second bit set to obtain a DSP frame. The modulator is configured to perform electrical-to-optical conversion according to the DSP frame to obtain an optical signal, and transmit the optical signal through the interface.

29. A sending device, characterized in that: The sending device includes a host-side device and an optical module according to any one of claims 26 to 28, wherein the optical module is configured to generate an optical signal according to data from the host-side device and send the optical signal.

30. A communication system, characterized in that: It comprises: a sending device and a receiving device as claimed in claim 29, wherein the sending device is used to send an optical signal to the receiving device.

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