Encoding and decoding methods for LDPC and related apparatuses, device, and storage medium

Abstract

The present application discloses an encoding method for low-density parity-check (LDPC) codes. The method comprises: acquiring an information bit sequence; and on the basis of a check matrix, performing LDPC encoding on the information bit sequence to obtain an encoded bit sequence, wherein the check matrix is determined by a base matrix, the base matrix comprises a fundamental sub-matrix, and the fundamental sub-matrix is formed by concatenating at least two basic unit blocks with cyclic or translational properties. Compared with existing 5G new radio (NR) matrices of which shifting values are all obtained by random search without guidance from a fixed algebraic structure, the base matrix having cyclic block structures or translational block structures designed in the present application can be guided by a fixed algebraic structure, thereby solving the technical problems of the lack of practical code design for LDPC and the difficulty in finding a cycle-free exponent matrix by means of random search.

Description

LDPC encoding and decoding methods and related devices, equipment and storage media

[0001] This application claims priority to Chinese Patent Application No. 202410247233.5, filed on March 4, 2024, with the China National Intellectual Property Administration, entitled “Encoding and Decoding Method and Related Apparatus, Device and Storage Medium for LDPC”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communication technology, and in particular to LDPC encoding and decoding methods and related apparatus, devices and computer-readable storage media. Background Technology

[0003] Low-density parity-check (LDPC) codes are a channel coding scheme that is very close to Shannon lines. They have the advantages of good performance and low complexity, and have been selected by 3GPP as the 5G data channel coding scheme.

[0004] LDPC codes are encoded using a generator matrix. Mainstream LDPC codes employ a QC (Quick Correction) structure, which avoids bad structures like short loops and improves code distance by adjusting the shift of each block. Due to its powerful error correction capabilities, LDPC codes are widely used in wired communication systems, wireless communication systems, personal area networks (PANs), and solid-state drives (SSDs). In these applications, information transmission and retrieval are susceptible to errors due to channel noise. Employing LDPC encoding and decoding, with its high error correction performance and low decoding complexity, ensures reliable information transmission and storage.

[0005] How to further improve the performance of QC LDPC codes is a question of concern. Summary of the Invention

[0006] This application provides an LDPC encoding / decoding method and related apparatus, devices, and computer-readable storage medium, which can further improve the performance of QC LDPC codes.

[0007] Firstly, this application provides an encoding method for LDPC codes, the method comprising:

[0008] Obtain the information bit sequence;

[0009] Based on the parity check matrix, the information bit sequence is encoded using low-density parity check (LDPC) encoding to obtain the encoded bit sequence.

[0010] The verification matrix is ​​determined by the base matrix, which includes a basic submatrix; the basic submatrix is ​​formed by splicing together at least two basic unit blocks with cycles or translations.

[0011] Through the above embodiments, compared with the existing 5G new radio (NR) matrix shifting values ​​which are all random search results and lack fixed algebraic structure guidance, the basis matrix with cyclic block or translation block structure designed in this application can have fixed algebraic structure guidance, which solves the technical problem that LDPC lacks practical code design and it is difficult to find a cyclic free exponent matrix through random search.

[0012] Secondly, embodiments of this application provide a decoding method for LDPC codes, the method comprising:

[0013] Obtain the first log likelihood ratio (LLR) sequence corresponding to the first received channel sequence;

[0014] The first LLR sequence is decoded according to the parity check matrix;

[0015] The verification matrix is ​​determined by the base matrix, which includes basic submatrices; the basic submatrices are formed by concatenating at least two basic unit blocks.

[0016] In one possible implementation of the first and second aspects, the base matrix further includes a portion of the truncated and spliced ​​base submatrix.

[0017] Through the above embodiments, the concatenated fundamental submatrix can include not only the entire fundamental submatrix but also a truncated portion of it. The fundamental matrix with cyclic or translational block structures designed in this application can have a fixed algebraic structure guide, solving the technical problem of the lack of practical code design for LDPC and the difficulty in finding cycle-free exponent matrices through random search.

[0018] In one possible implementation of the first and second aspects, the basic unit block is formed by stacking at least two single-cycle blocks.

[0019] Through the above embodiments, the basic unit block is formed by superimposing single cyclic blocks, which is more conducive to achieving a fixed algebraic structure guidance and regular algebraic characteristics. It solves the technical problem that there is a lack of practical code design for LDPC and it is difficult to find the exponent matrix of cycle-free exponent by random search.

[0020] In one possible implementation of the first and second aspects, the loop structure of the single loop block itself is such that, starting from the second row, the non-zero position of the current row is the position of the non-zero position of the previous row shifted by 1 unit; the non-zero position of the first row is the position of the non-zero position of the last row shifted by 1 unit; and the number of non-zero positions and / or non-zero positions in the first row of different single loop blocks are different.

[0021] Through the above embodiments, the loop structure of the single loop block of this application can be realized reasonably and efficiently, thereby helping to achieve a fixed algebraic structure guide and regular algebraic properties, solving the technical problem that there is a lack of practical code design for LDPC and it is difficult to find the exponent matrix of loop free through random search.

[0022] In one possible implementation of the first and second aspects, the number and position of non-zero values ​​in the first row of the single loop block are determined by a column identifier vector; the number of elements in the column identifier vector corresponds to the number of non-zero values ​​in the first row, and the size of the elements in the column identifier vector represents the column identifier where the non-zero position in the first row is located;

[0023] The column identifier vector is determined by the degree of the non-zero coefficients in the polynomial; different polynomials correspond to different single loop blocks.

[0024] Through the above embodiments, the column identifier vector is determined by the degree of the non-zero coefficients in the polynomial. This can reasonably and efficiently implement a fixed algebraic structure guide with regular algebraic properties, solving the technical problem of lacking practical code design for LDPC and the difficulty in finding a cycle-free exponent matrix through random search.

[0025] In one possible implementation of the first and second aspects, the at least two basic unit blocks include at least two different basic unit blocks.

[0026] Through the above embodiments, the basic submatrix of this application can include two different basic unit blocks, which can solve the problem that LDPC parity-check matrices containing short cycles can cause a relatively high error floor in decoding.

[0027] In one possible implementation of the first and second aspects, the basic submatrix is ​​formed by superimposing at least two submatrices.

[0028] Through the above embodiments, the basic submatrix of this application can be split into at least two submatrix superimposed or combined, which can reasonably and efficiently realize the loop structure of the single loop block of this application, thereby helping to achieve a fixed algebraic structure guide and regular algebraic properties, solving the technical problem of lacking practical code design for LDPC and finding the loop-free exponent matrix through random search.

[0029] In one possible implementation of the first and second aspects, the values ​​of the basic submatrix include 0, 1, and 2; the position with a value of 0 represents no shifted element, the position with a value of 1 represents one shifted element, and the position with a value of 2 represents two shifted elements.

[0030] Through the above embodiments, this application adopts the idea of ​​joint design of the basis matrix and shifting value. The value of the basis submatrix can include a value used to represent the two shifting value elements, for example, a value of 2, which can realize fine-grained shifting value design for non-fully connected BGs. Compared with the existing short-cycle free design method, it can meet the lifting size condition with a smaller order of magnitude. Furthermore, the multi-edge cyclic basis matrix has a consistent threshold for the basis matrix of the 5G NR core matrix. Compared with single-edge LDPC, multi-edge can achieve cycle-free operation or a small number of cycles with a smaller lifting size.

[0031] In one possible implementation of the first and second aspects, the at least two submatrices include a first submatrix and a second submatrix; wherein,

[0032] The first submatrix is ​​formed by splicing together at least two single-sided quasi-cyclic LDPC cell blocks with single-block cycles.

[0033] The second submatrix is ​​formed by splicing together at least two single-sided quasi-cyclic LDPC cell blocks in a non-mixed or mixed manner.

[0034] Through the above embodiments, the design of the basis matrix in this application has regular algebraic characteristics, which solves the problem that existing 5G NR matrices are all random search results and lack fixed algebraic structure guidance. It also solves the problem that LDPC parity-check matrices containing short cycles will cause a relatively high error floor in decoding.

[0035] In one possible implementation of the first and second aspects, the shift value matrix corresponding to the basic submatrix is ​​formed by combining the first shift value matrix corresponding to the first submatrix and the second shift value matrix corresponding to the second submatrix;

[0036] The shift value matrix corresponding to each basic unit block in the first shift value matrix satisfies a p-row translation cycle, where p is an integer greater than or equal to 1;

[0037] The second shift value matrix satisfies a cyclic shift of W units; where W is related to the total number of columns of the basic submatrix.

[0038] Through the above embodiments, a combined form of Shifting Values ​​is realized. From the perspective of short-cycle freeing, the problem of LDPC parity-check matrices containing short cycles leading to a relatively high error floor in decoding is solved. The construction of algebraic features in this application supports fine-grained design. Compared with existing short-cycle freeing designs, the fine-grained Shifting Value design scheme of this application can meet the requirements with a smaller lifting size.

[0039] In one possible implementation of the first and second aspects, the base matrix includes a plurality of said basic submatrices, wherein the shift values ​​corresponding to the same positions of the plurality of said basic submatrices are the same or satisfy the arithmetic sequence property.

[0040] Through the above embodiments, the fine-grained shifting value design scheme of the non-fully connected block generation (BG) in this application can achieve C4-free performance on a smaller scale compared to the fully connected i*j design. For the fully connected BG constructed based on a finite field, the shifting value of row i and column j is constructed as S_i*R_j, requiring a minimum lifting size of n (the number of columns) that is a prime number. The shifting value design in this application can be jointly optimized with the non-fully connected BG, does not require the code length n to be a prime number, and achieves a smaller minimum lifting size for C4-free performance. The shifting value design has no error floor and performs consistent with the best shifting value obtained through random search.

[0041] In one possible implementation of the first and second aspects, the fundamental submatrix is ​​a 4×n matrix; the fundamental submatrix corresponds to a shift value A of the shift value matrix. i (j), A corresponding to the position where the value of the basic submatrix is ​​2. i (j) is related to the total number of columns of the basic submatrix and the column index of the position of 2.

[0042] Through the above embodiments, the construction of algebraic features in this application supports fine-grained design. Compared with existing short-cycle-free design methods, the fine-grained shifting value design scheme of this application can meet the lifting size requirements with a smaller order of magnitude. Specifically, the required lifting size for the C4-free shifting value design can reach the optimal bound; for the degree distribution of the same row and column, the lifting size bound for multi-edge to reach cycle-free is smaller than that for single-edge to reach cycle-free. Therefore, under reasonable design, multi-edge can achieve better performance for the same code length and code rate; the required lifting size for C4 and C6-free shifting value designs can reach the optimal bound or be on the same order of magnitude.

[0043] In one possible implementation of the first and second aspects, the shift value A of the shift value matrix i (j) satisfies the following formula:

[0044] The i is the column number identifier, ranging from 1 to n; the j is the value of the basic submatrix;

[0045] The B i (j) is generated by translating a vector h, wherein the value of the vector h satisfies the formula The sequence loops to the left in units of the column number of the fundamental submatrix. Each unit forms the next row.

[0046] Through the above embodiments, for any N, when the lifting size is within... When within the range, the matrix C4free.

[0047] In one possible implementation of the first and second aspects, the at least two basic unit blocks comprise the same basic unit block composition.

[0048] Through the above embodiments, the basic submatrix of this application can be formed by splicing or translating the same basic unit blocks, which can solve the problem that LDPC parity-check matrices containing short cycles will cause a relatively high error floor in decoding.

[0049] In one possible implementation of the first and second aspects, the same basic unit block is formed by superimposing two single-sided quasi-cyclic LDPC unit blocks.

[0050] Through the above embodiments, the design of the basis matrix in this application exhibits regular algebraic characteristics, solving the problem that existing 5G NR matrices are all random search results lacking a fixed algebraic structure for guidance. It also addresses the issue that LDPC parity-check matrices containing short cycles can lead to a relatively high error floor during decoding. Furthermore, it implements a combination of shifting values, addressing the issue of high error floors caused by LDPC parity-check matrices containing short cycles from a short-cycle-free perspective. The construction of the algebraic features in this application supports fine-grained design. Compared to existing short-cycle-free design methods, the fine-grained shifting value design scheme of this application can satisfy conditions with a smaller lifting size.

[0051] In one possible implementation of the first and second aspects, the shift value matrix corresponding to the basic submatrix has cyclic properties.

[0052] In one possible implementation of the first and second aspects, the basic submatrix is ​​a 4×n matrix; the shift values ​​corresponding to the first two rows of the basic submatrix are shifted two positions to serve as the shift values ​​corresponding to the third and fourth rows of the basic submatrix.

[0053] Through the above embodiments, the fine-grained shifting value design scheme of the non-fully connected block generation (BG) in this application can achieve C4-free performance on a smaller scale compared to the fully connected i*j design. For the fully connected BG constructed based on a finite field, the shifting value of row i and column j is constructed as S_i*R_j, requiring a minimum lifting size of n (the number of columns) that is a prime number. The shifting value design in this application can be jointly optimized with the non-fully connected BG, does not require the code length n to be a prime number, and achieves a smaller minimum lifting size for C4-free performance. The shifting value design has no error floor and performs consistent with the best shifting value obtained through random search.

[0054] In one possible implementation of the first and second aspects, the shift value A of the shift value matrix corresponding to the fundamental submatrix i (j), A corresponding to the position where the value of the basic submatrix is ​​2. i (j) is related to the total number of columns of the basic submatrix and the column index of the position of 2.

[0055] Through the above embodiments, the construction of algebraic features in this application supports fine-grained design. Compared with existing short-cycle-free design methods, the fine-grained shifting value design scheme of this application can meet the lifting size requirements with a smaller order of magnitude. Specifically, the required lifting size for the C4-free shifting value design can reach the optimal bound; for the degree distribution of the same row and column, the lifting size bound for multi-edge to reach cycle-free is smaller than that for single-edge to reach cycle-free. Therefore, under reasonable design, multi-edge can achieve better performance for the same code length and code rate; the required lifting size for C4 and C6-free shifting value designs can reach the optimal bound or be on the same order of magnitude.

[0056] In one possible implementation of the first and second aspects, the shift value A of the shift value matrix i (j) satisfies the following formula:

[0057] The i is the column number identifier, ranging from 1 to n; the j is the value of the basic submatrix.

[0058] Through the above embodiments, when When within the specified range, the C4free matrix can adapt to the requirements of fine-grained code lengths, ensuring performance.

[0059] In one possible implementation of the first and second aspects, the shift value A of the shift value matrix i (j) satisfies the following formula:

[0060] The i is the column number identifier, ranging from 1 to n; the j is the value of the basic submatrix.

[0061] Through the above embodiments, for any n, when When within the range, the matrix C4free.

[0062] In one possible implementation of the first and second aspects, the shift value A of the shift value matrix i (j) satisfies the following formula:

[0063] The i is the column number identifier, ranging from 1 to n; the j is the value of the basic submatrix.

[0064] Through the above embodiments, for any n, when the lifting size is greater than or equal to all odd numbers in the range n-1, the matrix C4free is achieved.

[0065] In one possible implementation of the first and second aspects, the shift value A of the shift value matrix i (j) satisfies the following formula:

[0066] The i is the column number identifier, ranging from 1 to n; the j is the value of the basic submatrix.

[0067] Through the above embodiments, when the lifting size is When, the matrix C4C6 is free. Only when the lifting size is z can be any positive integer that does not satisfy C4 and C6 free. It can satisfy the requirements of different code lengths for cyclic elements, ensuring stable performance.

[0068] In one possible implementation of the first and second aspects, the shift value A of the shift value matrix i (j) satisfies the following formula:

[0069] Where t is an odd number When t is even

[0070] The i is the column number identifier, ranging from 1 to n; the j is the value of the basic submatrix.

[0071] Through the above embodiments, for any n, when At this time, matrix C4 and C6 are free. This can meet the requirements of different code lengths for the loop, ensuring stable performance.

[0072] In one possible implementation of the first and second aspects, the shift value A of the shift value matrix i (j) satisfies the following formula:

[0073] The i is the column number identifier, ranging from 1 to n; the j is the value of the basic submatrix.

[0074] Through the above embodiments, when The matrix C4free contains all odd numbers.

[0075] In one possible implementation of the first and second aspects, the shift value A of the shift value matrix i (j) satisfies the following formula:

[0076] The i is the column number identifier, ranging from 1 to n; the j is the value of the basic submatrix.

[0077] Through the above embodiments, when The matrix is ​​C4free.

[0078] Thirdly, embodiments of this application provide a communication device that has the function of implementing the behavior described in the first aspect of the method embodiments. The communication device can be a communication equipment, a component of a communication equipment (e.g., a processor, chip, or chip system), or a logic module or software capable of implementing all or part of the functions of the communication equipment. The function of the communication device can be implemented by hardware or by hardware executing corresponding software, the hardware or software including one or more modules or units corresponding to the above functions. In one possible implementation, the communication device includes an interface module and a processing module, wherein: the interface module is used to acquire an information bit sequence, and the processing module is used to perform low-density parity-check (LDPC) encoding on the information bit sequence according to a parity check matrix to obtain an encoded bit sequence, wherein the parity check matrix is ​​determined by a base matrix, the base matrix including a basic submatrix; the basic submatrix is ​​formed by concatenating at least two basic unit blocks with cyclic or translational elements.

[0079] For possible implementations of the communication device in the third aspect, please refer to the various possible implementations in the first aspect.

[0080] For the technical effects of the various possible implementations of the third aspect, please refer to the introduction of the technical effects of the first aspect or the various possible implementations of the first aspect.

[0081] Fourthly, embodiments of this application provide a communication device that has the function of implementing the behavior described in the second aspect of the method embodiments. The communication device can be a communication equipment, a component of a communication equipment (e.g., a processor, chip, or chip system), or a logic module or software capable of implementing all or part of the functions of the communication equipment. The function of the communication device can be implemented by hardware or by hardware executing corresponding software, the hardware or software including one or more modules or units corresponding to the above functions. In one possible implementation, the communication device includes an interface module and a processing module, wherein: the interface module is used to receive a first channel received sequence; the processing module is used to obtain a first log-likelihood ratio (LLR) sequence corresponding to the received first channel received sequence, and decode the first LLR sequence according to a parity check matrix; wherein the parity check matrix is ​​determined by a base matrix, the base matrix including a basic submatrix; the basic submatrix is ​​formed by concatenating at least two basic unit blocks with cyclic or translational elements.

[0082] For the technical effects of the various possible implementations of the fourth aspect, please refer to the introduction of the technical effects of the first aspect or the various possible implementations of the first aspect.

[0083] Fifthly, embodiments of this application provide another communication device, which includes a processor coupled to a memory for storing programs or instructions. When the program or instructions are executed by the processor, the communication device performs the method shown in the first aspect or any possible implementation thereof, or when the program or instructions are executed by the processor, the communication device performs the method shown in the second aspect or any possible implementation thereof.

[0084] In this embodiment of the application, during the execution of the above method, the process of sending information (or signals) can be understood as a process of outputting information based on processor instructions. When outputting information, the processor sends the information to the transceiver for transmission. After being output by the processor, the information may require further processing before reaching the transceiver. Similarly, when the processor receives input information, the transceiver receives the information and inputs it into the processor. Furthermore, after the transceiver receives the information, it may require further processing before being input into the processor.

[0085] Unless otherwise specified, or unless their actual function or internal logic in the relevant description is contradicted, the sending and / or receiving operations involved by the processor can generally be understood as processor instruction output.

[0086] In implementation, the processor described above can be a processor specifically designed to execute these methods, or it can be a processor that executes computer instructions stored in memory to execute these methods, such as a general-purpose processor. For example, the processor can also be used to execute a program stored in memory, which, when executed, causes the communication device to perform the methods as shown in the first aspect, the second aspect, or any possible implementation of the first and second aspects described above.

[0087] In one possible implementation, the memory is located outside the aforementioned communication device. In another possible implementation, the memory is located inside the aforementioned communication device.

[0088] In one possible implementation, the processor and memory may be integrated into a single device; that is, the processor and memory may be integrated together.

[0089] In one possible implementation, the communication device also includes a transceiver for receiving or transmitting signals, etc.

[0090] Sixthly, this application provides a computer-readable storage medium storing a computer program, the computer program including program instructions that, when executed, cause a computer to perform the method as shown in the first aspect or any possible implementation thereof, or, when executed, cause a computer to perform the method as shown in the second aspect or any possible implementation thereof.

[0091] In a seventh aspect, this application provides a computer program product comprising a computer program, the computer program including program instructions that, when executed, cause a computer to perform the method as shown in the first aspect or any possible implementation thereof, or, when executed, cause a computer to perform the method as shown in the second aspect or any possible implementation thereof. Attached Figure Description

[0092] Figure 1 is an example of a parity check matrix H of an LDPC code provided in this application;

[0093] Figure 2 is a Tanner diagram of the parity check matrix H of an LDPC code provided in an embodiment of this application;

[0094] Figure 3 shows four examples of (4×4) CPM provided in this application;

[0095] Figure 4 is a schematic diagram of the structure of a BG1 provided in an embodiment of this application;

[0096] Figure 5 is a schematic diagram illustrating the relationship between encoding rate and the number of bits in a code block (CB) according to an embodiment of this application.

[0097] Figure 6 is a schematic diagram of the scenario architecture of the communication system provided in an embodiment of this application;

[0098] Figure 7 is a schematic diagram of the generation principle of the basic unit block in an embodiment of this application;

[0099] Figure 8 is a schematic diagram of the basic unit block splicing provided in the embodiments of this application;

[0100] Figure 9 is a schematic diagram of the principle of hybrid splicing provided in the embodiment of this application;

[0101] Figure 10 is a schematic diagram of a hybrid splicing of a 4×n high bitrate BG with a four-row 3 / 4-side density according to an embodiment of this application;

[0102] Figure 11 is a schematic diagram of a non-hybrid splicing 4×n high bitrate BG with a four-row 3 / 4 side density;

[0103] Figure 12a is a schematic diagram of the principle of SV value design provided in the embodiment of this application;

[0104] Figure 12b is a schematic diagram of a Shifting Value design corresponding to 4×n BG provided in an embodiment of this application;

[0105] Figure 13 is a schematic diagram of the SV value design principle provided in the embodiment of this application;

[0106] Figure 14 is a schematic diagram of a Shifting Value design corresponding to 4×n BG provided in an embodiment of this application;

[0107] Figure 15 is a schematic diagram of another Shifting Value design corresponding to 4×n BG provided in the embodiments of this application;

[0108] Figure 16 is a schematic diagram of another Shifting Value design corresponding to 4×n BG provided in an embodiment of this application;

[0109] Figure 17 is a schematic diagram of another Shifting Value design corresponding to 4×n BG provided in the embodiments of this application;

[0110] Figure 18 is a schematic diagram of another Shifting Value design corresponding to 4×n BG provided in an embodiment of this application;

[0111] Figure 19 is a schematic diagram of another Shifting Value design corresponding to 4×n BG provided in an embodiment of this application;

[0112] Figure 20a is a schematic diagram of another Shifting Value design corresponding to 4×n BG provided in an embodiment of this application;

[0113] Figure 20b is a schematic diagram of the coding performance provided in an embodiment of this application;

[0114] Figure 21 is a structural schematic diagram of a communication device 2100 provided in an embodiment of this application;

[0115] Figure 22 is a schematic diagram of another communication device 220 provided in an embodiment of this application;

[0116] Figure 23 is a schematic diagram of another communication device 230 provided in an embodiment of this application. Detailed Implementation

[0117] The terms "first" and "second," etc., used in the specification, claims, and drawings of this application are used only to distinguish different objects and not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0118] In this application, the words "exemplary" or "for example" are used to indicate that something is an example, illustration, or illustration. Any embodiment or design described as "exemplary," "for example," or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Rather, the use of the words "exemplary," "for example," or "for example" is intended to present the relevant concepts in a specific manner.

[0119] The term "embodiment" as used herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0120] The terminology used in the following embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. As used in the specification and appended claims of this application, the singular expressions “a,” “an,” “the,” “the,” “the,” and “this” are intended to include the plural expressions as well, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this application refers to and includes any or all possible combinations of one or more of the listed items. For example, “A and / or B” can mean: the presence of only A, the presence of only B, and the presence of both A and B, where A and B can be singular or plural. The term “multiple” as used in this application means two or more.

[0121] It is understood that in the various embodiments of this application, "B corresponding to A" means that there is a correspondence between A and B, and B can be determined based on A. However, it should also be understood that determining (or generating) B based on (or on) A does not mean that B is determined (or generated) solely based on (or on) A; B can also be determined (or generated) based on (or on) A and / or other information.

[0122] To facilitate understanding of the scheme in this application, the relevant concepts of LDPC codes in this application will be introduced first.

[0123] LDPC stands for Low-Density Parity-Check Code. As the name suggests, it's a parity-check code with low density. Here, low density refers to the low density of the parity-check matrix. Therefore, to understand what LDPC codes are, we must first understand the three concepts: parity-check code, parity-check matrix, and low density.

[0124] 1. Parity check code

[0125] Parity check codes are a type of encoding method that ensures the number of "1"s in a codeword is always odd or even by adding redundant bits. They are commonly used for encoding numbers in the 0-1 binary domain. One or more check bits are added to the end of the codeword, and the presence of an odd or even number of "1"s determines whether the codeword has been corrupted before or after transmission. For example, with the codeword 100, the check bit can be set to 1, ensuring that the sum (XOR) of all codewords equals 0 (s), i.e., 1001. If the codeword becomes 1101 after transmission, indicating an error in one bit, then s becomes 1, indicating a transmission error. It's important to understand that if an even number of bits are corrupted, the algorithm fails. Therefore, multiple check bits can be used. For example, the four-bit codeword 1101 can be grouped, with the first check bit used to check the first and second bits of the information bits (i.e., the first two bits, 11). For example, to make the sum of the first two information bits 0, the first parity bit should be 0. Similarly, the second parity bit can check the last two information bits of the codeword 1101, so it should be 1. Therefore, the encoded codeword is 110101. This is essentially the parity check concept of LDPC codes, i.e., the meaning of "PC". It is clear that LDPC codes are block codes and essentially use parity checking. Adding the low-density characteristic results in the LDPC code.

[0126] 2. Low-density property of LDPC codes

[0127] The low-density property of LDPC codes refers to the fact that the number of 1s in the parity-check matrix of an LDPC code is very small. LDPC codes are linear block codes, and their parity-check matrix is ​​a sparse matrix. The number of zero elements in the parity-check matrix of an LDPC code is far greater than the number of non-zero elements. In other words, the row weight (i.e., the number of 1s in each row) and column weight (i.e., the number of 1s in each column) of the parity-check matrix are very small compared to the code length of the LDPC code.

[0128] 3. Check matrix and generator matrix of LDPC code

[0129] Taking the 1101 codeword as an example, the check relationship between the information bits and the check bits can be written in matrix form. Let the information bits be c1, c2, c3, c4, and the check bits be p1, p2. c = [c1, c2, c3, c4], x = [c1, c2, c3, c4, p1, p2]. Here, c and x are the codeword before and after encoding, respectively; that is, c is the information bit, and x is the codeword bit or encoded bit. x can be understood as information bit + check bit. In the example of codeword 1101, the check relationship between the information bits and the check bits of codeword 1101 can be expressed as the following linear relationship: c1 + c2 + p1 = 0, c3 + c4 + p2 = 0. This linear relationship can be written as the following formula: x·H T =s=0 (1);

[0130] Where H is: s = (0,0). Here, H is the parity check matrix, s is the parity checksum, and H... T This represents the transpose of H. The idea behind formula (1) is that after the information bit c is encoded by the generator matrix G (G is determined by H), the resulting codeword bit x needs to satisfy x·H. T =0. To easily determine whether this result is 0, we introduce the concept of a checksum s. As long as s is all 0, then the transmission is fine. In this application, "·" represents matrix multiplication, and "A·B" represents the product of matrix multiplication of matrix A and matrix B.

[0131] The codeword bits x obtained by encoding c through the generator matrix G can satisfy the following formula: x=c·G; (2);

[0132] Where c represents the unencoded codeword (or bit sequence), and G represents the generator matrix. G and H T They are orthogonal to each other, i.e., G·H T =0. The generator matrix can be obtained by transforming the parity check matrix. That is, if the parity check matrix is ​​known, the generator matrix corresponding to the parity check matrix can be obtained. Equation (2) shows that the codeword bits are obtained by multiplying the information bits by the generator matrix.

[0133] 4. Tanner diagram

[0134] In 1981, Tanner represented the codewords of LDPC codes graphically. This type of graph is now called a Tanner graph, and there is a one-to-one correspondence between the Tanner graph and the parity-check matrix. A Tanner graph consists of two types of vertices: variable nodes, representing codeword bits, and parity nodes, representing parity-check constraints. Each parity node represents a parity-check constraint, which will be explained below with reference to Figures 1 and 2.

[0135] Referring to Figure 1, Figure 1 shows an example of a parity-check matrix H for an LDPC code provided in this application. In Figure 1, {Vi} represents the set of variable nodes, and {Ci} represents the set of parity-check nodes. Each row of the parity-check matrix H corresponds to a parity-check equation, and each column corresponds to a codeword bit. In Figure 1, there are 8 variable nodes and 4 parity-check nodes. If a codeword bit is included in the corresponding parity-check equation, a line is used to connect the involved variable nodes and parity-check nodes to obtain a Tanner diagram.

[0136] Referring to Figure 2, Figure 2 is a Tanner diagram of a parity-check matrix H of an LDPC code provided in an embodiment of this application. As shown in Figure 2, the Tanner diagram represents the parity-check matrix of the LDPC code. For example, for a parity-check matrix H of size m rows and n columns, the Tanner diagram contains two types of nodes: n variable nodes (also called information nodes or bit nodes) and m parity nodes, where m and n are both integers greater than 0. The n variable nodes correspond to the n columns of the parity-check matrix H, and the m parity nodes correspond to the m rows of the parity-check matrix H. The loops in the Tanner diagram are composed of interconnected vertices. The loop uses one vertex from this group of vertices as both the start and end point, and passes through each node only once. The length of the loop is defined as the number of edges it contains, and the circumference of the figure, also known as the size of the figure, is defined as the minimum loop length in the figure. In Figure 2, the circumference is 6, as shown by the bolded connecting line in Figure 2.

[0137] 5. Encoding of LDPC codes

[0138] Based on the above description, it can be seen that codeword bits are obtained by multiplying information bits by the generator matrix, and the generator matrix can be obtained by transforming the parity check matrix. Therefore, the entire LDPC code encoding process is actually a process of constructing a parity check matrix. The parity check matrix H can be transformed into H = [IP]; from G·H T =0, resulting in the generating matrix G = [-P T I]; The information bits c are encoded by the generator matrix G to obtain the codeword bits x, i.e., x = c·G. Where I represents the information bit part, P represents the parity bit part, and x is the codeword bit.

[0139] 6. Decoding LDPC codes

[0140] The LDPC code decoding process involves iterating through messages between the variable node and the check node using a check pattern between the check bits (or check symbols) and the information bits (or information symbols) until a pattern satisfying x·H is found. T = The codeword is given by the given condition, and the output x is the decoded codeword. LDPC code decoding algorithms fall into three main categories: hard-decision decoding, soft-decision decoding, and hybrid decoding.

[0141] 7. Obtain the parity-check matrix by expanding the basis matrix.

[0142] The basis matrix of an LDPC code can be extended to a parity check matrix of LDPC codes of various lengths as needed. Typically, the basis matrix of an LDPC code contains only 0 and 1 elements. In this application, 0 in the basis matrix can be replaced with blanks, "-", "-1", or other numbers or symbols; this application does not impose any limitations. In this application, when the parity check matrix is ​​obtained by extending the basis matrix, the 1s in the basis matrix can be extended to a non-all-zero square matrix (also called a non-all-zero square matrix), and the 0 elements in the basis matrix can be extended to a all-zero square matrix (also called an all-zero square matrix). In this application, an all-zero square matrix refers to a square matrix in which every element is 0, such as a square matrix of size (27×27). In this application, a non-all-zero square matrix refers to a square matrix containing at least one non-zero element, such as a circulant permutation matrix (CPM). CPM is a circulant shift of the identity matrix. In other words, a circulant shift of the identity matrix is ​​called CPM. The meaning of CPM will be the same thereafter and will not be elaborated further. In this application, any CPM can be represented by a numerical value and an extension factor. In other words, any CPM corresponds to a numerical value and an expansion factor. The difference in size between two CPMs refers to the difference in their corresponding expansion factors. In this application, the expansion factor corresponding to a CPM can be called the specific value of the expansion factor, the expansion factor value, or the cyclic shift factor, etc. The numerical value corresponding to a CPM can be called the cyclic shift coefficient. The expansion factor corresponding to a CPM characterizes the size of the CPM; that is, different sizes of CPMs have different expansion factors. For example, a CPM of size (27×27) has an expansion factor of 27. Or, a CPM with an expansion factor of 27 indicates that the size of that CPM is (27×27). Another example is a CPM of size (54×54) with an expansion factor of 54. The meaning of the expansion factor for subsequent CPMs follows the same pattern and will not be elaborated further. It should be noted that the expansion factors of all CPMs in the parity check matrix are the same. For example, a base matrix of size (12×24) is expanded using an expansion factor Z = 27 to obtain a parity check matrix, where the expansion factor of each CPM in the parity check matrix is ​​Z. In this application, the numerical value (integer) corresponding to CPM represents the number of bits shifted to the right cyclically from the identity matrix. Figure 3 shows examples of four (4×4) CPMs provided in this application. As shown in Figure 3, P0 represents a (4×4) identity matrix. P0 can be considered as a CPM with an expansion factor of 4 and a corresponding numerical value of 0. P1 is a CPM with an expansion factor of 4 and a corresponding numerical value of 1. P2 is a CPM with an expansion factor of 4 and a corresponding numerical value of 2. P3 is a CPM with an expansion factor of 4 and a corresponding numerical value of 3. Figure 3 shows examples of four CPMs provided in the embodiments of this application. It should be understood that any CPM can be obtained by cyclically shifting the corresponding identity matrix to the right, which will not be detailed here. It should be understood that 1 in the basis matrix can be expanded to a CPM of any size, and 0 in the basis matrix can be expanded to a square matrix of all zeros of any size.The meaning or function of 1 or 0 in the basis matrix is ​​the same as that described above, and will not be repeated here.

[0143] The parity-check matrix can be obtained by expanding the basis matrix as follows: replace the 1s in the basis matrix with CPMs, and replace the 0s with a square matrix of all zeros of the corresponding size. For example, if each element in the basis matrix is ​​either 0 or 1, when expanding the parity-check matrix from this basis matrix, each 0 in the basis matrix is ​​expanded into a (Z×Z) matrix of all zeros, and each 1 in the basis matrix is ​​expanded into a (Z×Z) CPM, where Z is the expansion factor corresponding to the CPM. Different CPMs may have the same or different values. Therefore, a series of parity-check matrices for LDPC codes can be obtained from the basis matrix. The size of these parity-check matrices and the expansion factor of each CPM may be different, but they correspond to or conform to the same basis matrix.

[0144] In this application, the basis matrix of the LDPC code can contain three elements: 0, 1, and 2. The 2 in the basis matrix can also be extended into a non-all-zero square matrix. The 2 in the basis matrix can represent an element with two shift values. The non-all-zero square matrix extended from the basis matrix is ​​formed by shifting the corresponding values ​​of the two shift values ​​according to CPM and then superimposing them.

[0145] It is understood that the value representing an element with two shift values ​​can be 2 or other values. This application does not limit this, as long as the agreement specifies a value to represent an element with two shift values.

[0146] Before introducing the method provided in the embodiments of this application, the base graph (BG), BG1, and BG2 are briefly described below. It should be understood that the following descriptions of BG1 and BG2 are merely examples, and other descriptions of BG1 and BG2 can be found in relevant standards or protocols, etc., which are not limited in this application embodiment.

[0147] Taking BG1 as an example: Figure 4 is a structural schematic diagram of BG1 provided in an embodiment of this application. Figure 5 is a schematic diagram showing the relationship between the encoding code rate and the number of bits in the CB provided in an embodiment of this application. For example, the applicable code length of BG1 is information bits K = 308~8448 bits, and the code rate R is 0.25 <= R <= 0.95. The applicable code length of BG2 is information bits K = 40~3840 bits, and the code rate R is 0.20 <= R <= 0.95. It can be seen that BG1 is mainly for medium to high code rates and long data packets, while BG2 is mainly for medium to low code rates and short data packets.

[0148] However, the current 5G air interface NR-LDPC codes BG1 and BG2 have the following drawbacks: the basis matrix and shifting values ​​(SV) are obtained by random search, which relies on a large number of searches; the short-cycle free characteristic cannot be theoretically guaranteed; currently, both 5G NR-LDPC codes BG1 and BG2 are single-edge LDPCs, and the theoretical lower bound of the lifting size that guarantees short-cycle free for single-edge LDPCs is inferior to that of multi-edge LDPCs.

[0149] Given the lack of theoretical guarantees for short-cycle free decoding in 5G NR-LDPC codes, this paper designs the LDPC base graph from the perspective of short-cycle free decoding, and implements shifting value design for a fixed base matrix. This ensures short-cycle free decoding, thus providing a fundamental guarantee for LDPC decoding performance. The joint design of the base matrix and shifting values, as shown in Table 1, guarantees short-cycle free decoding.

[0150] Shifting Value characteristics: For an n*n fully connected matrix, the row and column index set is {0,…,n-1}, and the shifting value of the i-th row and j-th column is designed as i*j; (if n is a prime number p, the shifting value of the i-th row and j-th column can be designed as i*j (mod p)).

[0151] However, this design is an n*n fully connected layer, which has high complexity and cannot guarantee performance; in addition, the condition is only C4free, which is far from sufficient for medium to long code.

[0152] The technical solutions provided in this application can be applied to various communication systems, such as Internet of Things (IoT) systems, narrowband Internet of Things (NB-IoT) systems, long term evolution (LTE) systems, 5th generation (5G) communication systems, and new communication systems that will emerge in the future development of communication.

[0153] Wireless communication systems typically consist of cells, each containing a base station (BS). The base station provides communication services to multiple mobile stations (MS). A base station includes a baseband unit (BBU) and a remote radio unit (RRU). The BBU and RRU can be located in different places; for example, the RRU can be deployed remotely to a high-traffic area, while the BBU is located in a central equipment room. Alternatively, the BBU and RRU can be located in the same equipment room. Furthermore, the BBU and RRU can be different components within the same rack.

[0154] Figure 6 shows a schematic diagram of the scenario architecture of a communication system provided in an embodiment of this application. This communication system may include at least one network device and at least one terminal device, as shown in Figure 6 as terminal device 1 to terminal device 4. For example, terminal device 3 and terminal device 4 shown in Figure 6 can communicate directly. For instance, direct communication between terminal devices can be achieved through D2D technology. Terminal devices 1 to 4 can communicate with the network device respectively. It is understood that terminal devices 3 and 4 can communicate directly with the network device or indirectly with it, such as via other terminal devices (not shown in Figure 6). It should be understood that Figure 6 exemplarily illustrates one network device and multiple terminal devices, as well as the communication links between the communication devices. Optionally, the communication system may include multiple network devices, and the coverage area of ​​each network device may include other numbers of terminal devices, such as more or fewer terminal devices; this embodiment of the application does not limit this. The terminal devices and network devices are described in detail below.

[0155] A terminal device is a device with wireless transceiver capabilities. It can communicate with access network equipment (or access devices) in a radio access network (RAN). Terminal devices can also be referred to as user equipment (UE), access terminal, terminal, subscriber unit, user station, mobile station, remote station, remote terminal, mobile device, user terminal, user agent, or user device, etc. In one possible implementation, the terminal device can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; it can also be deployed on water (such as on a ship). In one possible implementation, the terminal device can be a handheld device with wireless communication capabilities, a vehicle-mounted device, a wearable device, a sensor, a terminal in the Internet of Things (IoT), a terminal in the Internet of Vehicles (IoV), a drone, a terminal device in a 5G network, or any form of terminal device in a future network, etc., and this application embodiment does not limit this. It is understood that the terminal device shown in this application embodiment can include not only vehicles (such as cars) in the IoV, but also vehicle-mounted equipment or vehicle-mounted terminals in the IoV, and this application embodiment does not limit the specific form of the terminal device when applied to the IoV. It is understood that the terminal devices shown in the embodiments of this application can also communicate with each other through technologies such as D2D, V2X or M2M. The embodiments of this application do not limit the communication method between terminal devices.

[0156] A network device can be a device deployed in a radio access network to provide wireless communication services to terminal devices. This network device can also be called an access network device, access equipment, or RAN device, etc. For example, the network device can be a next-generation node B (gNB), a next-generation evolved node B (ng-eNB), or a network device in 6G communication, etc. The network device can be any device with wireless transceiver capabilities, including but not limited to the base stations mentioned above (including base stations deployed on satellites). The network device can also be a device with base station functionality in 6G. Optionally, the network device can be an access node, wireless relay node, or wireless backhaul node in a wireless-fidelity (Wi-Fi) system. Optionally, the network device can be a wireless controller in a cloud radio access network (CRAN) scenario. Optionally, the network device can be a wearable device or an in-vehicle device, etc. Optionally, the network device can also be a small cell, a transmission reception point (TRP) (or also called a transmission point), etc. It is understood that the network device can also be a base station, satellite, etc., in a future evolved public land mobile network (PLMN). The network device can also be a communication device carrying base station functions in non-terrestrial communication systems, D2D, V2X, or M2M, etc. This application embodiment does not limit the specific type of network device. In systems with different wireless access technologies, the names of communication devices with network device functions may differ, and this application embodiment will not list them all. Optionally, in some deployments of the network device, the network device can include a centralized unit (CU) and a distributed unit (DU), etc. In other deployments of the network device, the CU can also be divided into a CU-control plane (CP) and a CU-user plane (UP), etc. In still other deployments of the network device, the network device can also be an open radio access network (ORAN) architecture, etc. This application embodiment does not limit the specific deployment method of the network device.

[0157] This application provides an LDPC encoding method, executed by a network device at the transmitting end, comprising: acquiring an information bit sequence; performing low-density parity-check (LDPC) encoding on the information bit sequence according to a parity check matrix to obtain an encoded bit sequence; wherein the parity check matrix is ​​determined by a base matrix, the base matrix including a basic submatrix; the basic submatrix is ​​formed by concatenating at least two basic unit blocks with cycles or translations; and then transmitting the encoded bit sequence to a receiving end device.

[0158] Correspondingly, the LDPC code decoding method provided in this application embodiment is executed by the network device at the receiving end, including obtaining the first log-likelihood ratio (LLR) sequence corresponding to the received first channel received sequence; and decoding the first LLR sequence according to the parity check matrix.

[0159] This application proposes a design scheme for a multi-edge LDPC code based on a cyclic structure, covering all isomorphic matrices and their submatrices. It employs a joint design approach of basis matrix and shifting value, proposing a combination form of shifting value. From the perspective of short-cycle free, the numerical characteristics of the shifting value are characterized by a formula, and the relationship between the shifting value design scheme and lifting size is described. The basis matrix of this multi-edge cyclic form has a consistent threshold compared to the basis matrix of the core matrix in 5G NR. Multi-edge LDPC lacks practical code design, and finding a cycle-free exponent matrix through random search is difficult. Compared to single-edge LDPC, multi-edge LDPC can achieve cycle free or a smaller number of cycles with a smaller lifting size. This scheme, with a fixed basis matrix, has no error floor in the shifting value design, ensuring both fine granularity and performance.

[0160] First, the form of the basis matrix BG in this application is explained: it is generated by splicing / truncating a single cyclic block. A single cyclic block can be composed of a superposition of multiple polynomials with coefficients of 0 and 1, and its dimension m is determined by the block length.

[0161] Specifically, the number and position of non-zero values ​​in the first row of a single loop block are determined by a column identifier vector; the number of elements in this column identifier vector corresponds to the number of non-zero values ​​in the first row, and the size of the elements in the column identifier vector represents the column identifier of the non-zero position in the first row; the column identifier vector is determined by the degree of the non-zero coefficients in the polynomial; different single loop blocks correspond to different polynomials. That is, the specific formation method can be as follows:

[0162] First, let the base matrix have dimension m*m. The first row of the matrix is ​​generated by taking the position value of the element of vector p (where vector p is the degree of the non-zero coefficient in the polynomial) as the column index and setting it to 1, and setting the other elements to 0. Then, the non-zero position of each row is formed by shifting the previous row 1 unit to the right, generating an m*m dimensional cyclic block. Then, the cyclic blocks generated by the vector p of multiple polynomials are superimposed to generate the basic unit block.

[0163] For example: polynomial g(x) = 2 + x 3 This can be expressed by the polynomial g(x) = 1 + x 3 The polynomial g(x) = 1 is superimposed with the polynomial p. The cyclic blocks generated by the vector p of these two polynomials are then superimposed to generate basic unit blocks, as shown in Figure 7, a schematic diagram illustrating the generation principle of basic unit blocks in this embodiment of the application. The polynomial g(x) = 1 + x 3 The exponents of the non-zero coefficients of the polynomial g(x) = 1 are 0 and 3. Therefore, vector p = (0, 3) yields the non-zero elements of the first row of the left matrix. This is achieved by shifting the non-zero positions of each row one unit to the right of the previous row. Similarly, the exponents of the non-zero coefficients of the polynomial g(x) = 1 are 0. Therefore, vector p = (0) yields the non-zero elements of the first row of the right matrix. This is achieved by shifting the non-zero positions of each row one unit to the right of the previous row. This results in two distinct single-loop blocks, which are then superimposed to generate the basic unit block.

[0164] The base matrix of this application is formed by concatenating basic submatrices, which are formed by concatenating at least two basic unit blocks with cycles or translations. The basic unit blocks can be generated by superimposing at least two single-cycle blocks (as shown in Figure 7, where two different single-cycle blocks are superimposed). That is, the base matrix of this application can include the range of: the base graph of basic unit block concatenation / truncation, and all matrices isomorphic to it.

[0165] Taking an m×N base graph as an example, the concatenation of basic unit blocks, specifically a 4-row, N-column non-fully connected base graph, is illustrated in Figure 8 as a schematic diagram of the basic unit block concatenation. The graph has m rows and n columns, with the last basic unit block g... j (x) can be partially extracted as BG. Furthermore, g j (x) Select columns with row weights as evenly as possible.

[0166] In this application embodiment, there are two ways to splice the basic unit blocks: mixed splicing (i.e., splicing different basic unit blocks) and non-mixed splicing (i.e., splicing the same basic unit blocks). Taking a 4×n basis matrix BG as an example, with both rows and columns having a weight of three, we will illustrate this further:

[0167] As shown in Figure 9, hybrid splicing can be formed by combining four different basic unit blocks in any proportion to create a 4×n column base region (BG) with a weight of three. Figure 10 shows a schematic diagram of a 4×n high-rate BG with a four-row, three- / four-sided density. The three different basic unit blocks can be regarded as a hybrid unit (i.e., the basic submatrix corresponding to the hybrid splicing method). The base matrix in the embodiments of this application can be formed by splicing multiple hybrid units.

[0168] As shown in Figure 11, non-hybrid splicing can be achieved by having identical basic unit blocks in each splice. In this case, each basic unit block can be considered as a basic submatrix. The base matrix in this embodiment can be formed by splicing multiple identical basic unit blocks. Figure 11 shows a schematic diagram of a non-hybrid splicing 4×n high-rate BG with a four-row 3 / 4-side density.

[0169] This construction method is very common. The embodiments of this application are designed for this type of base map and their corresponding Shifting Values.

[0170] The following describes the design scheme of the Shifting Value with a loop structure in this application:

[0171] For different basic unit blocks, the basic submatrix can be formed by superimposing at least two submatrices. These at least two submatrices can include a first submatrix and a second submatrix; wherein, the first submatrix can be formed by mixing and splicing at least two single-sided quasi-cyclic LDPC unit blocks with single-block cycles; and the second submatrix can be formed by splicing at least two single-sided quasi-cyclic LDPC unit blocks with non-mixed or mixed splicing.

[0172] The values ​​in the basic submatrix include 0, 1, and 2; a value of 0 indicates no shifted element, a value of 1 indicates one shifted element, and a value of 2 indicates two shifted elements. This embodiment uses a value of 2 as an example to represent two shifted elements, but it is not limited to a value of 2.

[0173] The shift value matrix corresponding to the basic submatrix is ​​formed by combining the first shift value matrix corresponding to the first one-sided quasi-cyclic LDPC cell block and the second shift value matrix corresponding to the second one-sided quasi-cyclic LDPC cell block; the shift value matrix corresponding to each basic cell block in the first shift value matrix satisfies a single-block cycle; the second shift value matrix satisfies a cycle by shifting W units; W is related to the total number of columns of the basic submatrix.

[0174] In one implementation, at least one matrix is ​​translated in a non-mixed manner; the splitting rule is that values ​​at the same position are split into at least two matrices, such that any one matrix is ​​a single-sided QC-LDPC; the at least two matrices have SV value design methods that satisfy the cyclic characteristics, wherein the mixed form of the single-sided QC-LDPC is a single-block cycle of the basic unit block, and the split non-mixed matrix is ​​a cycle of translating the entire mixed unit by a certain unit (e.g., the example in the figure is a translation). (left loop of units).

[0175] Taking the four-row, 3 / 4-side density polygonal QC-LDPC base map in Figure 10 as an example, and as shown in Figure 12a, a schematic diagram of the SV value design principle provided by the embodiment of this application, the SV value can be decomposed into combinations of different forms of single-sided QC-LDPC. The mixed form of single-sided QC-LDPC is the first sub-matrix of this application, and the corresponding shift value matrix is ​​the first shift value matrix of this application; the non-mixed form of single-sided QC-LDPC is the second sub-matrix of this application, and the corresponding shift value matrix is ​​the second shift value matrix of this application. That is, the second sub-matrix in Figure 12a is illustrated using the example of non-mixed splicing of single-sided QC-LDPC.

[0176] As shown in Figure 12a, the SV values ​​satisfy the cyclic characteristic, and the SV values ​​of the same texture are the same. It is understood that the texture filling used in this embodiment is for illustrating the cyclic or translational rules of SV values; in actual applications, the matrix does not contain textures. For the basic submatrix formed by splicing blending units, the shift values ​​corresponding to the same positions (which can be understood as the same positions of the blending units) between the basic submatrixes are the same or satisfy the arithmetic sequence characteristic. Taking n=12 in Figure 10 as an example, the entire blending unit of the non-blended single-sided QC-LDPC conforms to a cyclic left translation of W=3 units.

[0177] For example, for a 4×n matrix as the fundamental submatrix; the shift value A of the shift value matrix corresponding to the fundamental submatrix. i (j) satisfies the following formula (3):

[0178] The i is the column number identifier, ranging from 1 to n; the j is the value of the basic submatrix;

[0179] The B i (j) is generated by translating a vector h, wherein the value of the vector h satisfies the formula The sequence loops to the left in units of the column number of the fundamental submatrix. Each unit forms the next row.

[0180] Taking 12 columns as an example, Figure 12b shows a schematic diagram of the Shifting Value design corresponding to 4×n BG provided by the embodiment of this application. The hybrid unit is shown in the upper part of Figure 12b. An example of the SV value in the lower part of Figure 12b can be obtained by the above formula (3).

[0181] The above example provides the following theoretical guarantee: for any N, when the lifting size is within the range of... When within the range, the matrix C4free.

[0182] For a basic submatrix formed by concatenating identical basic unit blocks: identical basic unit blocks are formed by superimposing two unilateral quasi-cyclic LDPC unit blocks; the shift value matrix corresponding to the basic submatrix has cyclic properties. The values ​​in the basic submatrix include 0, 1, and 2; a value of 0 indicates no shift value element, a value of 1 indicates one shift value element, and a value of 2 indicates two shift value elements.

[0183] For example, the basic submatrix can be a 4×n matrix; the shift values ​​corresponding to the first two rows in the basic submatrix are shifted two positions to become the shift values ​​corresponding to the third and fourth rows in the basic submatrix.

[0184] Taking the four-row 3 / 4-side density polygonal QC-LDPC base map in Figure 11 as an example, and the schematic diagram of the SV value design provided by the embodiment of this application shown in Figure 13, a single basic loop block with the same texture CPM has the same shifting value; corresponding to the lower part of Figure 13, for BG with the same row and column transformation (isomorphism), the shifting value number sequence in the same color box is the same.

[0185] For example, for a 4×n matrix as the fundamental submatrix; the shift value A of the shift value matrix corresponding to the fundamental submatrix. i (j) satisfies the following formula (4):

[0186] Where x and y are functions of i and are related to the size of the lifting factor and the total number of columns in the base graph. The following examples of five options provide specific x and y design methods.

[0187] Option 1:

[0188] Regarding formula (4),

[0189] The i is the column number identifier, ranging from 1 to n; the j is the value of the basic submatrix.

[0190] Taking 12 columns and 16 columns as examples respectively, Figure 14 shows a schematic diagram of the Shifting Value design corresponding to 4×n BG provided by the embodiment of this application. The SV value can be obtained by the above formula (4).

[0191] Option 1 above can be theoretically guaranteed as follows: when When within the specified range, the C4free matrix can adapt to the requirements of fine-grained code lengths, ensuring performance.

[0192] Option 2:

[0193] Regarding formula (4),

[0194] The i is the column number identifier, ranging from 1 to n; the j is the value of the basic submatrix.

[0195] Taking 20 columns and 24 columns as examples respectively, Figure 15 shows another 4×n BG corresponding to the Shifting Value design provided by the embodiment of this application. The SV value can be obtained by the above formula (4).

[0196] Option 2 above can be theoretically guaranteed as follows: For any n, when When within the range, the matrix C4free.

[0197] Option 3:

[0198] Regarding formula (4),

[0199] The i is the column number identifier, ranging from 1 to n; the j is the value of the basic submatrix.

[0200] Taking 12 columns as an example, Figure 16 shows another design schematic diagram of Shifting Value corresponding to 4×n BG provided by the embodiment of this application. An example of SV value can be obtained by the above formula (4).

[0201] Option 3 above can be theoretically guaranteed to be: for any n, when the lifting size is greater than or equal to all odd numbers in the range n-1, the matrix C4free.

[0202] Option 4:

[0203] Regarding formula (4),

[0204] The i is the column number identifier, ranging from 1 to n; the j is the value of the basic submatrix.

[0205] Taking columns 12, 16, 20 and 24 as examples respectively, Figure 17 shows another 4×n BG corresponding to the Shifting Value design provided by the embodiment of this application. The SV value can be obtained by the above formula (4). The value on the left side of the matrix is ​​the minimum lifting size that satisfies the loop property.

[0206] Option 4 above provides the following theoretical guarantee: when the lifting size is... When, the matrix C4 and C6 are free. When lifting Only when the lifting size is z can be any positive integer that does not satisfy C4 and C6 free. It can satisfy the requirements of different code lengths for cyclic elements, ensuring stable performance.

[0207] Option 5:

[0208] Regarding formula (4),

[0209] Where t is an odd number When t is even

[0210] The i is the column number identifier, ranging from 1 to n; the j is the value of the basic submatrix.

[0211] Option 5 above can be theoretically guaranteed as follows: For any n, when At this time, matrix C4 and C6 are free. This can meet the requirements of different code lengths for the loop, ensuring stable performance.

[0212] Using columns 12, 16, 20, and 24 respectively, and when t is an odd number, take... When t is even

[0213] For example, as shown in Figure 18, another design diagram of the Shifting Value corresponding to 4×n BG provided in this application embodiment can be used to obtain an example of the SV value through the above formula (4). The values ​​on the left side of the matrix are the minimum Lifting Sizes that satisfy the loop property.

[0214] That is, the following theoretical guarantee can be obtained at this time: when t is odd, when When t is even, when C4, C6free, or only a small number of C6s, evenly distributed with no error floor. This can meet the requirements for loops of different code lengths, ensuring stable performance.

[0215] For example, for a 4×n matrix as the fundamental submatrix; the shift value A of the shift value matrix corresponding to the fundamental submatrix. i (j) satisfies the following formula (5):

[0216] Where x and y are functions of i and are related to the size of the lifting factor and the total number of columns in the base graph. The following examples of two options provide specific x and y design methods.

[0217] Option a:

[0218] Regarding formula (5),

[0219] The i is the column number identifier, ranging from 1 to n; the j is the value of the basic submatrix.

[0220] Taking 12 columns as an example, Figure 19 shows another design schematic diagram of Shifting Value corresponding to 4×n BG provided by the embodiment of this application. An example of SV value can be obtained by the above formula (5).

[0221] Option a above can be theoretically guaranteed as follows: when The matrix C4free contains all odd numbers.

[0222] Understandably, there may be other ways to take the values ​​of y1(i) and y2(i): for all i and j, and i≠j, y1 and y2 that satisfy the conditions y1(i)≠y1(j), y2(i)≠y2(j), y1(i)≠y2(j), y1(i)≠y2(i) can replace the corresponding positions in the above formula.

[0223] Option b:

[0224] Regarding formula (5),

[0225] The i is the column number identifier, ranging from 1 to n; the j is the value of the basic submatrix.

[0226] Taking 12 columns as an example, as shown in Figure 20a, another design diagram of Shifting Value corresponding to 4×n BG provided by the embodiment of this application can be obtained by formula (5) above.

[0227] Option b above can be theoretically guaranteed as follows: when The matrix is ​​C4free.

[0228] Through the above embodiments, the fine-grained shifting value design scheme of the non-fully connected block group (BG) designed in this application can achieve C4-free performance on a smaller scale compared to the fully connected i*j design. For the fully connected BG constructed based on a finite field, the shifting value of row i and column j is constructed as S_i*R_j, requiring a minimum lifting size of n (the number of columns) that is a prime number. The shifting value design of this application can be jointly optimized with the non-fully connected BG, does not require the code length n to be a prime number, and achieves a smaller minimum lifting size for C4-free performance. The shifting value design has no error floor and performs consistent with the best shifting value found through random search, as shown in the performance diagram in Figure 20b.

[0229] The structure of a communication device that can implement the LDPC code encoding method or LDPC code decoding method provided in the embodiments of this application is described below with reference to the accompanying drawings.

[0230] Figure 21 is a schematic diagram of a communication device 2100 provided in an embodiment of this application. This communication device 2100 can correspondingly implement the functions or steps implemented by the transmitting or receiving network devices in the various method embodiments described above. The communication device may include a processing module 2110 and an interface module 2120. Optionally, it may also include a storage unit, which can be used to store instructions (code or program) and / or data. The processing module 2110 and the interface module 2120 can be coupled to the storage unit. For example, the processing module 2110 can read the instructions (code or program) and / or data from the storage unit to implement the corresponding method. The various units described above can be set independently, or partially or completely integrated. For example, the interface module 2120 may include a transmitting module and a receiving module. The transmitting module can be a transmitter, and the receiving module can be a receiver. The entity corresponding to the interface module 2120 can be a transceiver or a communication interface.

[0231] In some possible implementations, the communication device 2100 can correspondingly implement the behavior and functions of the transmitting or receiving network device in the above method embodiments. For example, the communication device 2100 can be a transmitting or receiving device, or a component (e.g., a chip or circuit) applied in the transmitting or receiving device. The interface module 2120 is used to perform all information receiving or sending operations. The processing module 2110 is used to perform all operations other than the sending and receiving operations.

[0232] Figure 22 is a schematic diagram of another communication device 220 provided in an embodiment of this application. The communication device in Figure 22 can correspondingly implement the functions or steps implemented by the transmitting network device or the receiving network device in the above-described method embodiments.

[0233] As shown in Figure 22, the communication device 220 includes at least one processor 2210 and a transceiver 2220.

[0234] In some embodiments of this application, transceiver 2220, for example, performs all receive or transmit operations of the transmitting or receiving network device in the various method embodiments described above. Processor 2210, for example, performs all operations of the transmitting or receiving network device in the various method embodiments described above, except for the transmit and receive operations.

[0235] Transceiver 2220 is used to communicate with other devices / appliances via a transmission medium. Processor 2210 uses transceiver 2220 to send and receive data and / or signaling, and to implement the methods in the above method embodiments. Processor 2210 can implement the functions of processing module 2110, and transceiver 2220 can implement the functions of interface module 2120.

[0236] Optionally, the communication device 220 may further include at least one memory 2230 for storing program instructions and / or data. The memory 2230 is coupled to the processor 2210. The coupling in this embodiment is an indirect coupling or communication connection between devices, units, or modules, and can be electrical, mechanical, or other forms, for information exchange between devices, units, or modules. The processor 2210 may operate in conjunction with the memory 2230. The processor 2210 may execute program instructions stored in the memory 2230. At least one of the at least one memory may be included in the processor.

[0237] This embodiment does not limit the specific connection medium between the transceiver 2220, processor 2210, and memory 2230. In Figure 22, the memory 2230, processor 2210, and transceiver 2220 are connected via a bus 2240, which is represented by a thick line. The connection methods between other components are for illustrative purposes only and are not intended to be limiting. This bus can be an address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used in Figure 22, but this does not indicate that there is only one bus or one type of bus.

[0238] In the embodiments of this application, the processor may be a general-purpose processor, a digital signal processor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0239] Figure 23 is a schematic diagram of another communication device 230 provided in an embodiment of this application. As shown in Figure 23, the communication device includes a logic circuit 2301 and an interface 2302. The processing module 2110 in Figure 21 can be implemented using the logic circuit 2301, and the interface module 2120 in Figure 21 can be implemented using the interface 2302. The logic circuit 2301 can be a chip, processing circuit, integrated circuit, or system-on-chip (SoC) chip, etc., and the interface 2302 can be a communication interface, input / output interface, etc. In this embodiment, the logic circuit and the interface can also be coupled to each other. The specific connection method of the logic circuit and the interface is not limited in this embodiment.

[0240] In some embodiments of this application, the logic circuit and interface can be used to perform the functions or operations performed by the transmitting network device or the receiving network device in the above-described method embodiments.

[0241] This application also provides a computer-readable storage medium storing a computer program or instructions that, when run on a computer, cause the computer to perform the methods of the above embodiments.

[0242] This application also provides a computer program product, which includes instructions or a computer program that, when run on a computer, causes the methods in the above embodiments to be executed.

[0243] This application also provides a communication system, including the aforementioned transmitting end and the aforementioned receiving end.

[0244] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of protection of the above claims.

Claims

1. An encoding method for LDPC codes, characterized in that, include: Obtain the information bit sequence; Based on the parity check matrix, the information bit sequence is encoded using low-density parity check (LDPC) encoding to obtain the encoded bit sequence. The verification matrix is ​​determined by the base matrix, which includes a basic submatrix; the basic submatrix is ​​formed by splicing together at least two basic unit blocks with cycles or translations.

2. A decoding method for LDPC codes, characterized in that, include: Obtain the first log-likelihood ratio (LLR) sequence corresponding to the first received channel sequence; The first LLR sequence is decoded according to the parity check matrix; The verification matrix is ​​determined by the base matrix, which includes a basic submatrix; the basic submatrix is ​​formed by splicing together at least two basic unit blocks with cycles or translations.

3. The method according to claim 1 or 2, characterized in that, The base matrix also includes a portion of the truncated and spliced ​​base submatrix.

4. The method according to any one of claims 1-3, characterized in that, The basic unit block is formed by stacking at least two single-cycle blocks.

5. The method according to any one of claims 1-4, characterized in that, The loop structure of the single loop block is as follows: starting from the second row, the non-zero position of the current row is the position of the non-zero position of the previous row shifted by 1 unit; the non-zero position of the first row is the position of the non-zero position of the last row shifted by 1 unit; different single loop blocks have different non-zero positions and / or the number of non-zero positions in the first row.

6. The method according to any one of claims 1-5, characterized in that, The at least two basic unit blocks include at least two different basic unit blocks.

7. The method according to claim 6, characterized in that, The basic submatrix is ​​formed by superimposing at least two submatrices.

8. The method according to claim 7, characterized in that, The values ​​of the basic submatrix include 0, 1, and 2; the position with a value of 0 represents no shifted element, the position with a value of 1 represents one shifted element, and the position with a value of 2 represents two shifted elements.

9. The method according to claim 8, characterized in that, The at least two submatrices include a first submatrix and a second submatrix; wherein... The first submatrix is ​​formed by splicing together at least two single-sided quasi-cyclic LDPC cell blocks with single-block cycles. The second submatrix is ​​formed by splicing together at least two single-sided quasi-cyclic LDPC cell blocks in a non-mixed or mixed manner.

10. The method according to claim 9, characterized in that, The shift value matrix corresponding to the basic submatrix is ​​formed by combining the first shift value matrix corresponding to the first submatrix and the second shift value matrix corresponding to the second submatrix; The shift value matrix corresponding to each basic unit block in the first shift value matrix satisfies a p-row translation cycle, where p is an integer greater than or equal to 1; The second shift value matrix satisfies a cycle of shifting by W units; The W is related to the total number of columns of the basic submatrix.

11. The method according to any one of claims 8-10, characterized in that, The basis matrix includes multiple basic sub-matrices, and the shift values ​​corresponding to the same positions of the multiple basic sub-matrices are the same or satisfy the arithmetic sequence property.

12. The method according to any one of claims 8-11, characterized in that, The fundamental submatrix is ​​a 4×n matrix; the fundamental submatrix corresponds to the shift value A of the shift value matrix. i (j), A corresponding to the position where the value of the basic submatrix is ​​2. i (j) is related to the total number of columns of the basic submatrix and the column index of the position of 2.

13. The method according to claim 12, characterized in that, The shift value A of the shift value matrix i (j) satisfies the following formula: The i is the column number identifier, ranging from 1 to n; the j is the value of the basic submatrix; The B i (j) is generated by translating a vector h, wherein the value of the vector h satisfies the formula The sequence loops to the left in units of the column number of the fundamental submatrix. Each unit forms the next row.

14. The method according to any one of claims 1-5, characterized in that, The at least two basic unit blocks consist of the same basic unit block composition.

15. The method according to claim 14, characterized in that, The same basic unit block is formed by superimposing two single-sided quasi-cyclic LDPC unit blocks.

16. The method according to claim 15, characterized in that, The values ​​of the basic submatrix include 0, 1, and 2; the position with a value of 0 represents no shifted element, the position with a value of 1 represents one shifted element, and the position with a value of 2 represents two shifted elements.

17. The method according to claim 16, characterized in that, The shift value matrix corresponding to the basic submatrix has cyclic properties.

18. The method according to claim 16, characterized in that, The basic submatrix is ​​a 4×n matrix; the shift values ​​corresponding to the first two rows in the basic submatrix are shifted two positions to become the shift values ​​corresponding to the third and fourth rows in the basic submatrix.

19. The method according to claim 18, characterized in that, The shift value A of the shift value matrix corresponding to the basic submatrix i (j), A corresponding to the position where the value of the basic submatrix is ​​2. i (j) is related to the total number of columns of the basic submatrix and the column index of the position of 2.

20. The method according to claim 19, characterized in that, The shift value A of the shift value matrix i (j) satisfies the following formula: The i is the column number identifier, ranging from 1 to n; the j is the value of the basic submatrix.

21. The method according to claim 19, characterized in that, The shift value A of the shift value matrix i (j) satisfies the following formula: The i is the column number identifier, ranging from 1 to n; the j is the value of the basic submatrix.

22. The method according to claim 19, characterized in that, The shift value A of the shift value matrix i (j) satisfies the following formula: The i is the column number identifier, ranging from 1 to n; the j is the value of the basic submatrix.

23. The method according to claim 19, characterized in that, The shift value A of the shift value matrix i (j) satisfies the following formula: The i is the column number identifier, ranging from 1 to n; the j is the value of the basic submatrix.

24. The method according to claim 19, characterized in that, The shift value A of the shift value matrix i (j) satisfies the following formula: Where t is an odd number When t is even The i is the column number identifier, ranging from 1 to n; the j is the value of the basic submatrix; and the s is any integer.

25. The method according to claim 19, characterized in that, The shift value A of the shift value matrix i (j) satisfies the following formula: The i is the column number identifier, ranging from 1 to n; the j is the value of the basic submatrix.

26. The method according to claim 19, characterized in that, The shift value A of the shift value matrix i (j) satisfies the following formula: The i is the column number identifier, ranging from 1 to n; the j is the value of the basic submatrix.

27. A communication device, characterized in that, Includes modules or units for implementing the method of any one of claims 1 to 26.

28. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, the computer program including program instructions that, when executed, cause the method as described in any one of claims 1 to 26 to be performed.

29. A communication device, characterized in that, The device includes a processor coupled to a memory storing instructions, the processor executing the instructions to cause the communication device to perform the method as described in any one of claims 1 to 26.

30. The communication device according to claim 29, characterized in that, It also includes the memory.

31. The communication device according to claim 29 or 30, characterized in that, It also includes transceivers for receiving and / or transmitting signals.

32. A computer program product, characterized in that, It includes a computer program, the computer program comprising program instructions that, when executed, cause the method as described in any one of claims 1 to 26 to be performed.

33. A communication device, characterized in that, It includes logic circuitry and an interface, the logic circuitry being used to perform the method as described in any one of claims 1 to 26, and the interface being used to receive and / or transmit signals.

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