Tag-non-preserving write operation

Abstract

An apparatus includes memory access type determining circuitry to: determine whether a given write operation specifying a target address is to be a tag-non-preserving write operation; and memory access circuitry to: trigger, in response to determining that the given write operation is to be the tag-non-preserving write operation, a memory system to process the tag-non-preserving write operation specifying the target address, the tag-non-preserving write operation indicating that, following completion of the tag-non-preserving write operation, the memory system is not required to preserve a current value of a memory safety check tag associated with the target address.

Description

[0001] TAG-NON-PRESERVING WRITE OPERATION

[0002] The present technique relates to the field of data processing.

[0003] Software to be executed by a data processing apparatus may typically be written in a high- level programming language and then compiled into code according to the instruction set architecture supported by the apparatus on which the software is to be executed. Some high-level programming languages, such as C and C++, are considered to be memory-unsafe languages because they do not include runtime error detection checks for checking for certain errors relating to memory accesses.

[0004] Hence, a memory safety check may be performed to assist with runtime detection of certain errors relating to memory accesses.

[0005] At least some examples of the present technique provide an apparatus comprising: memory access type determining circuitry to: determine whether a given write operation specifying a target address is to be a tag-non-preserving write operation; and memory access circuitry to: trigger, in response to determining that the given write operation is to be the tag- non-preserving write operation, a memory system to process the tag-non-preserving write operation specifying the target address, the tag-non-preserving write operation indicating that, following completion of the tag-non-preserving write operation, the memory system is not required to preserve a current value of a memory safety check tag associated with the target address.

[0006] At least some examples of the present technique provide a non-transitory computer- readable medium to store computer-readable code for fabrication of the apparatus described above.

[0007] At least some examples of the present technique provide a method comprising: determining, by memory access type determining circuitry, whether a given write operation specifying a target address is to be a tag-non-preserving write operation; and triggering, by memory access circuitry, in response to determining that the given write operation is to be the tag-non-preserving write operation, a memory system to process the tag- non-preserving write operation specifying the target address, the tag-non-preserving write operation indicating that, following completion of the tag-non-preserving write operation, the memory system is not required to preserve a current value of a memory safety check tag associated with the target address. At least some examples provide a computer program for controlling a host data processing apparatus to provide an instruction execution environment for execution of target program code, the computer program comprising: simulated memory access type determining program logic to: determine whether a given write operation specifying a target address is to be a tag-non-preserving write operation; and simulated memory access program logic to: trigger, in response to determining that the given write operation is to be the tag- non-preserving write operation, a simulated memory system to process the tag-non-preserving write operation specifying the target address, the tag-non-preserving write operation indicating that, following completion of the tag-non-preserving write operation, the simulated memory system is not required to preserve a current value of a memory safety check tag associated with the target address.

[0008] Further aspects, features and advantages of the present technique will be apparent from the following description of examples, which is to be read in conjunction with the accompanying drawings, in which:

[0009] Figure 1 illustrates an example of a system having circuitry as described herein;

[0010] Figure 2 illustrates an example apparatus including memory access type determining circuitry and memory access circuitry;

[0011] Figures 3a and 3b illustrates a concept of tag-guarded memory accesses;

[0012] Figure 4 illustrates steps for triggering a memory system to process a tag-non-preserving write operation;

[0013] Figure 5a illustrates using a page table entry of a page table in determining whether to trigger the tag-non-preserving write operation;

[0014] Figure 5b illustrates steps for checking an attribute associated with the page table entry of the page table of figure 5a;

[0015] Figure 6a illustrates using a range of addresses in determining whether to trigger the tag — non-preserving write operation;

[0016] Figure 6b illustrates using an instruction type of an instruction which triggered the given write operation in determining whether to trigger the tag-non-preserving write operation;

[0017] Figure 6c illustrates using a current mode of operation in determining whether to trigger the tag-non-preserving write operation;

[0018] Figure 7 illustrates an example operation according to the present technique when a tag- non-preserving write operation is triggered; and

[0019] Figure 8 illustrates a simulation example. An approach for protecting against memory usage errors as described above may be to provide memory safety check functionality to determine whether to trigger an error handling response in response to a given memory access operation. Memory safety check tags may be used as part of this memory safety check and may be stored in a memory system in association with blocks of one or more memory locations. The memory safety check may rely on values of the memory safety check tags stored in the memory system for performing the memory safety check. Accordingly, typically in an implementation with memory safety check functionality, when a write memory access operation is requested that does not require a memory safety check, values of any memory safety check tags associated with the accessed memory locations may nevertheless be preserved because a subsequent memory access operation may be required that does require a memory safety check and thus relies on the value of the memory safety check tag for the memory location associated with the write memory access operation.

[0020] Further, in some implementations capable of supporting memory safety checking, memory safety checking may be disabled. For example, a processing element may support memory safety checking but software executing thereon may not. In some cases, memory safety checking may be disabled for a given virtual machine or software process executing on the processing element. Further, memory safety checking may be disabled for a specified region in memory, such that memory accesses to memory addresses in the specified region in memory do not result in a memory safety check being performed. In cases such as these, as described above, even though memory safety checking may not be currently enabled, values of memory safety check tags require preserving because a later write operation for which memory safety checking is enabled may rely upon the value of the memory safety check tag and memory safety checking may be enabled at that later point.

[0021] As described above, memory safety check tags may be stored in association with blocks of one or more memory locations, the memory locations themselves storing data. In some cases, the values of memory safety check tags may be preserved by triggering a write operation for only the data stored at the memory locations, i.e. a data only-write, which writes data to the addressed location specified by a target address of a memory access operation and does not modify the value of the memory safety check tag associated with that addressed location. In contrast, for modifying a value of a memory safety check tag, in some implementations a tag-only write may be used that writes data only to the location in memory storing the value of the memory safety check tag (also referred to as a tag setting instruction) independent of the data stored at the memory location associated with the memory safety check tag. Further, when both the data and the memory safety check tag associated with the location where the data is stored are to be modified, in some implementations, a data and tag write operation may write data to both the location in memory storing the data and the location in memory storing the value of the memory safety check tag. As mentioned above, in cases where memory safety checking is not currently enabled, there may still be a requirement that the values of memory safety check tags are preserved. However, for some implementations, when memory safety check functionality is disabled, preserving values of memory safety check tags may require increased processing resources and memory bandwidth.

[0022] For example, in some implementations, it may not be possible to perform data-only write operations, i.e. it may not be possible to write to only the data stored at a memory location without also writing to the portion of memory containing the memory safety check tag associated with the memory location.

[0023] One such example implementation is an ECO (error correction code) memory implementation. In an ECO memory implementation, there may exist spare ECC memory bits in a given line of memory, and these spare ECC memory bits may be used to store the values of memory safety check tags. For example, a memory safety check tag associated with a given line of memory may be stored in the spare bits in that line of memory. However, it is a feature of ECC memory implementations that data-only write operations, i.e. write operations that write to data and not the tags, are not possible. This can be because it is necessary to recalculate the error correction code and write the recalculated error correction code to the ECC bits when a line of memory or a portion of a line of memory is written to. As a result, any allocation tag that was being stored in spare ECC bits may be written over. That is to say, in some ECC memory implementations, it may not be possible to write to the data without also writing to the tags. For example, if a byte of data in a given line of memory is modified, then the associated tag must also be written. In some implementations, only full line writes that write to a full line of memory may be possible. Thus, when performing a write operation in an ECC memory implementation, in order to preserve a current value of a memory safety check tag, the line of memory is first read, then the data portion of the line of memory is modified, and then the line of memory is written back including the unmodified value of the memory safety check tag (i.e. a read-modify-write). Thus, twice the memory bandwidth is required to preserve the value of the memory safety check tag than compared to an implementation able to perform a data-only write.

[0024] Further, for some cache implementations, only write operations to update a full cache entry may be possible. Thus, again, when tags require preserving in such cache implementations, a read-modify-write memory operation may be required, thereby incurring increased processing resources and memory bandwidth.

[0025] Thus, in the examples described below, memory access type determining circuitry is provided to determine whether a given write operation specifying a target address is to be a tag- non-preserving write operation, and memory access circuitry is provided to trigger, in response to determining that the given write operation is to be the tag-non-preserving write operation, a memory system to process the tag-non-preserving write operation specifying the target address, the tag-non-preserving write operation indicating that, following completion of the tag-non- preserving write operation, the memory system is not required to preserve a current value of a memory safety check tag associated with the target address.

[0026] Hence, a tag-non-preserving write operation may be triggered that indicates that the memory system is not required to preserve a current value of a memory safety check tag associated with the target address following completion of the tag-non-preserving write operation. Thus, the memory system may be allowed to determine for itself how to handle processing of the memory safety check tag.

[0027] By supporting this mechanism in an ISA (instruction set architecture) and / or memory system bus protocol, the source of memory system requests (e.g. software) is able to indicate its intent to the memory system hardware as to whether the value of memory safety check tags require preserving or not. Indeed, there exists considerable flexibility for how memory designers may choose to implement a given memory type. As such, being able to indicate, using the tag- non-preserving write operation, whether or not values of memory safety check tags require preserving allows the memory system to determine the most efficient way to process a given write operation, depending on the specific implementation of the memory system. It will be appreciated that the apparatus having the memory access type determining circuitry and the memory access circuitry may not have awareness of the given memory implementation or indeed control over how the memory system may operate, so the specifics of how the memory system chooses to process the tag-non-preserving write operation are not an essential part of the apparatus. However, the present mechanism allows the memory system to determine the optimal manner in which to operate following the tag-non-preserving write operation, which would not be possible in an implementation that does not support the tag-non-preserving write operation and so does not give the memory system any hint over whether the memory safety check tag associated with a target address of a write operation needs to be preserved.

[0028] As a result, in implementations where memory safety check functionality is not enabled or not otherwise currently being used, processing resources and memory bandwidth may be preserved. This is because, as discussed above, it may no longer be necessary to perform two memory accesses to preserve a tag value (as part of a read-modify-write), or incur additional processing at the memory system in order to preserve a value of a tag when the values of tags are not being used in certain implementations.

[0029] In some examples, the memory access type determining circuitry is configured to determine that the given write operation is to be the tag-non-preserving write operation based on tag-non-preserving information indicating that a write operation to the target address is to be a tag-non-preserving write operation. The tag-non-preserving write information may take various forms depending on implementation. In some examples, the tag-non-preserving information is software-configurable. This may allow a software programmer to define whether a given write operation is to be a tag-non-preserving write operation, thereby increasing flexibility and configurability for a given implementation and giving the ability for software to provide a hint to the hardware over whether a given write requires preservation of the memory safety check tag associated with the target address of the write.

[0030] The tag-non-preserving write operation may be triggered in various ways, depending on implementation. It will be appreciated that the different ways in which the tag-non-preserving write operation may be triggered may be variously combined.

[0031] In some examples, the memory access type determining circuitry is configured to: determine that the given write operation is to be the tag-non-preserving write operation based on data structure entry information associated with a data structure accessed from the memory system. For example, the data structure may be a structure providing entries for respective address regions of a given address space (e.g. a virtual, intermediate or physical address space), which describes properties of each address region. Where a data structure is provided to describe properties of regions of memory (which may also indicate properties other than whether writes to the region should be regarded as tag-non-preserving write operations), the data structure can also provide information indicating whether writes to the address region should be regarded as tag-non-preserving write operations, This means it is not necessary to provide any dedicated instruction encodings for defining the tag-non-preserving write operation, preserving instruction encoding space which may be limited in a given ISA.

[0032] In some examples, the memory access type determining circuitry is configured to: determine that the given write operation is to be the tag-non-preserving write operation based on page table entry information associated with a page table entry associated with the target address. Accordingly, in some cases, a page table entry may be used to designate a given address in memory as not requiring values of tags to be preserved when a write operation specifies that address. This may provide an efficient indication of whether a tag-non-preserving write operation is to be used. In some examples, as access to the page table entry is already required in order to perform translation of the target address, using page table entry information associated with the page table may provide a particularly efficient mechanism for determining whether to trigger a tag-non-preserving write operation. Furthermore, in some examples, information from the page table entry may be cached in a translation lookaside buffer (TLB) and so determining whether to trigger a tag-non-preserving write operation may be performed more rapidly than in an example where the information to determine whether to trigger the tag-nonpreserving write operation is not stored in a TLB. Hence, while the tag-non-preserving write operation may be identified based on page table entry information associated with a page table entry associated with the target address, this does not necessarily require the page table entry itself to be accessed each time a tag-non-preserving write operation is executed, as sometimes the tag-non-preserving write operation may be identified based on information previously obtained from the page table entry information that is cached in the TLB.

[0033] The page table entry information may comprise one or more attributes associated with the page table entry that indicates that write operations to the target address associated with the page table entry are to be tag-non-preserving write operations. That is to say, in some examples an attribute may be stored in a page table entry and used to identify tag-non-preserving write operations for a given target address. In some examples, the one or more attributes are referenced in one or more registers specified by the page table entry. Thus, rather than being specified directly in the page table entry, the one or more attributes associated with the page table entry may be stored in one or more registers and referenced by the page table.

[0034] The one or more attributes may have an encoding capable of specifying: a first encoding indicating that write operations to the target address do not require a memory safety tag check but should cause the memory system to preserve a current value of the memory safety check tag associated with the target address; and a second encoding indicating that write operations to the target address are to be the tag-non-preserving operation that does not require the memory safety tag check and for which the memory system is not required to preserve the current value of a memory safety check tag associated with the target address.

[0035] Thus, when a memory safety check is not required for a target address of a given write operation, the encoding of the one or more attributes distinguishes between the case where memory safety check tag values require preserving, and the case where they do not require preserving. Accordingly, the one or more attributes may indicate how the memory system is to operate following completion of the tag-non-preserving write operation in an efficient manner. As described above, by providing a mechanism in the ISA for software to indicate to hardware whether or not memory safety check tags require preserving, the memory system is able to determine the more performant manner in which to operate following completion of the tag-nonpreserving write operation. Accordingly, in some implementations, the memory system is no longer required to perform a read-modify-write and thus flexibility in the response of the memory system may be increased.

[0036] In some examples, the memory access type determining circuitry is configured to: determine that the given write operation is to be the tag-non-preserving write operation based on range information specifying a range of addresses for which write operations to addresses in the range are to be tag-non-preserving write operations. Hence, whether the target address specified in a given write operation is within a defined range of addresses designated as triggering tag-nonpreserving write operations may be used to trigger a tag-non-preserving write operation. The range information may comprise information indicating one or more of a start address for the range, an end address for the range, or a size of the range. Further, the range information may be specified in one or more system or control registers. As a result, one or more registers may be checked to efficiently determine the range of addresses for which a write request to a target address corresponding to an address in the range triggers a tag-non-preserving write operation. The range information can be configurable by software so that software can influence which range of addresses should have write operations treated as tag-non-preserving write operations. In some examples, the range information may support defining two or more non-contiguous ranges as ranges of addresses for which write operations to addresses in each such range are to be tag- non-preserving write operations.

[0037] In some examples, the memory access type determining circuitry is configured to: determine that the given write operation is to be the tag-non-preserving write operation based on mode information that indicates that a current mode of operation requires that write operations to the target address are to be tag-non-preserving write operations. Hence, when operating in a tagpreserving mode, tag-non-preserving write operations may not be triggered (instead a tagpreserving write operation may be triggered which requires the memory system to preserve any memory safety check tag associated with the target address). However, when operating in a tag- non-preserving mode, tag-non-preserving write operations may be triggered. Thus, tag-nonpreserving operations may be selectively enabled depending on a current mode of operation. The mode information may be stored in one or more system or control registers, and as such a rapid determination as to whether to trigger a tag-non-preserving write operation may be possible. The mode information may be configurable by software, e.g. by executing a mode switching instruction or a system register updating instruction.

[0038] In some examples, the memory access type determining circuitry is configured to: determine that the given write operation is to be the tag-non-preserving write operation based on an instruction type of an instruction which triggered the given write operation. Thus, in this example, the instruction type which triggers the write operation may indicate that the write operation is to be a tag-non-preserving write operation. A new instruction type specific for triggering tag-non-preserving write operations may be defined and used to trigger tag-nonpreserving write operations (distinct from an instruction type for triggering tag-preserving write operations which require the memory system to preserve the value of any memory safety check tag associated with the target address). This may provide an efficient way to trigger tag-nonpreserving write operations. The memory access type determining circuitry may be configured to: determine that the given write operation is to be the tag-non-preserving write operation based on an opcode of the instruction which triggered the given write operation.

[0039] That is to say, a new type of instruction (a write operation) may be supported in the ISA that indicates to the memory system that, following completion, the memory system is not required to preserve a current value of a memory safety check tag associated with the target address. As discussed above, this provides a mechanism by which processing resources and memory bandwidth may be reduced when memory safety checking is not currently enabled in some implementations.

[0040] In some examples, the memory access circuitry is configured to: provide an indication to the memory system, based on triggering the tag-non-preserving write operation, that the memory safety check tag associated with the target address does not require preserving. The indication may comprise a field of a request signal that indicates that the memory safety check tag associated with the target address does not need preserving. How the memory system may then operate in response to the indication is not particularly limited. It will be appreciated that the apparatus having the memory access circuitry may not have awareness of the given memory implementation or indeed control over how the memory system may operate. Instead, the indication allows the memory system to determine the preferred manner in which to operate following the tag-non-preserving write operation.

[0041] In some examples, memory system circuitry is provided to select, based on the indication, whether to preserve the current value of the memory safety check tag associated with the target address. In some examples, memory system circuitry may be provided to: select, based on the indication, between a read-modify-write operation and a write operation performed for a storage location corresponding to the target address. Hence, in an example ECC memory implementation or other implementation where memory safety check tags are stored alongside data items and modification of only the data item while preserving the memory safety check tag would require a read-modify-write operation, the memory system may select a write operation based on the indication indicating that the memory safety check tag does not require preserving. In some examples, memory system circuitry may be provided to: select, based on the indication, between a read-modify-write operation and a full-line write operation performed for a storage location corresponding to the target address. However, it will be appreciated that in some implementations, the apparatus does not itself comprise memory system circuitry and instead is configured to communicate with a memory system external from the apparatus.

[0042] In some examples, tag checking circuitry is provided to perform a tag check in response to a tag-checked memory access instruction specifying an address operand for defining a target address of a memory access operation, the tag check comprising triggering an error handling response in response to detection of a tag mismatch between the memory safety check tag obtained from the memory system for the target address and an address tag associated with the address operand. As referred to herein, tag checking corresponds to memory safety checking and a tag check corresponds to a memory safety tag check. Thus, the apparatus may itself have memory safety checking functionality. However, it will be appreciated that in some implementations, the apparatus may not have this functionality itself. For example, the component that does the tag check using the memory safety check tag may be external to the component that determines whether a given write operation should be a tag-non-preserving write operation. Also, some sources of write requests sent to the memory system (such as a system memory management unit (SMMU) described below) may not themselves have tag checking circuitry but may nevertheless be able to specify whether a write request is a tag-non-preserving write operation to enable the memory system (shared with another processor that does have tag checking circuitry) to determine whether it is necessary to preserve stored memory safety check tags associated with the target address of the write request sent by the SMMU. Hence, even if the source of the write request does not itself support tag checking using the memory safety check tag, it can still be useful to provide support for designating particular write operations as being a tag-non-preserving write operation.

[0043] Specific examples will now be described with reference to the drawings.

[0044] Figure 1 schematically illustrates an example of an apparatus (e.g. a data processing system, integrated circuit or system on chip) 2 having at least one processor 4. In this example the processor is a CPU (Central Processing Unit), but other examples of processors include a GPU (Graphics Processing Unit) or NPU (Neural Processing Unit - a type of processor with specialized hardware for accelerating vector and / or matrix operations or other operations used in Neural Network and other machine learning processing). The processor 4 has an instruction decoder 6 for decoding program instructions and processing circuitry 8 which is controlled to perform processing operations in response to the instructions decoded by the instruction decoder 6. The processor 4 has a cache 10 for caching data from memory for faster access by the processor and has a memory management unit (MMU) 12 which functions as address translation circuitry for translating virtual addresses specified by instructions executed by the processor 4 into physical addresses identifying locations within the memory system. The MMU may have at least one TLB 14 for storing translation entries which depend on page table data from page table structures stored in the memory system. The page table structures define the address mappings between virtual and physical addresses and may also define memory access permissions which may define whether certain software processes executing on the processor 4 are allowed to access certain addresses. The MMU 12 may support 2-stage address translation where the mapping of a virtual address to a physical address depends on both stage 1 address translation data which maps the virtual address (VA) to an intermediate physical address (IPA) and stage 2 translation data which maps the IPA to a physical address (PA). The stage 1 address translation data may be set by an operating system or virtual machine. The stage 2 translation data may be set by a hypervisor.

[0045] The processor 4 is an example of a requester device which is capable of executing program instructions. While Figure 1 only shows one such requester device, it will be appreciated that system 2 could have two or more such devices, which may include further CPUs or could include other types of instruction execution devices such as a graphics processing unit (GPU).

[0046] In addition to the processor 4 or other devices capable of instruction execution which have their own internal MMU 12, the system may also include requester devices 20 which may not have an internal MMU, and so for accessing memory and providing address translation functionality, such devices may communicate with the rest of the system via a system memory management unit (SMMU) 22 which includes address translation circuitry which controls address translation and memory permissions based on translation data defined in page table structures in memory. Again, the SMMU 22 may have one or more TLBs 24 which have a similar functionality to the TLBs 14 within the MMU 12 of the processor 4. The devices 20 which access memory via the SMMU 22 can include cached devices which include an internal cache 26 and uncached devices which do not have any cache. For example, a device 20 could include a display controller for controlling display of image frames on display, a network controller for controlling input or output of data via a network, a hardware accelerator for performing certain dedicated processing functions in a more efficient manner than can be achieved using software executing on a generic processor such as the processor 4, and so on.

[0047] All of the requester devices 4, 20 communicate with each other via an interconnect 30 which is responsible for routing transactions between the requester devices and memory 32. Interconnect 30 may also be responsible for managing coherency between data cached in respective caches 10, 26 of the system. It will be appreciated that Figure 1 is a simplified diagram and the system 2 may have many other components not shown in Figure 1 for conciseness.

[0048] As shown in figure 1 , requester devices 4 and 20 and memory system 32 may have memory access type determining circuitry 34 and memory access circuitry 36. Thus, each of processor 4, SMMU 22, and memory system 32 may comprise circuitry configured to perform the present techniques. Alternatively, in some examples only a subset of the processor 4, SMMU 22 and memory system 32 may comprise the memory access type determining circuitry 34 and memory access circuitry 36 that supports the tag-non-preserving write operation, so it is not essential for all components to support the tag-non-preserving write operation. Processor 4 may additionally comprise tag checking circuitry 38 in some implementations. Further, memory system 32 may have memory system circuitry 40.

[0049] Figure 2 illustrates an example apparatus 42 that may implement the present techniques. As described, apparatus 42 may be the processor 4, SMMU 22, or memory system 32 of figure 1 , or another requester device not shown in figure 1 . Apparatus / data processing apparatus 42 includes memory access type determining circuitry 34. Memory access type determining circuitry 34 determines whether a given write operation specifying a target address is to be a tag-nonpreserving write operation. Apparatus 42 also includes memory access circuitry 36. Memory access circuitry 36 triggers, in response to determining that the given write operation is to be the tag-non-preserving write operation, a memory system to process the tag-non-preserving write operation specifying the target address, the tag-non-preserving write operation indicating that, following completion of the tag-non-preserving write operation, the memory system is not required to preserve a current value of a memory safety check tag associated with the target address. Memory access circuitry 36 may trigger the tag-non-preserving write operation in various ways as described herein.

[0050] Memory safety check functionality (for example memory tagging and tag checking) will now be described in more detail with reference to figure 3a. As described herein, an example of memory safety check functionality is the Memory Tagging Extension provided by Arm® Ltd of Cambridge, UK, but it will be appreciated that the techniques described herein could also be applied to other memory safety check functionality that uses memory safety check tags. When a tag-guarded memory access operation (i.e. a memory access for which a memory safety check / tag check is to be performed) is requested that specifies an address operand for defining a target address identifying a particular addressed location in the memory system, tag checking circuitry may compare an address tag that is associated with the address operand with a memory safety check tag (also known as an allocation tag) that is stored in the memory system in association with a block of one or more memory locations which includes the addressed location identified by the address operand (a tag-check). The tag checking circuitry may generate an indication of whether a match is detected between the memory safety check tag and the address tag. This indication can be used to control whether the memory access is allowed to succeed or whether subsequent operations can succeed, or could merely be reported while allowing memory accesses to continue as normal.

[0051] This can be useful as, for example, a compiler compiling code based on a memory-unsafe language such as C or C++ can, when initialising regions of memory, set the memory safety check tags for blocks of memory which the code is expected to access to particular values, and may associate the corresponding address tag values with the target addresses pointing to those blocks. If a memory usage error occurs, and for example, the address pointer is used out of scope or extends out of bounds of the valid range which was initialised, then it may be likely that the memory safety check tag associated with the addressed location may not match the address tag associated with the address operand, and then in this case the indication of whether a match is detected can be used to trigger some error handling response or error reporting mechanism. The particular response taken can depend on the needs of the software being executed or on the particular micro-architectural implementation of the architecture. Hence, even if the high level language does not have means for performing run time error checks in order to guard against memory access errors, the ISA used for the compiled code may include architectural features for performing such checks.

[0052] Figure 3a shows an example tag check technique. As shown in figure 3a, an address space used to refer to memory locations within the memory system may be logically partitioned into a number of blocks 44 each comprising a certain number of addressable locations. Each block 44 is associated with a corresponding allocation tag (also referred to herein as a memory safety check tag) 46. The allocation tags associated with a certain number of blocks 44 can be gathered together and stored either within a different architecturally accessible memory location within the physical address space, or within additional storage locations provided in main memory which are not architecturally accessible (not mapped in the physical address space). In some examples, as described below in reference to figure 3b, a given storage location (line) of a memory storage unit or a cache may store data (i.e. not tags) and also store the allocation tag associated with the line of memory and used for the tag check for memory accesses to that line of memory. The particular way in which the location storing the allocation tag 46 is associated with the location storing the corresponding data may vary significantly from implementation to implementation.

[0053] Hence, when a tag-guarded memory access (i.e. a memory access for which a memory safety check is enabled) is required, an address tag 48 is compared against the allocation tag 46 which is associated with the block of memory locations 44 which includes the addressed location 52 indicated by the target address 50. For example, in Figure 3a the target physical address 50 points to a certain location B1 in memory, marked 52 in the address space of Figure 3a. Therefore, the allocation tag B which is associated with the block of locations B including location B1 is compared against the address tag 48 associated with the target physical address 50.

[0054] Hence, when a memory access is performed, tag checking circuitry may compare the address tag 48 associated with the address operand used to compute the target address 50 and the allocation tag 46 (obtained from the memory system) that is associated with a block 44 including the addressed location 52 identified based on the target physical address 50, and determine whether they match. The tag checking circuitry 38 generates a match indication indicating whether the address tag 48 and the allocation tag 46 matched. For example, this match indication could be a fault signal which is generated if there is a mismatch between the address tag 48 and the allocation tag 46, or an indication placed in a status register indicating whether there was a match, or an entry added to an error report to indicate the address for which the error was detected and / or the instruction address of the instruction which triggered the error.

[0055] As shown in the example of Figure 3a, in some examples the address tag 48 may be obtained from a portion of upper bits of the address operand used to compute the target address 50. This exploits the fact that in a 64-bit architecture, there is typically not yet any need for using the full 64-bit address space to provide 264distinct addressable locations in memory, so some upper bits of the address operand may be unused and valid addresses may be limited to addresses representable using fewer than 64 bits. Therefore, some unused bits can be used to denote the address tag 48 which is assigned to an address operand when memory regions are allocated, and compared with the allocation tag 46 for an accessed memory location, so that memory usage errors, such as where an address operand is used to access a memory region not intended to be accessed using that address operand, can be detected.

[0056] An example ECC memory implementation will now be described with reference to Figure 3b. Figure 3b shows the addressed memory location 52 of figure 3a. In this example, addressed memory location 52 corresponds to a line of memory in the ECC memory system. As such, the allocation tag 46 of figure 3a may be stored in spare ECC bits associated with the line of memory 52 (e.g. error correction functionality may not always be in use, so where the error correction functionality is not required the storage capacity provided for storing error correction codes can be reused to store allocation tags. Alternatively, even when error correction functionality is in use, there may be spare bits that can be used to store allocation tags). Thus, the line of memory 52 includes data 54 stored at the addressed memory location, as well as the allocation tag value 46 associated with that addressed memory location and used in the tag check for memory accesses with a target address corresponding to that addressed location.

[0057] As described herein, in ECC memory implementations, only write operations to full lines of memory may be possible (i.e. also including the ECC bits, since normally when the error correction functionality is supported, it would not make sense to update the data item without updating the corresponding error correction code that depends on the stored data item). The hardware providing write access to the memory line may be restricted to updating a whole line and may not support the ability to specify, for a given write operation, a subset of bits that are to be updated. Accordingly, in this implementation, when a write operation specifying the target address corresponding to addressed location 52 is received, and when a current value of the allocation tag B is to be preserved, the memory line 52 is read (i.e. to temporarily store the value of the allocation tag B), the data portion is modified at a location (e.g. a buffer structure) separate from the memory storage, and the line of memory is written using the modified data portion and the read out value of the allocation tag B. In other words, a read-modify-write operation is performed to preserve the current value of the allocation tag B. This requires twice the memory bandwidth compared to a single write operation (since a read followed by a write is required).

[0058] However, with the present technique, if memory safety check functionality is not currently enabled, a tag-non-preserving write operation may instead be triggered. The tag-non-preserving write operation indicates to the memory system that a current value of the allocation tag B is not required to be preserved. This allows the memory system to process the write operation without requiring the preservation of the value of the allocation tag B. For example, the memory system may overwrite the allocation tag B to a given value (for example any value, such as zeros, or ones, or any other arbitrary value). By not requiring the preservation of the allocation tag B value, the read-modify-write operation associated with preserving the value of the allocation tag B can be avoided (for example by instead using a single write operation).

[0059] Figure 4 illustrates steps for triggering a memory system to process the tag-nonpreserving write operation.

[0060] At step 401 , it is determined whether a write operation specifying a target address is to be a tag-non-preserving write operation. As discussed herein, this determination may be made in various ways depending on implementation. For example, this determination may be based on tag-non-preserving information indicating that a write operation to the target address is to be a tag-non-preserving write operation. This information may be software configurable and so a programmer may be able to define the information. For example, the tag-non-preserving information could be any of: an instruction type executed to trigger the write operation; a mode indicating value stored in a control register; range information defining a range of addresses for which write operations should be considered to be tag-non-preserving write operations; information stored in an entry of data structure (stored in the memory system) that corresponds to the target address (e.g. the data structure could be a page table structure). In some examples, the determination is based on data structure entry information associated with a data structure accessed from the memory system. Thus, a data structure providing entries associated with specific address regions may be used to store information that defines whether a given write operation specifying a target address is to be a tag-non-preserving write operation. Other examples for how this determination may be performed are described with reference to figures 5 and 6.

[0061] If it is determined at step 401 that the write operation is to be a tag-non-preserving write operation, the process continues to step 402. At step 402, a memory system is triggered to process the tag-non-preserving write operation. The tag-non-preserving write operation indicates that, following completion of the tag-non-preserving write operation, the memory system is not required to preserve a current value of a memory safety check tag associated with the target address.

[0062] Alternatively, if it is determined at step 401 that the write operation is not to be a tag-nonpreserving write operation, the process continues to step 403. At step 403, the memory system is triggered to process the write operation (i.e. as a tag-preserving write operation which indicates to the memory system that it is required to preserve the value of allocation tags).

[0063] Although the tag-non-preserving write operation at step 402 indicates that the memory safety check tag is not required to be preserved, the memory system may have flexibility in whether or not to actually preserve the memory safety check tag in response to receiving the indication of the tag-non-preserving write operation. That is, some implementations of the memory system may nevertheless choose to implement a read-modify-write operation to preserve the memory safety check tag, even if a tag-non-preserving write operation is instructed by the CPU 4 or SMMU 22. Hence, some implementations of the memory system 32 may not distinguish processing of tag-non-preserving write operations from processing of tag-preserving write operations. The support for the tag-non-preserving write operation at the CPU 4 and SMMU 22 is helpful to allow those components to be used in conjunction with a memory system component that does have memory system circuitry 40 which responds differently to tag-non-preserving write operations and tag-preserving write operations respectively, but there is no guarantee that when the CPU 4 or SMMU 22 is implemented in a processing system, the system designer chooses to couple those components with a memory system component that has awareness of tag-nonpreserving write operations (e.g. legacy memory system components may continue to treat tag- non-preserving write operations as tag-preserving write operations which preserve the stored memory safety check tag). Nevertheless, by supporting tag-non-preserving write operations at a CPU 4 or SMMU 22, this provides an improved processing platform because the hint provided to the memory system for tag-non-preserving write operations enables the CPU 4 and SMMU 22 to be integrated into a system which does comprise a memory system component supporting tag- non-preserving write operations (which would enable improved performance by eliminating the read operation from the read-modify-write sequence when the tags do not need to be preserved), which would not be possible if the CPU 4 and SMMU 22 did not provide any support the tag-nonpreserving write operations at an architectural level.

[0064] Further examples of how the memory access type determining circuitry may determine whether a given write operation specifying a target address is to be a tag-non-preserving write operation will now be described.

[0065] Figure 5a shows an example using a page table entry of a page table in determining whether to trigger the tag-non-preserving write operation based on using a page table.

[0066] Page table 56 may store one or more page table entries, including page table entry 58. Page table entry 58 may include page table entry information 60 indicating an attribute or reference to a register referencing the attribute.

[0067] Page table entry 58 of page table 56 may be associated with a target address specified in a requested write operation. Thus, when a write operation specifying the target address is requested, the page table entry 58 and the page table entry information 60 associated with the page table entry 58 may be used to determine whether the write request to the target address is to be a tag-non-preserving write request. For example, the page table entry information 60 may include an attribute (or combination of two or more attribute values) that indicates whether write operations to the target address associated with the page table entry 58 are to be tag-nonpreserving write operations. Additionally, or alternatively, page table entry information 60 may include a reference to a register which comprises one or more attributes used to identify whether write operations to the target address associated with the page table entry should be considered tag-non-preserving write operations.

[0068] It will be appreciated that page table 58 may in some examples represent part of a multilevel page table structure traversed in a multi-level page table walk. The page table could be a stage-1 page table or a stage-2 page table in a translation regime involving multiple stages of address translation (stage 1 translating from virtual address space to an intermediate address space under control of page tables set by an operating system, and stage 2 translating from the intermediate address space to a physical address space under control of page tables set by a hypervisor). Page table 58 may be stored in a memory system, but information derived from page tables may also be cached in a translation lookaside buffer (TLB). Hence, it is not essential that the page table entry itself is actually accessed at the time of checking at step 401 whether a write operation specifying a target address is a tag-non-preserving write operation. In some examples, this could be determined based on information cached in the TLB that was derived from a previous access to the page table entry stored in the memory system.

[0069] The attribute information 60 may have different encodings depending on whether the memory system is required to preserve the current value of a memory safety check tag associated with the target address. For example, the attribute information may have a first encoding for indicating that write operations to the target address are tag-preserving write operations which do not require a memory safety tag check but should cause the memory system to preserve a current value of the memory safety check tag associated with the target address. The attribute information may have a second encoding for indicating that write operations to the target address are to be the tag-non-preserving operation that does not require the memory safety tag check and for which the memory system is not required to preserve the current value of a memory safety check tag associated with the target address. This is described in further detail with reference to figure 5b.

[0070] Figure 5b shows example steps for determining whether a tag check is required and whether allocation tags (i.e. memory safety check tags) are to be preserved, based on attribute information (e.g. a single attribute value or a combination of multiple attribute values) associated with a page table entry associated with a target address of a write operation.

[0071] As shown in figure 5b, at step 501 , the attribute information is checked. The attribute information may take a number of encodings that indicate whether a tag-check is required for a given write operation (tagged), and if a tag-check is not required for a given write operation (untagged), whether the allocation tags require preserving (preserving) or do not require preserving (non-preserving).

[0072] At step 502, it is determined whether the attribute indicates that a tag-check is required for a given write operation (i.e. does the attribute value indicate ‘tagged’?). At step 503, it is determined that the write operation requires a tag-check and that allocation tags require preserving. A memory system may subsequently process the write operation accordingly.

[0073] At step 504, it is determined whether the attribute indicates that a tag -check is not required for the given write operation and that the allocation tag for the accessed address requires preserving (i.e. untagged and preserving). At step 505, it is determined that the write operation does not require a tag-check and that the allocation tag requires preserving. A request is sent to the memory system requesting that a tag-preserving write operation is performed to update the data item associated with the target address while preserving the stored allocation tag stored in the memory system for that data item. A memory system may subsequently process the write operation accordingly.

[0074] At step 506, it is determined whether the attribute indicates that a tag -check is not required for a given write operation and that allocation tags do not require preserving. At step 507, it is determined that the write operation does not require a tag-check and that allocation tags do not require preserving. The tag-non-preserving write operation may thus be triggered. The tag-nonpreserving write operation requests that the memory system updates the data item associated with the target address, but is not required to preserve the stored allocation tag stored in the memory system for that data item (although optionally the memory system could choose to preserve the stored allocation tag if it wishes). A memory system may process the tag-non- preserving write operation accordingly as described herein.

[0075] It will be appreciated that tag-non-preserving write operations may not be triggered for write requests that require a tag-check, or that require that allocation tags be preserved. Figure 6a shows an example of how to determine whether to trigger a tag-non-preserving write operation using a range of addresses. As shown, a range of addresses 62 may define a range of addresses, which when a target address specified in a write operation corresponds to an address within the defined range, causes the write operation to be triggered as a tag-nonpreserving write operation. The range of addresses 62 may be defined using one or more registers 64 that specify a start address, and an end address or a size for the range. Thus, when a write operation is requested, the target address specified in the write request may be compared against the range of addresses 62 to determine whether the target address corresponds to an address included in the range of addresses 62. If the target address does correspond to an address included in the range of addresses 62, then the write operation specifying that target address may be triggered as a tag-non-preserving write operation. Otherwise, if the target address does not correspond to an address included in the range of addresses 62, the write operation specifying that target address may be triggered as a tag-preserving write operation (indicating that values of tags require preserving).

[0076] Figure 6b shows an example of how to determine whether to trigger a tag-non-preserving write operation using an instruction type of an instruction which triggered the write operation. In this example, a specific instruction type is used to trigger a tag-non-preserving write operation. For example, a normal write operation (i.e. a write operation that triggers a tag-preserving write operation that indicates that, following completion of the tag-non-preserving write operation, the memory system is required to preserve a current value of a memory safety check tag associated with the target address) may correspond to a store operation (STR). In contrast, a tag-nonpreserving write operation may correspond to a tag-non-preserving store operation (STRNP). A tag-non-preserving write operation may thus be triggered when a given write operation is a tag- non-preserving write operation.

[0077] In some examples, whether a write operation to data at the target address of the write operation is accepted or rejected may be independent of the determination of whether the write operation is the type of write operation that triggers a tag-non-preserving write operation (i.e. whether the write operation is the new type of write operation). Hence, the difference between the tag-preserving write operation and the tag-non-preserving write operation may merely be a hint to the memory system on whether or not it is required to preserve a stored allocation tag value for the target address of the write operation, but may not affect whether or not the write operation succeeds or fails.

[0078] Figure 6c shows an example of how to determine whether to trigger a tag-non-preserving write operation using a current mode of operation. In this example, a current mode of operation may be used to determine whether to trigger a tag-non-preserving write operation. Register 66 may store information indicating a current mode of operation. For example, the current mode of operation may be a mode of operation that requires that allocation tags be preserved, or a mode of operation that does not require that allocation tags be preserved. Based on the current mode of operation, it can be determined whether to trigger a tag-non-preserving write operation or not. The current mode of operation may be software-configurable, and so when software executing on a processor does not require that tags be preserved, the current mode of operation may be set accordingly.

[0079] If the current mode of operation indicates that allocation tags are to be preserved, a given write operation may trigger a write operation (i.e. not a tag-non-preserving write operation). A memory system may thus process the write operation and preserve any allocation tags. However, if a current mode of operation indicates that allocation tags do not require preserving, a given write operation may trigger a tag-non-preserving write operation. The memory system may thus process the tag-non-preserving write operation and, following completion, not preserve a current value of the allocation tag.

[0080] Figure 7 shows an example requester / completer arrangement when a tag-non-preserving write operation is triggered.

[0081] As shown in figure 7, a requester 68 includes memory access type determining circuitry 34 and memory access circuitry 36. Requester 68 may correspond to the processor 4, SMMU 22, or memory system 32 of figure 1 or a requester not shown in figure 1 . Memory access type determining circuitry 34 and memory access circuitry 36 may correspond to the respective circuitries of figures 1 and / or 2.

[0082] When a tag-non-preserving write operation is triggered, requester 68 provides an indication to a completer (i.e. memory system) 70 that the memory safety check tag associated with a target address specified in the write operation that triggered the tag -non-preserving write operation does not require preserving. The completer 70 may thus complete the tag-nonpreserving write operation, and following completion, may not be required to preserve a current value of a memory safety check tag / allocation tag associated with the target address.

[0083] Completer 70 may include memory system circuitry 40 (which may correspond to the memory system circuitry 40 of figure 1 ). Memory system circuitry 40 may select, based on the indication from the requester 68, whether to preserve the current value of the memory safety check tag associated with the target address. In some examples, the memory system circuitry 40 may select, based on the indication from the requester 68, between a read-modify-write operation and a write operation performed for a storage location corresponding to the target address. In some examples, the memory system circuitry 40 may select a full-line write operation.

[0084] How the completer 70 operates following the completion of the tag-non-preserving write operation is not particularly limited. In some implementations, the completer 70 may allow the value of the memory safety check tag / allocation tag to become unknown, for example by setting the value to any value, such as all zeroes, all ones, or any other value. In some implementations, the completer 70 may nevertheless preserve the current value of the tag, even though the tag- non-preserving operation indicates that preserving a current value of the tag is not required. The completer 70 may determine how to operate following completion of the tag-non-preserving write operation based on performance considerations. For example, if the completer 70 determines that it would be more performant to set the value of the tag to all zeroes, the completer 70 may act in this way.

[0085] Figure 7 also shows an example memory line T before and after a tag-non-preserving write operation is triggered. As discussed above, before a tag-non-preserving write operation is triggered, memory line T may comprise data and the associated allocation tag (i.e. data indicative of the value of the allocation tag). After a tag-non-preserving write operation has been triggered that specifies a target address corresponding to memory line T, the value of the tag may be allowed to be become ‘unknown’, for example by writing any value (such as ones or zeroes) to the bits of the memory line T where the allocation tag value data is stored. The value written is not particularly limited and will depend on implementation. For example, from the point of view of the software being executed, the value may be unknown, and the value inserted by the hardware (such as the completer 70) may be any value (e.g. all zeros, all ones, or any other value) and this may not be architecturally defined. Alternatively, the value of the tag may nevertheless be preserved. It will be appreciated that the data portion of the memory line T before and after the tag-non-preserving operation may well have been modified.

[0086] Concepts described herein may be embodied in computer-readable code for fabrication of an apparatus that embodies the described concepts. For example, the computer-readable code can be used at one or more stages of a semiconductor design and fabrication process, including an electronic design automation (EDA) stage, to fabricate an integrated circuit comprising the apparatus embodying the concepts. The above computer-readable code may additionally or alternatively enable the definition, modelling, simulation, verification and / or testing of an apparatus embodying the concepts described herein.

[0087] For example, the computer-readable code for fabrication of an apparatus embodying the concepts described herein can be embodied in code defining a hardware description language (HDL) representation of the concepts. For example, the code may define a register-transfer-level (RTL) abstraction of one or more logic circuits for defining an apparatus embodying the concepts. The code may define a HDL representation of the one or more logic circuits embodying the apparatus in Verilog, SystemVerilog, Chisel, or VHDL (Very High-Speed Integrated Circuit Hardware Description Language) as well as intermediate representations such as FIRRTL. Computer-readable code may provide definitions embodying the concept using system-level modelling languages such as SystemC and SystemVerilog or other behavioural representations of the concepts that can be interpreted by a computer to enable simulation, functional and / or formal verification, and testing of the concepts.

[0088] Additionally or alternatively, the computer-readable code may define a low-level description of integrated circuit components that embody concepts described herein, such as one or more netlists or integrated circuit layout definitions, including representations such as GDSIL The one or more netlists or other computer-readable representation of integrated circuit components may be generated by applying one or more logic synthesis processes to an RTL representation to generate definitions for use in fabrication of an apparatus embodying the invention. Alternatively or additionally, the one or more logic synthesis processes can generate from the computer-readable code a bitstream to be loaded into a field programmable gate array (FPGA) to configure the FPGA to embody the described concepts. The FPGA may be deployed for the purposes of verification and test of the concepts prior to fabrication in an integrated circuit or the FPGA may be deployed in a product directly.

[0089] The computer-readable code may comprise a mix of code representations for fabrication of an apparatus, for example including a mix of one or more of an RTL representation, a netlist representation, or another computer-readable definition to be used in a semiconductor design and fabrication process to fabricate an apparatus embodying the invention. Alternatively or additionally, the concept may be defined in a combination of a computer-readable definition to be used in a semiconductor design and fabrication process to fabricate an apparatus and computer- readable code defining instructions which are to be executed by the defined apparatus once fabricated.

[0090] Such computer-readable code can be disposed in any known transitory computer- readable medium (such as wired or wireless transmission of code over a network) or non- transitory computer-readable medium such as semiconductor, magnetic disk, or optical disc. An integrated circuit fabricated using the computer-readable code may comprise components such as one or more of a central processing unit, graphics processing unit, neural processing unit, digital signal processor or other components that individually or collectively embody the concept.

[0091] Figure 8 illustrates a simulator implementation that may be used. Whilst the earlier described embodiments implement the present invention in terms of apparatus and methods for operating specific processing hardware supporting the techniques concerned, it is also possible to provide an instruction execution environment in accordance with the embodiments described herein which is implemented through the use of a computer program. Such computer programs are often referred to as simulators, insofar as they provide a software based implementation of a hardware architecture. Varieties of simulator computer programs include emulators, virtual machines, models, and binary translators, including dynamic binary translators. Typically, a simulator implementation may run on host hardware 730 such as a host processor, optionally running a host operating system 720, supporting the simulator program 710. In some arrangements, there may be multiple layers of simulation between the hardware and the provided instruction execution environment, and / or multiple distinct instruction execution environments provided on the same host processor. Historically, powerful processors have been required to provide simulator implementations which execute at a reasonable speed, but such an approach may be justified in certain circumstances, such as when there is a desire to run code native to another processor for compatibility or re-use reasons. For example, the simulator implementation may provide an instruction execution environment with additional functionality which is not supported by the host processor hardware, or provide an instruction execution environment typically associated with a different hardware architecture. An overview of simulation is given in “Some Efficient Architecture Simulation Techniques”, Robert Bedichek, Winter 1990 USENIX Conference, Pages 53 - 63.

[0092] To the extent that embodiments have previously been described with reference to particular hardware constructs or features, in a simulated embodiment, equivalent functionality may be provided by suitable software constructs or features. For example, particular circuitry may be implemented in a simulated embodiment as computer program logic. Similarly, memory hardware, such as a register or cache, may be implemented in a simulated embodiment as a software data structure. In arrangements where one or more of the hardware elements referenced in the previously described embodiments are present on the host hardware (for example, host processor 730), some simulated embodiments may make use of the host hardware, where suitable.

[0093] The simulator program 710 may be stored on a computer-readable storage medium (which may be a non-transitory medium), and provides a program interface (instruction execution environment) to the target code 700 (which may include applications, operating systems and a hypervisor) which is the same as the interface of the hardware architecture being modelled by the simulator program 710. Thus, the program instructions of the target code 700 described above, may be executed from within the instruction execution environment using the simulator program 710, so that a host computer 730 which does not actually have the hardware features of the apparatus 2 discussed above can emulate these features.

[0094] In the example of figure 8, simulator code 710 comprises simulated memory access type determining program logic 740 to determine whether a given write operation specifying a target address is to be a tag-non-preserving write operation. Simulator code 710 also includes simulated memory access program logic 750 to trigger, in response to determining that the given write operation is to be the tag-non-preserving write operation, a simulated memory system to process the tag-non-preserving write operation specifying the target address, the tag-non-preserving write operation indicating that, following completion of the tag-non-preserving write operation, the simulated memory system is not required to preserve a current value of a memory safety check tag associated with the target address.

[0095] In the present application, the words “configured to...” are used to mean that an element of an apparatus has a configuration able to carry out the defined operation. In this context, a “configuration” means an arrangement or manner of interconnection of hardware or software. For example, the apparatus may have dedicated hardware which provides the defined operation, or a processor or other processing device may be programmed to perform the function. “Configured to” does not imply that the apparatus element needs to be changed in any way in order to provide the defined operation. In the present application, lists of features preceded with the phrase “at least one of” mean that any one or more of those features can be provided either individually or in combination. For example, “at least one of: [A], [B] and [C]” encompasses any of the following options: A alone (without B or C), B alone (without A or C), C alone (without A or B), A and B in combination (without C), A and C in combination (without B), B and C in combination (without A), or A, B and C in combination.

[0096] Although illustrative embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various changes and modifications can be effected therein by one skilled in the art without departing from the scope of the invention as defined by the appended claims.

Claims

CLAIMS1. An apparatus comprising: memory access type determining circuitry to: determine whether a given write operation specifying a target address is to be a tag-non-preserving write operation; and memory access circuitry to: trigger, in response to determining that the given write operation is to be the tag- non-preserving write operation, a memory system to process the tag-non-preserving write operation specifying the target address, the tag-non-preserving write operation indicating that, following completion of the tag-non-preserving write operation, the memory system is not required to preserve a current value of a memory safety check tag associated with the target address.

2. The apparatus of claim 1 , in which the memory access type determining circuitry is configured to: determine that the given write operation is to be the tag-non-preserving write operation based on tag-non-preserving information indicating that a write operation to the target address is to be a tag-non-preserving write operation.

3. The apparatus of claim 2, in which the tag-non-preserving information is software- configurable.

4. The apparatus of any preceding claim, in which the memory access type determining circuitry is configured to: determine that the given write operation is to be the tag-non-preserving write operation based on data structure entry information associated with a data structure accessed from the memory system.

5. The apparatus of any preceding claim, in which the memory access type determining circuitry is configured to: determine that the given write operation is to be the tag-non-preserving write operation based on page table entry information associated with a page table entry associated with the target address.

6. The apparatus of claim 5, in which the page table entry information comprises one or more attributes associated with the page table entry that indicates that write operations to the target address associated with the page table entry are to be tag-non-preserving write operations.

7. The apparatus of claim 6, in which the one or more attributes are referenced in one or more registers specified by the page table entry.

8. The apparatus of any of claims 6 to 7, in which the one or more attributes have an encoding capable of specifying: a first encoding indicating that write operations to the target address do not require a memory safety tag check but should cause the memory system to preserve a current value of the memory safety check tag associated with the target address; and a second encoding indicating that write operations to the target address are to be the tag-non-preserving operation that does not require the memory safety tag check and for which the memory system is not required to preserve the current value of a memory safety check tag associated with the target address.

9. The apparatus of any preceding claim, in which the memory access type determining circuitry is configured to: determine that the given write operation is to be the tag-non-preserving write operation based on range information specifying a range of addresses for which write operations to addresses in the range are to be tag-non-preserving write operations.

10. The apparatus of claim 9, in which the range information comprises information indicating one or more of a start address for the range, an end address for the range, or a size of the range.

11. The apparatus of any preceding claim, in which the memory access type determining circuitry is configured to: determine that the given write operation is to be the tag-non-preserving write operation based on mode information that indicates that a current mode of operation requires that write operations to the target address are to be tag-non-preserving write operations.

12. The apparatus of any preceding claim, in which the memory access type determining circuitry is configured to: determine that the given write operation is to be the tag-non-preserving write operation based on an instruction type of an instruction which triggered the given write operation.

13. The apparatus of claim 12, in which the memory access type determining circuitry is configured to: determine that the given write operation is to be the tag-non-preserving write operation based on an opcode of the instruction which triggered the given write operation.

14. The apparatus of any preceding claim, in which the memory access circuitry is configured to: provide an indication to the memory system, based on triggering the tag-non-preserving write operation, that the memory safety check tag associated with the target address does not require preserving.

15. The apparatus of claim 14, in which the indication comprises a field of a request signal that indicates that the memory safety check tag associated with the target address does not need preserving.

16. The apparatus of claims 14 or 15, comprising memory system circuitry to: select, based on the indication, whether to preserve the current value of the memory safety check tag associated with the target address.

17. The apparatus of claims 14 to 16, comprising memory system circuitry to: select, based on the indication, between a read-modify-write operation and a write operation performed for a storage location corresponding to the target address.

18. The apparatus of any preceding claim, comprising: tag checking circuitry to: perform a tag check in response to a tag-checked memory access instruction specifying an address operand for defining a target address of a memory access operation, the tag check comprising triggering an error handling response in response to detection of a tag mismatch between the memory safety check tag obtained from the memory system for the target address and an address tag associated with the address operand.

19. A computer-readable medium to store computer-readable code for fabrication of the apparatus of any preceding claim.

20. A method comprising: determining, by memory access type determining circuitry, whether a given write operation specifying a target address is to be a tag-non-preserving write operation; and triggering, by memory access circuitry, in response to determining that the given write operation is to be the tag-non-preserving write operation, a memory system to process the tag- non-preserving write operation specifying the target address, the tag-non-preserving write operation indicating that, following completion of the tag-non-preserving write operation, the memory system is not required to preserve a current value of a memory safety check tag associated with the target address.

21. A computer program for controlling a host data processing apparatus to provide an instruction execution environment for execution of target program code, the computer program comprising: simulated memory access type determining program logic to: determine whether a given write operation specifying a target address is to be a tag-non-preserving write operation; and simulated memory access program logic to: trigger, in response to determining that the given write operation is to be the tag- non-preserving write operation, a simulated memory system to process the tag-non-preserving write operation specifying the target address, the tag-non-preserving write operation indicating that, following completion of the tag-non-preserving write operation, the simulated memory system is not required to preserve a current value of a memory safety check tag associated with the target address.

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