Method for manufacturing interposer and interposer

Abstract

A method for manufacturing an interposer, the method involving: forming a redistribution layer including a via on a first support substrate; forming a connection plug layer including a conductive plug on a second support substrate; bonding the first support substrate and the second support substrate in such a manner that the via and the conductive plug overlap each other; electrically connecting the via and the conductive plug; delaminating the redistribution layer from the first support substrate; and delaminating the connection plug layer from the second support substrate.

Description

Method for manufacturing an interposer and an interposer

[0001] An embodiment of the present invention relates to a method for manufacturing an interposer and an interposer.

[0002] When electrically connecting a semiconductor chip manufactured by a wafer process to a printed wiring board, an intermediate substrate for pitch conversion called an interposer (a substrate that relays electrical continuity between front and back circuits using through-hole electrodes) is used. For example, an interposer (glass interposer) having multiple wiring layers and multiple microbumps formed on a glass substrate has been disclosed (see Patent Document 1). Also disclosed is an interposer having a first core with a first through-hole electrode formed thereon, a second core with a second through-hole electrode formed thereon, and wiring connecting the first through-hole electrode and the second through-hole electrode, in which the first core and the second core are stacked (see Patent Document 2).

[0003] International Publication No. 2001 / 082666 Japanese Patent Application Laid-Open No. 2017-130571

[0004] Interposers have a structure in which vias are provided to fill via holes formed in a resin layer, and wiring is further formed on top of the resin layer. Several such structures are stacked to form a rewiring layer. The vias and the wiring connected to the vias are fabricated using a plating method. Forming vias using a plating method requires a seed layer. However, as the resin layer becomes thicker, the via holes become deeper, making it difficult to form a seed layer using a sputtering method. Alternatively, filling via holes using electroless plating can be considered, but electroless plating grows a film through a chemical reaction, which results in a slow deposition rate and reduces the productivity of interposers.

[0005] A method for manufacturing an interposer according to one embodiment of the present invention includes forming a redistribution layer including vias on a first support substrate, forming a connection plug layer including conductive plugs on a second support substrate, bonding the first support substrate and the second support substrate together so that the vias and the conductive plugs overlap, electrically connecting the vias and the conductive plugs, peeling the redistribution layer from the first support substrate, and peeling the connection plug layer from the second support substrate.

[0006] An interposer according to one embodiment of the present invention has a rewiring layer including a first resin layer, a via provided in the first resin layer, and wiring electrically connected to the via, and a connection plug layer including a second resin layer, a through hole penetrating the second resin layer, and a conductive plug provided in the through hole, and the rewiring layer and the connection plug layer are stacked so that the via and the conductive plug are electrically connected.

[0007] 1 shows a cross-sectional view of an interposer according to an embodiment of the present invention; 2 shows a cross-sectional view of an interposer according to an embodiment of the present invention; 3 shows a manufacturing process of an interposer according to an embodiment of the present invention; 4 shows a manufacturing process of an interposer according to an embodiment of the present invention; 5 shows a manufacturing process of an interposer according to an embodiment of the present invention; 6 shows a manufacturing process of an interposer according to an embodiment of the present invention; 7 shows a manufacturing process of an interposer according to an embodiment of the present invention; 8 shows a manufacturing process of an interposer according to an embodiment of the present invention; 9 shows a manufacturing process of an interposer according to an embodiment of the present invention; 10 shows a manufacturing process of an interposer according to an embodiment of the present invention; 11 shows a manufacturing process of an interposer according to an embodiment of the present invention; 12 shows a manufacturing process of an interposer according to an embodiment of the present invention; 13 shows a manufacturing process of an interposer according to an embodiment of the present invention; 14 shows a manufacturing process of an interposer according to an embodiment of the present invention; 15 shows a manufacturing process of an interposer according to an embodiment of the present invention;

[0008] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different forms, and should not be construed as being limited to the description of the following exemplary embodiments. For clarity of explanation, the drawings may show schematic representations of the width, thickness, shape, etc. of each part compared to the actual form. However, these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, elements similar to those previously described with reference to the preceding drawings are designated by the same reference numerals (or reference numerals with A, B, etc. suffixed thereto), and detailed descriptions may be omitted as appropriate. Furthermore, the letters "first" and "second" attached to each element are convenient labels used to distinguish each element and have no further meaning unless otherwise specified.

[0009] In this specification, when a component or region is referred to as being "on (or under)" another component or region, unless otherwise specified, this includes not only the case where it is directly above (or directly under) the other component or region, but also the case where it is above (or under) the other component or region, i.e., the case where another component is included between the component or region and above (or under) the other component or region.

[0010] 1 shows a cross-sectional structure of an interposer 10 according to one embodiment of the present invention. The interposer 10 includes a redistribution layer 100 and a connection plug layer 150, and has a structure in which the redistribution layer 100 and the connection plug layer 150 are stacked. The interposer 10 includes vias and conductive plugs, the vias being exposed on the outer surface of the redistribution layer 100, and the conductive plugs being exposed on the outer surface of the connection plug layer.

[0011] The redistribution layer 100 includes at least one resin layer, at least one via formed in the resin layer, and at least one wiring layer electrically connected to the at least one via. Figure 1 shows, as an example, a structure in which the redistribution layer 100 includes a first resin layer 104, an interlayer resin layer 106 stacked on the first resin layer 104, via holes T11 to T16, T21 to T24, and T31 to T35 formed in the first resin layer 104 and the interlayer resin layer 106, vias V11 to V16, V21 to V24, and V31 to V35 formed in these via holes, and wiring layers W11 to W16 and W21 to W25 connected to these vias.

[0012] The connection plug layer 150 includes at least one resin layer and at least one conductive plug. 1 shows, as an example, a structure in which the connection plug layer 150 includes a second resin layer 154, through holes H11 to H15 penetrating the second resin layer 154, and conductive plugs P11 to P15 provided in these through holes.

[0013] The redistribution layer 100 and the connection plug layer 150 are stacked so that at least one via and at least one conductive plug are electrically connected. For example, when focusing on the via V31, the via V31 contacts the conductive plug P11 and forms an electrical connection. Also, when focusing on the via V11, the via V11 is electrically connected to the conductive plug P11 via the wiring layer W11, the via V21, the wiring layer W21, and the via V31.

[0014] In this embodiment, the conductive plug is a conductive member that penetrates the resin layer, and the conductive plug is provided in a via hole formed in the resin layer. The wiring layer is a conductive layer provided on the resin layer, and is disposed between the underlying resin layer and the upper resin layer. The wiring layer can form an electrical connection with the via. The wiring layer and the via are electrically connected by direct contact between them. Although not shown, the rewiring layer 100 can form various circuits by any three-dimensional layout of the wiring layer and the via.

[0015] Furthermore, interlayer resin layer 106 refers to a resin layer provided between first resin layer 104 and second resin layer 154, and there is no limit to the number of layers that can be stacked. As an example, Fig. 1 shows a structure in which first interlayer resin layer 1062 and second interlayer resin layer 1064 are stacked as interlayer resin layer 106. In this stacked structure, first interlayer resin layer 1062 is provided to embed wiring layers W11 to W16 provided on first resin layer 104, and second interlayer resin layer 1064 is provided to embed wiring layers W21 to W25 provided on first interlayer resin layer 1062.

[0016] As described above, redistribution layer 100 includes vias V11 to V16, V21 to V24, and V31 to V35. Vias V11 to V16 are conductive members provided in via holes T11 to T16 that penetrate first resin layer 104, vias V21 to V24 are conductive members provided in second via holes T21 to T24 that penetrate first interlayer resin layer 1062, and vias V31 to V35 are conductive members that penetrate second interlayer resin layer 1064. Each via is arranged so as to form an electrical connection with an upper or lower wiring layer.

[0017] For example, as shown in FIG. 1, vias V11 to V16 are arranged so as to be electrically connected to the wiring layers W11 to W16 on the first resin layer 104, respectively, vias V21 to V24 are arranged so as to be electrically connected to the wiring layers W11, W13, W14, W16 on the first resin layer 104 and the wiring layers W21, W22, W24, W25 on the first interlayer resin layer 1062, respectively, and vias V31 to V35 are electrically connected to the wiring layers W21 to W25, respectively.

[0018] Although not shown in Fig. 1, the redistribution layer 100 and the connection plug layer 150 are each fabricated on a support substrate. The redistribution layer 100 and the connection plug layer 150 fabricated on the respective support substrates are bonded together so that the vias and the conductive plugs are electrically connected. Thereafter, the respective support substrates are removed to obtain the interposer 10 shown in Fig. 1.

[0019] A glass substrate, for example, is used as the support substrate used in manufacturing the interposer 10. Preferably, an alkali-free glass substrate is used as the glass substrate. The alkali-free glass substrate can also be used as a large-area glass substrate (mother glass substrate) such as that used in manufacturing liquid crystal displays. By using such a large-area glass substrate, multiple redistribution layers 100 and connection plug layers 150 can be fabricated within a single glass substrate, thereby increasing the productivity of the interposer 10. Note that the support substrate is not limited to a glass substrate, and a semiconductor substrate such as a silicon wafer, a ceramic substrate, a quartz substrate, or the like may also be used.

[0020] An interposer is a substrate for forming electrical connections between front and back circuits. The interposer 10 can be used to connect a semiconductor chip to a package substrate or a printed wiring board. In the interposer 10 shown in FIG. 1, vias V11 to V16 are exposed on the outer surface on the redistribution layer 100 side, and conductive plugs P11 to P15 are exposed on the outer surface on the connection plug layer 150 side. The pitch (spacing) of the vias V11 to V16 exposed on the outer surface of the redistribution layer 100 can be made smaller than the pitch (spacing) of the conductive plugs P11 to P15 exposed on the outer surface of the connection plug layer 150. On the other hand, the diameter of the conductive plugs P11 to P15 can be made larger than the diameter of the conductive plugs P11 to P15. Therefore, it is preferable to arrange the vias V11 to V16 exposed on the outer surface of the redistribution layer 100 on the side of the semiconductor chip where the terminal spacing is narrow, and to arrange the conductive plugs P11 to P15 on the package substrate or printed wiring board. Although it is possible to form electrical connections with the circuits on the front and back sides using vias V11 to V16 and conductive plugs P11 to P15, it is preferable to use bumps for connection with the circuits.

[0021] 2 shows a structure in which bumps are further provided on the interposer 10 shown in FIG. 1. For example, bumps E11 to E16 are provided on the first resin layer 104 side to electrically connect to vias V11 to V16, and bumps E21 to E25 are provided on the second resin layer 154 side to electrically connect to conductive plugs P11 to P15. As described above, bumps E11 to E16 are used for electrical connection with a semiconductor chip, and bumps E21 to E25 can be used for electrical connection with a package substrate or a printed wiring board. Bumps E11 to E16 and bumps E21 to E25 are formed using metal materials such as solder (gold containing lead and tin), gold (Au), or copper (Cu).

[0022] Referring again to FIG. 1 , the first resin layer 104 and the interlayer resin layer 106 (first interlayer resin layer 1062, second interlayer resin layer 1064) constituting the redistribution layer 100 are formed of a resin material. The second resin layer 154 constituting the connection plug layer 150 is also formed of a resin material. The first resin layer 104, the interlayer resin layer 106 (first interlayer resin layer 1062, second interlayer resin layer 1064), and the second resin layer 154 may be formed of the same type of resin material or different types of resin materials. For example, the first resin layer 104 and the interlayer resin layer 106 (first interlayer resin layer 1062, second interlayer resin layer 1064) may be formed of the same type of resin material, and the second resin layer 154 may be formed of a different resin material. As an example, the first resin layer 104 and the interlayer resin layer 106 (first interlayer resin layer 1062, second interlayer resin layer 1064) may be formed from a photosensitive resin material, and the second resin layer 154 may be formed from a non-photosensitive (thermosetting) resin material.

[0023] The resin materials for forming the first resin layer 104 and the interlayer resin layer 106 (first interlayer resin layer 1062, second interlayer resin layer 1064), as well as the second resin layer 154, may include phenolic resin materials, polyimide resin materials, and epoxy resin materials. The second resin layer 154 may be formed from a coating-type thermosetting epoxy resin composition containing an epoxy resin, an active ester compound containing a naphthalene structure, and an inorganic filler. The second resin layer 154 may also be formed by using a film- or sheet-like intermediate material (prepreg not containing glass fiber) made of a thermosetting epoxy resin material, attaching it to a support substrate, and then thermally curing it.

[0024] By using the above-described thermosetting resin material as the resin material for forming the second resin layer 154, the film thickness of the second resin layer 154 can be made thicker than that of the first resin layer 104. By making the second resin layer 154 thicker, the portion where the conductive plug is provided can be made to have a sturdy structure. Furthermore, by making the second resin layer 154 thicker, the rigidity and flatness of the interposer 10 can be improved.

[0025] Next, a method for manufacturing the interposer 10 shown in Fig. 1 will be described. In this embodiment, the first resin layer 104 and the interlayer resin layer 106 (first interlayer resin layer 1062, second interlayer resin layer 1064) are formed using a photosensitive resin composition, the second resin layer 154 is formed using a non-photosensitive resin composition (thermosetting resin composition), and the vias V11 to V16, V21 to V24, and V31 to V35 are formed by a semi-additive method.

[0026] 3A shows a step of forming a first sacrificial layer 102 on a first support substrate 101 and further forming a seed layer SL11 thereon. The first sacrificial layer 102 is provided to peel the redistribution layer 100 from the first support substrate 101 after the redistribution layer 100 is formed on the first support substrate 101. As described above, the first support substrate 101 may be a glass substrate.

[0027] The first sacrificial layer 102 can be formed of an organic material or an inorganic material. For example, the first sacrificial layer 102 can be formed of a hydrogenated amorphous silicon film. Hydrogenated amorphous silicon can be formed by silane (SiH ４ ) and hydrogen (H ２ The first sacrificial layer 102 can be formed by vapor deposition (plasma CVD) using a hydrogenated amorphous silicon (H2S) gas. The hydrogenated amorphous silicon film can be explosively heated to a high temperature with a laser beam or the like, thereby weakening its adhesive strength. The first sacrificial layer 102 can be formed from a resin material such as polyimide. By forming the first sacrificial layer 102 from a resin material, the redistribution layer 100 can be peeled off from the first support substrate 101 by laser ablation.

[0028] In addition, since the first resin layer 104 is formed of a resin material, if the rewiring layer 100 can be peeled off without providing the first sacrificial layer 102, this sacrificial layer can be omitted.

[0029] A seed layer SL11 is formed on the first sacrificial layer 102. The seed layer SL11 is used in a later process when growing the vias V11 to V16 by electrolytic plating. The seed layer SL11 is formed using the same metal material as the vias V11 to V16. For example, when the vias V11 to V16 are formed of copper (Cu), it is preferable that the seed layer SL11 is also formed of a thin copper film. The seed layer SL11 has a film thickness of approximately 10 nm to 100 nm. A seed layer SL11 having such a film thickness can be produced by a sputtering method.

[0030] FIG. 3B shows a step of forming a first resin layer 104 on the seed layer SL11. The first resin layer 104 is formed using a photosensitive resin composition. Examples of the photosensitive resin composition that can be used include a precursor of a phenolic resin material, a polyimide resin material, an epoxy resin material, or the like, and a solvent containing a photosensitive group. The first resin layer 104 can be formed by applying the above-described resin composition onto the seed layer SL11 and exposing it to light. There are no limitations on the thickness of the first resin layer 104, but it is preferable to form it to a thickness of 3 μm to 10 μm, for example, 5 μm.

[0031] After applying a resin composition onto the seed layer SL11, the via holes T11 to T16 can be simultaneously formed by using a photomask when exposing the applied film. The photosensitive resin composition for forming the first resin layer 104 may be either a positive type or a negative type.

[0032] In this way, by using the photosensitive resin composition, the first resin layer 104 can be formed on the first support substrate 101, and at the same time, the via holes T11 to T16 that expose the seed layer SL11 can be formed. There are no limitations on the diameter of the via holes T11 to T12, and the diameter can be, for example, 5 μm to 10 μm.

[0033] The first resin layer 104 can also be formed from a thermosetting resin composition. For example, the first resin layer 104 can also be formed from a thermosetting (non-photosensitive) polyimide material. For example, the first resin layer 104 can be formed by applying a composition containing a polyimide precursor (not containing a photosensitive group) onto the seed layer SL11 and baking it. In this case, the baking temperature is preferably in the range of 350°C to 450°C. When the first resin layer 104 is formed from a thermosetting resin material, the via holes T11 to T16 can be formed by forming an etching mask by photolithography and etching the first resin layer 104.

[0034] 3C shows a step of forming vias V11 to V16 in the via holes T11 to T16. The vias V11 to V16 can be formed by electrolytic plating. For example, copper (Cu) can be grown by electrolytic plating in the areas where the seed layer SL11 is exposed by the via holes T11 to T16, thereby forming the vias V11 to V16. By using electrolytic plating, copper (Cu) can be grown so as to fill the via holes T11 to T16. The thickness of the vias V11 to V16 can be appropriately controlled by the electrolytic plating conditions (concentration of the plating solution, current, time, etc.).

[0035] 3D shows a step of forming a seed layer SL12 on the first resin layer 104 and the vias V11 to V16. The seed layer SL12 can be formed in the same manner as the seed layer SL11. The seed layer SL12 is preferably formed so as to extend over the entire surface of the first resin layer 104 and to be in contact with (conductively connect to) the vias V11 to V16.

[0036] 3E shows the step of forming a resist mask 130 on the seed layer SL12. The resist mask 130 is a mask for forming the wiring layers W11 to W16 and is formed by photolithography. The resist mask 130 has a region that covers the seed layer SL12 and a region that exposes the seed layer SL12. A plating film can be grown in the region where the seed layer SL12 is exposed from the resist mask 130, and this region becomes the region where the wiring layers W11 to W16 will be formed.

[0037] 3F shows the step of forming a conductive layer for forming the wiring layers W11-W16 on the seed layer SL12. The conductive layer for forming the wiring layers W11-W16 is formed by electrolytic plating. The conductive layer for forming the wiring layers W11-W16 can be formed, for example, by growing copper (Cu) by electrolytic plating. The thickness of the copper (Cu) grown by electrolytic plating can be appropriately controlled by the thickness of the resist mask 130 and the electrolytic plating conditions (plating solution concentration, current, time, etc.). For example, the thickness of the copper (Cu) for forming the wiring layers W11-W16 can be 4 μm to 6 μm.

[0038] 3G shows the stage of forming the wiring layers W11 to W16. When the resist mask 130 is peeled off from the state shown in FIG. 3F, the pattern of the conductive layer grown by electrolytic plating is exposed. The seed layer SL12 is etched using the pattern of the conductive layer, thereby forming the wiring layers W11 to W16 as shown in FIG.

[0039] FIG. 3H shows the step of forming a first interlayer resin layer 1062 on the wiring layers W11-W16. The first interlayer resin layer 1062 can be formed in the same manner as the first resin layer 104, using a photosensitive resin composition. By using a photomask when exposing the photosensitive resin composition applied to the wiring layers W11-W16, via holes T21-T24 can be simultaneously formed in the first interlayer resin layer 1062. The via hole T21 exposes the top surface of the wiring layer W11, the via hole T22 exposes the top surface of the wiring layer W13, the via hole T23 exposes the top surface of the wiring layer W14, and the via hole T24 exposes the top surface of the wiring layer W16. In this way, via holes can be appropriately formed in the first interlayer resin layer 1062 depending on the connection location with the wiring layer to be formed above. The thickness of the first interlayer resin layer 1062 is not limited, but it can be formed to a thickness of 3 μm to 10 μm, for example, 5 μm.

[0040] 3I shows the step of forming vias V21 to V24. The vias V21 to V24 are formed so as to fill the via holes T21 to T24. The method of forming the vias V21 to V24 is the same as the method of forming the vias V11 to V16 described with reference to FIG. 3C.

[0041] 3J shows a stage in which wiring layers W21 to W25 are formed on first interlayer resin layer 1062, second interlayer resin layer 1064 is formed, and vias V31 to V35 are further formed. The method for fabricating wiring layers W21 to W25 is the same as the method for fabricating wiring layers W11 to W16 described with reference to FIG. 3G. The method for fabricating second interlayer resin layer 1064 is the same as the method for fabricating first interlayer resin layer 1062 described with reference to FIG. 3H, and the method for fabricating vias V31 to V35 is the same as the method for fabricating vias V11 to V16 described with reference to FIG. 3C.

[0042] In this manner, rewiring layer 100 can be formed on first support substrate 101. Note that although Figures 3A to 3J show wiring layers W11 to W16 on first interlayer resin layer 1062 and wiring layers W21 to W25 on second interlayer resin layer 1064, the wiring layers can be further multi-layered by repeating similar steps.

[0043] Next, a method for manufacturing the connection plug layer 150 will be described. The connection plug layer 150 has a layer structure different from that of the redistribution layer 100, and therefore is manufactured in a separate process.

[0044] 4A shows a step of forming a second sacrificial layer 152 and a seed layer SL21 on a second support substrate 151. The second sacrificial layer 152 and the seed layer SL21 can be formed in the same manner as the first sacrificial layer 102 and the seed layer SL11 described with reference to FIG. 3A. The second support substrate 151 can also be a substrate similar to the first support substrate 101, such as a glass substrate.

[0045] FIG. 4B shows the step of forming a second resin layer 154 on the seed layer SL21. The second resin layer 154 is formed using a thermosetting resin composition. For example, the second resin layer 154 can be formed by attaching a film called a prepreg (a prepreg that does not contain glass fiber) made of a thermosetting epoxy resin material to the seed layer SL21 and curing it by heat treatment at a temperature of 150°C to 250°C. The second resin layer 154 made of such a thermosetting epoxy resin material can be formed to a thickness of 30 μm to 40 μm. By forming the second resin layer 154 to such a thickness, the connection plug layer 150 can be thickened. The second resin layer 154 can also be formed using a photosensitive resin composition, as with the first resin layer 104.

[0046] 4C shows a step of forming through holes H11 to H15 in the second resin layer 154. The through holes H11 to H15 may be formed by etching or laser processing. For example, the through holes H11 to H15 can be formed by irradiating the second resin layer 154 with laser light focused by an optical system. The light source of the laser light can be, for example, a CO ２ A laser, a YAG laser, or the like can be used. The through holes H11 to H15 are holes that expose the seed layer SL21. The through holes H11 to H15 can have any diameter, but can be formed with a diameter of, for example, 40 μm to 60 μm.

[0047] The through holes H11 to H15 preferably have a sidewall shape in which the diameter increases from the bottom of the hole toward the top in a cross-sectional view. That is, the through holes H11 to H15 preferably have tapered sidewalls. By having the through holes H11 to H15 have such a shape, it is possible to prevent voids from being formed inside the through holes H11 to H15 when forming conductive plugs by electroplating in the next step.

[0048] 4D shows the step of forming the conductive plugs P11 to P15. The conductive plugs P11 to P15 are formed so as to fill the through holes H11 to H15 formed in the second resin layer 154. The conductive plugs P11 to P15 can be formed in the same manner as the vias. The seed layer SL21 is exposed at the bottom surfaces of the through holes H11 to H15. Therefore, even if the second resin layer 154 is thick, the conductive plugs P11 to P15 can be formed by electrolytic plating.

[0049] The conductive plugs P11 to P15 have a tapered shape that reflects the shape of the through holes H11 to H15. That is, the hole diameter is small on the seed layer SL21 side (the outer surface side when viewed as an interposer) and large on the upper end side (the inner side when viewed as an interposer). In other words, the conductive plugs P11 to P15 have a cylindrical shape that tapers toward the tip.

[0050] The conductive plugs P11 to P15 may be entirely made of a single metal material, or may be made of multiple metal materials. For example, the conductive plugs P11 to P15 may be made of a first metal layer made of a first metal material and a second metal layer made of a second metal material. The first and second metal materials preferably have different melting points, and the melting point of the second metal material is preferably lower than the melting point of the first metal material.

[0051] In this case, as shown in FIG. 4D , it is preferable to form a first metal layer (conductive plugs P11-P15) made of a first metal material on the seed layer SL21, and then form a second metal layer (low-melting-point metal layers P11s-P15s) made of a second metal material on top of the first metal layer. For example, if the conductive plugs P11-P15 corresponding to the first metal layer are formed of a copper (Cu) plating layer, the low-melting-point metal layers P11s-P15s corresponding to the second metal layer may be formed of a tin (Sn) plating layer on top of this plating layer. Because tin (Sn) has a lower melting point than copper (Cu), it can be used as a material for establishing a connection, like solder, when forming an electrical connection with the redistribution layer 100. Therefore, the low-melting-point metal layers P11s-P15s only need to be formed at the tip portions of the conductive plugs P11-P15, and can be formed as relatively thin layers.

[0052] In this manner, the connection plug layer 150 can be formed on the second support substrate 151 .

[0053] 5 shows the step of connecting the redistribution layer 100 and the connection plug layer 150. The surface of the first support substrate 101 on which the redistribution layer 100 is formed and the surface of the second support substrate 151 on which the connection plug layer 150 is formed are made to face each other, and are superimposed so that the vias (vias V31 to V35) of the redistribution layer 100 come into contact with the conductive plugs P11 to P15.

[0054] Next, by irradiating a laser beam from the second support substrate 151 side, the contact portions between the vias (vias V31 to V35) and the conductive plugs P11 to P15 are heated, thereby forming a bond between the two metal layers and forming an electrical connection. ２ A laser, YAG laser, or the like can be used. The laser light is focused by an optical system so that it is irradiated only on the area where the via and the conductive plug contact, thereby preventing damage to other areas. In this case, by interposing low-melting-point metal layers P11s to P15s between the vias (vias V31 to V35) and the conductive plugs P11 to P15, electrical connection can be formed even with a relatively low laser irradiation intensity.

[0055] FIG. 6 shows the step of removing the first support substrate 101 and the second support substrate 151. The redistribution layer 100 can be peeled off from the first support substrate 101 by laser ablation of the first sacrificial layer 102 from the first support substrate 101 side. As described above, if the first sacrificial layer 102 is made of hydrogenated amorphous silicon, it can be instantaneously heated to a high temperature by irradiating it with laser light, thereby explosively releasing hydrogen and weakening the adhesion of the layers above the seed layer SL11 to the first support substrate 101. Furthermore, if the first sacrificial layer 102 is made of a resin material such as polyimide, the layers above the seed layer SL11 can be peeled off from the first support substrate 101 by absorbing and evaporating the laser light into the first sacrificial layer 102. It is preferable to use an ultraviolet laser such as an all-solid-state ultraviolet laser or an excimer laser as the laser light source. Using an ultraviolet laser can prevent the laser light from reaching the inside of the redistribution layer 100 or the inside of the connection plug layer 150, thereby preventing damage.

[0056] The first sacrificial layer 102 and the second sacrificial layer 152 are removed by laser ablation, but the seed layer SL11 on the redistribution layer 100 side and the seed layer SL21 on the connection plug layer 150 side remain. Therefore, it is preferable to remove the seed layers SL11 and SL21 by etching after removing the first support substrate 101 and the second support substrate 151.

[0057] In this manner, it is possible to manufacture the interposer 10 shown in Fig. 1. Furthermore, the interposer 10 may be provided with bumps E11 to E16 and E21 to E25 as shown in Fig. 2.

[0058] FIG. 7 shows a structure in which the interposer 10 is mounted between the semiconductor chip 200 and the circuit board 250. Bumps E11 to E16 provided on the rewiring layer 100 side of the interposer 10 are connected to pad electrodes 202 of the semiconductor chip 200, and bumps E21 to E25 on the connection plug layer 150 side are connected to pad electrodes 252 of the circuit board 250. While FIG. 7 shows a structure in which one semiconductor chip 200 is mounted on the interposer 10, multiple semiconductor chips 200 may be mounted. The semiconductor chip 200 may be a chip (bare chip) called a silicon die. The circuit board 250 is a substrate equivalent to a package substrate or a printed wiring board.

[0059] 1 and 2 show a state in which both the first support substrate 101 and the second support substrate 151 are removed to form the interposer 10, but the process of removing the support substrates is not limited to this. For example, the first support substrate 101 may be removed first, and then the semiconductor chip 200 (silicon die) may be mounted on the redistribution layer 100 with the second support substrate 151 remaining, and then the process of removing the second support substrate 151 may be performed.

[0060] As described above, according to this embodiment, productivity can be improved by fabricating the redistribution layer 100 and the connection plug layer 150 on separate support substrates and then bonding them together. That is, even if the resin layer is thickened when forming the conductive plug, a seed layer can be provided as an underlayer, so that the conductive plug can be fabricated by electrolytic plating with high productivity. In other words, by thickening the resin layer in which the conductive plug is embedded, the rigidity and flatness of the interposer can be improved.

[0061] The interposer 10 according to this embodiment can be applied to a panel-based fan-out package (FOPLP: Fan-Out Panel Level Package) that connects a semiconductor chip and a printed wiring board. According to the manufacturing method of the interposer 10 according to this embodiment, a large glass substrate can be used as a support substrate, which increases the productivity of the interposer 10 and reduces the manufacturing costs of semiconductor products using FOPLP.

[0062] The interposer and the method for manufacturing the interposer according to an embodiment of the present invention can be used as a rewiring member for a panel-level fan-out package.

[0063] 10: Interposer, 100: Rewiring layer, 101: First support substrate, 102: First sacrificial layer, 104: First resin layer, 106: Interlayer resin layer, 1062: First interlayer resin layer, 1064: Second interlayer resin layer, 130: Resist mask, 150: Connection plug layer, 151: Second support substrate, 152: Second sacrificial layer, 154: Second resin layer, 200: Semiconductor chip, 202: Pad electrode, 250: Circuit board , 252: pad electrode, E11 to E16, E21 to E25: bump, H11 to H15: through hole, P11 to P15: conductive plug, P11s to P15s: low melting point metal layer, SL11, SL12, SL21: seed layer, T11 to T16, T21 to T24, T31 to T35: via hole, V11 to V16, V21 to V24, V31 to V35: via, W11 to W16, W21 to W25: wiring layer

Claims

1. A method for manufacturing an interposer, comprising: forming a redistribution layer including vias on a first support substrate; forming a connection plug layer including conductive plugs on a second support substrate; bonding the first support substrate and the second support substrate together so that the vias and the conductive plugs overlap; electrically connecting the vias and the conductive plugs; peeling the redistribution layer from the first support substrate; and peeling the connection plug layer from the second support substrate.

2. The method for manufacturing an interposer according to claim 1, wherein the via and the conductive plug are overlapped so as to be in contact with each other, and then irradiated with laser light to electrically connect the via and the conductive plug.

3. The method for manufacturing an interposer according to claim 2, further comprising forming the conductive plug from a first metal layer made of a first metal material and a second metal layer made of a second metal material on the first metal layer, wherein the second metal material has a lower melting point than the first metal material, and melting the second metal layer by irradiating the laser light to electrically connect the via and the conductive plug.

4. A method for manufacturing an interposer as described in claim 1, comprising: forming a first seed layer on the first support substrate; forming a first resin layer on the first seed layer, the first resin layer having a via hole that exposes the first seed layer; forming the via in an area overlapping the via hole by electroplating using the first seed layer; forming a second seed layer on the second support substrate; forming a second resin layer on the second seed layer, the second resin layer having a through hole that exposes the second seed layer; and forming the conductive plug in an area overlapping the through hole by electroplating using the second seed layer.

5. A method for manufacturing an interposer as described in claim 4, comprising: forming a first sacrificial layer between the first support substrate and the first seed layer; and forming a second sacrificial layer between the second support substrate and the second seed layer; irradiating the first sacrificial layer with laser light from the side of the first support substrate to peel off the redistribution layer from the first support substrate; and irradiating the second sacrificial layer with laser light from the side of the second support substrate to peel off the connection plug layer from the second support substrate.

6. A method for manufacturing an interposer as described in claim 5, wherein the first seed layer is etched after the redistribution layer is peeled off from the first support substrate, and the second seed layer is etched after the connection plug layer is peeled off from the second support substrate.

7. The method for manufacturing an interposer according to claim 4, wherein the first resin layer is formed using a photosensitive resin composition, and the second resin layer is formed using a thermosetting resin composition.

8. An interposer comprising: a rewiring layer including a first resin layer, a via provided in the first resin layer, and a wiring electrically connected to the via; and a connection plug layer including a second resin layer, a through hole penetrating the second resin layer, and a conductive plug provided in the through hole, wherein the rewiring layer and the connection plug layer are stacked so that the via and the conductive plug are electrically connected.

9. The interposer according to claim 8, wherein the connection plug layer has an outer surface from which the conductive plug is exposed, and the through-holes have diameters that increase from the outer surface of the connection plug layer toward the inside.

10. The interposer of claim 8, wherein the conductive plug includes a first metal layer formed from a first metal material and a second metal layer formed from a second metal material on the first metal layer, the second metal material having a lower melting point than the first metal material.

11. The interposer according to claim 8, wherein the second resin layer is thicker than the first resin layer.

12. The interposer according to claim 8, wherein the first resin layer is formed of a photosensitive resin material, and the second resin layer is formed of a thermosetting resin material.

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