Display panel and operating method thereof

Abstract

Disclosed is a display panel comprising a plurality of pixels in which one frame is divided into a plurality of sub-frames so as to display same. Each of the plurality of pixels can include: a light-emitting element; a first transistor for controlling the amplitude of a current flowing through the light-emitting element; a second transistor for controlling, in each of a plurality of sub-frames, the duration for which the current flows through the light emitting-element; a constant current generation (CCG) driving unit for controlling the first transistor on the basis of a first data signal; and a pulse width modulation (PWM) driving unit for controlling, in each of the plurality of sub-frames, the second transistor such that same is turned on for a duration corresponding to a second data signal and a step signal, wherein the second data signal can be determined on the basis of a gray level that can be expressed by a pixel in each of the plurality of sub-frames, and the step signal can include a number of steps determined on the basis of the second data signal.

Description

Display panel and method of operation thereof

[0001] The present disclosure relates to a display panel and a method of operating the same.

[0002] Display panels that use self-luminous elements, such as micro light emitting diodes (LEDs) or organic light emitting diodes (OLEDs), may include pixel circuitry that controls the current flowing to the light emitting elements.

[0003] The method of controlling the current of a light-emitting element can be divided into the PAM (Pulse Amplitude Modulation) method, which controls the amplitude of the current, and the PWM (Pulse Width Modulation) method, which fixes the amplitude of the current and controls the time for which the current flows.

[0004] The PAM method has the advantage of a simple pixel circuit and excellent display image quality, but has the disadvantage of causing a wavelength shift as the amplitude of the current flowing through the light-emitting element changes, resulting in different color coordinates for each gray level.

[0005] On the other hand, the PWM method has the advantage of minimizing the wavelength shift of the light-emitting element because a fixed amplitude current flows, and high power efficiency by fixing the current amplitude to a value that can maximize the efficiency of the element included in the pixel circuit, but it has the disadvantage of requiring an additional circuit to compensate for the deviation of the PWM transistor and low quality of low grayscale expression. In addition, the digital PWM method, which divides one frame into multiple sub-frames and displays it, requires a data signal for each sub-frame, so it is difficult to secure data charging time, and it is not easy to apply it to high-speed driving and high-resolution panels.

[0006] A display panel according to one embodiment of the present disclosure may include a plurality of pixels that divide one frame into a plurality of sub-frames and display the same, and each of the plurality of pixels may include a light-emitting element, a first transistor that controls the amplitude of a current flowing in the light-emitting element, a second transistor that controls the time for which the current flows in the light-emitting element in each of the plurality of sub-frames, a CCG (Constant Current Generation) driver that controls the first transistor based on a first data signal, and a PWM (Pulse Width Modulation) driver that controls the second transistor so that the second transistor is turned on for a time corresponding to a second data signal and a step signal in each of the plurality of sub-frames, and the second data signal may be determined based on a gray level that can be expressed by the pixel in each of the plurality of sub-frames, and the step signal may include a number of steps determined based on the second data signal.

[0007] FIG. 1 schematically illustrates the configuration of a display panel according to one embodiment of the present disclosure.

[0008] FIG. 2 schematically illustrates a pixel circuit according to one embodiment of the present disclosure.

[0009] FIG. 3 illustrates whether a light-emitting element emits light according to a PWM data signal and a step signal, according to one embodiment of the present disclosure.

[0010] FIG. 4 illustrates the operation of a pixel circuit in one frame according to one embodiment of the present disclosure.

[0011] FIG. 5 illustrates an implementation example of a pixel circuit according to one embodiment of the present disclosure.

[0012] FIG. 6 illustrates the operation timing of a pixel circuit according to one embodiment of the present disclosure.

[0013] FIG. 7 illustrates a state of a pixel circuit in an initialization period according to one embodiment of the present disclosure.

[0014] FIG. 8 illustrates a state of a pixel circuit in a sampling interval according to one embodiment of the present disclosure.

[0015] FIG. 9 illustrates a state of a pixel circuit in a light-emitting section according to one embodiment of the present disclosure.

[0016] FIG. 10 illustrates an implementation example of a pixel circuit according to one embodiment of the present disclosure.

[0017] FIG. 11 illustrates the operation timing of a pixel circuit according to one embodiment of the present disclosure.

[0018] In this disclosure, the expression “at least one of a, b, and c” may refer to “a,” “b,” “c,” “a and b,” “a and c,” “b and c,” “all of a, b, and c,” or variations thereof.

[0019] The terms used in this disclosure have been selected from widely used, current terms, taking into account the functions of the embodiments. However, these terms may vary depending on the intentions of those skilled in the art, precedents, the emergence of new technologies, etc. Furthermore, in certain cases, terms may be arbitrarily selected by the applicant, and in such cases, their meanings will be described in detail in the relevant description of the invention. Therefore, the terms used in this disclosure should not be understood simply as names, but rather based on their meanings and the overall content of this disclosure.

[0020] While terms like "first" and "second" may be used to describe various components, these components should not be limited by these terms. These terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a first component could be referred to as a "second component," and similarly, a second component could also be referred to as a "first component."

[0021] When a component is referred to as being "connected" or "connected" to another component, it should be understood that it may be directly connected or connected to that other component, but that there may be other components intervening. Conversely, when a component is referred to as being "directly connected" or "connected" to another component, it should be understood that there are no other components intervening.

[0022] Singular expressions may include plural expressions unless the context clearly indicates otherwise. Terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art described herein.

[0023] In this disclosure, it should be understood that terms such as “include” or “have” are intended to specify the presence of a feature, number, step, operation, component, part, or combination thereof described in this disclosure, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0024] In this disclosure, components expressed as "units", "modules", etc. may be two or more components combined into one component, or one component may be divided into two or more components with more detailed functions. In addition, each component described below may additionally perform some or all of the functions performed by other components in addition to its own main function, and of course, some of the main functions performed by each component may be exclusively performed by other components.

[0025] In the present disclosure, a device-readable storage medium may be provided in the form of a non-transitory storage medium. Here, the term "non-transitory storage medium" simply means a tangible device that does not contain signals (e.g., electromagnetic waves). This term does not distinguish between cases where data is permanently stored in the storage medium and cases where data is temporarily stored. For example, a "non-transitory storage medium" may include a buffer in which data is temporarily stored.

[0026] According to one embodiment, a method according to various aspects described in the present disclosure may be provided as a computer program product. The computer program product may be traded as a commodity between a seller and a buyer. The computer program product may be distributed in the form of a machine-readable storage medium (e.g., a compact disc read-only memory (CD-ROM)), or may be distributed online (e.g., downloaded or uploaded) through an application store or directly between two user devices (e.g., smartphones). In the case of online distribution, at least a portion of the computer program product (e.g., a downloadable app) may be temporarily stored or temporarily generated in a machine-readable storage medium, such as the memory of a manufacturer's server, an application store's server, or an intermediary server.

[0027] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the attached drawings so that those skilled in the art can easily implement the present disclosure. However, the present disclosure may be implemented in various different forms and is not limited to the embodiments described herein.

[0028] In the present disclosure, a gray level may refer to the number of levels of luminance that a pixel can express. In this case, each level of luminance may be expressed in units of "gray." For example, "256 gray levels" may be understood to mean that a pixel can express 256 levels of luminance, and each of the 256 levels may be referred to as one of 0 gray to 255 gray. In this case, a level of relatively low luminance may be referred to as a "low gray level," and a level of relatively high luminance may be referred to as a "high gray level."

[0029] In the present disclosure, a subframe may refer to a partial frame that temporally divides one frame. That is, one frame may include multiple subframes. In this case, all subframes within one frame may be displayed for the same amount of time. For example, if the refresh rate of a display panel is 60 Hz and one frame includes four subframes, one frame may be displayed for 1 / 60 second, and each subframe may be displayed for 1 / 60×1 / 4 second. That is, four subframes each displayed for 1 / 60×1 / 4 second may constitute one frame.

[0030] Conversely, the display times of each subframe within a single frame may differ. For example, if the refresh rate of the display panel is 60 Hz and one frame includes four subframes, the four subframes may be displayed for 1 / 60×1 / 15 seconds, 1 / 60×2 / 15 seconds, 1 / 60×4 / 15 seconds, and 1 / 60×8 / 15 seconds, respectively.

[0031] In the present disclosure, the base number may refer to the number of luminance levels that a pixel can express in one subframe. For example, a 4-base number may be understood to mean that a pixel can express four levels of luminance in one subframe.

[0032] In the present disclosure, the number of bits may mean the number of subframes included in one frame. For example, 5 bits may be understood to mean that one frame includes 5 subframes.

[0033] For example, 4-bit 5-bit can be understood to mean that one frame contains 5 sub-frames, and each sub-frame can express 4 levels of brightness. In this case, if the length of the light-emitting section of each sub-frame is all different, the pixels can be expressed in total 1024 (=4) in one frame. 5) can express gradation.

[0034] FIG. 1 schematically illustrates the configuration of a display panel (100) according to one embodiment of the present disclosure.

[0035] Referring to FIG. 1, a display panel (100) according to one embodiment of the present disclosure may include a display driver integrated circuit (DDI) (110), a scan driver (SCAN driver) (120), an emission driver (130), a power supply (140), and an active area (160). However, the configuration of the display panel (100) is not limited thereto. For example, the display panel (100) may further include a timing controller for synchronizing an operation timing of the display panel (100) with a signal received from the outside, or a digital-to-analog converter for converting a digital signal into an analog signal.

[0036] In one embodiment of the present disclosure, the display driver IC (110) generates data signals (Data[1] to Data[H]) based on image data acquired from an external processor (e.g., an Application Processor (AP), a Graphic Processing Unit (GPU), etc.), and can apply the generated data signals to a plurality of data lines (Data Lines) included in the display area (160). In one embodiment of the present disclosure, the data signals (Data[1] to Data[H]) are CCG (Constant Current Generation) data signals (V) related to the amplitude of the current flowing in the light-emitting element. CCG_Data ) and PWM (Pulse Width Modulation) data signal (V) associated with the time of current flow PWM_Data) may be included. In the present disclosure, the CCG data signal (V CCG_Data ) may be referred to as a first data signal. In the present disclosure, the PWM data signal (V PWM_Data ) may be referred to as a second data signal.

[0037] In one embodiment of the present disclosure, the scan driver (120) can apply scan signals (SC[1] to SC[V]) to a plurality of scan lines (SC Lines) included in a display area (160). In one embodiment of the present disclosure, the scan signals (SC[1] to SC[V]) can be voltages for turning on or off a corresponding transistor included in each pixel (161). In one embodiment of the present disclosure, the scan driver (120) can include a plurality of scan drivers.

[0038] In one embodiment of the present disclosure, the light emitting driver (130) can apply light emitting signals (EM[1] to EM[V]) to cause a plurality of pixels (161) included in a display area (160) to emit light. In one embodiment of the present disclosure, the light emitting signals (EM[1] to EM[V]) can be voltages for turning on or off a corresponding transistor included in each pixel (161). In one embodiment of the present disclosure, the light emitting driver (130) can include a plurality of light emitting drivers.

[0039] In one embodiment of the present disclosure, the power supply unit (140) can supply a first voltage (VDD), a second voltage (VSS), and an initialization voltage (Vini) to the display area (160). In one embodiment of the present disclosure, the first voltage (VDD) may be a voltage of higher potential than the second voltage (VSS). However, the voltage supplied to the pixel by the power supply unit (140) is not suggested here, and for example, the power supply unit (140) may additionally supply a reference voltage for compensating for a deviation in the threshold voltage of the driving transistor included in the display panel (100). The operation of the pixel (161) according to the voltage supplied by the power supply unit (140) will be described later with reference to FIGS. 5 to 9.

[0040] In one embodiment of the present disclosure, the step driver (150) can apply a step signal (STEP) to each pixel (161) included in the display area (160). The step signal can be associated with the time at which the pixel (161) emits light in each subframe. The operation of the pixel (161) according to the step signal will be described later with reference to FIGS. 2 to 4.

[0041] In one embodiment of the present disclosure, the display area (160) may include a plurality of pixels (161), a plurality of scan lines (SC Lines, single-dotted and dashed lines in FIG. 1), and a plurality of data lines (Data Lines, double-dotted and dashed lines in FIG. 1). However, the configuration of the display area (160) is not limited thereto. For example, the display area (160) may further include a plurality of power lines for applying a first voltage (VDD), a second voltage (VSS), and an initialization voltage (Vini) supplied from a power supply unit (140) to the pixels (161), and a plurality of step lines for applying a step signal (STEP) supplied from a step driver (150) to the pixels (161).

[0042] In one embodiment of the present disclosure, scan lines (SC Lines) may be arranged for each row. The scan lines (SC Lines) are lines for applying scan signals (SC[1] to SC[V]) to pixels (161). For example, a number of scan lines (SC Lines) equal to the vertical resolution may be arranged in the display area (160).

[0043] In one embodiment of the present disclosure, data lines may be arranged for each column. The data lines are lines for applying data signals (Data[1] to Data[H]) to pixels (161). For example, a number of data lines equal to the horizontal resolution may be arranged in the display area (160). Alternatively, if each pixel includes three sub-pixels, three data lines equal to the horizontal resolution may be arranged in the display area (160). When a multiplexer (MUX) that selects some of a plurality of data signals is used, a smaller number of data lines may be arranged in the display area (160).

[0044] In one embodiment of the present disclosure, a pixel (161) may be placed in an area where scan lines and data lines intersect.

[0045] In one embodiment of the present disclosure, a pixel (161) may include a light-emitting element (D1 of FIG. 2) that emits light by itself when current flows, a first transistor (T1 of FIG. 2) that controls the amplitude of the current flowing in the light-emitting element, and a second transistor (T2 of FIG. 2) that controls the time for which the current flows. The first transistor (T1 of FIG. 2) may control the amplitude of the current by being turned on or off in response to a CCG data signal, and the second transistor (T2 of FIG. 2) may control the time for which the current flows by being turned on or off in response to a PWM data signal and a step signal. In the present disclosure, the first transistor (T1 of FIG. 2) may be referred to as a driving transistor or a CCG transistor, and the second transistor (T2 of FIG. 2) may be referred to as a PWM transistor.

[0046] In one embodiment of the present disclosure, the pixel (161) may include a plurality of sub-pixels (not shown). For example, the pixel (161) may include three sub-pixels, each corresponding to red (R), green (G), and blue (B). In this case, each sub-pixel may include a light-emitting element, a first transistor, and a second transistor.

[0047] FIG. 2 schematically illustrates a pixel circuit (200) according to one embodiment of the present disclosure.

[0048] The pixel circuit (200) illustrated in FIG. 2 may be included in a pixel (161) corresponding to the nth row and mth column of the display area (160 of FIG. 1). Here, n is any natural number between 1 and the vertical resolution (V), and m is any natural number between 1 and the horizontal resolution (H).

[0049] Referring to FIG. 2, the pixel circuit (200) may include a light-emitting element (D1), a first transistor (T1), a second transistor (T2), a CCG driver (210), and a PWM driver (220). However, the components of the pixel circuit (200) are not limited thereto, and for example, the pixel circuit (200) may generate a current (I) in response to a light-emitting signal (EM[1] to EM[V]). D1 ) may further include one or more transistors (e.g., the fifth transistor (T5) or the sixth transistor (T6) of FIG. 5) that allow or block the flow of current.

[0050] In FIG. 2, the first and second transistors (T1 and T2) are shown as being P-type transistors, but this is only an example, and the first and second transistors (T1 and T2) may also be N-type transistors.

[0051] In one embodiment of the present disclosure, the light emitting element (D1) is a current (I D1 ) can emit light when current (I) flows. For example, the light-emitting element (D1) may be a self-emitting element such as a micro LED (Micro Light Emitting Diode) or an OLED (Organic Light Emitting Diode). The pixel circuit (200) may be configured to emit light when current (I D1 ) amplitude and / or current (I D1 ) can be controlled by controlling the time at which the current (I) flows. For example, the brightness of the light emitted from the light emitting element (D1) can be controlled by controlling the time at which the current (I) flows. D1 ) can be higher, the larger the amplitude of the current (I D1 ) can be higher the longer the time it takes to flow.

[0052] In one embodiment of the present disclosure, the first transistor (T1) is configured to supply current (I) flowing to the light-emitting element (D1). D1 ) can control the amplitude of the current (I). For example, the current (I D1) can be controlled according to the gate-source voltage of the first transistor (T1) as in mathematical expression 1. The gate voltage of the first transistor (T1) can be determined based on the CCG data signal by the CCG driver (210).

[0053]

[0054] In mathematical expression 1, |I D1 | is the current (I D1 ) is the amplitude, μ is the mobility of the carrier, and C ox is the capacitance of the oxide film of the first transistor (T1), W and L are the width and length of the channel formed in the first transistor (T1), respectively, and V GS1 is the gate-source voltage of the first transistor (T1), and V th1 is the threshold voltage of the first transistor (T1).

[0055] In one embodiment of the present disclosure, for every pixel (161) in the display panel (100), a current (I D1 ) can be equal to a given value. For example, the current (I D1 ) may be a value that maximizes the efficiency of the transistor included in the display panel (100). In this case, the pixel circuit (200) may be a current (I D1 ) can control the brightness of the pixel (161) by controlling the time it flows.

[0056] In one embodiment of the present disclosure, the second transistor (T2) supplies current (I) to the light emitting element (D1). D1 ) can control the time at which the PWM data signal (V) flows. For example, the second transistor (T2) controls the time at which the PWM data signal (V) flows for each subframe. PWM_Data ) and the current (I) during the time corresponding to the step signal (STEP). D1 ) can be turned on or off to flow. The gate voltage of the second transistor (T2) is controlled by the PWM driver (220) to generate a PWM data signal (VPWM_Data ) and step signal (STEP).

[0057] In one embodiment of the present disclosure, the CCG driving unit (210) receives a CCG data signal (V CCG_Data ) can control (e.g., turn on or off) the first transistor (T1). The CCG driving unit (210) can include one or more transistors that turn on or off in response to a scan signal (SC[1] to SC[V] of FIG. 1). The CCG driving unit (210) can control (e.g., turn on or off) the first transistor (T1) by applying a CCG data signal (V) to the gate of the first transistor (T1) through the on or off operation of one or more transistors. CCG_Data ) can be authorized.

[0058] In one embodiment of the present disclosure, a current (I) is applied to all pixels (161) in the display panel (100). D1 ) so that the amplitude of the CCG data signal (V) applied to all pixels (161) is the same. CCG_Data ) can be equal to a given value. For example, the CCG data signal (V CCG_Data ) is a current (I) of amplitude that maximizes the efficiency of the transistor included in the display panel (100). D1 ) can be a value that causes the flow.

[0059] In one embodiment of the present disclosure, the CCG driver (210) may include a circuit that compensates for deviations in threshold voltages of driving transistors included in the display panel (100) and compensates for voltage drops that may occur due to resistance components of power wiring. For example, the threshold voltages of a plurality of driving transistors included in the display panel may differ from each other due to non-uniformity in manufacturing processes such as ELA (Excimer Laser Annealing) and etching, and the voltages applied to the source nodes of the driving transistors may differ from each other depending on the location within the display panel due to voltage drops that occur due to resistance components of the power wiring. In this case, even if the same CCG data signal is applied, the amplitude of the current flowing to the light-emitting element may vary depending on the location within the display panel, which may result in problems such as non-uniform brightness of the display panel, afterimages, and reduced lifespan. The CCG driving unit (210) may include a structure such as 4T (transistor) 1C (capacitor), 6T1C, 7T1C, or 8T1C that can compensate for the deviation and voltage drop of the threshold voltage. However, the structure of the CCG driving unit (210) is not limited to the above-described examples.

[0060] An example of the implementation of the CCG driving unit (220) and its operation will be described later with reference to FIGS. 5 to 11.

[0061] In one embodiment of the present disclosure, the PWM driver (220) receives a PWM data signal (V PWM_Data ) and a step signal (STEP) can be used to control (e.g., turn on or off) the second transistor (T2). The PWM driving unit (220) can include one or more transistors that turn on or off in response to a scan signal (SC[1] to SC[V] of FIG. 1). The PWM driving unit (220) can control the gate of the second transistor (T2) by applying a PWM data signal (VPWM_Data ) and step signal (STEP) can be applied.

[0062] In one embodiment of the present disclosure, the PWM driver (220) has a second transistor (T2) in each subframe that outputs a PWM data signal (V PWM_Data ) and the current (I) during the time corresponding to the step signal (STEP) D1 ) can control the second transistor (T2) to flow. For example, if one frame includes four sub-frames, the PWM driver (220) controls the current (I) for the first time in the first sub-frame. D1 ) flows, and the current (I) flows for the second time in the second subframe. D1 ) flows, and the current (I) flows for the third time in the third subframe. D1 ) flows, and the current (I) flows for the fourth time in the fourth subframe. D1 ) can be controlled to flow the second transistor (T2).

[0063] An example of the implementation of the PWM driver (220) and its operation will be described later with reference to FIGS. 5 to 11.

[0064] In one embodiment of the present disclosure, in each subframe, a PWM data signal (V PWM_Data ) may be one of a predetermined first number of values. For example, as illustrated in FIG. 2, in each subframe, the PWM data signal (V PWM_Data ) can be one of four values ​​(i.e., V0, V1, V2, and V3). In one embodiment of the present disclosure, the first number may correspond to the number of levels of luminance that the pixel (161) can express in one subframe, i.e., the base number. For example, as illustrated in FIG. 2, when the PWM data signal can have four values ​​(i.e., V0, V1, V2, and V3), it can be understood that the pixel (161) operates in the 4-base system.

[0065] In one embodiment of the present disclosure, the grayscale that a pixel (161) can express in one frame can be determined based on the base number and the number of sub-frames included in one frame. For example, as shown in FIG. 2, if the pixel circuit (200) operates in the 4-base system and one frame includes four sub-frames, the pixel (161) can express 256 (=4) sub-frames in one frame. 4 ) can express gradation.

[0066] In order to implement a pixel (161) that can express a specific grayscale in one frame, a method of making the base number small and increasing the number of sub-frames (i.e., the number of bits) included in one frame, or a method of making the base number large and decreasing the number of sub-frames included in one frame can be considered. For example, in order to express 256 grayscales, a method in which each sub-frame operates in binary and 8 sub-frames are included in one frame, or a method in which each sub-frame operates in quaternary and 4 sub-frames are included in one frame can be considered.

[0067] As the number of sub-frames included in one frame increases, the operating time of each sub-frame becomes shorter, so there is insufficient time for charging the data signal, a driver capable of high-speed operation (e.g., display driver IC (110 in FIG. 1)) is required, and power consumption increases when driving the display. The pixel circuit (200) according to one embodiment of the present disclosure can reduce the number of sub-frames included in one frame by increasing the base number (e.g., 3-base or higher), thereby improving the driving speed of the display panel and reducing power consumption.

[0068] In one embodiment of the present disclosure, in each subframe, the step signal (STEP) may include a second predetermined number of steps. For example, as illustrated in FIG. 2, in each subframe, the step signal (STEP) may include two steps (e.g., from V2 to V1, and from V1 to V0). In one embodiment of the present disclosure, the second number may be a PWM data signal (V PWM_Data ) can be determined based on the first number of values ​​(i.e., the base number) that it can have. For example, the second number can be (the first number - 2).

[0069] In one embodiment of the present disclosure, the amplitude of each step included in the step signal (STEP) is PWM_Data ) can be determined based on a first number of values ​​that the step signal (STEP) can have. For example, as illustrated in FIG. 2, the amplitude of each step (e.g., V2-V1, and V1-V0) included in the step signal (STEP) can be determined to be equal to the difference of the first number of values.

[0070] In one embodiment of the present disclosure, the time length of each step included in the step signal (STEP) may be determined based on the time length of the light emission period of the corresponding subframe and the second number of steps included in the step signal (STEP). For example, if the step signal includes two steps, a step signal (STEP) in which each step has a length of T may be applied to a subframe including a light emission period of 3T in length, and a step signal (STEP) in which each step has a length of 4T may be applied to a subframe including a light emission period of 12T in length.

[0071] In Fig. 2, the step signal (STEP) is illustrated as including a step from a high voltage to a low voltage, but the direction of the step is not limited thereto. For example, if the second transistor (T2) is an N-type transistor, the step signal (STEP) may include a step from a low voltage to a high voltage.

[0072] PWM data signal (V PWM_Data ) and the operation of the second transistor (T2) according to the step signal (STEP) will be described later with reference to FIG. 3.

[0073] FIG. 3 is a PWM data signal (V) according to one embodiment of the present disclosure. PWM_Data ) and whether the light-emitting element (D1) emits light according to a step signal (STEP). FIG. 3 describes a case where the pixel circuit (200) operates in 4-base as shown in FIG. 2, but the present disclosure is not limited thereto, and the pixel circuit (200) may operate in any N-base (N is a natural number greater than or equal to 2).

[0074] In Fig. 3, the PWM data signal (V PWM_Data ) is one of V0, V1, V2 and V3 as shown in Fig. 2, and V0 is the threshold voltage (V of the second transistor th2 ) is smaller than V1, V2 and V3 are the threshold voltages (V) of the second transistor. th2 ) is assumed to be greater than. Hereinafter, the explanation will be given with reference to FIGS. 2 and 3.

[0075] In FIG. 3, the graph (310) illustrates the operation of the pixel circuit (200) when the light-emitting element (D1) does not emit light in one sub-frame, and the graph (320) illustrates the operation of the pixel circuit (200) when the light-emitting element (D1) emits light for a time corresponding to 1 / 3 of the emission period in one sub-frame. In addition, the graph (330) illustrates the operation of the pixel circuit (200) when the light-emitting element (D1) emits light for a time corresponding to 2 / 3 of the emission period in one sub-frame, and the graph (340) illustrates the operation of the pixel circuit (200) when the light-emitting element (D1) emits light for the entire emission period in one sub-frame. In the four cases, the luminance of the sub-frame increases in the order of the graph (310), the graph (320), the graph (330), and the graph (340), and each luminance can be referred to as 0 gray, 1 gray, 2 gray, and 3 gray.

[0076] In the graphs (310 to 340), "Initial & Sampling" corresponds to the initial period and the sampling period, and "Emission" corresponds to the emission period. In the initial period, the gate voltages of the first and second transistors (T1 and T2) are initialized, and in the sampling period, the CCG data signal (V CCG_Data ), PWM data signal (V PWM_Data ), and a step signal (STEP) is applied to the pixel circuit (200), and in the light emission section, a current (I D1 ) flows to the light-emitting element (D1), and the light-emitting element (D1) emits light. Since the operation of the pixel circuit (200) in the initialization section and the sampling section differs depending on the implementation method, the description is omitted in FIG. 3 and is described later together with the implementation example of FIG. 5.

[0077] Graph (310) shows the PWM data signal (V PWM_Data) is V3, the gate-source voltage (V) of the second transistor (T2) GS2 ), the threshold voltage (V) of the second transistor (T2) th2 ), and whether the light emitting element (D1) emits light. As described above, the PWM driving unit (220) transmits the PWM data signal (V PWM_Data ) and a step signal (STEP) can be applied to the gate of the second transistor (T2). In this case, the gate-source voltage (V of the second transistor (T2) GS2 ) is V3 at the beginning of the emission period and decreases stepwise by the step signal (STEP) (i.e., V3 → V2 → V1). Since V3 is a sufficiently large value in the graph (310), the gate-source voltage (V) of the second transistor (T2) GS2 ) is lowered by the step signal, the threshold voltage (V) of the second transistor (T2) throughout the entire emission period. th2 ) is higher than the PWM data signal (V ), so the second transistor (T2) remains in the off state. Therefore, the PWM data signal (V PWM_Data ) is V3, the light emitting element (D1) has a current (I D1 ) does not flow and the light emitting element (D1) does not emit light during the corresponding subframe.

[0078] Graph (320) shows the PWM data signal (V PWM_Data ) is V2, the gate-source voltage (V) of the second transistor (T2) GS2 ), the threshold voltage (V) of the second transistor (T2) th2 ), and whether the light-emitting element (D1) emits light. In this case, the gate-source voltage (V) of the second transistor (T2) GS2 ) is V2 at the beginning of the emission period and decreases stepwise by the step signal (STEP) (i.e., V2 → V1 → V0). In the graph (320), the gate-source voltage (V) of the second transistor (T2) GS2 ) in the section where V2 and V1, the threshold voltage (V) of the second transistor (T2) th2) is higher than the gate-source voltage (V) of the second transistor (T2). GS2 ) is V0, the threshold voltage (V) of the second transistor (T2) th2 ) is lower than that of the PWM data signal (V PWM_Data ) is V2, the gate-source voltage (V) of the second transistor (T2) GS2 ) only in the section where V0 is applied to the light emitting element (D1) D1 ) flows, and the light-emitting element (D1) emits light for a time corresponding to 1 / 3 of the light-emitting section of the corresponding sub-frame. As a result, the pixel (161) in the graph (320) can express a higher luminance than the graph (310).

[0079] Graph (330) shows the PWM data signal (V PWM_Data ) is V1, the gate-source voltage (V) of the second transistor (T2) GS2 ), the threshold voltage (V) of the second transistor (T2) th2 ), and whether the light-emitting element (D1) emits light. In this case, the gate-source voltage (V) of the second transistor (T2) GS2 ) is V1 at the beginning of the emission period and is gradually lowered by the step signal (STEP) (i.e., V1 → V0 → a voltage lower than V0). In the graph (330), the gate-source voltage (V) of the second transistor (T2) GS2 ) in the section where V1 is the threshold voltage (V) of the second transistor (T2) th2 ) is higher than the threshold voltage (V) of the second transistor (T2) in the remaining section. th2 ) is lower than that of the PWM data signal (V PWM_Data ) is V1, the light-emitting element (D1) emits light for a time corresponding to 2 / 3 of the light-emitting section of the corresponding sub-frame. As a result, the pixel (161) in the graph (330) can express higher brightness than the graph (310) and the graph (320).

[0080] Graph (340) shows the PWM data signal (VPWM_Data ) is V0, the gate-source voltage (V) of the second transistor (T2) GS2 ), the threshold voltage (V) of the second transistor (T2) th2 ), and whether the light-emitting element (D1) emits light. In this case, the gate-source voltage (V) of the second transistor (T2) GS2 ) is V0 at the beginning of the emission period and decreases stepwise by the step signal (STEP). Since V0 is a sufficiently small value in the graph (330), the gate-source voltage (V) of the second transistor (T2) GS2 ) The threshold voltage (V) of the second transistor (T2) throughout the entire emission period th2 ) is lower than the second transistor (T2) and remains on. Therefore, the PWM data signal (V PWM_Data ) is V0, the light emitting element (D1) emits light in the entire light emitting section of the corresponding subframe. As a result, the pixel (161) in the graph (340) can express a higher luminance than the graph (310), the graph (320), and the graph (330).

[0081] In this way, the pixel circuit (200) according to one embodiment of the present disclosure receives a PWM data signal (V PWM_Data ) and step signal (STEP), and by controlling the time at which the light-emitting element (D1) emits light for each sub-frame, multiple gray levels can be expressed in one sub-frame. Meanwhile, as shown in the graphs (310 to 340) of FIG. 3, the gate-source voltage (V of the second transistor (T2) GS2 ) changes rapidly by the step signal (STEP), so the second transistor (T2) can be turned on or off at high speed, so that the current (I D1) is reduced, and the pixel circuit (200) can improve the quality of low-grayscale expression. In addition, since the size of the step included in the step signal (STEP) is designed to be sufficiently large, the pixel circuit (200) according to one embodiment of the present disclosure does not require a circuit for compensating for a voltage drop that may occur due to a deviation in the threshold voltage of a PWM transistor included in the display panel (100) or a resistance component of a power supply wire, and therefore the structure of the entire PWM driver (220) and the pixel circuit (200) can be simplified and applied to a high-resolution display.

[0082] FIG. 4 illustrates the operation of a pixel circuit (200) in one frame according to one embodiment of the present disclosure.

[0083] Although FIG. 4 illustrates a case where the pixel circuit (200) operates in 4-base as illustrated in FIGS. 2 and 3, the present disclosure is not limited thereto, and the pixel circuit (200) may operate in any N-base (N is a natural number greater than or equal to 2). In FIG. 4, it is assumed that one frame includes 4 sub-frames (i.e., 4-bits), but the present disclosure is not limited thereto.

[0084] Referring to FIG. 4, the PWM data signals in the first to fourth subframes (subframe #1 to subframe #4) are V2, V3, V1, and V0, respectively. In this case, as described in FIG. 3, the light-emitting element (D1) emits light for a time corresponding to 1 / 3 of the light-emitting period in the first subframe (subframe #1), does not emit light in the second subframe (subframe #2), emits light for a time corresponding to 2 / 3 of the light-emitting period in the third subframe (subframe #3), and emits light for the entire light-emitting period in the fourth subframe (subframe #4). In this way, the time for which the light-emitting element (D1) emits light in each subframe may vary depending on the PWM data signal, and the luminance expressed by the pixel (161) in the corresponding frame may vary.

[0085] In one embodiment of the present disclosure, the lengths of the light-emitting periods of each of a plurality of subframes included in one frame may be different from each other. For example, as illustrated in FIG. 4, the lengths of the light-emitting periods in the first to fourth subframes (subframe #1 to subframe #4) may be different from each other, such as 192T, 48T, 12T, and 3T, respectively. Here, T is an arbitrary time period. If the lengths of the light-emitting periods of each subframe are all the same, the same PWM data signal (V PWM_Data ) for different sub-frames, the sub-frames will express the same grayscale since they emit light for the same amount of time. However, if the lengths of the emission sections of the sub-frames are all different, the same PWM data signal (V PWM_Data ), each sub-frame can express different grayscales, so the grayscales that can be expressed by the pixel (161) can increase.

[0086] FIG. 5 illustrates an implementation example of a pixel circuit (500) according to one embodiment of the present disclosure.

[0087] The pixel circuit (500) of FIG. 5 is an example of implementing the pixel circuit (200) of FIG. 2 using a P-type transistor, but the implementation examples of the pixel circuit (200) are not limited thereto. In the following descriptions related to FIGS. 5 to 9, the first terminal of the transistor may be a source, and the second terminal may be a drain.

[0088] Referring to FIG. 5, in one embodiment of the present disclosure, a pixel circuit (500) may include a light-emitting element (D1), first to ninth transistors (T1 to T9), a first capacitor (C1), and a second capacitor (C2). In FIG. 5, the first and second transistors (T1, T2) may correspond to the first and second transistors (T1, T2) of the pixel circuit (200), the third transistor (T3), the fourth transistor (T4), the eighth transistor (T8), and the first capacitor (C1) may correspond to the CCG driver (210), and the seventh transistor (T7), the ninth transistor (T9), and the second capacitor (C2) may correspond to the PWM driver (220).

[0089] In one embodiment of the present disclosure, the first to ninth transistors (T1 to T9) can be turned on or off in response to a first scan signal (SC[n-1]), a second scan signal (SC[n]), and a light emitting signal (EM[n]). In one embodiment of the present disclosure, the first scan signal (SC[n-1]) can be a scan signal applied to the (n-1)th scan wire, and the second scan signal (SC[n]) can be a scan signal applied to the nth scan wire. In one embodiment of the present disclosure, the first to second scan signals (SC[n-1], SC[n]) can be generated by the scan driver (120). As described below, depending on the state (i.e., on or off) of the first to ninth transistors (T1 to T9), the voltage of each node in the pixel circuit (200) can change, and the current of the light emitting element (D1) can change.

[0090] In one embodiment of the present disclosure, the first to ninth transistors (T1 to T9) may be low-temperature polycrystalline silicon thin film transistors (LTPS TFTs), oxide thin film transistors (Oxide TFTs), low-temperature polycrystalline silicon oxide (LTPO), or silicon-based switching elements.

[0091] In one embodiment of the present disclosure, the gate of the first transistor (T1) can be connected to the second terminal of the first capacitor (C1), the second terminal of the third transistor (T3), and the second terminal of the fourth transistor (T4).

[0092] In one embodiment of the present disclosure, a first terminal of a first transistor (T1) may be connected to a second terminal of a fifth transistor and a second terminal of an eighth transistor (T8), and a second terminal of the first transistor (T1) may be connected to a first terminal of a third transistor (T3) and a first terminal of a second transistor (T2).

[0093] In one embodiment of the present disclosure, the first transistor (T1) is configured to supply current (I) flowing to the light-emitting element (D1). D1 ) can control the amplitude of the current (I). For example, the current (I D1 ) can be controlled as in the above-described mathematical expression 1. When the fifth transistor (T5), the first transistor (T1), the second transistor (T2), and the sixth transistor (T6) are turned on, a current (I) is supplied to a path including the first voltage (VDD), the fifth transistor (T5), the first transistor (T1), the second transistor (T2), the sixth transistor (T6), the light-emitting element (D1), and the second voltage (VSS). D1 ) can flow.

[0094] In one embodiment of the present disclosure, the gate of the second transistor (T2) can be connected to the second terminal of the second capacitor (C2), the second terminal of the seventh transistor (T7), and the second terminal of the ninth transistor (T9).

[0095] In one embodiment of the present disclosure, a first terminal of a second transistor (T2) can be connected to a second terminal of a first transistor (T1) and a first terminal of a third transistor (T3), and a second terminal of a second transistor (T2) can be connected to a first terminal of a sixth transistor (T6).

[0096] In one embodiment of the present disclosure, the second transistor (T2) supplies current (I) to the light emitting element (D1). D1 ) can control the time at which the PWM data signal (V) flows. For example, the second transistor (T2) controls the time at which the PWM data signal (V) flows for each subframe. PWM_Data ) and the current (I) during the time corresponding to the step signal (STEP). D1 ) can be turned on or off to flow.

[0097] In one embodiment of the present disclosure, the gate of the third transistor (T3) may be connected to the nth scan wiring. A second scan signal (SC[n]) may be applied to the gate of the third transistor (T3), and the third transistor (T3) may be turned on or off in response to the second scan signal (SC[n]). For example, the third transistor (T3) may be turned on when the second scan signal (SC[n]) is low, and may be turned off when the second scan signal (SC[n]) is high.

[0098] In one embodiment of the present disclosure, a first terminal of a third transistor (T3) may be connected to a second terminal of a first transistor (T1) and a first terminal of a second transistor (T2), and a second terminal of a third transistor (T3) may be connected to a gate of the first transistor (T1), a second terminal of a fourth transistor (T4), and a second terminal of a first capacitor (C1). When the third transistor (T3) and the eighth transistor (T8) are turned on, V is applied to the gate of the first transistor (T1) through diode compensation. CCG_Data - V th1 A voltage of can be applied.

[0099] In one embodiment of the present disclosure, the gate of the fourth transistor (T4) may be connected to the (n-1)th scan wiring. A first scan signal (SC[n-1]) may be applied to the gate of the fourth transistor (T4), and the fourth transistor (T4) may be turned on or off in response to the first scan signal (SC[n-1]). For example, the fourth transistor (T4) may be turned on when the first scan signal (SC[n-1]) is low, and may be turned off when the first scan signal (SC[n-1]) is high.

[0100] In one embodiment of the present disclosure, a first terminal of the fourth transistor (T4) may be connected to a power line supplying an initialization voltage (Vini), and a second terminal of the fourth transistor (T4) may be connected to a gate of the first transistor (T1), a second terminal of the third transistor (T3), and a second terminal of the first capacitor (C1). When the fourth transistor (T4) is turned on, the initialization voltage (Vini) may be applied to the gate of the first transistor (T1).

[0101] In one embodiment of the present disclosure, the gate of the fifth transistor (T5) may be connected to a wiring that applies a light-emitting signal (EM[n]). The light-emitting signal (EM[n]) may be applied to the gate of the fifth transistor (T5), and the fifth transistor (T5) may be turned on or off in response to the light-emitting signal (EM[n]). For example, the fifth transistor (T5) may be turned on when the light-emitting signal (EM[n]) is low, and may be turned off when the light-emitting signal (EM[n]) is high.

[0102] In one embodiment of the present disclosure, a first terminal of the fifth transistor (T5) may be connected to a power line supplying a first voltage (VDD), and a second terminal of the fifth transistor (T5) may be connected to a first terminal of the first transistor (T1) and a second terminal of the eighth transistor (T8). When the fifth transistor (T5) is turned off, a current (I D1 ) will not flow.

[0103] In one embodiment of the present disclosure, the gate of the sixth transistor (T6) may be connected to a wiring that applies a light-emitting signal (EM[n]). The light-emitting signal (EM[n]) may be applied to the gate of the sixth transistor (T6), and the sixth transistor (T6) may be turned on or off in response to the light-emitting signal (EM[n]). For example, the sixth transistor (T6) may be turned on when the light-emitting signal (EM[n]) is low, and may be turned off when the light-emitting signal (EM[n]) is high.

[0104] In one embodiment of the present disclosure, the first terminal of the sixth transistor (T6) may be connected to the second terminal of the second transistor (T2), and the second terminal of the sixth transistor (T6) may be connected to the anode of the light-emitting element (D1). When the sixth transistor (T6) is turned off, the current (I D1 ) will not flow.

[0105] In one embodiment of the present disclosure, the gate of the seventh transistor (T7) may be connected to the (n-1)th scan wiring. A first scan signal (SC[n-1]) may be applied to the gate of the seventh transistor (T7), and the seventh transistor (T7) may be turned on or off in response to the first scan signal (SC[n-1]). For example, the seventh transistor (T7) may be turned on when the first scan signal (SC[n-1]) is low, and may be turned off when the first scan signal (SC[n-1]) is high.

[0106] In one embodiment of the present disclosure, a first terminal of the seventh transistor (T7) may be connected to a power line supplying an initialization voltage (Vini), and a second terminal of the seventh transistor (T7) may be connected to a gate of a second transistor (T2), a second terminal of a ninth transistor (T9), and a second terminal of a second capacitor (C2). When the seventh transistor (T7) is turned on, the initialization voltage (Vini) may be applied to the gate of the second transistor (T2).

[0107] In one embodiment of the present disclosure, the gate of the eighth transistor (T8) may be connected to the nth scan wiring. A second scan signal (SC[n]) may be applied to the gate of the eighth transistor (T8), and the eighth transistor (T8) may be turned on or off in response to the second scan signal (SC[n]). For example, the eighth transistor (T8) may be turned on when the second scan signal (SC[n]) is low, and may be turned off when the second scan signal (SC[n]) is high.

[0108] In one embodiment of the present disclosure, the first terminal of the eighth transistor (T8) is connected to a CCG data signal (V CCG_Data) can be connected to the wiring supplying the CCG data signal (V), and the second terminal of the eighth transistor (T8) can be connected to the first terminal of the first transistor (T1) and the second terminal of the fifth transistor (T5). When the eighth transistor (T8) is turned on, the CCG data signal (V) is supplied to the first terminal of the first transistor (T1). CCG_Data ) may be authorized.

[0109] In one embodiment of the present disclosure, the gate of the ninth transistor (T9) may be connected to the nth scan wiring. A second scan signal (SC[n]) may be applied to the gate of the ninth transistor (T9), and the ninth transistor (T9) may be turned on or off in response to the second scan signal (SC[n]). For example, the ninth transistor (T9) may be turned on when the second scan signal (SC[n]) is low, and may be turned off when the second scan signal (SC[n]) is high.

[0110] In one embodiment of the present disclosure, the first terminal of the ninth transistor (T9) is connected to a PWM data signal (V PWM_Data ) can be connected to the wiring supplying the PWM data signal (V ), and the second terminal of the ninth transistor (T9) can be connected to the gate of the second transistor (T2) and the second terminal of the second capacitor (C2). When the ninth transistor (T9) is turned on, the PWM data signal (V ) is applied to the gate of the second transistor (T2). PWM_Data ) may be authorized.

[0111] In one embodiment of the present disclosure, a first terminal of a first capacitor (C1) may be connected to a power wiring supplying a first power source (VDD), and a second terminal of the first capacitor (C1) may be connected to a gate of a first transistor (T1), a second terminal of a third transistor (T3), and a second terminal of a fourth transistor (T4).

[0112] In one embodiment of the present disclosure, a first terminal of the second capacitor (C2) may be connected to a wiring that supplies a step signal (STEP), and a second terminal of the second capacitor (C2) may be connected to a gate of a second transistor (T2), a second terminal of a seventh transistor (T7), and a second terminal of a ninth transistor (T9).

[0113] FIG. 6 illustrates the operation timing of a pixel circuit (500) according to one embodiment of the present disclosure.

[0114] FIG. 6 illustrates a case where the pixel circuit (500) operates in 4-bit mode and one frame includes four sub-frames, but the present disclosure is not limited thereto.

[0115] In one embodiment of the present disclosure, the pixel circuit (500) may operate in an initialization period (1), a sampling period (2), and an emission period (3) for each sub-frame. In one embodiment of the present disclosure, a holding period may be added between the sampling period and the emission period.

[0116] Each operation section can be distinguished by the first and second scan signals (SC[n-1], SC[n]) or the emission signal (EM[n]). In one embodiment of the present disclosure, in the initialization section, the first scan signal (SC[n-1]) can be a first value for turning on the transistor, and the second scan signal (SC[n]) can be a second value for turning off the transistor. In one embodiment of the present disclosure, in the sampling section, the first scan signal (SC[n-1]) can be a second value for turning off the transistor, and the second scan signal (SC[n]) can be a first value for turning on the transistor. In one embodiment of the present disclosure, in the emission section, the first and second scan signals (SC[n-1], SC[n]) can be a second value for turning off the transistor, and the emission signal (EM[n]) can be a first value for turning on the transistor. Here, the first value can be low and the second value can be high.

[0117] Similar to FIG. 4, in FIG. 6, the lengths of the light emission periods in the first to fourth subframes (subframe #1 to subframe #4) included in one frame may be different from each other, such as 3T, 12T, 48T, and 192T, respectively. Here, T is an arbitrary time period. Each subframe may operate in an initialization period, a sampling period, and a light emission period.

[0118] As described above, the total length of each subframe, including the initialization interval, the sampling interval, and the flashing interval, may be different in proportion to the length of the flashing interval. Conversely, each subframe may further include a holding interval of different lengths so that the total length of each subframe is the same.

[0119] Below, the state and operation of the pixel circuit (500) in each operation section are described with reference to FIGS. 7 to 9.

[0120] FIG. 7 illustrates the state of a pixel circuit (500) in an initialization period according to one embodiment of the present disclosure.

[0121] In one embodiment of the present disclosure, the initialization period may be a period for initializing the gate voltages of the first and second transistors (T1, T2). In the initialization period, the first scan signal (SC[n-1]) may be a first value for turning on the transistor, and the second scan signal (SC[n]) and the emission signal (EM[n]) may be second values ​​for turning off the transistor.

[0122] Referring to FIG. 7, in the initialization section, the fourth transistor (T4) and the seventh transistor (T7) may be turned on in response to the first scan signal (SC[n-1]) being a first value (e.g., low), and the third transistor (T3), the fifth transistor (T5), the sixth transistor (T6), the eighth transistor (T8), and the ninth transistor (T9) may be turned off in response to the second scan signal (SC[n]) and the emission signal (EM[n]) being a second value (e.g., high).

[0123] When the fourth transistor (T4) and the seventh transistor (T7) are turned on, the gate voltage of the first transistor (T1) can be initialized to the initialization voltage (Vini) through the fourth transistor (T4), and the gate voltage of the second transistor (T2) can be initialized to the initialization voltage (Vini) through the seventh transistor (T7).

[0124] FIG. 8 illustrates a state of a pixel circuit (500) in a sampling interval according to one embodiment of the present disclosure.

[0125] In one embodiment of the present disclosure, the sampling interval is a CCG data signal (V) to the pixel circuit (500). CCG_Data ) and PWM data signal (V PWM_Data) is applied, and the threshold voltage of the driving transistor is sampled. In the sampling period, the first scan signal (SC[n-1]) and the emission signal (EM[n]) may be the second value for turning off the transistor, and the second scan signal (SC[n]) may be the first value for turning on the transistor.

[0126] Referring to FIG. 8, in the sampling interval, the fourth transistor (T4), the fifth transistor (T5), the sixth transistor (T6), and the seventh transistor (T7) may be turned off in response to the first scan signal (SC[n-1]) and the emission signal (EM[n]) being a second value (e.g., high), and the third transistor (T3), the eighth transistor (T8), and the ninth transistor (T9) may be turned on in response to the second scan signal (SC[n]) being a first value (e.g., low).

[0127] When the third transistor (T3) and the eighth transistor (T8) are turned on, V is applied to the gate of the first transistor (T1) through the diode connection compensation of the first transistor (T1). CCG_Data - V th1 A voltage of can be applied. When the ninth transistor (T9) is turned on, V is applied to the gate of the second transistor (T2). PWM_Data A voltage of can be applied.

[0128] FIG. 9 illustrates a state of a pixel circuit (500) in a light-emitting section according to one embodiment of the present disclosure.

[0129] In one embodiment of the present disclosure, the light emitting section is configured to supply current (I) to the light emitting element (D1). D1 ) flows, and the light-emitting element (D1) emits light. In the light-emitting section, the first and second scan signals (SC[n-1], SC[n]) may be second values ​​for turning off the transistor, and the light-emitting signal (EM[n]) may be first values ​​for turning on the transistor.

[0130] Referring to FIG. 9, in the emission section, the third transistor (T3), the fourth transistor (T4), the seventh transistor (T7), the eighth transistor (T8), and the ninth transistor (T9) may be turned off in response to the first and second scan signals (SC[n-1], SC[n]) being a second value (e.g., high), and the fifth transistor (T5) and the sixth transistor (T6) may be turned on in response to the emission signal (EM[n]) being a first value (e.g., low).

[0131] When the fifth transistor (T5) is turned on, a first voltage (VDD) is applied to the first terminal of the first transistor (T1), and the gate-source voltage of the first transistor (T1) becomes lower than the threshold voltage of the first transistor (T1), so that the first transistor (T1) can be turned on.

[0132] Meanwhile, a step signal is applied to the first terminal of the second capacitor (C2), and the gate voltage of the second transistor (T2) changes according to the step signal (STEP) due to the coupling phenomenon of the second capacitor (C2). As described above with reference to FIGS. 3 and 4, when the gate-source voltage of the second transistor (T2) becomes smaller than the threshold voltage of the second transistor (T2), the second transistor (T2) can be turned on. At this time, the V applied in the sampling period PWM_Data Depending on the size of the second transistor (T2), the second transistor (T2) may be off throughout the entire light-emitting section, on throughout a portion of the light-emitting section, or on throughout the entire light-emitting section.

[0133] When the second transistor (T2) is turned on, a current having an amplitude determined by the gate-source voltage of the first transistor (T1) can flow through a path including the first voltage (VDD), the fifth transistor (T5), the first transistor (T1), the second transistor (T2), the sixth transistor (T6), the light-emitting element (D1), and the second voltage (VSS).

[0134] FIG. 10 illustrates an implementation example of a pixel circuit (1000) according to one embodiment of the present disclosure, and FIG. 11 illustrates the operation timing of a pixel circuit (1000) according to one embodiment of the present disclosure.

[0135] The pixel circuit (1000) of FIG. 10 is an example of implementing the pixel circuit (200) of FIG. 2 using an N-type transistor, but the implementation example of the pixel circuit (200) is not limited thereto. In the following description related to FIG. 10 and FIG. 11, the first terminal of the transistor may be a drain, and the second terminal may be a source.

[0136] Referring to FIG. 10, in one embodiment of the present disclosure, a pixel circuit (1000) may include a light-emitting element (D1), first to ninth transistors (T1 to T9), a first capacitor (C1), a second capacitor (C2), and a third capacitor (C3). In FIG. 10, the first and second transistors (T1, T2) may correspond to the first and second transistors (T1, T2) of the pixel circuit (200), the third transistor (T3), the seventh transistor (T7), the eighth transistor (T8), the first capacitor (C1), and the second capacitor (C2) may correspond to the CCG driver (210), and the sixth transistor (T6), the ninth transistor (T9), and the third capacitor (C3) may correspond to the PWM driver (220).

[0137] In the present disclosure, the first capacitor (C1) of FIG. 10 may be referred to as a third capacitor. In the present disclosure, the second capacitor (C2) of FIG. 10 may be referred to as a fourth capacitor. In the present disclosure, the third capacitor (C3) of FIG. 10 may be referred to as a fifth capacitor. In the present disclosure, the third transistor (T3) of FIG. 10 may be referred to as a tenth transistor. In the present disclosure, the fourth transistor (T4) of FIG. 10 may be referred to as an eleventh transistor. In the present disclosure, the fifth transistor (T5) of FIG. 10 may be referred to as a twelfth transistor. In the present disclosure, the sixth transistor (T6) of FIG. 10 may be referred to as a thirteenth transistor. In the present disclosure, the seventh transistor (T7) of FIG. 10 may be referred to as a fourteenth transistor. In the present disclosure, the eighth transistor (T8) of FIG. 10 may be referred to as a fifteenth transistor. In the present disclosure, the ninth transistor (T9) of FIG. 10 may also be referred to as the sixteenth transistor.

[0138] In one embodiment of the present disclosure, the first to ninth transistors (T1 to T9) are configured to receive a first initialization voltage (V ini1 ), second initialization voltage (V ini2 ), can be turned on or off in response to a scan signal (SC[n]), a first emission signal (EM1[n]) and a second emission signal (EM2[n]). In one embodiment of the present disclosure, the first and second initialization voltages (V ini1 , V ini2 ) can be applied by a power supply unit (140 in FIG. 1), the scan signal (SC[n]) can be a scan signal applied to the n-th scan wire, and the first and second light-emitting signals (EM1[n], EM2[n]) can be applied by a plurality of light-emitting drivers. As described below, the voltage of each node in the pixel circuit (1000) can change and the current of the light-emitting element (D1) can change depending on the state (i.e., on or off) of the first to ninth transistors (T1 to T9).

[0139] In one embodiment of the present disclosure, the first to ninth transistors (T1 to T9) may be low-temperature polycrystalline silicon thin film transistors (LTPS TFTs), oxide thin film transistors (Oxide TFTs), low-temperature polycrystalline silicon oxide (LTPO), or silicon-based switching elements.

[0140] Referring to FIG. 11, in one embodiment of the present disclosure, the pixel circuit (1000) may operate in an initialization period, a sampling period, and an emission period for each subframe (subframe #1 to subframe #4). In one embodiment of the present disclosure, a holding period may be added between the sampling period and the emission period.

[0141] Each operating section has a first initialization voltage (V ini1 ), second initialization voltage (V ini2 ), can be distinguished by a scan signal (SC[n]), a first emission signal (EM1[n]), and a second emission signal (EM2[n]).

[0142] In one embodiment of the present disclosure, in the initialization period, the scan signal (SC[n]) and the second emission signal (EM2[n]) may be second values ​​for turning off the transistor.

[0143] In one embodiment of the present disclosure, the initialization period comprises a first initialization voltage (V ini1 ) is the first value to turn on the transistor, and the second initialization voltage (V ini2 ) and a first initialization period in which the first emission signal (EM1[n]) is a second value for turning off the transistor. In the first initialization period, the first initialization voltage (Vini1 ) can be turned on in response to the first value being the eighth transistor (T8) and the ninth transistor (T9).

[0144] In one embodiment of the present disclosure, the initialization period comprises a first initialization voltage (V ini1 ) and the second initialization voltage (V ini2 ) may include a second initialization period in which the first value for turning on the transistor and the first light emitting signal (EM1[n]) is a second value for turning off the transistor. In the second initialization period, the first initialization voltage (V ini1 ) and the second initialization voltage (V ini2 ) can be turned on in response to the first value being the third transistor (T3), the eighth transistor (T8), and the ninth transistor (T9). The third transistor (T3) can have a second terminal connected to the gate of the first transistor (T1) to apply a reference voltage (Vref).

[0145] In one embodiment of the present disclosure, the initialization period comprises a first initialization voltage (V ini1 ) is the second value to turn off the transistor, and the second initialization voltage (V ini2 ) and a third initialization period in which the first emission signal (EM1[n]) is a first value for turning on the transistor. In the third initialization period, the second initialization voltage (V ini2 ) and the third transistor (T3) and the fourth transistor (T4) can be turned on in response to the first light emitting signal (EM1[n]) being the first value.

[0146] In one embodiment of the present disclosure, the sampling interval includes a first initialization voltage (V ini1 ), second initialization voltage (V ini2 ), the first emission signal (EM1[n]) and the second emission signal (EM2[n]) may be second values ​​for turning off the transistor.

[0147] In one embodiment of the present disclosure, the sampling interval may include a first sampling interval in which the scan signal (SC[n]) is a first value for turning on the transistor. In the first sampling interval, the sixth transistor (T6) and the seventh transistor (T7) may be turned on in response to the scan signal (SC[n]) being the first value. In the first sampling interval, the CCG data signal (V CCG_Data ) can be applied to the gate of the first transistor (T1), and the PWM data signal (V PWM_Data ) can be applied to the gate of the second transistor (T2).

[0148] In one embodiment of the present disclosure, the sampling interval may include a second sampling interval in which the scan signal (SC[n]) is a second value for turning off the transistor. In the second sampling interval, the sixth transistor (T6) and the seventh transistor (T7) may be turned off in response to the scan signal (SC[n]) being the second value.

[0149] In one embodiment of the present disclosure, in the light-emitting section, the first light-emitting signal (EM1[n]) and the second light-emitting signal (EM2[n]) may be first values ​​for turning on the transistors. In response to the first light-emitting signal (EM1[n]) and the second light-emitting signal (EM2[n]) being the first values, the fourth transistor (T4) and the fifth transistor (T5) may be turned on.

[0150] In one embodiment of the present disclosure, a step signal (STEP) is applied in the light-emitting section, and the gate voltage of the second transistor (T2) can change according to the step signal (STEP) by the coupling phenomenon of the third capacitor (C3). When the gate-source voltage of the second transistor (T2) increases according to the step signal (STEP) and becomes higher than the threshold voltage of the second transistor (T2), the second transistor (T2) is turned on, and current can flow to the light-emitting element (D1). In the sampling section, V applied PWM_DataDepending on the size of the second transistor (T2), the second transistor (T2) may be off throughout the entire light-emitting section, on throughout a portion of the light-emitting section, or on throughout the entire light-emitting section.

[0151] A display panel according to one embodiment of the present disclosure may include a plurality of pixels that divide one frame into a plurality of sub-frames and display the same, and each of the plurality of pixels may include a light-emitting element, a first transistor that controls the amplitude of a current flowing in the light-emitting element, a second transistor that controls the time for which the current flows in the light-emitting element in each of the plurality of sub-frames, a CCG (Constant Current Generation) driver that controls the first transistor based on a first data signal, and a PWM (Pulse Width Modulation) driver that controls the second transistor so that the second transistor is turned on for a time corresponding to a second data signal and a step signal in each of the plurality of sub-frames, and the second data signal may be determined based on a gray level that the pixel can express in each of the plurality of sub-frames, and the step signal may include a number of steps determined based on the second data signal.

[0152] In one embodiment of the present disclosure, the amplitude of each step included in the step signal can be determined based on the number of values ​​that the second data signal can have.

[0153] In one embodiment of the present disclosure, the time length of each step included in the step signal can be determined based on the time length of the light emission period of the corresponding subframe and the number of steps included in the step signal.

[0154] In one embodiment of the present disclosure, the CCG driving unit may include a first capacitor having a first terminal connected to a first power source and a second terminal connected to a gate of the first transistor, a third transistor having a first terminal connected to a second terminal of the first transistor and a second terminal connected to a gate of the first transistor, a fourth transistor having a second terminal connected to the gate of the first transistor and applying an initialization voltage, and an eighth transistor having a second terminal connected to the first terminal of the first transistor and applying the first data signal.

[0155] In one embodiment of the present disclosure, the PWM driving unit may include a second capacitor having a second terminal connected to a gate of the second transistor to apply the step signal, a seventh transistor having a second terminal connected to a gate of the second transistor to apply an initialization voltage, and a ninth transistor having a second terminal connected to a gate of the second transistor to apply the second data signal.

[0156] In one embodiment of the present disclosure, the pixel may further include a fifth transistor having a second terminal connected to a first terminal of the first transistor to apply a first voltage, and a sixth transistor having a first terminal connected to a second terminal of the second transistor and a second terminal connected to an anode of the light-emitting element.

[0157] In one embodiment of the present disclosure, the pixel can operate in an initialization period, a sampling period, and a light emission period for each of the plurality of sub-frames, and in the initialization period, the fourth transistor and the seventh transistor can be turned on, and the initialization voltage can be applied to the gate of the first transistor and the gate of the second transistor.

[0158] In one embodiment of the present disclosure, in the sampling period, the third transistor, the eighth transistor, and the ninth transistor may be turned on, the first data signal may be applied to a first terminal of the first transistor, a voltage determined based on the first data signal and a threshold voltage of the first transistor may be applied to a gate of the first transistor, and the second data signal may be applied to a gate of the second transistor.

[0159] In one embodiment of the present disclosure, in the light-emitting section, the first transistor, the fifth transistor, and the sixth transistor can be turned on, the step signal can be applied to the gate of the second transistor through the second capacitor, and the gate voltage of the second transistor can change according to the step signal.

[0160] In one embodiment of the present disclosure, the time length of the light emission period of each of the plurality of sub-frames may be different.

[0161] In one embodiment of the present disclosure, the CCG driving unit may include a third capacitor, a fourth capacitor having a first terminal connected to a second terminal of the third capacitor and a second terminal connected to a gate of the first transistor, a tenth transistor having a second terminal connected to a gate of the first transistor to apply a reference voltage, a fourteenth transistor having a second terminal connected to a gate of the first transistor to apply the first data signal, and a fifteenth transistor having a first terminal connected to a first terminal of the fourth capacitor and a second terminal connected to a second power source.

[0162] In one embodiment of the present disclosure, the PWM driving unit may include a fifth capacitor having a second terminal connected to a gate of the second transistor to apply the step signal, a thirteenth transistor having a second terminal connected to a gate of the second transistor to apply the second data signal, and a sixteenth transistor having a first terminal connected to the gate of the second transistor and a second terminal connected to a second power source.

[0163] In one embodiment of the present disclosure, the pixel may further include an eleventh transistor applying a first voltage, a first terminal of which is connected to a first power source and a second terminal of which is connected to a first terminal of the first transistor, and a twelfth transistor having a first terminal of which is connected to a second terminal of the first transistor and a second terminal of which is connected to a first terminal of the second transistor.

[0164] In one embodiment of the present disclosure, in a first initialization period, the 15th transistor and the 16th transistor may be turned on, in a second initialization period, the 10th transistor, the 15th transistor, and the 16th transistor may be turned on, and in a third initialization period, the 10th transistor and the 11th transistor may be turned on.

[0165] In one embodiment of the present disclosure, in a first sampling period, the 13th transistor and the 14th transistor may be turned on, the first data signal may be applied to a gate of the first transistor, the second data signal may be applied to a gate of the second transistor, and in a second sampling period, the 13th transistor and the 14th transistor may be turned off.

[0166] In one embodiment of the present disclosure, in the light-emitting section, the first transistor, the eleventh transistor, and the twelfth transistor can be turned on, the step signal can be applied to the gate of the second transistor through the fifth capacitor, and the gate voltage of the second transistor can change according to the step signal.

Claims

1. In a display panel (100) including a plurality of pixels (161) that divide one frame into a plurality of sub-frames and display them, Each of the above plurality of pixels (161) is Light-emitting element (D1); A first transistor (T1) that controls the amplitude of the current flowing through the light-emitting element (D1); In each of the plurality of sub-frames, a second transistor (T2) that controls the time for which the current flows to the light-emitting element (D1); A CCG (Constant Current Generation) driver (210) that controls the first transistor based on a first data signal; and In each of the plurality of sub-frames, a PWM (Pulse Width Modulation) driving unit (220) that controls the second transistor (T2) so that the second transistor (T2) is turned on for a time corresponding to the second data signal and the step signal; Including, The second data signal is determined based on the gray level that the pixel (161) can express in each of the plurality of sub-frames, The step signal includes a number of steps determined based on the second data signal, Display panel (100).

2. In paragraph 1, A display panel (100) in which the amplitude of each step included in the step signal is determined based on the number of values ​​that the second data signal can have.

3. In paragraph 1 or 2, A display panel (100) in which the time length of each step included in the step signal is determined based on the time length of the light emission section of the corresponding subframe and the number of steps included in the step signal.

4. In any one of paragraphs 1 to 3, The above CCG driving unit (210) is A first capacitor (C1) having a first terminal connected to a first power source (VDD) and a second terminal connected to a gate of the first transistor (T1); A third transistor (T3) having a first terminal connected to a second terminal of the first transistor (T1) and a second terminal connected to a gate of the first transistor (T1); A fourth transistor (T4) having a second terminal connected to the gate of the first transistor (T1) to apply an initialization voltage (Vini); and An eighth transistor (T8) having a second terminal connected to the first terminal of the first transistor (T1) to apply the first data signal; A display panel (100) including:

5. In any one of paragraphs 1 to 4, The above PWM driving unit (220) is A second capacitor (C2) having a second terminal connected to the gate of the second transistor (T2) to apply the step signal; A seventh transistor (T7) having a second terminal connected to the gate of the second transistor (T2) to apply an initialization voltage (Vini); and A ninth transistor (T9) having a second terminal connected to the gate of the second transistor (T2) to apply the second data signal; A display panel (100) including:

6. In any one of paragraphs 1 to 5, The above pixel (161) is, A fifth transistor (T5) having a second terminal connected to the first terminal of the first transistor (T1) to apply a first voltage (VDD); and A sixth transistor (T6) having a first terminal connected to a second terminal of the second transistor (T2) and a second terminal connected to an anode of the light emitting element (D1); A display panel (100) further comprising:

7. In any one of paragraphs 1 to 6, The above pixel (161) operates in an initialization section, a sampling section, and a light emission section for each of the plurality of sub-frames, In the above initialization section, The fourth transistor (T4) and the seventh transistor (T7) are turned on, A display panel (100) in which the initialization voltage (Vini) is applied to the gate of the first transistor (T1) and the gate of the second transistor (T2).

8. In any one of paragraphs 1 to 7, In the above sampling interval, The third transistor (T3), the eighth transistor (T8), and the ninth transistor (T9) are turned on, The first data signal is applied to the first terminal of the first transistor (T1), A voltage determined based on the first data signal and the threshold voltage of the first transistor (T1) is applied to the gate of the first transistor (T1), A display panel (100) in which the second data signal is applied to the gate of the second transistor (T2).

9. In any one of paragraphs 1 to 8, In the luminous section, The first transistor (T1), the fifth transistor (T5), and the sixth transistor (T6) are turned on, The step signal is applied to the gate of the second transistor (T2) through the second capacitor (C2), The gate voltage of the second transistor (T2) changes according to the step signal, in a display panel (100).

10. In any one of paragraphs 1 to 9, The time length of the light emission section of each of the plurality of sub-frames is all different, display panel (100).

11. In any one of paragraphs 1 to 3, The above CCG driving unit (210) is Third capacitor (C1); A fourth capacitor (C2) having a first terminal connected to a second terminal of the third capacitor (C1) and a second terminal connected to a gate of the first transistor (T1); A tenth transistor (T3) having a second terminal connected to the gate of the first transistor (T1) to apply a reference voltage; A 14th transistor (T7) having a second terminal connected to the gate of the first transistor (T1) to apply the first data signal; and A fifteenth transistor (T8) having a first terminal connected to a first terminal of the fourth capacitor (C2) and a second terminal connected to a second power source (VSS); A display panel (100) including:

12. In any one of paragraphs 1 to 4 and paragraph 11, The above PWM driving unit (220) is A fifth capacitor (C3) having a second terminal connected to the gate of the second transistor (T2) to apply the step signal; A 13th transistor (T6) having a second terminal connected to the gate of the second transistor (T2) to apply the second data signal; and A 16th transistor (T9) having a first terminal connected to the gate of the second transistor (T2) and a second terminal connected to the second power supply (VSS); A display panel (100) including:

13. In any one of paragraphs 1 to 5, paragraph 11, and paragraph 12, The above pixel (161) is, An eleventh transistor (T4) having a first terminal connected to a first power source (VDD) and a second terminal connected to a first terminal of the first transistor (T1); and A display panel (100) further comprising a twelfth transistor (T5) having a first terminal connected to a second terminal of the first transistor (T1) and a second terminal connected to a first terminal of the second transistor (T2).

14. In any one of paragraphs 1 to 13, In the first initialization section, the 15th transistor (T8) and the 16th transistor (T9) are turned on, In the second initialization section, the 10th transistor (T3), the 15th transistor (T8), and the 16th transistor (T9) are turned on, In the third initialization section, the display panel (100) in which the 10th transistor (T3) and the 11th transistor (T4) are turned on.

15. In any one of paragraphs 1 to 14, In the first sampling period, the 13th transistor (T6) and the 14th transistor (T7) are turned on, the first data signal is applied to the gate of the first transistor (T1), and the second data signal is applied to the gate of the second transistor (T2). In the second sampling period, the display panel (100) in which the 13th transistor (T6) and the 14th transistor (T7) are turned off.

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