Task scheduling method and apparatus, and device, storage medium and program product

Abstract

A task scheduling method, comprising: during the process in which a first scheduler creates a first computing task, modifying task submission information of the first computing task by means of a second scheduler, wherein the first computing task has a first priority (220); during the process in which the first scheduler submits the first computing task on the basis of the modified task submission information, sensing submission of the first computing task by means of the second scheduler (240); and when the submission of the first computing task has been sensed by means of the second scheduler, suspending execution of a second computing task, and submitting the first computing task to a processor and running same (260), wherein the second computing task has a second priority, and the first priority is higher than the second priority.

Description

Task scheduling method, device, equipment, storage medium and program product

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on March 11, 2024, with application number 202410279265.3 and application name “Task Scheduling Method, Apparatus, Equipment and Medium”, all contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of cloud servers, and in particular to a task scheduling method, apparatus, device and medium. Background Art

[0003] Current artificial intelligence (AI) tasks are performed by hardware acceleration processors such as graphics processing units (GPUs) or neural network processing units (NPUs).

[0004] In some technologies, the GPU / NPU's computing time is divided into different time slices. When different computing tasks are submitted to the GPU / NPU, a time-slice-based scheduler runs each task in the order in which they were submitted.

[0005] However, since different computing tasks have different real-time requirements, the above scheduling method cannot meet the needs of computing tasks with higher real-time requirements, affecting the service quality of computing tasks with higher real-time requirements. Summary of the Invention

[0006] According to various embodiments of the present application, a task scheduling method is provided, the method comprising:

[0007] During the process of creating a first computing task by the first scheduler, modifying task submission information of the first computing task by the second scheduler, the first computing task having a first priority;

[0008] In the process of the first scheduler submitting the first computing task based on the task submission information, the second scheduler senses the submission of the first computing task;

[0009] When the second scheduler senses the submission of the first computing task, pausing the execution of the second computing task and submitting the first computing task to the processor for execution, the second computing task having a second priority;

[0010] The first priority is higher than the second priority.

[0011] A task scheduling device is provided, the device comprising: a first scheduler module and a second scheduler module;

[0012] The second scheduler module is configured to modify task submission information of a first computing task during a process in which the first scheduler module creates the first computing task, the first computing task having a first priority;

[0013] The second scheduler module is configured to sense submission of the first computing task during a process in which the first scheduler module submits the first computing task based on the task submission information;

[0014] The second scheduler module is configured to, upon sensing submission of the first computing task, suspend execution of a second computing task and submit the first computing task to the processor for execution, wherein the second computing task has a second priority;

[0015] The first priority is higher than the second priority.

[0016] A computer device is provided, comprising: a processor, a memory, and a hardware acceleration processor, wherein the memory stores at least one segment of computer-readable instructions; and the processor is configured to execute the at least one segment of computer-readable instructions in the memory to implement the task scheduling method described above.

[0017] A non-volatile computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer-readable instructions, and the computer-readable instructions are loaded and executed by a processor to implement the task scheduling method described above.

[0018] A computer program product is provided, which includes computer-readable instructions stored in a computer-readable storage medium. A processor of a computer device reads and executes the computer-readable instructions from the computer-readable storage medium to implement the task scheduling method described above.

[0019] The details of one or more embodiments of the present application are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0021] FIG1 is a structural block diagram of a computer device provided in some embodiments of the present application;

[0022] FIG2 is a flowchart of a task scheduling method provided by some embodiments of the present application;

[0023] FIG3 is a schematic diagram of the direction of task submission information before and after modification provided in some embodiments of the present application;

[0024] FIG4 is a flowchart of a task scheduling method provided by some embodiments of the present application;

[0025] FIG5 is a schematic diagram of the architecture of a cloud computing system provided by some embodiments of the present application;

[0026] FIG6 is a flowchart of a method for notifying a priority of a computing task provided by some embodiments of the present application;

[0027] FIG7 is a flowchart of a method for prefetching information for a computing task provided by some embodiments of the present application;

[0028] FIG8 is a flowchart of a task scheduling method provided by some embodiments of the present application;

[0029] FIG9 is a flowchart of a method for pausing a second priority task provided by some embodiments of the present application;

[0030] FIG10 is a flowchart of a method for submitting a native computing task provided by some embodiments of the present application;

[0031] FIG11 is a flowchart of a method for submitting an online task (a high-priority task or a first-priority task) according to some embodiments of the present application;

[0032] FIG12 is a flowchart of a method for submitting an offline task (a low-priority task or a second-priority task) according to some embodiments of the present application;

[0033] FIG13 is a block diagram of a task scheduling device provided by some embodiments of the present application;

[0034] FIG14 is a block diagram of a computer device provided in some embodiments of the present application. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0036] Kubernetes is an open-source container orchestration engine used to automate the deployment, scaling, and management of containerized applications. Kubernetes is abbreviated as K8s.

[0037] Containers are a type of sandbox technology whose main purpose is to isolate applications from the outside world and to facilitate the transfer of this sandbox to other host machines.

[0038] Processor: A unit in a computer device that performs computing tasks. Processors can be divided into at least one of the following: a central processing unit (CPU), an accelerated processing unit (APU), a neural network processing unit (NPU), a deep learning processing unit (DPU), a floating point calculator (FPU), a holographic processing unit (HPU), an intelligent processing unit (IPU), a tensor processing unit (TPU), a vector processing unit (VPU), and an intelligent cloud acceleration processor.

[0039] Hardware acceleration processor: A processor other than the CPU that has accelerated computing capabilities for certain types of operations. This processor can be at least one of the aforementioned GPUs, NPUs, DPUs, FPUs, HPUs, IPUs, TPUs, VPUs, and intelligent cloud acceleration processors.

[0040] 1 shows a block diagram of a computer device 100 according to an exemplary embodiment of the present application. The computer device 100 includes a central processing unit 120 , a system memory 140 , and at least one hardware acceleration processor 160 .

[0041] The central processing unit 120 is used to create and schedule various computing tasks. Different computing tasks can have different priorities. A first scheduler 122 and a second scheduler 124 are running in the central processing unit 120. The schedulers use different scheduling strategies to decide which task should obtain the time slice of computing resources (such as CPU, GPU or NPU) and when to obtain it. Among them, the first scheduler 122 is a native task scheduler, such as the task scheduler natively provided in the K8s system; the second scheduler 124 is a custom task scheduler newly added in this application. The first scheduler 122 does not have the ability to schedule computing tasks based on priority, and the second scheduler 124 has the ability to schedule computing tasks based on priority. In this application, without significantly modifying the working mechanism of the first scheduler 122, the second scheduler 124 can take over the computing tasks submitted by the first scheduler 122 to the operating system, and the second scheduler 124 re-schedules each computing task based on priority. Optionally, an operating system runs on the computer device 100, and the operating system includes a kernel layer and an application layer. The first scheduler 122 is a scheduler located at the application layer, and the second scheduler 124 is a scheduler located at the application layer or the kernel layer.

[0042] System memory 140 is used to provide the memory space required by the CPU 120 during operation. System memory 140 is a type of memory. Memory can also include other forms of memory such as flash memory and hard disk.

[0043] At least one hardware acceleration processor 160 is configured to execute various computing tasks in a hardware-accelerated manner. The hardware acceleration processor 160 may be a GPU or an NPU. The computing tasks may be those related to artificial intelligence (AI), such as face recognition tasks or question-answering tasks based on natural language processing.

[0044] The computer device 100 can be implemented as a server in cloud computing. The server can be an independent physical server, or a server cluster or distributed system composed of multiple physical servers. It can also be a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, content delivery networks (CDN), and big data and artificial intelligence platforms. The terminal can be a smart phone, tablet computer, laptop computer, desktop computer, smart speaker, smart watch, etc., but is not limited to this. The terminal and the server can be directly or indirectly connected via wired or wireless communication, and this application is not limited here.

[0045] The embodiments of the present application provide a task scheduling method that can schedule multiple computing tasks according to their priorities. When a high-priority computing task is running, it is allowed to preempt a low-priority computing task in real time and fully occupy the time slice; when a high-priority computing task is idle, the time slice is released to the low-priority computing task, thereby achieving mixed deployment of computing tasks of different priorities. Among them, the high-priority computing task can be simply referred to as a high-priority task, and the low-priority computing task can be simply referred to as a low-priority task.

[0046] FIG2 shows a flowchart of a task scheduling method according to some exemplary embodiments of the present application. The method may be executed by the central processing unit 120 in the computer device 100. For example, the method may be executed collaboratively by a first scheduler and a second scheduler running in the central processing unit 120. The method includes:

[0047] Step 220: During the process of creating the first computing task by the first scheduler, modifying the task submission information of the first computing task by the second scheduler, so that the first computing task has a first priority;

[0048] The first scheduler has the ability to create and submit computing tasks. The ability to create computing tasks refers to the ability to initialize and generate a computing task. The ability to submit computing tasks refers to the ability to submit computing tasks to the processor for execution. The processor can be a central processing unit or a hardware acceleration processor. In this embodiment, the hardware acceleration processor is taken as an example. In some embodiments, the first scheduler is a native scheduler of the hardware accelerated computing system. Taking the hardware accelerated computing system as K8s as an example, the first scheduler is the native scheduler provided by K8s. The first scheduler does not have the ability to schedule computing tasks according to priority. Optionally, the first scheduler has the ability to schedule computing tasks according to time slices.

[0049] The task submission information of the first computing task is information related to submitting the first computing task to the processor for execution. Optionally, the task submission information of the first computing task includes address information indicating a storage location of control information used to control the first computing task. Optionally, the storage location stores a device control bit for the first computing task, and the device control bit is used to control the start or pause of the first computing task.

[0050] The second scheduler is a custom scheduler newly added in this embodiment. The second scheduler has the ability to schedule computing tasks according to priority. Optionally, in order to prevent the first scheduler from directly submitting the first computing task to the processor for execution, the second scheduler needs to modify the task submission information of the first computing task. The modified task submission information points to the target storage location specified by the second scheduler. Optionally, the modified task submission information points to the target storage location in the system memory specified by the second scheduler. Optionally, the target storage location stores the device control bit of the first computing task.

[0051] The first computing task has a first priority. The first priority is higher than the second priority. That is, the first priority is a high priority and the second priority is a low priority. In some embodiments, there may be more than three priorities, and the first priority and the second priority can be understood as any two priorities among the three or more priorities.

[0052] Step 240: During the process of the first scheduler submitting the first computing task based on the modified task submission information, the second scheduler senses the submission of the first computing task;

[0053] Because the task submission information is modified by the second scheduler, the second scheduler perceives the submission of the first computing task while the first scheduler is submitting the first computing task based on the modified task submission information. In other words, the second scheduler can perceive the submission of the first computing task, the submission of the first computing task, or the submission progress of the first computing task in real time.

[0054] Step 260: When the second scheduler senses the submission of the first computing task, suspending the execution of the second computing task and submitting the first computing task to the processor for execution, the second computing task having a second priority;

[0055] When the second scheduler senses the submission of the first computing task, it suspends the execution of the second computing task and submits the first computing task to the processor for execution.

[0056] The first computing task has a first priority, the second computing task has a second priority, and the first priority is higher than the second priority.

[0057] In summary, the method provided by this embodiment is that since the first scheduler does not have the ability to schedule computing tasks based on priority, by adding a second scheduler on the basis of the native first scheduler, the second scheduler has the ability to schedule computing tasks based on priority. When the native first scheduler does not need to be significantly modified, the task submission information of the first computing task is modified by the second scheduler, and the first scheduler can submit the first computing task to the target storage location according to the original process and based on the target storage location specified by the modified task submission information. At this time, the second scheduler can perceive the submission of the first computing task, and the second scheduler will take over the actual task submission process of the first computing task and suspend the operation of the second computing task with a low priority. In this way, the computing task with a high priority is run first and the computing task with a low priority is suspended by the second scheduler. This can meet the computing requirements of computing tasks with higher real-time requirements, improve the service quality of computing tasks with higher real-time requirements, and significantly improve the utilization rate of computing resources of computer equipment, achieve full utilization of resources, and reduce resource waste.

[0058] In one example, with reference to FIG3 , the task submission information before modification is allocated by the operating system for the first computing task. The task submission information before modification points to the first storage location allocated by the operating system for the first computing task, for example, the first storage location is located in the hardware acceleration processor 160; the task submission information after modification points to the target storage location specified by the second scheduler, for example, the target storage location is located in the system memory 140.

[0059] During the process of the first scheduler submitting the first computing task to the target storage location using the modified task submission information, the second scheduler can sense the submission (or submission or submission progress) of the first computing task. However, the submitted first computing task will not be triggered to run at this time. The first computing task will only be triggered to run when the second scheduler actually submits the first computing task to the processor.

[0060] In the above process, the second scheduler can take over the work of the first scheduler without the knowledge of the first scheduler by modifying the task submission information of the first computing task. That is, the second scheduler can take over the work of the first scheduler without changing the working mechanism of the first scheduler.

[0061] FIG4 shows a flow chart of a task scheduling method according to an exemplary embodiment of the present application. The method includes:

[0062] Step 320: During the process of the first scheduler creating the first computing task to the operating system, modify the task submission information of the first computing task through the second scheduler;

[0063] The task submission information is information related to the submission of the first computing task to the processor for execution. The task submission information before modification is allocated by the operating system. Optionally, the task submission information includes address information, which is used to indicate the storage location when the first computing task is submitted. Optionally, the storage location stores a device control bit for the first computing task, which is used to control the start or pause of the first computing task. The processor can be a central processing unit or a hardware acceleration processor. This embodiment uses the hardware acceleration processor as an example for illustration.

[0064] To prevent the first scheduler from directly submitting the first computing task to the processor for execution, the second scheduler modifies the task submission information of the first computing task, where the task submission information before the modification is the task submission information assigned to the first computing task by the operating system. Optionally, the process includes the following steps 322 to 326.

[0065] Step 322: During the process of creating the first computing task by the first scheduler, obtain first address information allocated by the operating system to the first computing task, where the first address information points to a first storage location in the processor;

[0066] Taking the processor as a hardware acceleration processor as an example, during the initialization process of the first scheduler creating a first computing task to the operating system, memory mapping (mmap) technology is needed to obtain first address information. The first address information is the address information allocated by the operating system to the first computing task, and the first address information points to the first storage location in the hardware acceleration processor.

[0067] When the operating system returns the first address information to the first scheduler, the second scheduler intercepts the first address information, wherein the first address information includes a first address pointer and a first address length.

[0068] Step 324: Replace the first address information with second address information, where the second address information points to a target storage location in the system memory;

[0069] The second scheduler applies to the system memory for a memory page as a masquerading memory page for the first computing task. The masquerading memory page has second address information. The second address information includes a second address pointer and a second address length. Optionally, the second address length is greater than or equal to the first address length.

[0070] The second scheduler replaces the first address information with the second address information.

[0071] Step 326: Save the correspondence between the first computing task, the first priority, the first address information, and the second address information, and return the second address information to the first scheduler.

[0072] The second scheduler applies for a pseudo-memory page, which impersonates the physical page actually allocated by the operating system. This allows the first scheduler to write the first computing task into the pseudo-memory page requested by the second scheduler when submitting the first computing task. Because the first computing task is not actually written to the real physical page, it does not trigger the execution of the first computing task. This allows the second scheduler to smoothly take over the work of the first scheduler without changing the operating mechanism of the first scheduler.

[0073] Optionally, since the priority of the first computing task is the first priority, the second scheduler further sets write protection permission for the impersonated memory page applied for the first computing task, that is, sets write protection permission for the second address information.

[0074] It should be noted that when the first scheduler creates a second computing task with a second priority, a similar process to steps 322 through 326 is also executed. Specifically, when the first scheduler creates the second computing task for the operating system, the second scheduler modifies the task submission information assigned by the operating system to the second computing task. In other words, regardless of the priority of the computing task, the actual triggering and submission is completed by the second scheduler.

[0075] Optionally, during the process of creating the second computing task by the first scheduler, the first scheduler may obtain third address information assigned by the operating system for the second computing task. The third address information points to a second storage location in the (hardware accelerated) processor. Optionally, during the initialization process of the first scheduler creating the second computing task for the operating system, the mmap technique may be used to obtain the third address information assigned by the operating system for the second computing task. The third address information points to the second storage location. When the operating system returns the third address information to the first scheduler, the second scheduler intercepts the third address information. The third address information includes a third address pointer and a third address length. The second scheduler replaces the third address information with fourth address information, which points to a storage location in system memory. For the second computing task, the second scheduler requests a pseudo memory page from the system memory. The pseudo memory page has fourth address information. The fourth address information includes a fourth address pointer and a fourth address length. Optionally, the fourth address length is greater than or equal to the third address length. The second scheduler stores the correspondence between the second computing task, the second priority, the third address information, and the fourth address information, and returns the fourth address information to the first scheduler.

[0076] It should be noted that for the second computing task with the second priority, there is no need to set write protection permissions for the impersonated memory page applied for the second computing task through the second scheduler, that is, there is no need to set write protection permissions for the fourth address information.

[0077] Step 340: During the process of the first scheduler submitting the first computing task to the target storage location based on the task submission information, the second scheduler senses the submission of the first computing task;

[0078] Because the target storage location is the storage location specified by the second scheduler, the second scheduler detects information related to the target storage location and is able to detect the submission of the first computing task. "Detecting the submission of the first computing task" can be understood as: detecting that the first computing task has been submitted by the first scheduler, or detecting the submission progress of the first computing task.

[0079] The second scheduler senses the submission of the first computing task in at least three ways, and different embodiments may use any one or at least one of the following:

[0080] Perception method 1: Perception based on system error information; the system error information is triggered when the first scheduler submits the first computing task to the target storage location;

[0081] Perception method 2: Perception based on target storage location;

[0082] Perception method three: based on control channel perception; computing tasks of the first priority correspond to the first submission channel, and computing tasks of the second priority correspond to the second submission channel.

[0083] For perception method 1, the following steps may be optional:

[0084] Step 342: Obtain system error information through the second scheduler;

[0085] The second scheduler detects system error information generated in the operating system. Optionally, the system error information is a memory page fault.

[0086] Step 344: When the system error information is triggered by the first scheduler failing to write to the target storage location due to write protection permission when submitting the first computing task to the target storage location through task submission information, the second scheduler senses the submission of the first computing task based on the system error information.

[0087] Because the target storage location is write-protected, when the first scheduler attempts to write to the target storage location using the modified task submission information, it will be unable to write due to the write protection, triggering a memory page fault exception. If the system error information detected by the second scheduler is triggered by the above reason, the second scheduler will be aware of the submission of the first computing task.

[0088] Perception method 1 cleverly utilizes the memory page fault exception mechanism of the operating system. The second scheduler sets write protection permissions for the second address information in advance. Then, when the first scheduler submits the first computing task, a memory page fault exception is triggered due to the write protection permissions, thereby enabling the second scheduler to perceive the submission timing of the first computing task by the first scheduler in real time.

[0089] For the second sensing method, the second scheduler can periodically detect the state (enabled or disabled) of the device control bit corresponding to the first computing task in the target storage location. When the first scheduler submits the first computing task to the target storage location, the device control bit corresponding to the first computing task is modified to the enabled state, and the enabled state represents the execution of the first computing task. If the second scheduler detects that the device control bit corresponding to the first computing task is modified to the first value, it senses that the first scheduler submits the first computing task to the target storage location.

[0090] For perception method three, a first submission channel (such as a first submission function interface) can be designed in advance for the computing task of the first priority, and a second submission channel (such as a second submission function interface) can be designed in advance for the computing task of the second priority. The second scheduler can perceive the submission of the first computing task by monitoring the first submission channel.

[0091] It should be noted that in the second and third perception methods, there is no need for the second scheduler to set write protection permissions for the target storage location pointed to by the second address information, otherwise the first scheduler cannot write information to the target storage location.

[0092] Step 360: pausing the execution of the second computing task when the second scheduler senses the submission of the first computing task, and submitting the first computing task to the processor for execution, wherein the second computing task has a second priority;

[0093] If at least one second computing task has not yet completed, the second scheduler will suspend the execution of all second computing tasks and submit the first computing task to the processor for execution, thereby enabling the first computing task to preempt the time slice of the second computing task and be executed first.

[0094] In some embodiments, the second scheduler is provided with an operation mode bit (or operation state), which is used to indicate one of a first priority mode (also called a high priority mode) and a second priority mode (also called a low priority mode). Upon sensing the submission of the first computing task, the operation mode bit is set to the first priority mode; if the duration of the first computing task to be completed reaches a preset duration and no other computing tasks with the first priority (or higher priority) are submitted within the preset duration, the operation mode bit is set to the second priority mode.

[0095] The second scheduler periodically checks the operating mode bit. If the detection result in the periodic detection is that the current operating mode is the first priority mode, the second scheduler pauses the execution of the second computing task and submits the first computing task to the processor for execution.

[0096] The first priority mode is set by the second scheduler when the second scheduler senses the submission of the first computing task.

[0097] By setting the operating mode bit, the real-time detection logic of the first computing task can be decoupled from the actual submission logic of the first computing task, allowing the two logics to run independently, thereby improving the operational reliability of the overall logic. In addition, the periodic detection period is freely configurable and can be changed based on business needs, thus having good business applicability.

[0098] In some embodiments, when the second scheduler senses the submission of the first computing task, it sets the current task mode to the first priority mode and resets the idle timer of the first priority task to zero. When the idle time corresponding to the idle timer of the first priority task reaches a preset threshold, the current task mode is set to the second priority mode, and the second priority mode is used to trigger or resume the execution of the second computing task.

[0099] The preset threshold can reduce the frequent switching between the first priority mode and the second priority mode, and avoid the offline task (low priority task) being suspended again when it is just resumed, which wastes computing resources and increases unnecessary time.

[0100] Submission of the first computing task:

[0101] The second scheduler sets the device control bit of the second computing task to a disable state based on the task submission information of the first computing task, so as to start the operation of the first computing task.

[0102] The second scheduler stores a correspondence between the first computing task, the first priority, the first address information, and the second address information. Based on the first address information, the second scheduler submits the first computing task to the processor for execution.

[0103] Optionally, the second scheduler sets the device control bit of the first computing task to an enable state based on the first address information, thereby triggering the execution of the first computing task.

[0104] Since the second scheduler pre-saves the first address information assigned by the operating system to the first computing task, the second scheduler can actually submit the first computing task to the GPU / NPU for execution according to its own scheduling needs, thereby realizing the scheduling management of the first priority task (that is, the high priority task) by the second scheduler.

[0105] Pause of the second computing task:

[0106] The second scheduler sets the device control bit of the second computing task to a disabled state based on the task submission information of the second computing task to suspend the running of the second computing task.

[0107] The second scheduler stores a correspondence between the second computing task, the second priority, the third address information, and the fourth address information. Based on the third address information, the second scheduler sets the device control bit of the second computing task to a disabled state, thereby suspending the execution of the second computing task.

[0108] Since the second scheduler pre-saves the third address information assigned by the operating system to the second computing task, the second scheduler can actually pause / suspend / start / resume the second computing task according to its own scheduling needs, thereby realizing the scheduling management of the second priority task (that is, the low priority task) by the second scheduler.

[0109] This application can be applied to servers that include hardware acceleration processors, and can also be applied in containerized scenarios. By configuring different priorities for different containers, different computing tasks (or services) in multiple containers can be scheduled according to different high and low priorities. Computing tasks in the same container have the same priority.

[0110] In an exemplary application scenario, online tasks are high-priority or first-priority computing tasks, while offline tasks are low-priority or second-priority computing tasks. For example, online face recognition tasks require fast computation and high real-time performance. Offline content review tasks require processing to be completed within two days and have lower real-time performance requirements. High-priority computing tasks generally require real-time response and low latency, while low-priority computing tasks generally require high throughput and can be completed within a fixed time.

[0111] 5 shows a schematic diagram of the architecture of a cloud computing system according to an exemplary embodiment of the present application. The cloud computing system comprises, from bottom to top, an application layer 52 , a native scheduler layer 54 , a custom scheduler layer 56 , a driver layer 58 and a hardware layer 50 .

[0112] The application layer 52 includes: K8s program and K8s cluster scheduling algorithm.

[0113] The native scheduler layer 54 includes: a native K8s scheduler, that is, a first scheduler 53. The native first scheduler 53 can create high-priority and low-priority containers (PODs) respectively, run computing tasks of the same priority in the same POD, and run computing tasks of different priorities in different PODs. For example, the native first scheduler 53 is used to create online POD1 and offline POD2 respectively. The computing tasks deployed in the online POD1 are online tasks or online computing tasks or computing tasks of the first priority or computing tasks of high priority, etc., and the computing tasks deployed in the offline POD2 are offline tasks or offline computing tasks or computing tasks of the second priority or computing tasks of low priority, etc., etc. Optionally, the first scheduler 53 can also create an ordinary POD3. The native computing tasks in the ordinary POD are computing tasks without priority, and the submission method of the ordinary POD3 is different from the submission method of the online POD1 and the offline POD2.

[0114] The custom scheduling layer 56 includes: an xGPU scheduler, that is, a second scheduler 55. The second scheduler 55 is a newly added scheduler in the embodiment of the present application. Regardless of the high or low priority computing tasks, they are handed over to the second scheduler 55 to complete the actual triggering / submission. When the offline POD is triggered to run, the second scheduler 55 checks whether the system is currently in an idle state (or low priority mode or first priority mode); if it is in an idle state, it continues to submit the offline POD to the GPU / NPU for operation; if it is not in an idle state, it pauses or suspends the running offline task as needed. When the online POD is triggered to run, the second scheduler 55 will perceive the task submission of the online POD in real time, immediately pause the running offline POD, and allocate multiple subsequent time slices to the online POD until the online POD is finished running. When the computing task in the online POD is completed, the second scheduler 55 will self-loop for x milliseconds (x is a configurable value). If it is found that no other online POD continues to submit within x milliseconds, it will resume the suspended offline POD and complete the switching between the online POD and the offline POD.

[0115] The second scheduler 55 needs to perceive the submission time point of the online POD in real time so as to make a decision on the next action in a timely manner.

[0116] The driver layer 58 includes: GPU / NPU drivers.

[0117] The hardware layer 50 includes multiple GPUs / NPUs. Figure 5 shows one GPU / NPU as an example. The scheduling processes of different GPUs / NPUs are the same or similar.

[0118] In a typical example, step ①: the first scheduler submits an offline task; step ②: the second scheduler determines whether it is currently in an idle state. If it is currently in an idle state (i.e., first priority mode or high priority mode), the offline task is submitted to the GPU / NPU for execution; step ③: the first scheduler submits an online task; the second scheduler senses the submission of the online task and switches the idle state to a non-idle state (i.e., second priority mode or low priority mode); step ④: the second scheduler suspends the offline task; step ⑤: the second scheduler submits the online task to the GPU / NPU for execution. At this time, 100% computing power preemption can be set for the online task; step ⑥: after the online task is completed, wait until X milliseconds to switch to the idle state; step ⑦: resume the offline task.

[0119] The above process is introduced from different aspects below.

[0120] Aspect 1: High and low priority configuration of POD / computing tasks;

[0121] FIG6 shows a flow chart of a method for notifying a priority of a POD / computing task provided by an exemplary embodiment of the present application. The method is executed by a central processing unit or a first scheduler. The method includes:

[0122] In the K8s scenario, users can create a POD by specifying configuration information (such as a YAML file), and then start computing tasks within the POD to complete the calculation of the tasks.

[0123] In some embodiments, a user sets a priority tag in the configuration information, which indicates the priority level of the current POD. When the priority tag has a first value, it is considered a first priority or high priority tag; when the priority tag has a second value, it is considered a second priority or low priority tag. The first value is 1 and the second value is 0; or the first value is 0 and the second value is 1.

[0124] Step 601: Is POD the first priority?

[0125] The first scheduler determines whether the POD has the first priority.

[0126] The first scheduler searches for the priority tag of the POD in the configuration information. If the first priority tag is found, step 602 is executed; if the second priority tag is found instead of the first priority tag, step 603 is executed.

[0127] Step 602: The first scheduler notifies the second scheduler of the first priority.

[0128] Alternatively, the first scheduler notifies the second scheduler of the first priority via an application programming interface (API). If the priority flag of POD "xxx" is checked using the "echo" command, the priority value is 1, i.e., echo 1> / x / xGPU / xxx / is_on line.

[0129] Step 603: The first scheduler notifies the second scheduler of the second priority.

[0130] Alternatively, the first scheduler notifies the second scheduler of the second priority through an API. If the priority flag of POD "xxx" is checked using the "echo" command, the priority value is 0, i.e., echo 0> / x / xGPU / xxx / is_online.

[0131] Step 604: The second scheduler saves the priority information of the POD.

[0132] To sum up, this embodiment sets a priority mark in the configuration information, so that the first scheduler can obtain the priority information of the POD, and then the first scheduler notifies the second scheduler of the priority information of the POD. The second scheduler can save the priority information of the POD to implement the subsequent priority scheduling process.

[0133] Aspect 2: The second scheduler pre-fetches task submission information of computing tasks.

[0134] FIG7 shows a flow chart of a method for prefetching information for a computing task according to an exemplary embodiment of the present application. The method is executed by a first scheduler and a second scheduler. The method includes:

[0135] Step 701: Obtain task submission information of a computing task.

[0136] When a business process (the process corresponding to a computing task) within a POD runs, it first performs a series of system configuration operations. One of these configuration operations involves mapping a bar space on a Peripheral Component Interconnect (PCI) device (i.e., the GPU / NPU), allowing the computing task to obtain a pointer and length as task submission information. The pointer points to a starting address allocated for the computing task within the PCI device, and the length indicates the length of the address allocated for the computing task.

[0137] Since PCI devices uniformly use mmap technology, the service process of the first scheduler obtains the task submission information of the computing task based on the mmap call. The PCI device refers to a hardware acceleration processor connected to the PCI bus.

[0138] Step 702: hijacking system calls and analyzing;

[0139] The second scheduler hijacks the mmap system call and analyzes the mmap call result information returned by mmap, which includes: pointer (addr), length (length), device control bit (flag), and the offset value (offset) of the device control bit relative to the address pointed to by the pointer. The pointer points to the starting position of a storage location in the GPU / NPU, and the length indicates the length of the storage location. The device control bit is stored in the storage location and is used to trigger the start / resume / pause / suspend of the computing task. In this embodiment, pause and suspend can be understood as the same meaning. "Hijacking" is a technical term in the computer field. In this application, it means that the second scheduler intercepts the call result information returned by mmap and modifies it so that the modified call result information points to another storage location.

[0140] The mmap call result information is the task submission information of the computing task.

[0141] Step 703: Whether it points to the Bar space of the GPU / NPU.

[0142] The second scheduler determines whether the pointer in the mmap call result information points to the Bar space of the GPU / NPU.

[0143] If the pointer points to the Bar space of the GPU / NPU, execute step 704 ; if the pointer does not point to the Bar space of the GPU / NPU, execute step 709 .

[0144] Step 704: Save the task submission information of the computing task.

[0145] The second scheduler saves the mmap call result information as the task submission information for the compute task. When the compute task is fully configured and needs to be submitted to the GPU / NPU for execution, the first scheduler uses this address information to set the device control bit of the compute task to the enabled state, triggering the GPU / NPU to execute the compute task. This is also known as the hardware doorbell triggering operation. Upon receiving this doorbell message, the GPU / NPU executes the compute task.

[0146] Step 705: Map the Bar space.

[0147] The second scheduler uses the pointer in the mmap call result to map the GPU / NPU's bar space and obtain information about the tasks that can be submitted within the bar space. For example, the device control bit is used to control the start or pause of computing tasks.

[0148] Step 706: Save the task information that can be submitted to the Bar space, the priority of the POD and other related information.

[0149] The second scheduler associates and stores related information such as the computing task, the POD where the computing task is located, the priority of the POD, the pointer and length (first address information) of the Bar space corresponding to the computing task.

[0150] Step 707: Allocate memory pages.

[0151] The second scheduler also allocates a memory page in the system memory as the storage location specified by the second scheduler. The address information of the memory page includes a pointer and a length. The pointer points to the starting address of the memory page, and the length indicates the address length of the memory page. Optionally, the length of the memory page is greater than or equal to the length returned by mmap.

[0152] Step 708: Return the address information of the memory page to the user state, and set the write protection and callback function.

[0153] The second scheduler replaces the address information (first address information) returned by mmap with the address information (second address information) of the memory page, and then returns the modified mmap mapping result information to the first scheduler in the user state.

[0154] Optionally, when the priority of the computing task / POD is the first priority, it is also necessary to set write protection permissions for the memory page so that a system error message is triggered when the first scheduler subsequently submits a computing task. It is also necessary to set a callback function, which is used to set the current operating mode to high priority mode when it senses that a computing task of the first priority has been submitted. When the priority of the computing task / POD is the second priority, there is no need to set write protection permissions for the memory page or set a callback function.

[0155] Because the second scheduler uses the address information of the system memory pages instead of the address information returned by the operating system, after the first scheduler submits the computing task using the address information of the system memory pages, it only writes the doorbell message (the message with the device control bit enabled) to these memory pages and does not actually trigger the GPU / NPU to run the computing task.

[0156] Step 709: Complete the mmap operation and return.

[0157] Aspect 3: Task scheduling management of the second scheduler.

[0158] FIG8 shows a flowchart of a task scheduling method based on a hardware acceleration processor according to an exemplary embodiment of the present application. The method is executed by a second scheduler. The method includes:

[0159] Step 801: Initialize the task queue.

[0160] The task queue is used to store computing tasks that have not yet been completed. The same POD includes at least one computing task. In the method shown in Figure 7, the second scheduler can obtain the task submission information of each computing task and initialize the task queue based on the task submission information.

[0161] When the second scheduler is loaded into kernel mode and runs, it needs to first create corresponding kernel threads according to the dimensions of each hardware acceleration processor. Each hardware acceleration processor corresponds to its own kernel thread, that is, there is a one-to-one correspondence between hardware acceleration processors and kernel threads. Optionally, the kernel thread is a kernel kthread of the Linux kernel.

[0162] Step 802: Determine whether to stop.

[0163] The stop condition is a parameter that the kernel kthread needs to set. In this embodiment, the stop condition is set to null, that is, the judgment result of step 802 is always no.

[0164] If the stop condition is met, exit; if the stop condition is not met, execute step 803.

[0165] Step 803: Determine whether it has timed out.

[0166] The timeout condition is a parameter that the kernel kthread needs to set. In this embodiment, the timeout period is set to never time out. That is, the judgment result of step 803 is always no.

[0167] If the timeout occurs, exit; if the timeout does not occur, execute step 804.

[0168] Step 804: Determine whether the idle time of the online task is less than a configured threshold.

[0169] In this embodiment, the online task is a task of the first priority or a high priority task. The idle time is the accumulated time after the latest online task is submitted.

[0170] If the idle time of the online task is less than the configured threshold, step 805 is executed; if the idle time of the online task is greater than or equal to the configured threshold, step 806 is executed.

[0171] Step 805: Continue to count the idle time of the online task.

[0172] Optionally, the idle time of the online task is measured by a timer. The second scheduler resets the timer when a preset condition is met. Optionally, the preset condition is that the online task is perceived to be submitted.

[0173] Step 806: Set the current operating mode to the second priority mode.

[0174] Step 807: Determine whether the current mode is the first priority mode.

[0175] If the current operating mode is the first priority mode, execute step 808 ; if the current operating mode is not the second priority mode, execute step 809 .

[0176] Step 808: Pause (all) offline tasks;

[0177] When the current operation mode is the first priority mode, all offline tasks in the task queue are suspended. In this embodiment, the second priority computing task is an offline task for example.

[0178] Step 809: Resume the offline task.

[0179] When the current operating mode is the second priority mode, one or more offline tasks in the task queue are restored. Optionally, the second scheduler restores one or more offline tasks in the task queue according to the scheduling policy of the offline tasks. The embodiment of the present application does not limit the scheduling policy of the offline tasks.

[0180] Step 810: End this round of iteration.

[0181] When the kernel kthread is created, it is assigned a time for each iteration check, such as 1ms. In various embodiments, this time can be smaller, such as just one kernel system clock tick. This time can also be larger and can be dynamically adjusted based on business needs.

[0182] Aspect 4: Suspension (or suspension) of low-priority tasks.

[0183] FIG9 shows a flowchart of a method for pausing a low-priority task provided by an exemplary embodiment of the present application. This embodiment takes the method executed by the second scheduler, the high-priority task being an online task, and the low-priority task being an offline task as an example. The method includes:

[0184] Step 901: Determine whether there are any offline PODs that have not been traversed.

[0185] The second scheduler traverses all offline PODs. The second scheduler determines whether there are any offline PODs that have not been traversed. An offline POD includes at least one offline task. In this embodiment, an offline POD refers to a POD with the second priority, and an offline task refers to a computing task with the second priority.

[0186] If there are any offline PODs that have not been traversed, execute step 902; if all offline PODs have been traversed, exit.

[0187] Step 902: Determine whether the current POD has any untraversed offline tasks.

[0188] The second scheduler obtains a POD that has not been traversed yet as the current POD, and determines whether the current POD has any offline tasks that have not been traversed yet.

[0189] If there are offline tasks that have not been traversed in the current POD, step 903 is executed; if all offline tasks in the current POD have been traversed, the process returns to step 901.

[0190] Step 903: Obtain task submission information of the offline task.

[0191] In the method shown in FIG. 7 , the second scheduler has pre-saved the correspondence between the offline task, the POD where the offline task is located, the priority of the POD, the third address information, and the fourth address information.

[0192] The third address information points to a storage location (Bar space) in the GPU / NPU, and the fourth address information points to a storage location in the system memory.

[0193] Step 904: Write the device control bit of the offline task to the disabled state.

[0194] Based on the third address information, the second scheduler writes the device control bit of the offline task in the GPU / NPU to a disabled (enable) state, thereby pausing or suspending the offline task.

[0195] Aspect 5: High-priority tasks preempt low-priority tasks.

[0196] When an offline task is running, if an online task is submitted to the GPU / NPU, triggering a doorbell message, the second scheduler needs to implement the following capabilities:

[0197] 1) Real-time perception of online task submission;

[0198] 2) Pause offline tasks (described in aspect 4);

[0199] 3) Perform online tasks.

[0200] Before analyzing the specific process of online tasks preempting offline tasks, let's first refer to the task submission process of native computing tasks in related technologies.

[0201] FIG10 shows a flowchart of a method for submitting a native computing task provided by an exemplary embodiment of the present application. The method is executed by a first scheduler and includes:

[0202] Step 1001: Read the task submission information of the native computing task.

[0203] The first scheduler reads the task submission information of the native computing task to obtain the real address information obtained by mmap during initialization. This real address information points to the address information within the GPU / NPU.

[0204] Step 1002: triggering a doorbell message based on the task submission information.

[0205] The device control bit of the native computing task is stored in the storage location indicated by the real address information. When the device control bit is set to an enabled state, it indicates that the native computing task is running; when the device control bit is set to a disabled state, it indicates that the native computing task is paused or suspended.

[0206] Setting the device control bit to the enabled state can be considered as triggering a doorbell message. The first scheduler sets the device control bit to the enabled state through a memory-mapped input / output (MMIO) write operation, thereby triggering the doorbell message corresponding to the native computing task.

[0207] The GPU / NPU contains a PCI Bar space mapping task control module. When the device control bit is set to enabled, the PCI Bar space mapping task control module runs the native computing task. This task submission process does not require driver participation, thus achieving better performance.

[0208] For 1) and 3), when the first scheduler submits the online task, it will perform an MMIO write operation in the same manner as FIG10 to trigger the doorbell message.

[0209] FIG11 shows a flowchart of a method for submitting an online task (high-priority task) provided by an exemplary embodiment of the present application. This embodiment is illustrated by taking the method as an example where the method is executed by a first scheduler and a second scheduler, the high-priority task is an online task, and the low-priority task is an offline task. The method includes:

[0210] Step 1101: Read the task submission information of the online task.

[0211] The first scheduler reads the task submission information of the task, thereby obtaining the second address information of the impersonated memory page obtained by mmap during initialization. The second address information is modified by the second scheduler and points to a memory page in the system memory.

[0212] Step 1102: trigger a doorbell message based on the second address information.

[0213] Since the fake memory page pointed to by the second address information is set with write protection permission, when the first scheduler uses the MMIO write operation to write the doorbell message to the second address information, the write protection permission will cause the triggering system error message to be unable to be written.

[0214] Step 1103: A system error message is triggered due to write protection permission.

[0215] This system error message is a memory page fault message. This memory page fault message is triggered because the write protection permission makes it impossible to write.

[0216] Step 1104: Analyze system error information.

[0217] The second scheduler monitors system error information. After detecting a system error message, it analyzes the system error message. For example, if the system error message is a memory page fault message, the address to which the memory page fault message is to be written and the type of the write instruction are determined through analysis.

[0218] Step 1105: Whether it is a doorbell triggering message;

[0219] The second scheduler determines whether the write operation is to trigger a doorbell message based on the address to which the memory page fault information is to be written and the type of the write instruction.

[0220] If the doorbell message is to be triggered, step 1106 is executed; if the doorbell message is not to be triggered, the system error message is ignored and the operating system executes the original process.

[0221] Step 1106: Call the callback function.

[0222] This callback function is pre-registered using the operating system kernel's vma, which is the abbreviation for the kernel's user space management data structure (struct vm_area_struct).

[0223] The callback function is used to set the current operating mode to the first priority mode (ie, high priority mode) when the second scheduler senses that a computing task of the first priority is submitted.

[0224] Step 1107: Set the idle time of the online task to zero, and set the current operation mode to the first priority mode.

[0225] This callback function is used to update the current operating mode of the second scheduler. On the one hand, it sets the current operating mode to the first priority mode; on the other hand, it resets the idle time of the first priority task to zero, so as to trigger the second scheduler to perform step 804 and subsequent steps in Figure 8.

[0226] Step 1108: Write the device control bit of the online task to the enabled state through the first address information.

[0227] The second scheduler performs an MMIO write operation using the first address information, enabling the device control bit of the online task. This writes the doorbell message for the online task to the actual physical page of the Bar space in the GPU / NPU, completing the doorbell triggering operation in the online task submission process.

[0228] There is a PCI Bar control mapping task control module in the GPU / NPU. When the device control bit is set to the enabled state, the PCI Bar control mapping task control module will run the online task.

[0229] Aspect 6: Submission of low-priority tasks.

[0230] FIG12 shows a flowchart of a method for submitting an offline task (low priority task) according to an exemplary embodiment of the present application. The method is executed by a first scheduler and includes:

[0231] Step 1220: Read the task submission information of the offline task.

[0232] The first scheduler reads the task submission information of the offline computing task, thereby obtaining the fourth address information obtained by mmap during initialization, where the fourth address information points to the spoofed memory page in the system memory.

[0233] The first scheduler is unaware of the process in which the second scheduler replaces the third address information with the fourth address information. Therefore, the first scheduler will perform the MMIP write operation according to the fourth address information it has saved.

[0234] Step 1240: Trigger a doorbell message based on the fourth address information.

[0235] Since the fourth address information points to a fake memory page in the system memory, rather than an actual memory page in the GPU / NPU, it does not trigger a real doorbell message. The offline task is not actually submitted to the GPU / NPU for execution.

[0236] The GPU / NPU starts running or resumes running, which is completed by the second scheduler based on the third address information.

[0237] FIG13 shows a block diagram of a task scheduling device according to an exemplary embodiment of the present application, the device comprising: a first scheduler module 1320 and a second scheduler module 1340;

[0238] A second scheduler module 1340 is configured to modify task submission information of the first computing task during the process of the first scheduler module 1320 creating the first computing task, the first computing task having a first priority;

[0239] The second scheduler module 1340 is used to perceive the submission of the first computing task during the process of the first scheduler module 1320 submitting the first computing task based on the modified task submission information; wherein, perceiving the submission of the first computing task can be understood as: perceiving that the first computing task is submitted by the first scheduler module, or perceiving the submission progress of the first computing task.

[0240] A second scheduler module 1340 is configured to suspend the execution of the second computing task and submit the first computing task to the processor for execution, wherein the second computing task has a second priority;

[0241] Among them, the first priority is higher than the second priority.

[0242] In some embodiments, the task submission information points to a target storage location specified by the second scheduler module 1340 ;

[0243] The second scheduler module 1340 is configured to sense submission of the first computing task when the first scheduler module 1320 submits the first computing task to the target storage location based on the task submission information.

[0244] In some embodiments, the target storage location specified by the second scheduler module 1340 is set with write protection permissions;

[0245] The second scheduler module 1340 is used to obtain system error information; when the system error information is triggered by the first scheduler module 1320 submitting the first computing task to the target storage location based on the task submission information but failing to write due to write protection permission, the second scheduler module 1340 senses the submission of the first computing task.

[0246] In some embodiments, the second scheduler module 1340 is configured to modify task submission information of the first computing task during the process of the first scheduler module 1320 creating the first computing task to the operating system, where the task submission information before the modification is assigned by the operating system to the first computing task;

[0247] The modified task submission information is used to submit the first computing task to the target storage location specified by the second scheduler module 1340 .

[0248] In some embodiments, the second scheduler module 1340 is used to obtain the first address information assigned by the operating system to the first computing task during the process of the first scheduler module 1320 creating the first computing task, the first address information pointing to the first storage location in the processor; replace the first address information with the second address information, the second address information pointing to the target storage location in the system memory; save the correspondence between the first computing task, the first priority, the first address information and the second address information, and return the second address information to the first scheduler module 1320.

[0249] In some embodiments, the second scheduler module 1340 is further configured to set write protection permissions for the second address information.

[0250] In some embodiments, the second scheduler module 1340 is further configured to, when the detection result in the periodic detection is that the current operation mode is the first priority mode, suspend the execution of the second computing task and submit the first computing task to the processor for execution;

[0251] The first priority mode is set by the second scheduler module 1340 when it senses the submission of the first computing task.

[0252] In some embodiments, the second scheduler module 1340 is further configured to set the current task mode to the first priority mode and reset the idle timer of the first priority task to zero upon sensing the submission of the first computing task.

[0253] In some embodiments, the second scheduler module 1340 is also used to set the current task mode to the second priority mode when the idle time corresponding to the idle timer of the first priority task reaches a preset threshold. The low priority mode is used to trigger or resume the operation of the second computing task.

[0254] In some embodiments, the second scheduler module 1340 is further configured to set the device control bit of the second computing task to a disabled state based on the task submission information of the second computing task through the second scheduler to suspend the operation of the second computing task.

[0255] In some embodiments, the second scheduler module 1340 is further configured to notify the second scheduler module 1340 of the first priority of the first computing task and the second priority of the second computing task through the first scheduler module 1320 .

[0256] FIG14 shows a block diagram of a computer device 1400 provided in an exemplary embodiment of the present application. The computer device includes a processor 1420 and a memory 1440 .

[0257] At least one computer-readable instruction is stored in the memory 1440. The processor 1420 is configured to execute the at least one computer-readable instruction in the memory 1440 to implement the task scheduling method described above.

[0258] In some embodiments, the processor used to perform computing tasks is processor 1420.

[0259] In some embodiments, the computer device further includes a hardware acceleration processor 1460, which is connected to the processor 1420 via a PCI bus. The processor 1420 is used to execute the task scheduling method, and the hardware acceleration processor 1460 is used to execute the computing task.

[0260] In an exemplary embodiment, a chip is further provided. The chip includes a programmable logic circuit and / or program instructions. When the chip runs on a computer device, it is used to implement the task scheduling method described in the above aspects.

[0261] In an exemplary embodiment, a computer program product is also provided, comprising computer-readable instructions stored in a non-volatile computer-readable storage medium. A processor of a computer device reads the computer-readable instructions from the computer-readable storage medium and executes the computer-readable instructions, causing the computer device to perform the task scheduling methods provided in the above-described method embodiments.

[0262] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, which stores at least one computer-readable instruction. When the computer-readable instruction is loaded and executed by a processor of a computer device, the task scheduling method provided by the above-mentioned method embodiments is implemented.

[0263] Those skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware, or may be accomplished by instructing the relevant hardware through computer-readable instructions, and the computer-readable instructions may be stored in a non-volatile computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk, or an optical disk, etc.

[0264] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A task scheduling method, executed by a computer device, comprising: During the process of creating a first computing task by the first scheduler, modifying task submission information of the first computing task by the second scheduler, the first computing task having a first priority; In the process of the first scheduler submitting the first computing task based on the modified task submission information, the second scheduler senses the submission of the first computing task; When the second scheduler senses the submission of the first computing task, pausing the execution of the second computing task and submitting the first computing task to the processor for execution, the second computing task having a second priority; The first priority is higher than the second priority.

2. The method according to claim 1, characterized in that The task submission information points to the target storage location specified by the second scheduler; The step of sensing the submission of the first computing task by the second scheduler during the process of the first scheduler submitting the first computing task based on the modified task submission information includes: In the process of the first scheduler submitting the first computing task to the target storage location based on the modified task submission information, the submission of the first computing task is perceived by the second scheduler.

3. The method according to claim 2, characterized in that The target storage location specified by the second scheduler is set with write protection permission; The step of sensing the submission of the first computing task by the second scheduler during the process of the first scheduler submitting the first computing task based on the modified task submission information includes: Obtaining system error information through the second scheduler; In the case where the system error information is triggered by the first scheduler submitting the first computing task to the target storage location based on the modified task submission information and being unable to write due to the write protection permission, the second scheduler perceives the submission of the first computing task based on the system error information.

4. The method according to any one of claims 1 to 3, characterized in that: The step of modifying the task submission information of the first computing task by the second scheduler during the process of the first scheduler creating the first computing task includes: During the process of the first scheduler creating the first computing task to the operating system, modifying task submission information of the first computing task by the second scheduler, where the task submission information is allocated by the operating system to the first computing task; The modified task submission information is used to submit the first computing task to the target storage location specified by the second scheduler.

5. The method according to claim 4, characterized in that The step of modifying the task submission information of the first computing task by the second scheduler during the process of the first scheduler creating the first computing task to the operating system includes: During the process of the first scheduler creating the first computing task, obtaining, through the second scheduler, first address information allocated by the operating system to the first computing task, where the first address information points to a first storage location in the processor; replacing the first address information with second address information by the second scheduler, where the second address information points to the target storage location in the system memory; The second scheduler saves the correspondence between the first computing task, the first priority, the first address information, and the second address information, and returns the second address information to the first scheduler.

6. The method according to claim 5, characterized in that The method further comprises: Set write protection permission for the second address information.

7. The method according to any one of claims 1 to 6, characterized in that: The step of pausing the execution of the second computing task and submitting the first computing task to the processor for execution upon sensing the submission of the first computing task through the second scheduler includes: Periodically detecting, by the second scheduler, an operation mode bit, the operation mode bit being used to indicate one of a first priority mode and a second priority mode, the operation mode bit being set to the first priority mode when the second scheduler senses submission of the first computing task, and being set to the second priority mode when the duration of completion of the first computing task reaches a preset duration and no other computing task with the first priority is submitted within the preset duration; When the detection result in the periodic detection is that the current operation mode is the first priority mode, the second scheduler suspends the operation of the second computing task and submits the first computing task to the processor for operation.

8. The method according to claim 7, characterized in that The method further comprises: When the second scheduler senses the submission of the first computing task, it sets the current task mode to the first priority mode and resets the idle timer of the task of the first priority to zero.

9. The method according to claim 8, characterized in that The method further comprises: When the idle time corresponding to the idle timer of the task of the first priority reaches a preset threshold, the current task mode is set to the second priority mode, and the second priority mode is used to trigger or resume the operation of the second computing task.

10. The method according to any one of claims 1 to 9, characterized in that: The pausing the execution of the second computing task by the second scheduler includes: The second scheduler sets the device control bit of the second computing task to a disabled state based on the task submission information of the second computing task to suspend the running of the second computing task.

11. The method according to any one of claims 1 to 10, characterized in that: The method further comprises: The first scheduler notifies the second scheduler of the first priority of the first computing task and the second priority of the second computing task.

12. A task scheduling device, comprising: a first scheduler module and a second scheduler module; The second scheduler module is configured to modify task submission information of a first computing task during a process in which the first scheduler module creates the first computing task, the first computing task having a first priority; The second scheduler module is configured to sense submission of the first computing task during a process in which the first scheduler module submits the first computing task based on the modified task submission information; The second scheduler module is configured to, upon sensing submission of the first computing task, suspend execution of a second computing task and submit the first computing task to the processor for execution, wherein the second computing task has a second priority; The first priority is higher than the second priority.

13. The device according to claim 12, characterized in that The task submission information points to the target storage location specified by the second scheduler module; The second scheduler module is configured to sense submission of the first computing task during a process in which the first scheduler module submits the first computing task to the target storage location based on the modified task submission information.

14. The device according to claim 13, characterized in that The target storage location specified by the second scheduler module is set with write protection permission; The second scheduler module is used to obtain system error information; When the system error information is triggered by the first scheduler module submitting the first computing task to the target storage location based on the modified task submission information and being unable to write due to the write protection permission, the submission of the first computing task is perceived.

15. The device according to any one of claims 12 to 14, characterized in that The second scheduler module is configured to modify task submission information of the first computing task during the process of the first scheduler module creating the first computing task to the operating system, where the task submission information is allocated by the operating system to the first computing task; The modified task submission information is used to submit the first computing task to the target storage location specified by the second scheduler module.

16. The device according to claim 15, characterized in that The second scheduler module is configured to obtain first address information allocated by the operating system to the first computing task during the process of the first scheduler module creating the first computing task, where the first address information points to a first storage location in the processor; The first address information is replaced with the second address information, where the second address information points to the target storage location in the system memory; the correspondence between the first computing task, the first priority, the first address information and the second address information is saved, and the second address information is returned to the first scheduler module.

17. The device according to claim 16, characterized in that The second scheduler module is further configured to set write protection permissions for the second address information.

18. A computer device, comprising: A processor and a memory, wherein the memory stores at least one segment of computer-readable instructions; the processor is configured to execute the at least one segment of computer-readable instructions in the memory to implement the task scheduling method according to any one of claims 1 to 11.

19. A non-volatile computer-readable storage medium, wherein the computer-readable storage medium stores computer-readable instructions, wherein the computer-readable instructions are loaded and executed by a processor to implement the task scheduling method according to any one of claims 1 to 11.

20. A computer program product, comprising computer-readable instructions, wherein the computer-readable instructions are loaded and executed by a processor to implement the task scheduling method according to any one of claims 1 to 11.

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