Processing method, platform, and apparatus based on chip simulator platform

Abstract

Provided in the embodiments of the present disclosure are a processing method, platform, and apparatus based on a chip simulator platform. The chip simulator platform is deployed with a first test end and a second test end, and the first test end and the second test end are respectively bound with different CPU resources in the chip simulator platform. The method comprises: performing received data packet redirection configuration on a local virtual network interface card of the chip simulator platform, the data packet redirection configuration being used for sending a specified data packet to a designated CPU resource; and when a soft interrupt is triggered in response to a network request issued by the first test end, according to an instruction of the received data packet redirection configuration and by means of the local virtual network interface card, sending a data packet corresponding to the soft interrupt to a CPU resource bound to the second test end for processing. According to the embodiments of the present disclosure, network environment simulation in a chip simulator environment is achieved by utilizing received data packet redirection technology.

Description

[0001] Processing Method, Platform, and Apparatus Based on a Chip Simulator Platform. This disclosure claims priority to Chinese patent application number 202410281646.5, filed with the China Patent Office on March 12, 2024, entitled "Processing Method, Platform, and Apparatus Based on a Chip Simulator Platform," the entire contents of which are incorporated herein by reference. Technical Field: This disclosure relates to the field of chip simulation technology, and more particularly to processing methods, platforms, and apparatus based on a chip simulator platform. Background: In the chip R&D process, tapeout refers to the process of converting a complete chip circuit design into a physical chip. It is a key step in the entire chip manufacturing process. Before tapeout, multiple verifications and optimizations are required to ensure the chip circuit's correctness and performance meet expectations. This stage is also known as pre-silicon. Since there are no physical chips for testing during the pre-silicon stage, testing can only be performed using a chip simulator. Due to implementation complexity and cost factors, chip simulators can only provide basic components to support testing. Chip simulators generally do not support network card devices and cannot support network communication through hardware devices. For test scenarios involving network communication, network communication can only be simulated in Local Host mode. However, the network simulation scheme of Local Host differs significantly from a real network, significantly impacting the accuracy of network-related performance tests and the accuracy of chip evaluation in the pre-silicon phase, thus failing to effectively ensure chip tape-out quality. In view of the above problems, a processing method, platform, and apparatus based on a chip simulator platform are proposed to overcome or at least partially resolve the above problems. The method includes: a processing method based on a chip simulator platform, wherein the chip simulator platform is deployed with a first test end and a second test end, each bound to a different CPU resource in the chip simulator platform. The method includes: configuring a local virtual network card of the chip simulator platform to redirect received packets; wherein the packet redirection configuration is used to send a specified packet to a specified CPU resource; and when a soft interrupt is triggered by a network request issued by the first test end, sending the packet corresponding to the soft interrupt to the CPU resource bound to the second test end via the local virtual network card for processing in accordance with the instructions of the received packet redirection configuration. Optionally, before configuring the local virtual network card of the chip simulator platform to redirect received data packets, the method further includes: binding the first test end and the second test end to different CPU resources.Optionally, the configuration of redirecting received data packets on the local virtual network card of the chip simulator platform includes: when configuring the redirection of received data packets on the local virtual network card of the chip simulator platform, setting the address range of the CPU resource bound to the second test end to the address for configuring the redirection of received data packets on the local virtual network card. Optionally, when a soft interrupt is triggered when the first test end issues a network request, the data packet corresponding to the soft interrupt is sent to the CPU resource bound to the second test end for processing through the local virtual network card in accordance with the instructions of the redirection configuration of received data packets, including: when a soft interrupt is triggered when the first test end issues a network request, the target process identifier of the service corresponding to the CPU resource bound to the second test end is determined in accordance with the instructions of the redirection configuration of received data packets, and the data packet corresponding to the soft interrupt is determined based on the target process identifier, and the i data packet corresponding to the soft interrupt is sent to the CPU resource bound to the second test end for processing through the local virtual network card. Optionally, sending the data packet corresponding to the soft interrupt to the CPU resource bound to the second test end for processing includes: using an inter-processor interrupt mechanism to send the data packet corresponding to the soft interrupt to the CPU resource bound to the second test end for processing. Optionally, sending the data packet corresponding to the soft interrupt to the CPU resource bound to the second test end for processing includes: using a delay mechanism to delay the process of sending the data packet corresponding to the soft interrupt to the CPU resource bound to the second test end. A chip simulator platform is deployed with a first test end and a second test end, the first test end and the second test end are respectively bound to different CPU resources in the chip simulator platform, the chip simulator platform is used to implement the processing method based on the chip simulator platform described above. A processing device based on the chip simulator platform is used to implement the processing method based on the chip simulator platform described above. An electronic device includes a processor, a memory, and a computer program stored in the memory and capable of running on the processor, the computer program implementing the processing method based on the chip simulator platform described above when executed by the processor. A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the aforementioned processing method based on a chip simulator platform. A computer program product includes the computer program, which, when executed by a processor, implements the aforementioned processing method based on a chip simulator platform.The embodiment of the present disclosure has the following advantages: In the embodiment of the present disclosure, the chip simulator platform is deployed with a first test end and a second test end, and the first test end and the second test end are respectively bound to different CPU resources in the chip simulator platform. By configuring the local virtual network card of the chip simulator platform to redirect received data packets, when a soft interrupt is triggered when the first test end issues a network request, the data packet corresponding to the soft interrupt is sent to the CPU resource bound to the second test end for processing through the local virtual network card in accordance with the instructions of the received data packet redirection configuration, thereby realizing the simulation of the network environment in the chip simulator environment by using the received data packet redirection technology, and making the two test ends deployed in a single chip simulator communicate with each other, that is, simulating the real network multi-machine communication scenario by a single machine, highly restoring the real network scenario, improving the accuracy of network-related performance testing, ensuring the accuracy of performance evaluation in the pre-silicon stage, and thus effectively ensuring the chip tape-out quality. To more clearly illustrate the technical solution of the present disclosure, the following briefly introduces the drawings required for the description of the present disclosure. Obviously, the drawings described below represent only some embodiments of the present disclosure. A person skilled in the art can derive other drawings based on these drawings without inventive effort. Figure 1a is a schematic diagram of communication in a real network scenario; Figure 1b is a schematic diagram of communication in a network simulation solution for a Local Host; Figure 1c is a schematic diagram of CPU resource allocation in a network simulation solution for a Local Host; Figure 1d is a schematic diagram of CPU resource allocation provided in an embodiment of the present disclosure; Figure 1e is a schematic diagram of a packet receiving process in a network simulation solution for a Local Host; Figure 1f is a schematic diagram of a packet receiving process provided in an embodiment of the present disclosure; Figure 2 is a flowchart of a processing method based on a chip simulator platform provided in an embodiment of the present disclosure; Figure 3 is a flowchart of another processing method based on a chip simulator platform provided in an embodiment of the present disclosure; and Figure 4 is a flowchart of another processing method based on a chip simulator platform provided in an embodiment of the present disclosure. To make the above-mentioned objectives, features, and advantages of the present disclosure more readily apparent, the present disclosure is further described below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the described embodiments represent only a portion of the present disclosure, and are not exhaustive. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present disclosure without inventive effort are intended to fall within the scope of protection of the present disclosure.In a real network scenario, as shown in Figure 1a, a network request is initiated by a test client (deployed on Server A), sent through a hardware network card, received by the peer machine's hardware network card, and distributed to a test server (deployed on Server B). Packet processing is completed by the test server's CPU. In a local host network simulation solution (used for network performance testing), as shown in Figure 1b, both the test client and the test server (i.e., the first and second test clients) are deployed on a chip emulator platform (deployed on Server C). The chip emulator platform uses a local virtual network card to receive network requests, triggering a soft interrupt to complete the packet reception process. In IPv4 networks, the local host is typically defined as the IP address 127.0.0.1. o This special IP address is called a loopback address and is used for local communication on the computer. When applications on the computer need to interact with it, they can use the local host as the destination address. Compared to real network scenarios, the local host network simulation solution has the following drawbacks: As shown in Figure 1a, in a real network scenario, the processing process is: system call, network protocol stack processing, soft interrupt, hard interrupt, network card driver processing, physical link. As shown in Figure 1b, in the local host network simulation solution, the processing process is: system call, network protocol stack processing, soft interrupt.

[0002] 1. In the Local Host network simulation solution, the test client and the test server share computing resources (i.e., CPU resources). Under high load conditions, resource competition and interference may occur, which may further distort the performance evaluation of the network performance test.

[0003] 2. In the Local Host network simulation solution, network requests initiated by the test client, after passing through the local virtual network card, trigger a packet reception software interrupt on the test server's local CPU, directly completing the packet reception process. For the packet reception and processing entities, the Local Host network simulation solution differs from the real-world scenario, which may further distort performance evaluations.

[0004] 3. The actual network scenario takes time: system call + network protocol stack processing + soft interrupt + hard interrupt + network card driver processing + physical link latency. The Local Host network simulation solution takes time: system call + network protocol stack processing + soft interrupt. Because the local virtual network card triggers a soft interrupt when processing a network request and is processed by the local CPU, the processing overhead of this portion of the process is lower than the actual network overhead due to the lack of network card hard interrupts, hardware network card driver processing overhead, and physical link transmission overhead. This may further distort performance evaluation. A hard interrupt is a signal sent by a hardware device to the CPU that can interrupt CPU operation. The CPU can be configured to decide whether to be interrupted by a hard interrupt. A soft interrupt is a software-triggered interrupt mechanism used for communication and coordination between the operating system kernel and user space. It can be triggered by a trigger instruction or system call, and the corresponding operation is executed in the handler. In the disclosed embodiments, the following improvements are proposed based on the Local Host network simulation solution:

[0005] 1. Using core binding technology, the test client and test server (i.e., the first test client and the second test client) are separately bound to each other to ensure that the CPU resources used by them do not interfere with each other. This can effectively avoid resource (such as CPU resource) competition between the client and server under high load conditions. For example, Figure 1c shows the CPU resource allocation in the Local Host network simulation solution, and Figure 1d shows the CPU resource allocation in the embodiment of the present disclosure.

[0006] 2. Based on RPS (Receive Packet Steer) technology and a process name filtering mechanism in the kernel, the packet reception soft interrupt triggered by the server or client is delivered to the CPU range where the peer service is located. This can effectively avoid the differences between the packet reception processing subject and the packet reception processing subject in real scenarios. For example, Figure 1e shows the packet reception process in the network simulation solution of the Local Host, and the figure shows the packet reception process in the embodiment of the present disclosure.

[0007] 3. Based on RPS technology, the target CPU is first determined through software logic. An IPI (Inter-Processor Interconnect) interrupt is simultaneously triggered to deliver the soft interrupt triggered by the local network packet. The additional time consumed by core selection and soft interrupt delivery is approximately equivalent to the hardware driver processing and hard interrupt overhead in real-world scenarios. A delay mechanism is added to the kernel to simulate physical link propagation delay, effectively resolving the issue where the simulated network scenario overhead is smaller than the real-world scenario overhead. Specifically, the real-world network scenario consumes the following: system call + network protocol stack processing + soft interrupt + hard interrupt + network card driver processing + physical link delay. The local host network simulation solution consumes the following: system call + network protocol stack processing + soft interrupt. The disclosed embodiment consumes the following: system call + network protocol stack processing + soft interrupt + RPS core selection + IPI delivery + kernel delay mechanism. Clearly, the real-world network scenario consumes the same amount of time as the simulated network scenario in the disclosed embodiment, and both consume more time than the local host network simulation solution. The present disclosure is further described below. This method can be applied to a chip simulator platform. Referring to FIG2 , a flowchart of a processing method based on a chip simulator platform according to an embodiment of the present disclosure is shown. The chip simulator platform can be deployed with a first test terminal and a second test terminal, each bound to a different CPU resource in the chip simulator platform. The first test terminal and the second test terminal can be deployed in the same virtual host. In some embodiments of the present disclosure, the first test terminal can be a client and the second test terminal can be a server, or the first test terminal can be a server and the second test terminal can be a client. Of course, in some scenarios, both the first test terminal and the second test terminal can be clients or both servers. Specifically, the method can include the following steps: Step 201: Configure the local virtual network card of the chip simulator platform to redirect received packets; the packet redirection configuration is used to send a specified packet to a specified CPU resource. In some embodiments of the present disclosure, before configuring the local virtual network card of the chip simulator platform to redirect received packets, the method further includes: binding the first test terminal and the second test terminal to different CPU resources.After deploying the first and second test terminals on a chip simulator platform, they share computing resources (e.g., CPU resources) on the same virtual host. Under high load, resource contention and interference can occur between the two terminals, potentially distorting chip performance evaluation. To address this, core binding can be used to bind the first and second test terminals to different CPU resources, such as different CPU cores, to ensure that the CPU resources used by each terminal do not interfere with each other. Core binding involves associating a thread or process with a specific CPU core, ensuring that it always runs on that core during execution. Core binding separates the computing resources (e.g., CPU resources) of the server and client, enabling a single-machine simulation of resource usage in a real-world multi-machine communication scenario on the chip simulator platform. In some embodiments of the present disclosure, configuring the local virtual network card of the chip simulator platform for packet reception redirection includes setting the address range of the CPU resources bound to the second test terminal to the address for configuring packet reception redirection on the local virtual network card. In actual applications, the first test end and the second test end can be deployed on the same virtual host (i.e., the virtual host where the chip emulator platform resides). The virtual host has a local virtual network card (NIC). For example, if the virtual host is a Linux operating system, the local virtual network card can be a loopback (Lo) interface. Receive packet steering (RPS) can be configured on the local virtual network card to reproduce the interruption behavior in a real network multi-machine communication scenario. Specifically, the address range of the CPU resource bound to the second test end can be set to the address configured for receive packet steering on the local virtual network card. By configuring the receive packet steering address to the address range of the CPU resource bound to the second test end, the corresponding soft interrupt packets can be subsequently sent to the corresponding CPU resource according to the configured address. In some examples, the receive packet steering configuration for the local virtual network card can also include other configuration methods, such as setting the address range of other CPU resources to the address configured for receive packet steering, and then having the other CPU resources forward the corresponding packets to the CPU resource bound to the second test end. RPS is a network card technology that can evenly distribute the processing load of network received packets among multiple CPU cores, improving processing efficiency.The RPS can configure the address range of the target CPU resource (the target CPU resource is the CPU resource bound to the second test end) and deliver the packet reception soft interrupt to the target CPU resource via an IPI, which then processes the corresponding soft interrupt. In step 202, when the first test end issues a network request and triggers a soft interrupt, the RPS sends the data packet corresponding to the soft interrupt to the CPU resource bound to the second test end via the local virtual network interface card for processing, in accordance with the instructions of the received data packet diversion configuration. Because the received data packet diversion configuration has been previously configured, when the first test end triggers a soft interrupt, the CPU resource bound to the second test end can be selected in accordance with the instructions of the received data packet diversion configuration, and the soft interrupt triggered by the first test end can be sent to the CPU resource bound to the second test end for processing. In some embodiments of the present disclosure, when a soft interrupt is triggered when the first test end issues a network request, the data packet corresponding to the soft interrupt is sent to the CPU resource bound to the second test end for processing via the local virtual network card in accordance with the instructions of the received data packet redirection configuration. This includes: when a soft interrupt is triggered when the first test end issues a network request, determining the target process identifier of the service corresponding to the CPU resource bound to the second test end in accordance with the instructions of the received data packet redirection configuration, determining the data packet corresponding to the soft interrupt based on the target process identifier, and sending the data packet corresponding to the soft interrupt to the CPU resource bound to the second test end for processing via the local virtual network card. As an example, the process identifier can be a process name. In practical applications, a process ID filtering mechanism can be employed to filter process IDs within the kernel's RPS logic (i.e., filter out the process IDs of services that will use the CPU resources bound to the second test end). The filtered process IDs are specifically the process IDs of services corresponding to the address range of the CPU resources configured by the RPS. If a match is successful (i.e., a process ID matching the target process ID is found through the process name filtering mechanism), the RPS return result can be redirected to another CPU resource among different CPU resources. Specifically, since the address range of the CPU resources bound to the second test end is set to the address of the received packet redirection configuration when receiving packet redirection configuration, that is, the process IDs of the services that are required to use the CPU resources bound to the second test end are configured, the target process IDs of the services that will use the CPU resources bound to the second test end can be determined.When a soft interrupt is triggered, the corresponding process ID can be determined. If the process ID corresponding to the soft interrupt matches (e.g., is the same as) the target process ID, the CPU resource to handle the soft interrupt can be determined to be the CPU resource bound to the second test end. The data packet corresponding to the soft interrupt can then be sent to the CPU resource bound to the second test end. In embodiments of the present disclosure, a virtual network card and RPS technology, combined with a kernel process filtering mechanism, enable mutual delivery of local packet reception soft interrupts between the server and client, highly recreating the interrupt behavior in a real multi-machine network communication scenario. In some embodiments of the present disclosure, sending the data packet corresponding to the soft interrupt to the CPU resource bound to the second test end for processing includes: utilizing an inter-processor interrupt mechanism to send the data packet corresponding to the soft interrupt to the CPU resource bound to the second test end for processing. In practical applications, an inter-processor interrupt mechanism (IPI) can be utilized to send the soft interrupt to the CPU resource bound to the second test end for processing. IPI is a mechanism for implementing inter-processor communication in a multi-processor system, enabling one processor to send an interrupt signal to other processors to trigger an operation or notify them of an event. For example, a client network request triggers a packet reception soft interrupt, which, through RPS core selection, further triggers an IPI mechanism to deliver the soft interrupt to the CPU resource where the server resides. In another example, a server network request triggers a packet reception soft interrupt, which, through RPS core selection, further triggers an IPI mechanism to deliver the soft interrupt to the CPU resource where the client resides. In some embodiments of the present disclosure, sending the data packet corresponding to the soft interrupt to the CPU resource bound to the second test end for processing includes: employing a delay mechanism to delay the process of sending the data packet corresponding to the soft interrupt to the CPU resource bound to the second test end. To simulate the propagation delay of a real physical link, a delay mechanism can be employed to add a corresponding delay to the process of sending the soft interrupt to the CPU resource bound to the second test end. Specifically, a waiting period can be set during data packet transmission, that is, the data packet is controlled to wait for a preset period before being sent, thereby implementing the added delay. In the embodiments of the present disclosure, the additional overhead of the RPS and IPI mechanisms is introduced to replace the hardware overhead in the real network scenario. At the same time, a delay mechanism is added to the kernel to simulate the physical link propagation delay, so that the overall delay of the simulated network scenario is highly restored to the real network scenario.In an embodiment of the present disclosure, a chip simulator platform is deployed with a first test end and a second test end. The first test end and the second test end are respectively bound to different CPU resources in the chip simulator platform. By configuring receive packet diversion on the local virtual network card of the chip simulator platform, when a soft interrupt is triggered by a network request from the first test end, the data packet corresponding to the soft interrupt is sent to the CPU resource bound to the second test end via the local virtual network card for processing in accordance with the instructions of the receive packet diversion configuration. This utilizes receive packet diversion technology to simulate a network environment in the chip simulator environment, enabling communication between two test ends deployed in a single chip simulator. This means that a single machine simulates a real network multi-machine communication scenario, highly reproducing the real network scenario, improving the accuracy of network-related performance testing, ensuring the accuracy of pre-silicon performance evaluation, and effectively ensuring chip tape-out quality. FIG3 shows a flowchart of another processing method based on a chip simulator platform according to an embodiment of the present disclosure. Specifically, the method may include the following steps: Step 301: Bind the first test end and the second test end to different CPU resources. Step 302: Configure receive packet diversion on the local virtual network card of the chip simulator platform. In step 303, when a soft interrupt is triggered by the first test end issuing a network request, the data packet corresponding to the soft interrupt is sent to the CPU resource bound to the second test end for processing via the local virtual network card using an inter-processor interrupt mechanism, in accordance with the instructions of the received packet redirection configuration. Referring to FIG4 , a flowchart of another processing method based on a chip simulator platform according to an embodiment of the present disclosure is shown. The method may specifically include the following steps: Step 401: Bind the first test end and the second test end to different CPU resources. Step 402: Configure the local virtual network card of the chip simulator platform for received packet redirection. Step 403: When a soft interrupt is triggered by the first test end issuing a network request, the data packet corresponding to the soft interrupt is sent to the CPU resource bound to the second test end for processing via the local virtual network card using an inter-processor interrupt mechanism, in accordance with the instructions of the received packet redirection configuration. Step 404: During the process of sending the data packet corresponding to the soft interrupt to the CPU resource bound to the second test end, a delay mechanism is implemented to delay the sending of the data packet corresponding to the soft interrupt to the CPU resource bound to the second test end.It should be noted that, for simplicity of description, the method embodiments are described as a series of combined actions. However, those skilled in the art should be aware that the embodiments of the present disclosure are not limited by the order of the actions described, as certain steps may be performed in a different order or simultaneously according to the embodiments of the present disclosure. Furthermore, those skilled in the art should also be aware that the embodiments described in this specification are preferred embodiments, and the actions described are not necessarily required for the embodiments of the present disclosure. One embodiment of the present disclosure provides a processing device based on a chip simulator platform. The device implements the aforementioned processing method based on the chip simulator platform. The chip simulator platform is deployed with a first test end and a second test end, each bound to a different CPU resource in the chip simulator platform. The method specifically includes: configuring a local virtual network card of the chip simulator platform to redirect received packets; wherein the packet redirection configuration is configured to send a specified packet to a specified CPU resource; and when a soft interrupt is triggered by a network request issued by the first test end, sending the packet corresponding to the soft interrupt to the CPU resource bound to the second test end via the local virtual network card for processing, in accordance with the instructions of the received packet redirection configuration. In some embodiments of the present disclosure, before configuring the local virtual network card of the chip emulator platform to redirect received packets, the method further includes: binding the first test end and the second test end to different CPU resources. In some embodiments of the present disclosure, configuring the local virtual network card of the chip emulator platform to redirect received packets includes: when configuring the local virtual network card of the chip emulator platform to redirect received packets, setting the address range of the CPU resource bound to the second test end to the address for configuring the local virtual network card to redirect received packets. In some embodiments of the present disclosure, when a soft interrupt is triggered by the first test end issuing a network request, sending the packet corresponding to the soft interrupt to the CPU resource bound to the second test end for processing via the local virtual network card in accordance with the instructions of the packet redirection configuration includes: when a soft interrupt is triggered by the first test end issuing a network request, determining the target process identifier of the service corresponding to the CPU resource bound to the second test end in accordance with the instructions of the packet redirection configuration, determining the packet corresponding to the soft interrupt based on the target process identifier, and sending the packet corresponding to the soft interrupt to the CPU resource bound to the second test end for processing via the local virtual network card.In some embodiments of the present disclosure, sending the data packet corresponding to the soft interrupt to the CPU resource bound to the second test end for processing includes: using an inter-processor interrupt mechanism to send the data packet corresponding to the soft interrupt to the CPU resource bound to the second test end for processing. In some embodiments of the present disclosure, sending the data packet corresponding to the soft interrupt to the CPU resource bound to the second test end for processing includes: using a delay mechanism to delay the process of sending the data packet corresponding to the soft interrupt to the CPU resource bound to the second test end. In an embodiment of the present disclosure, a chip simulator platform is deployed with a first test end and a second test end. The first and second test ends are each bound to a different CPU resource in the chip simulator platform. By configuring receive packet diversion on the local virtual network interface card of the chip simulator platform, when a network request from the first test end triggers a soft interrupt, the packet corresponding to the soft interrupt is sent to the CPU resource bound to the second test end via the local virtual network interface card for processing, in accordance with the instructions of the receive packet diversion configuration. This utilizes receive packet diversion technology to simulate a network environment within the chip simulator environment, enabling communication between two test ends deployed in a single chip simulator. This allows a single machine to simulate a real network multi-machine communication scenario, highly reproducing the real network scenario, improving the accuracy of network-related performance testing, ensuring the accuracy of pre-silicon performance evaluation, and effectively guaranteeing chip tape-out quality. An embodiment of the present disclosure also provides a chip simulator platform. The chip simulator platform is deployed with a first test end and a second test end. The first and second test ends are each bound to different CPU resources in the chip simulator platform. The chip simulator platform is configured to implement the aforementioned processing method based on the chip simulator platform. An embodiment of the present disclosure further provides an electronic device, which may include a processor, a memory, and a computer program stored in the memory and executable on the processor. When executed by the processor, the computer program implements the processing method based on the chip simulator platform described above. An embodiment of the present disclosure further provides a computer-readable storage medium storing the computer program. When executed by the processor, the computer program implements the processing method based on the chip simulator platform described above. An embodiment of the present disclosure further provides a computer program product, including the computer program. When executed by the processor, the computer program implements the processing method based on the chip simulator platform described above. Since the apparatus embodiment is substantially similar to the method embodiment, the description thereof will be brief. For relevant details, please refer to the description of the method embodiment.It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, storage, and display) involved in this disclosure are all information and data authorized by the user or fully authorized by all parties. The collection, use, and processing of the relevant data must comply with the relevant laws, regulations, and standards of the relevant countries and regions, and corresponding operation portals are provided for the user to choose to authorize or reject. The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar parts between the various embodiments can be referenced to each other. Those skilled in the art will understand that the embodiments of the present disclosure can be provided as methods, apparatuses, or computer program products. Therefore, the embodiments of the present disclosure may take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, the embodiments of the present disclosure may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, compact disc read-only memory, optical storage, etc.) containing computer-usable program code. The embodiments of the present disclosure are described with reference to flowcharts and / or block diagrams of methods, terminal devices (systems), and computer program products according to the embodiments of the present disclosure. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, when executed by the processor of the computer or other programmable data processing terminal device, produce a device for implementing the functions specified in one or more processes in the flowcharts and / or one or more blocks in the block diagrams. These computer program instructions can also be stored in a computer-readable memory capable of directing the computer or other programmable data processing terminal device to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means that implement the functions specified in one or more processes in the flowcharts and / or one or more blocks in the block diagrams. These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device, so that a series of operating steps are executed on the computer or other programmable terminal device to produce computer-implemented processing, so that the instructions executed on the computer or other programmable terminal device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.Although preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they understand the underlying inventive concepts. Therefore, the appended claims are intended to be interpreted as encompassing the preferred embodiments as well as all changes and modifications falling within the scope of the present disclosure. Finally, it should be noted that, as used herein, relational terms such as first and second, etc., are used solely to distinguish one entity or operation from another, and do not necessarily require or imply any actual relationship or order between these entities or operations. Furthermore, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or terminal device comprising a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. Without further limitation, the phrase "comprising a..." does not preclude the presence of additional identical elements in the process, method, article, or terminal device comprising the elements. The processing method, platform, and device based on the chip simulator platform have been described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present disclosure. The description of the above embodiments is intended only to facilitate understanding of the method and core concept of the present disclosure. Furthermore, those skilled in the art will appreciate that variations in the specific implementation methods and scope of application may occur based on the concepts of the present disclosure. In summary, the contents of this specification should not be construed as limiting the present disclosure.

Claims

Claims 1. A processing method based on a chip simulator platform, wherein: The chip simulator platform is deployed with a first test end and a second test end, and the first test end and the second test end are respectively bound to different CPU resources in the chip simulator platform. The method includes: configuring the local virtual network card of the chip simulator platform to redirect received data packets; wherein, the data packet redirection configuration is used to send a specified data packet to a specified CPU resource; when a soft interrupt is triggered when the first test end issues a network request, the data packet corresponding to the soft interrupt is sent to the CPU resource bound to the second test end for processing through the local virtual network card in accordance with the instructions of the received data packet redirection configuration.

2. The method according to claim 1, wherein: Before configuring the local virtual network card of the chip simulator platform to redirect received data packets, the method further includes: binding the first test end and the second test end to different CPU resources.

3. The method according to claim 1 or 2, wherein: The configuration of redirecting received data packets on the local virtual network card of the chip simulator platform includes: when configuring redirection of received data packets on the local virtual network card of the chip simulator platform, setting the address range of the CPU resources bound to the second test end to the address of the local virtual network card for redirection of received data packets.

4. The method according to any one of claims 1 to 3, wherein: The method includes: when a soft interrupt is triggered when the first test end sends a network request, according to the instruction of the received data packet redirection configuration, sending the data packet corresponding to the soft interrupt to the CPU resource bound to the second test end for processing through the local virtual network card, including: when a soft interrupt is triggered when the first test end sends a network request, according to the instruction of the received data packet redirection configuration, determining the target process identifier of the service corresponding to the CPU resource bound to the second test end, and determining the data packet corresponding to the soft interrupt according to the target process identifier, and sending the data packet corresponding to the soft interrupt to the CPU resource bound to the second test end for processing through the local virtual network card.

5. The method according to any one of claims 1 to 4, wherein: The sending the data packet corresponding to the soft interrupt to the CPU resource bound to the second test end for processing includes: using an inter-processor interrupt mechanism to send the data packet corresponding to the soft interrupt to the CPU resource bound to the second test end for processing.

6. The method according to any one of claims 1 to 5, wherein: The sending of the data packet corresponding to the soft interrupt to the CPU resource bound to the second test end for processing includes: using a delay mechanism to delay the process of sending the data packet corresponding to the soft interrupt to the CPU resource bound to the second test end.

7. A chip simulator platform, wherein: The chip simulator platform is deployed with a first test end and a second test end, the first test end and the second test end are respectively bound to different CPU resources in the chip simulator platform, and the chip simulator platform is used to implement the processing method based on the chip simulator platform according to any one of claims 1 to 6.

8. A processing device based on a chip simulator platform, wherein: The device is used to implement the processing method based on the chip simulator platform as described in any one of claims 1 to 6.

9. An electronic device, wherein: The system comprises a processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein when the computer program is executed by the processor, the processing method based on the chip simulator platform as claimed in any one of claims 1 to 6 is implemented.

10. A computer-readable storage medium, wherein: The computer readable storage medium stores a computer program, and when the computer program is executed by the processor, the chip simulator platform based on any one of claims 1 to 6 is implemented. 9 The processing method of the platform.

11. A computer program product, wherein: The method comprises a computer program, wherein when the computer program is executed by a processor, the processing method based on the chip simulator platform according to any one of claims 1 to 6 is implemented.

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