Pixel circuit, driving method and display apparatus

Abstract

The embodiments of the present disclosure provide a pixel circuit, a driving method and a display apparatus. The pixel circuit comprises: a light-emitting device; a driving transistor configured to generate, on the basis of a data voltage signal, a driving current for driving the light-emitting device to emit light; a first control circuit configured to provide, in response to a signal of a first control signal end, a signal of a reference voltage signal end to a first node; a first coupling control circuit configured to stabilize the voltage of the first node and the voltage of a gate of the driving transistor; a second coupling control circuit configured to stabilize the voltage of the first node and the voltage of a second electrode of the driving transistor; a second control circuit configured to connect, in response to a signal of a second control signal end, the gate of the driving transistor to a first electrode of the driving transistor; and a data writing circuit configured to provide, in response to a signal of a first scanning signal end, a data voltage signal of a data signal end to the gate of the driving transistor.

Description

Pixel circuit, driving method and display device thereof

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on March 18, 2024, with application number 202410304961.5 and invention name "Pixel circuit, driving method and display device thereof", the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a pixel circuit, a driving method and a display device thereof. Background Art

[0004] Light-emitting devices such as organic light-emitting diodes (OLEDs), quantum dot light-emitting diodes (QLEDs), micro light-emitting diodes (Micro LEDs), and mini light-emitting diodes (Mini LEDs) offer advantages such as self-luminescence and low energy consumption, making them a hot topic in current display device application research. Display devices typically use pixel circuits to drive the light-emitting devices.

[0005] Among them, the pixel circuit may include a driving transistor that generates a driving current and a light-emitting device to which the driving current is applied. When the driving transistor of the pixel circuit does not work properly or the wiring is cut or short-circuited, the light-emitting device may not emit light normally because the driving current is not normally applied to the light-emitting device. Therefore, it is necessary to confirm whether the driving transistor or other transistors in the pixel circuit are defective before the light-emitting device manufacturing process, that is, to perform detection through array test (AT), so as to improve production efficiency and reduce costs. Summary of the Invention

[0006] The pixel circuit provided by the embodiment of the present disclosure includes:

[0007] Light-emitting devices;

[0008] a driving transistor coupled to the light emitting device and configured to generate a driving current for driving the light emitting device to emit light according to a data voltage signal;

[0009] a first control circuit coupled to the first node and configured to provide a signal from a reference voltage signal terminal to the first node in response to a signal from a first control signal terminal;

[0010] a first coupling control circuit coupled to the first node and the gate of the driving transistor, and configured to stabilize a voltage of the first node and a voltage of the gate of the driving transistor;

[0011] a second coupling control circuit coupled to the first node and the second electrode of the driving transistor, and configured to stabilize the voltage of the first node and the voltage of the second electrode of the driving transistor;

[0012] a second control circuit coupled to the gate of the driving transistor and the first electrode of the driving transistor, and configured to connect the gate of the driving transistor to the first electrode of the driving transistor in response to a signal at a second control signal terminal;

[0013] The data writing circuit is coupled to the gate of the driving transistor and is configured to provide the data voltage signal of the data signal terminal to the gate of the driving transistor in response to the signal of the first scanning signal terminal.

[0014] In some possible implementations, the first control circuit includes: a first transistor;

[0015] A gate of the first transistor is coupled to the first control signal terminal, a first electrode of the first transistor is coupled to the first node, and a second electrode of the first transistor is coupled to the reference voltage signal terminal.

[0016] In some possible implementations, the first coupling control circuit includes: a first capacitor;

[0017] A first electrode of the first capacitor is coupled to the gate of the driving transistor, and a second electrode of the first capacitor is coupled to the first node.

[0018] In some possible implementations, the second coupling control circuit includes: a second capacitor;

[0019] A first electrode of the second capacitor is coupled to the first node, and a second electrode of the second capacitor is coupled to the second electrode of the driving transistor.

[0020] In some possible implementations, the second control circuit includes: a second transistor;

[0021] The gate of the second transistor is coupled to the second control signal terminal, the first electrode of the second transistor is coupled to the gate of the driving transistor, and the second electrode of the second transistor is coupled to the first electrode of the driving transistor.

[0022] In some possible implementations, the data writing circuit includes: a third transistor;

[0023] The gate of the third transistor is coupled to the first scan signal terminal, the first electrode of the third transistor is coupled to the data signal terminal, and the second electrode of the third transistor is coupled to the gate of the driving transistor.

[0024] In some possible implementations, the system further includes: an initialization circuit coupled to the light-emitting device, configured to provide a signal from an initialization signal terminal to the light-emitting device in response to a signal from a reset signal terminal.

[0025] In some possible implementations, the initialization circuit includes: a fourth transistor;

[0026] A gate of the fourth transistor is coupled to the reset signal terminal, a first electrode of the fourth transistor is coupled to the second electrode of the driving transistor, and a second electrode of the fourth transistor is coupled to the initialization signal terminal.

[0027] In some possible implementations, the system further includes: a first light-emitting control circuit coupled to the first electrode of the driving transistor, configured to provide a signal from a first power supply terminal to the first electrode of the driving transistor in response to a signal from a first light-emitting control signal terminal.

[0028] In some possible implementations, the first light emitting control circuit includes: a fifth transistor;

[0029] A gate of the fifth transistor is coupled to the first light emitting control signal terminal, a first electrode of the fifth transistor is coupled to the first power supply terminal, and a second electrode of the fifth transistor is coupled to the first electrode of the driving transistor.

[0030] In some possible embodiments, the present invention further includes: a second light-emitting control circuit, which is located between the second electrode of the driving transistor and the light-emitting device, and is coupled to the second electrode of the driving transistor and the light-emitting device, and is configured to connect the second electrode of the driving transistor and the light-emitting device in response to a signal at the second light-emitting control signal terminal.

[0031] In some possible implementations, the second light emitting control circuit includes: a sixth transistor;

[0032] The gate of the sixth transistor is coupled to the second light emitting control signal terminal, the first electrode of the sixth transistor is coupled to the second electrode of the driving transistor, and the second electrode of the sixth transistor is coupled to the light emitting device.

[0033] In some possible implementations, the gate of the driving transistor includes: a first gate and a second gate; the first gate of the driving transistor is coupled to the data writing circuit, and the second gate of the driving transistor is coupled to the second electrode of the driving transistor.

[0034] The display device provided by the embodiment of the present disclosure includes the above-mentioned pixel circuit.

[0035] The embodiment of the present disclosure provides a driving method for the above pixel circuit, including:

[0036] In the reset phase, the first control circuit provides a signal from the reference voltage signal terminal to the first node in response to a signal from the first control signal terminal; the second control circuit connects the gate of the driving transistor to the first electrode of the driving transistor in response to a signal from the second control signal terminal;

[0037] In the threshold compensation stage, the first control circuit provides the signal of the reference voltage signal terminal to the first node in response to the signal of the first control signal terminal; the first coupling control circuit stabilizes the voltage of the first node and the voltage of the gate of the driving transistor; and the second coupling control circuit stabilizes the voltage of the first node and the voltage of the second electrode of the driving transistor;

[0038] In the data writing phase, the data writing circuit provides a data voltage signal at the data signal terminal to the gate of the driving transistor in response to a signal at the first scanning signal terminal; the first control circuit provides a signal at the reference voltage signal terminal to the first node in response to a signal at the first control signal terminal; the first coupling control circuit stabilizes the voltage at the first node and the voltage at the gate of the driving transistor; and the second coupling control circuit stabilizes the voltage at the first node and the voltage at the second electrode of the driving transistor.

[0039] In the light emitting stage, the driving transistor generates a driving current for driving the light emitting device to emit light according to the data voltage signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] FIG1 is a schematic diagram of some structures of pixel circuits provided by an embodiment of the present disclosure;

[0041] FIG2 is another schematic diagram of the structure of the pixel circuit provided by the embodiment of the present disclosure;

[0042] FIG3 is a flow chart of a driving method of a pixel circuit provided by an embodiment of the present disclosure;

[0043] FIG4 is a timing diagram of some signals provided by an embodiment of the present disclosure;

[0044] FIG5 is another signal timing diagram provided by an embodiment of the present disclosure;

[0045] FIG6 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0046] FIG7 is a schematic diagram of some further structures of pixel circuits provided by embodiments of the present disclosure;

[0047] FIG8 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0048] FIG9 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0049] FIG10 is a schematic diagram of some further structures of the pixel circuit provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0051] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0052] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present invention. The same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions.

[0053] The display device provided by the embodiment of the present disclosure includes: a display panel, and the display area of ​​the display panel includes a plurality of pixel units arranged in an array. Exemplarily, each pixel unit includes a plurality of sub-pixels. For example, the pixel unit may include a red sub-pixel, a green sub-pixel and a blue sub-pixel, so that red, green and blue can be mixed to achieve color display. Alternatively, the pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel and a white sub-pixel, so that red, green, blue and white can be mixed to achieve color display. Of course, in actual applications, the luminous color of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, and is not limited here.

[0054] In the disclosed embodiments, each sub-pixel includes a pixel circuit comprising a driver transistor and a light-emitting device to drive the light-emitting device to emit light, thereby enabling the display panel to display images. Due to factors such as process technology and device aging, the threshold voltage Vth of the driver transistor can vary. This causes variations in the current flowing through different light-emitting devices, resulting in uneven display brightness and, consequently, affecting the overall image quality.

[0055] Furthermore, if the driver transistors are defective, the display quality will also be affected. Since the material cost of the light-emitting devices in the subsequent light-emitting device manufacturing process is relatively high, if the array test (AT) is not first performed to check whether there are defects in the transistor manufacturing process, it will lead to waste of subsequent display backplane manufacturing costs and reduce production efficiency.

[0056] Therefore, an embodiment of the present disclosure provides a pixel circuit, as shown in FIG1 , comprising: a light emitting device L;

[0057] a driving transistor M0 coupled to the light emitting device L and configured to generate a driving current for driving the light emitting device L to emit light according to the data voltage signal;

[0058] The first control circuit 10 is coupled to the first node N1 and is configured to provide a signal of the reference voltage signal terminal VREF to the first node N1 in response to a signal of the first control signal terminal CS1;

[0059] a first coupling control circuit 20 coupled to the first node N1 and the gate of the driving transistor M0 and configured to stabilize the voltage of the first node N1 and the gate of the driving transistor M0;

[0060] a second coupling control circuit 30 coupled to the first node N1 and the second electrode of the driving transistor M0 and configured to stabilize the voltage of the first node N1 and the voltage of the second electrode of the driving transistor M0;

[0061] The second control circuit 40 is coupled to the gate of the driving transistor M0 and the first electrode of the driving transistor M0 and is configured to connect the gate of the driving transistor M0 and the first electrode of the driving transistor M0 in response to the signal of the second control signal terminal CS2;

[0062] The data writing circuit 50 is coupled to the gate of the driving transistor M0 and is configured to provide a data voltage signal of the data signal terminal DA to the gate of the driving transistor M0 in response to a signal of the first scan signal terminal SS1 .

[0063] In the embodiment of the present disclosure, through the mutual cooperation of the first control circuit, the first coupling control circuit, the second coupling control circuit, the second control circuit and the data writing circuit, it is possible to test the driving transistor when performing an array test (AT) before the light-emitting device preparation process, so as to determine whether the driving transistor is defective, thereby reducing the waste of display backplane manufacturing costs, that is, improving production efficiency and reducing costs.

[0064] Moreover, in the embodiment of the present disclosure, by using different paths for compensating the threshold voltage of the driving transistor and for writing the data voltage, the threshold voltage compensation of the driving transistor and the writing of the data voltage are performed separately, thereby achieving high-frequency driving and avoiding the influence of the threshold voltage drift of the driving transistor on the luminescence of the light-emitting device.

[0065] In the embodiment of the present disclosure, as shown in FIG1 , the driving transistor M0 can be configured as an N-type transistor; wherein the first electrode of the driving transistor M0 can be its source electrode, and the second electrode of the driving transistor M0 can be its drain electrode. Of course, the driving transistor M0 can also be configured as a P-type transistor, which is not limited here.

[0066] In the embodiment of the present disclosure, as shown in FIG1 , the second electrode of the driving transistor M0 is coupled to the anode of the light-emitting device L, and the cathode of the light-emitting device L is coupled to the second power supply terminal VSS. Exemplarily, the light-emitting device L may include at least one of: a micro light-emitting diode (Micro Light Emitting Diode, Micro LED), an organic light-emitting diode (Organic Light Emitting Diode, OLED) and a quantum dot light-emitting diode (Quantum Dot Light Emitting Diodes, QLED). Exemplarily, the light-emitting device L may include a stacked anode, a light-emitting layer, and a cathode. Furthermore, the light-emitting layer may also include film layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. In actual applications, the specific structure of the light-emitting device can be designed and determined according to the actual application environment, and is not limited here.

[0067] In some embodiments of the present disclosure, as shown in Figure 2, the first control circuit 10 includes: a first transistor M1; wherein the gate of the first transistor M0 is coupled to the first control signal terminal CS1, the first electrode of the first transistor M1 is coupled to the first node N1, and the second electrode of the first transistor M1 is coupled to the reference voltage signal terminal VREF.

[0068] For example, the first transistor M1 can be turned on under the control of the active level of the first control signal transmitted by the first control signal terminal CS1, and can be turned off under the control of the inactive level of the first control signal. For example, if the first transistor M1 is configured as a P-type transistor, the active level of the first control signal is a low level, and the inactive level of the first control signal is a high level. Alternatively, if the first transistor M1 is configured as an N-type transistor, the active level of the first control signal is a high level, and the inactive level of the first control signal is a low level.

[0069] In some embodiments of the present disclosure, as shown in FIG2 , the first coupling control circuit 20 includes: a first capacitor C1 ; wherein a first electrode of the first capacitor C1 is coupled to the gate of the driving transistor M0 , and a second electrode of the first capacitor C1 is coupled to the first node N1 .

[0070] In some embodiments of the present disclosure, as shown in FIG2 , the second coupling control circuit 30 includes: a second capacitor C2 ; wherein a first electrode of the second capacitor C2 is coupled to the first node N1 , and a second electrode of the second capacitor C2 is coupled to the second electrode of the driving transistor M0 .

[0071] In some embodiments of the present disclosure, as shown in Figure 2, the second control circuit 40 includes: a second transistor M2; wherein the gate of the second transistor M2 is coupled to the second control signal terminal CS2, the first electrode of the second transistor M2 is coupled to the gate of the driving transistor M0, and the second electrode of the second transistor M2 is coupled to the first electrode of the driving transistor M0.

[0072] For example, the second transistor M2 can be turned on under the control of the active level of the second control signal transmitted by the second control signal terminal CS2, and can be turned off under the control of the inactive level of the second control signal. For example, if the second transistor M2 is configured as a P-type transistor, the active level of the second control signal is a low level, and the inactive level of the second control signal is a high level. Alternatively, if the second transistor M2 is configured as an N-type transistor, the active level of the second control signal is a high level, and the inactive level of the second control signal is a low level.

[0073] In some embodiments of the present disclosure, as shown in Figure 2, the data writing circuit 50 includes: a third transistor M3; wherein the gate of the third transistor M3 is coupled to the first scan signal terminal SS1, the first electrode of the third transistor M3 is coupled to the data signal terminal DA, and the second electrode of the third transistor M3 is coupled to the gate of the driving transistor M0.

[0074] Exemplarily, the third transistor M3 can be turned on under the control of the active level of the first scan signal transmitted by the first scan signal terminal SS1, and can be turned off under the control of the inactive level of the first scan signal. Exemplarily, if the third transistor M3 is configured as a P-type transistor, the active level of the first scan signal is a low level, and the inactive level of the first scan signal is a high level. Alternatively, if the third transistor M3 is configured as an N-type transistor, the active level of the first scan signal is a high level, and the inactive level of the first scan signal is a low level.

[0075] In some embodiments of the present disclosure, as shown in FIG. 2 , the system further includes an initialization circuit 60 coupled to the light emitting device L and configured to provide a signal from an initialization signal terminal VINIT to the light emitting device L in response to a signal from a reset signal terminal RE.

[0076] In some embodiments of the present disclosure, as shown in Figure 2, the initialization circuit 60 includes: a fourth transistor M4; wherein the gate of the fourth transistor M4 is coupled to the reset signal terminal RE, the first electrode of the fourth transistor M4 is coupled to the second electrode of the driving transistor M0, and the second electrode of the fourth transistor M4 is coupled to the initialization signal terminal VINIT.

[0077] Exemplarily, the fourth transistor M4 can be turned on under the control of the active level of the reset signal transmitted by the reset signal terminal RE, and can be turned off under the control of the inactive level of the reset signal. Exemplarily, the fourth transistor M4 is configured as a P-type transistor, then the active level of the reset signal is a low level, and the inactive level of the reset signal is a high level. Alternatively, the fourth transistor M4 is configured as an N-type transistor, then the active level of the reset signal is a high level, and the inactive level of the reset signal is a low level.

[0078] For example, the reference voltage signal terminal VREF and the initialization signal terminal VINIT may be loaded with the same signal, which can reduce the number of signal lines, reduce the space occupied by wiring, and simplify circuit design.

[0079] In some embodiments of the present disclosure, as shown in Figure 2, it also includes: a first light-emitting control circuit 70, coupled to the first electrode of the driving transistor M0, and configured to provide a signal from the first power supply terminal VDD to the first electrode of the driving transistor M0 in response to a signal from the first light-emitting control signal terminal EM1.

[0080] In some embodiments of the present disclosure, as shown in Figure 2, the first light-emitting control circuit 70 includes: a fifth transistor M5; wherein the gate of the fifth transistor M5 is coupled to the first light-emitting control signal terminal EM1, the first electrode of the fifth transistor M5 is coupled to the first power supply terminal VDD, and the second electrode of the fifth transistor M5 is coupled to the first electrode of the driving transistor M0.

[0081] Exemplarily, the fifth transistor M5 can be turned on under the control of the active level of the first light-emitting control signal transmitted by the first light-emitting control signal terminal EM1, and can be turned off under the control of the inactive level of the first light-emitting control signal. Exemplarily, if the fifth transistor M5 is configured as a P-type transistor, the active level of the first light-emitting control signal is a low level, and the inactive level of the first light-emitting control signal is a high level. Alternatively, if the fifth transistor M5 is configured as an N-type transistor, the active level of the first light-emitting control signal is a high level, and the inactive level of the first light-emitting control signal is a low level.

[0082] In some embodiments of the present disclosure, as shown in Figure 2, the driving transistor M0 is a dual-gate transistor, and the gate of the driving transistor M0 includes: a first gate G1 and a second gate G2; the first gate G1 of the driving transistor M0 is coupled to the second electrode of the third transistor M3 in the data writing circuit 50, and the second gate G2 of the driving transistor M0 is coupled to the second electrode of the driving transistor M0.

[0083] For example, the first electrode of the transistor can be its source electrode, and the second electrode can be its drain electrode. Alternatively, the first electrode can be its drain electrode, and the second electrode can be its source electrode. This is not limited here.

[0084] Generally, transistors using low-temperature polysilicon (LTPS) as active layers have high mobility and can be made thinner and smaller, with lower power consumption. In a specific implementation, the active layer of at least one of the transistors can be made of low-temperature polysilicon. This allows the transistor to be an LTPS transistor, thereby achieving high mobility in the pixel circuit, and allowing it to be made thinner and smaller, with lower power consumption.

[0085] Generally, transistors using metal oxide semiconductor materials as their active layers have low leakage current. Therefore, to reduce leakage current, in some embodiments of the present disclosure, the active layer of at least one of the transistors may include a metal oxide semiconductor material, such as IGZO (Indium Gallium Zinc Oxide). Of course, other metal oxide semiconductor materials are also possible and are not limited here. In this way, the transistor can be configured as an oxide thin film transistor, thereby reducing leakage current in the pixel circuit.

[0086] Exemplarily, all transistors may be configured as LTPS transistors.

[0087] Alternatively, all transistors can be configured as oxide-type transistors. Since metal oxides are relatively inexpensive, there is no need to use laser equipment for crystallization.

[0088] Alternatively, some transistors may be configured as oxide-type transistors, and the remaining transistors may be configured as LTPS-type transistors.

[0089] In the disclosed embodiment, the first power supply terminal VDD can be configured to load a constant first power supply voltage VDD, and the first power supply voltage VDD is generally positive. Furthermore, the second power supply terminal VSS can be configured to load a constant second power supply voltage VSS, and the second power supply voltage VSS can generally be ground or negative. In actual applications, the specific values ​​of the first power supply voltage VDD and the second power supply voltage VSS can be designed and determined based on the actual application environment and are not limited here.

[0090] The driving method of the pixel circuit provided by the embodiment of the present disclosure, as shown in FIG3 , includes the following steps:

[0091] S100, reset stage, the first control circuit provides the signal of the reference voltage signal terminal to the first node in response to the signal of the first control signal terminal; the second control circuit connects the gate of the driving transistor to the first electrode of the driving transistor in response to the signal of the second control signal terminal;

[0092] S200, threshold compensation stage, the first control circuit provides the signal of the reference voltage signal terminal to the first node in response to the signal of the first control signal terminal; the first coupling control circuit stabilizes the voltage of the first node and the voltage of the gate of the driving transistor; the second coupling control circuit stabilizes the voltage of the first node and the voltage of the second electrode of the driving transistor;

[0093] S300, data writing stage, the data writing circuit provides a data voltage signal at the data signal terminal to the gate of the driving transistor in response to the signal at the first scanning signal terminal; the first control circuit provides a signal at the reference voltage signal terminal to the first node in response to the signal at the first control signal terminal; the first coupling control circuit stabilizes the voltage at the first node and the voltage at the gate of the driving transistor; the second coupling control circuit stabilizes the voltage at the first node and the voltage at the second electrode of the driving transistor;

[0094] S400, light emitting stage, the driving transistor generates a driving current for driving the light emitting device to emit light according to the data voltage signal.

[0095] The following describes the working process of the pixel circuit provided by the embodiment of the present disclosure by taking the pixel circuit shown in FIG. 2 as an example and combining it with the signal timing diagram shown in FIG. 4 .

[0096] In the embodiment of the present disclosure, as shown in Figure 4, em1 represents the first light-emitting control signal of the first light-emitting control signal terminal EM1, cs1 represents the first control signal of the first control signal terminal CS1, cs2 represents the second control signal of the second control signal terminal CS2, re represents the reset signal of the reset signal terminal RE, ss1 represents the first scan signal of the first scan signal terminal SS1, and da represents the data voltage signal of the data signal terminal DA.

[0097] Furthermore, a reset phase F1 , a threshold compensation phase F2 , a data writing phase F3 and a light emitting phase F4 in one display frame are selected.

[0098] In the reset stage F1, the first transistor M1 is turned on under the control of the high level of the first control signal cs1, the second transistor M2 is turned on under the control of the high level of the second control signal cs2, the third transistor M3 is turned off under the control of the low level of the first scanning signal ss1, the fourth transistor M4 is turned on under the control of the high level of the reset signal re, and the fifth transistor M5 is turned on under the control of the high level of the first light-emitting control signal em1. The turned-on first transistor M1 provides the signal of the reference voltage signal terminal VREF to the first node N1, then the voltage value VN1 of the first node N1 is Vref, where Vref represents the voltage value of the signal of the reference voltage signal terminal VREF; the turned-on fifth transistor M5 provides the signal of the first power supply terminal VDD to the first electrode of the driving transistor M0, and the turned-on second transistor M2 conducts the first electrode of the driving transistor M0 with the first gate G1 of the driving transistor M0, then the voltage value Vg1 of the first gate G1 of the driving transistor M0 is vdd, where vdd represents the first power supply voltage of the first power supply terminal VDD; the turned-on fourth transistor M4 provides the signal of the initialization signal terminal VINIT to the anode of the light-emitting device L, then the voltage value VL of the anode of the light-emitting device L is Vinit, where Vinit represents the voltage value of the signal of the initialization signal terminal VINIT.

[0099] In the threshold compensation stage F2, the first transistor M1 is turned on under the control of the high level of the first control signal cs1, the second transistor M2 is turned off under the control of the low level of the second control signal cs2, the third transistor M3 is turned off under the control of the low level of the first scan signal ss1, the fourth transistor M4 is turned off under the control of the low level of the reset signal re, and the fifth transistor M5 is turned on under the control of the high level of the first light-emitting control signal em1. The turned-on fifth transistor M5 provides the signal of the first power supply terminal VDD to the first electrode of the driving transistor M0; the turned-on first transistor M1 provides the signal of the reference voltage signal terminal VREF to the first node N1, then the voltage value VN1 of the first node N1 is Vref, the first capacitor C1 stabilizes the voltage of the first node N1 and the voltage of the first gate G1 of the driving transistor M0; the second capacitor C2 stabilizes the voltage of the first node N1 and the voltage of the second electrode of the driving transistor M0, and completes the compensation of the threshold voltage Vth of the driving transistor M0 in a source follower manner, then the voltage value Vg1 of the first gate G1 of the driving transistor M0 is vdd, and the voltage value Vs of the second electrode of the driving transistor M0 is vdd-Vth.

[0100] During the data writing phase F3, the first transistor M1 is turned on by the high level of the first control signal cs1, the second transistor M2 is turned off by the low level of the second control signal cs2, the third transistor M3 is turned on by the high level of the first scan signal ss1, the fourth transistor M4 is turned off by the low level of the reset signal re, and the fifth transistor M5 is turned off by the low level of the first emission control signal em1. The turned-on first transistor M1 provides the reference voltage signal terminal VREF to the first node N1. The first capacitor C1 stabilizes the voltage at the first node N1 and the voltage at the first gate electrode G1 of the driving transistor M0. The second capacitor C2 stabilizes the voltage at the first node N1 and the voltage at the second electrode of the driving transistor M0. The turned-on third transistor M3 provides the data voltage signal da at the data signal terminal DA to the first gate electrode G1 of the driving transistor M0. Consequently, the voltage Vg1 of the first gate electrode G1 of the driving transistor M0 is equal to Vda, where Vda represents the voltage of the data voltage signal da. The voltage Vs of the second electrode of the driving transistor M0 is equal to vdd-Vth.

[0101] During the light-emitting phase F4, the first transistor M1 is turned off by the low level of the first control signal cs1, the second transistor M2 is turned off by the low level of the second control signal cs2, the third transistor M3 is turned off by the low level of the first scan signal ss1, the fourth transistor M4 is turned off by the low level of the reset signal re, and the fifth transistor M5 is turned on by the high level of the first light-emitting control signal em1. The turned-on fifth transistor M5 provides the signal from the first power supply terminal VDD to the first electrode of the driving transistor M0. The driving transistor M0 generates a driving current based on the data voltage signal da. This driving current charges the anode of the light-emitting device L until the light-emitting device L stably emits light. At this time, the voltage value VL at the anode of the light-emitting device L is Vs = vdd - Vth. The voltage value Vg1 of the first gate electrode G1 of the driving transistor M0 is Vda. Therefore, the voltage difference Vgs between the first gate electrode G1 and the source electrode of the driving transistor M0 is Vda - vdd + Vth. Therefore, the driving transistor M0 operates in the saturation region, and the driving current I generated by it can be expressed as: I = K * (Vgs - Vth). 2 =K*(Vda-vdd+Vth-Vth) 2 =K*(Vda-vdd) 2 ;in, Where, μ represents the mobility of the driving transistor M0, C ox represents the capacitance per unit area of ​​the gate insulating layer of the driving transistor M0, represents the channel width-to-length ratio of the driving transistor M0.

[0102] As can be seen from the above, the drive current I is unrelated to the threshold voltage Vth of the drive transistor M0. Therefore, the pixel circuit can solve the problem of uneven threshold voltage compensation of the drive transistor, thereby improving the display effect. In addition, the path for compensating the threshold voltage of the drive transistor is different from the path for writing the data voltage. This allows the threshold voltage compensation of the drive transistor to be performed separately from the data voltage writing. This can achieve high-frequency driving and prevent the impact of threshold voltage drift of the drive transistor on the light emission of the light-emitting device.

[0103] The following describes the array detection process of the pixel circuit provided by the embodiment of the present disclosure by taking the pixel circuit shown in FIG. 2 as an example and combining it with the signal timing diagram shown in FIG. 5 .

[0104] In the embodiment of the present disclosure, as shown in Figure 5, em1 represents the first light-emitting control signal of the first light-emitting control signal terminal EM1, cs1 represents the first control signal of the first control signal terminal CS1, cs2 represents the second control signal of the second control signal terminal CS2, re represents the reset signal of the reset signal terminal RE, ss1 represents the first scan signal of the first scan signal terminal SS1, and da represents the data voltage signal of the data signal terminal DA.

[0105] In the initialization stage T1, the first transistor M1 is turned on under the control of the high level of the first control signal cs1, the second transistor M2 is turned on under the control of the high level of the second control signal cs2, the third transistor M3 is turned off under the control of the low level of the first scan signal ss1, the fourth transistor M4 is turned on under the control of the high level of the reset signal re, and the fifth transistor M5 is turned on under the control of the high level of the first light-emitting control signal em1. The turned-on first transistor M1 provides the signal of the reference voltage signal terminal VREF to the first node N1, then the voltage value VN1 of the first node N1 is Vref, where Vref represents the voltage value of the signal of the reference voltage signal terminal VREF; the turned-on fifth transistor M5 provides the signal of the first power supply terminal VDD to the first electrode of the driving transistor M0, and the turned-on second transistor M2 conducts the first electrode of the driving transistor M0 with the first gate G1 of the driving transistor M0, then the voltage value Vg1 of the first gate G1 of the driving transistor M0 is vdd, where vdd represents the first power supply voltage of the first power supply terminal VDD; the turned-on fourth transistor M4 provides the signal of the initialization signal terminal VINIT to the anode of the light-emitting device L, then the voltage value VL of the anode of the light-emitting device L is Vinit, where Vinit represents the voltage value of the signal of the initialization signal terminal VINIT.

[0106] During the detection phase, the first transistor M1 is turned on by a high level of the first control signal cs1, the second transistor M2 is turned on by a high level of the second control signal cs2, the third transistor M3 is turned on by a high level of the first scan signal ss1, the fourth transistor M4 is turned off by a low level of the reset signal re, and the fifth transistor M5 is turned off by a low level of the first emission control signal em1. The turned-on first transistor M1 provides a signal from the reference voltage signal terminal VREF to the first node N1, the turned-on second transistor M2 connects the first electrode of the drive transistor M0 to the first gate G1 of the drive transistor M0, and the turned-on third transistor M3 provides a detection signal te to the first gate G1 of the drive transistor M0. The detection signal te passes through the third transistor M3, the second transistor M2, and the drive transistor M0 to the second electrode of the drive transistor M0, and is used to detect whether the third transistor M3, the second transistor M2, and the drive transistor M0 are defective. After confirming that the third transistor M3, the second transistor M2, and the drive transistor M0 are not defective, the display backplane is confirmed to enter the next manufacturing process.

[0107] For example, the existence of a voltage divider caused by the parasitic capacitance Coled of the light-emitting device L (ie, the capacitance formed by the cathode and anode of the light-emitting device L) may also affect the display effect, causing a decrease in display quality.

[0108] The present disclosure provides some other schematic diagrams of pixel circuit structures, as shown in Figure 6, which are variations of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0109] In other embodiments of the present disclosure, as shown in Figure 6, it also includes: a second light-emitting control circuit 80, which is located between the second electrode of the driving transistor M0 and the light-emitting device L, and coupled to the second electrode of the driving transistor M0 and the light-emitting device L, and is configured to respond to the signal of the second light-emitting control signal terminal EM2 to turn on the second electrode of the driving transistor M0 and the light-emitting device L.

[0110] The embodiment of the present disclosure can effectively avoid voltage division of the parasitic capacitance Coled (i.e., the capacitance formed by the cathode and anode of the light-emitting device L) of the light-emitting device L by setting a second light-emitting control circuit, thereby improving the display effect and avoiding degradation of display quality.

[0111] In other embodiments of the present disclosure, as shown in Figure 7, the second light-emitting control circuit 80 includes: a sixth transistor M6; wherein the gate of the sixth transistor M6 is coupled to the second light-emitting control signal terminal EM2, the first electrode of the sixth transistor M6 is coupled to the second electrode of the driving transistor M0, and the second electrode of the sixth transistor M6 is coupled to the light-emitting device L.

[0112] Exemplarily, the sixth transistor M6 can be turned on under the control of the active level of the second light-emitting control signal transmitted by the second light-emitting control signal terminal EM2, and can be turned off under the control of the inactive level of the second light-emitting control signal. Exemplarily, if the sixth transistor M6 is configured as a P-type transistor, the active level of the second light-emitting control signal is a low level, and the inactive level of the second light-emitting control signal is a high level. Alternatively, if the sixth transistor M6 is configured as an N-type transistor, the active level of the second light-emitting control signal is a high level, and the inactive level of the second light-emitting control signal is a low level.

[0113] For example, the first light-emitting control signal terminal EM1 and the second light-emitting control signal terminal EM2 may be loaded with the same signal, which can reduce the number of signal lines, reduce the space occupied by wiring, and simplify circuit design.

[0114] The following describes the working process of the pixel circuit provided by the embodiment of the present disclosure by taking the pixel circuit shown in FIG. 2 as an example and combining it with the signal timing diagram shown in FIG. 8 .

[0115] In the embodiment of the present disclosure, as shown in Figure 8, em1 represents the first light-emitting control signal of the first light-emitting control signal terminal EM1, em2 represents the second light-emitting control signal of the second light-emitting control signal terminal EM2, cs1 represents the first control signal of the first control signal terminal CS1, cs2 represents the second control signal of the second control signal terminal CS2, re represents the reset signal of the reset signal terminal RE, ss1 represents the first scan signal of the first scan signal terminal SS1, and da represents the data voltage signal of the data signal terminal DA.

[0116] Furthermore, a reset phase F1 , a threshold compensation phase F2 , a data writing phase F3 and a light emitting phase F4 in one display frame are selected.

[0117] In the reset phase F1, the first transistor M1 is turned on under the control of the high level of the first control signal cs1, the second transistor M2 is turned on under the control of the high level of the second control signal cs2, the third transistor M3 is turned off under the control of the low level of the first scan signal ss1, the fourth transistor M4 is turned on under the control of the high level of the reset signal re, the fifth transistor M5 is turned on under the control of the high level of the first light-emitting control signal em1, and the sixth transistor M6 is turned on under the control of the high level of the second light-emitting control signal em2. The turned-on first transistor M1 provides the signal of the reference voltage signal terminal VREF to the first node N1, and the voltage value VN1 of the first node N1 is Vref, where Vref represents the voltage value of the signal of the reference voltage signal terminal VREF; the turned-on fifth transistor M5 provides the signal of the first power supply terminal VDD to the first electrode of the driving transistor M0, and the turned-on second transistor M2 conducts the first electrode of the driving transistor M0 with the first gate G1 of the driving transistor M0, and the voltage value Vg1 of the first gate G1 of the driving transistor M0 is Vdd, where vdd represents the first power supply voltage of the first power supply terminal VDD; the turned-on fourth transistor M4 provides the signal of the initialization signal terminal VINIT to the second electrode of the driving transistor M0, and the turned-on sixth transistor M6 conducts the second electrode of the driving transistor M0 with the anode of the light-emitting device L, and the voltage value VL of the anode of the light-emitting device L is Vinit, where Vinit represents the voltage value of the signal of the initialization signal terminal VINIT.

[0118] In the threshold compensation stage F2, the first transistor M1 is turned on under the control of the high level of the first control signal cs1, the second transistor M2 is turned off under the control of the low level of the second control signal cs2, the third transistor M3 is turned off under the control of the low level of the first scan signal ss1, the fourth transistor M4 is turned off under the control of the low level of the reset signal re, the fifth transistor M5 is turned on under the control of the high level of the first light-emitting control signal em1, and the sixth transistor M6 is turned on under the control of the high level of the second light-emitting control signal em2. The conductive fifth transistor M5 provides the signal of the first power supply terminal VDD to the first electrode of the driving transistor M0; the conductive sixth transistor M6 connects the second electrode of the driving transistor M0 to the anode of the light-emitting device L; the conductive first transistor M1 provides the signal of the reference voltage signal terminal VREF to the first node N1, then the voltage value VN1 of the first node N1 is Vref, the first capacitor C1 stabilizes the voltage of the first node N1 and the voltage of the first gate G1 of the driving transistor M0; the second capacitor C2 stabilizes the voltage of the first node N1 and the voltage of the second electrode of the driving transistor M0, and completes compensation for the threshold voltage Vth of the driving transistor M0 in a source follower manner, then, the voltage value Vg1 of the first gate G1 of the driving transistor M0 is vdd, and the voltage value Vs of the second electrode of the driving transistor M0 is vdd-Vth.

[0119] In the data writing stage F3, the first transistor M1 is turned on under the control of the high level of the first control signal cs1, the second transistor M2 is turned off under the control of the low level of the second control signal cs2, the third transistor M3 is turned on under the control of the high level of the first scan signal ss1, the fourth transistor M4 is turned off under the control of the low level of the reset signal re, the fifth transistor M5 is turned off under the control of the low level of the first light-emitting control signal em1, and the sixth transistor M6 is turned off under the control of the low level of the second light-emitting control signal em2. The turned-on first transistor M1 provides the signal of the reference voltage signal terminal VREF to the first node N1, the first capacitor C1 stabilizes the voltage of the first node N1 and the voltage of the first gate G1 of the driving transistor M0, the second capacitor C2 stabilizes the voltage of the first node N1 and the voltage of the second electrode of the driving transistor M0, and the turned-on third transistor M3 provides the data voltage signal da of the data signal terminal DA to the first gate G1 of the driving transistor M0. Then, the voltage value Vg1 of the first gate G1 of the driving transistor M0 is Vda, where Vda represents the voltage value of the data voltage signal da, and the voltage value Vs of the second electrode of the driving transistor M0 is vdd-Vth.

[0120] In the light-emitting phase F4, the first transistor M1 is turned off by the low level of the first control signal cs1, the second transistor M2 is turned off by the low level of the second control signal cs2, the third transistor M3 is turned off by the low level of the first scan signal ss1, the fourth transistor M4 is turned off by the low level of the reset signal re, the fifth transistor M5 is turned on by the high level of the first light-emitting control signal em1, and the sixth transistor M6 is turned on by the high level of the second light-emitting control signal em2. The turned-on fifth transistor M5 provides the signal from the first power supply terminal VDD to the first electrode of the driving transistor M0, and the turned-on sixth transistor M6 connects the second electrode of the driving transistor M0 to the anode of the light-emitting device L. The driving transistor M0 generates a driving current based on the data voltage signal da, which charges the anode of the light-emitting device L until the light-emitting device L stably emits light. At this time, the voltage value VL at the anode of the light-emitting device L is VL = Vs = vdd - Vth. The voltage value of the first gate G1 of the driving transistor M0 is Vg1 = Vda. Therefore, the voltage difference between the first gate G1 and the source of the driving transistor M0 is Vgs = Vda - vdd + Vth. The driving transistor M0 operates in the saturation region, and the driving current I generated by it can be expressed as: I = K * (Vgs - Vth). 2 =K*(Vda-vdd+Vth-Vth) 2 =K*(Vda-vdd) 2 ;in, Where, μ represents the mobility of the driving transistor M0, C ox represents the capacitance per unit area of ​​the gate insulating layer of the driving transistor M0, represents the channel width-to-length ratio of the driving transistor M0.

[0121] As can be seen from the above, the drive current I is unrelated to the threshold voltage Vth of the drive transistor M0. Therefore, the pixel circuit can solve the problem of uneven threshold voltage compensation of the drive transistor, thereby improving the display effect. In addition, the path for compensating the threshold voltage of the drive transistor is different from the path for writing the data voltage. This allows the threshold voltage compensation of the drive transistor to be performed separately from the data voltage writing. This can achieve high-frequency driving and prevent the impact of threshold voltage drift of the drive transistor on the light emission of the light-emitting device.

[0122] For example, since the first power supply terminal VDD is prone to voltage drop (IR Drop), the first power supply voltage vdd of the first power supply terminal VDD is uneven, thereby affecting the display effect and causing the display quality to deteriorate.

[0123] The present disclosure provides some structural diagrams of pixel circuits, as shown in Figure 9, which are modified from the implementation of the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0124] In the embodiment of the present disclosure, as shown in FIG9 , it further includes: a reset circuit 90, which is configured to provide a signal of the initialization signal terminal VINIT to the cathode of the light-emitting device L in response to a signal of the reset signal terminal RE; wherein the reset circuit 90 includes: a seventh transistor M7; the gate of the seventh transistor M7 is coupled to the reset signal terminal RE, the first electrode of the seventh transistor M7 is coupled to the cathode of the light-emitting device L, and the second electrode of the seventh transistor M7 is coupled to the initialization signal terminal VINIT. In addition, the anode of the light-emitting device L is coupled to the first power supply terminal VDD, and the cathode of the light-emitting device L is coupled to the first electrode of the fifth transistor M5. This arrangement can avoid the situation where a voltage drop (IR Drop) occurs at the first power supply terminal VDD, resulting in uneven first power supply voltage vdd, which causes a decrease in display quality and poor display effect.

[0125] Alternatively, as shown in FIG10 , the anode of the light-emitting device L is coupled to the first power supply terminal VDD, and the cathode of the light-emitting device L is coupled to the first electrode of the fifth transistor M5. The first electrode of the fourth transistor M4 in the initialization circuit 60 is coupled to the cathode of the light-emitting device L. This arrangement can avoid a voltage drop (IR drop) at the first power supply terminal VDD, which causes uneven first power supply voltage VDD and thus degrades display quality and poor display effects.

[0126] For example, the voltage drop problem in the pixel circuit can be improved by inverting the light-emitting device L, or by graphing the second power supply terminal VSS, or by arranging the anodes of the light-emitting device L in a grid pattern, thereby improving the display effect.

[0127] Based on the same disclosed concept, the present disclosure also provides a display device including the aforementioned pixel circuit provided in the present disclosure. The principles of this display device are similar to those of the aforementioned pixel circuit, so the implementation of this display device can refer to the implementation of the aforementioned pixel circuit, and the repeated parts will not be repeated here.

[0128] In specific implementations, in the embodiments of the present disclosure, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, an electronic watch, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. Other essential components of the display device are well understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present disclosure.

[0129] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0130] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A pixel circuit, wherein: include: Light-emitting devices; a driving transistor coupled to the light emitting device and configured to generate a driving current for driving the light emitting device to emit light according to a data voltage signal; a first control circuit coupled to the first node and configured to provide a signal from a reference voltage signal terminal to the first node in response to a signal from a first control signal terminal; a first coupling control circuit coupled to the first node and the gate of the driving transistor, and configured to stabilize a voltage of the first node and a voltage of the gate of the driving transistor; a second coupling control circuit coupled to the first node and the second electrode of the driving transistor, and configured to stabilize the voltage of the first node and the voltage of the second electrode of the driving transistor; a second control circuit coupled to the gate of the driving transistor and the first electrode of the driving transistor, and configured to connect the gate of the driving transistor to the first electrode of the driving transistor in response to a signal at a second control signal terminal; The data writing circuit is coupled to the gate of the driving transistor and is configured to provide the data voltage signal of the data signal terminal to the gate of the driving transistor in response to the signal of the first scanning signal terminal.

2. The pixel circuit according to claim 1, wherein: The first control circuit includes: a first transistor; A gate of the first transistor is coupled to the first control signal terminal, a first electrode of the first transistor is coupled to the first node, and a second electrode of the first transistor is coupled to the reference voltage signal terminal.

3. The pixel circuit according to claim 1, wherein: The first coupling control circuit includes: a first capacitor; A first electrode of the first capacitor is coupled to the gate of the driving transistor, and a second electrode of the first capacitor is coupled to the first node.

4. The pixel circuit according to claim 1, wherein: The second coupling control circuit includes: a second capacitor; A first electrode of the second capacitor is coupled to the first node, and a second electrode of the second capacitor is coupled to the second electrode of the driving transistor.

5. The pixel circuit according to claim 1, wherein: The second control circuit includes: a second transistor; The gate of the second transistor is coupled to the second control signal terminal, the first electrode of the second transistor is coupled to the gate of the driving transistor, and the second electrode of the second transistor is coupled to the first electrode of the driving transistor.

6. The pixel circuit according to claim 1, wherein: The data writing circuit includes: a third transistor; The gate of the third transistor is coupled to the first scan signal terminal, the first electrode of the third transistor is coupled to the data signal terminal, and the second electrode of the third transistor is coupled to the gate of the driving transistor.

7. The pixel circuit according to any one of claims 1 to 6, wherein: Also includes: The initialization circuit is coupled to the light emitting device and configured to provide a signal at an initialization signal terminal to the light emitting device in response to a signal at a reset signal terminal.

8. The pixel circuit according to claim 7, wherein: The initialization circuit includes: a fourth transistor; A gate of the fourth transistor is coupled to the reset signal terminal, a first electrode of the fourth transistor is coupled to the second electrode of the driving transistor, and a second electrode of the fourth transistor is coupled to the initialization signal terminal.

9. The pixel circuit according to any one of claims 1 to 8, wherein: Also includes: The first light emitting control circuit is coupled to the first electrode of the driving transistor and is configured to provide a signal from a first power supply terminal to the first electrode of the driving transistor in response to a signal from a first light emitting control signal terminal.

10. The pixel circuit according to claim 9, wherein: The first light emitting control circuit includes: a fifth transistor; A gate of the fifth transistor is coupled to the first light emitting control signal terminal, a first electrode of the fifth transistor is coupled to the first power supply terminal, and a second electrode of the fifth transistor is coupled to the first electrode of the driving transistor.

11. The pixel circuit according to any one of claims 1 to 10, wherein: Also includes: The second light-emitting control circuit is located between the second electrode of the driving transistor and the light-emitting device, and is coupled to the second electrode of the driving transistor and the light-emitting device, and is configured to connect the second electrode of the driving transistor and the light-emitting device in response to a signal at the second light-emitting control signal terminal.

12. The pixel circuit according to claim 11, wherein: The second light emitting control circuit includes: a sixth transistor; The gate of the sixth transistor is coupled to the second light emitting control signal terminal, the first electrode of the sixth transistor is coupled to the second electrode of the driving transistor, and the second electrode of the sixth transistor is coupled to the light emitting device.

13. The pixel circuit according to any one of claims 1 to 12, wherein: The gate of the driving transistor includes: a first gate and a second gate; the first gate of the driving transistor is coupled to the data writing circuit, and the second gate of the driving transistor is coupled to the second electrode of the driving transistor.

14. A display device, wherein: The method comprises the pixel circuit according to any one of claims 1 to 13.

15. A driving method for a pixel circuit according to any one of claims 1 to 13, wherein: include: In the reset phase, the first control circuit provides a signal from the reference voltage signal terminal to the first node in response to a signal from the first control signal terminal; The second control circuit connects the gate of the driving transistor to the first electrode of the driving transistor in response to a signal at the second control signal terminal; In the threshold compensation stage, the first control circuit provides a signal from the reference voltage signal terminal to the first node in response to a signal from the first control signal terminal; A first coupling control circuit stabilizes a voltage of the first node and a voltage of the gate of the driving transistor; A second coupling control circuit stabilizes the voltage of the first node and the voltage of the second electrode of the driving transistor; In the data writing phase, the data writing circuit provides a data voltage signal of the data signal terminal to the gate of the driving transistor in response to the signal of the first scanning signal terminal; The first control circuit provides a signal from a reference voltage signal terminal to the first node in response to a signal from a first control signal terminal; A first coupling control circuit stabilizes a voltage of the first node and a voltage of the gate of the driving transistor; A second coupling control circuit stabilizes the voltage of the first node and the voltage of the second electrode of the driving transistor; In the light emitting stage, the driving transistor generates a driving current for driving the light emitting device to emit light according to the data voltage signal.

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