Display panel and display device

Abstract

A display panel, comprising a display region and a fanout region. The display panel comprises multiple conductive layers; first data lines among multiple data lines are located in an edge region of the display region, and multiple second data lines are located in a central region of the display region; connection lines are electrically connected to the first data lines, and extend from the edge region to a junction between the central region and the fanout region; the connection lines cross over the data lines, and each of the connection lines has a second end located between two adjacent second data lines; fanout lines are connected to the connection lines or the second data lines; first-type fanout lines among multiple fanout lines comprise overlapping portions; the orthographic projections of two overlapping portions intersect each other, so that the arrangement order of the ends of two first-type fanout lines close to the display region is different from the arrangement order of the ends of the two first-type fanout lines away from the display region; at least one third conductive layer is located between a first conductive layer and a second conductive layer; and the intersecting overlapping portions of two first-type fanout lines are respectively located in the first conductive layer and the second conductive layer.

Description

Display panel and display device

[0001] This application claims priority to Chinese patent application No. 202410324205.9, filed on March 20, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0003] Organic light-emitting diode (OLED) display technology uses luminescent materials driven by an electric current to create a display. OLED displays offer advantages such as ultra-lightness, ultra-thinness, high brightness, wide viewing angles, low voltage, low power consumption, fast response, high definition, shock resistance, flexibility, low cost, simple manufacturing, minimal use of raw materials, high luminous efficiency, and a wide temperature range. Summary of the Invention

[0004] In one aspect, a display panel is provided, comprising a display area and a fan-out area, the fan-out area being located on one side of the display area. The display panel comprises a substrate and a multi-layer conductive layer stacked on one side of the substrate. The multi-layer conductive layer comprises a plurality of data lines, a plurality of connecting lines, and a plurality of fan-out lines. The plurality of data lines are spaced apart along a first direction and extend along a second direction that intersects the first direction. The plurality of data lines include a plurality of first data lines and a plurality of second data lines. The plurality of first data lines are located in at least one edge region of the display area, and the plurality of second data lines are located in a central region adjacent to the edge region. A first end of a connecting line is located in the edge region and electrically connected to a first data line, and a second end of the connecting line extends to the boundary between the central region and the fan-out area. At least one connecting line crosses over at least one data line and is insulated from the data line it crosses over. The plurality of fan-out lines are located in the fan-out area. A fan-out line is connected to either a connecting line or a second data line. The multiple fan-out lines include: multiple first-class fan-out lines. The first-class fan-out lines include overlapping portions. In the thickness direction of the substrate, the overlapping portions of at least two first-class fan-out lines intersect with each other in their orthographic projections on the substrate, so that the arrangement order of the at least two first-class fan-out lines along the first direction at one end close to the display area is different from the arrangement order of the at least two first-class fan-out lines along the first direction at one end away from the display area. Wherein, the multi-layer conductive layer includes at least: a first conductive layer, a second conductive layer and at least one third conductive layer. The at least one third conductive layer is located between the first conductive layer and the second conductive layer. The overlapping portions of the two intersecting first-class fan-out lines are located in the first conductive layer and the second conductive layer, respectively.

[0005] In some embodiments, the extension directions of the two overlapping portions of the two first-type fan-out lines intersect.

[0006] In some embodiments, the first-type fan-out line further includes: at least one transition portion. In the same first-type fan-out line, the overlapping portion is located in the first conductive layer, and the transition portion extends from any one of the conductive layers along the thickness direction of the substrate to the first conductive layer and connects to the overlapping portion.

[0007] In some embodiments, an extension direction of a portion of the conversion portion located in the first conductive layer is different from an extension direction of the overlapping portion.

[0008] In some embodiments, the first-type fan-out line further includes: at least one connecting portion. In the same first-type fan-out line, the connecting portion is connected to the overlapping portion and is disposed in the same layer.

[0009] In some embodiments, an extending direction of the connecting portion is the same as or substantially the same as an extending direction of the overlapping portion.

[0010] In some embodiments, an extending direction of the connecting portion is different from an extending direction of the overlapping portion.

[0011] In some embodiments, the display panel further comprises a bending region and a chip mounting region, which are sequentially spaced apart from the display region. The fan-out region comprises a first fan-out region and a second fan-out region, wherein the first fan-out region is located between the display region and the bending region, and the second fan-out region is located between the bending region and the chip mounting region. The overlapping portion is located in the second fan-out region.

[0012] In some embodiments, the width of the overlapping portion is greater than or equal to 1.0 μm.

[0013] In some embodiments, the display panel further includes: at least one shielding pattern. The shielding pattern receives a constant voltage signal. The shielding pattern is located in the fan-out region and in the third conductive layer. An overlapping region of orthographic projections of the two overlapping portions on the substrate is within the orthographic projection range of the shielding pattern on the substrate.

[0014] In some embodiments, at least two shielding patterns among the plurality of shielding patterns are located on the same third conductive layer and are connected to each other.

[0015] In some embodiments, the multi-layer conductive layer includes: at least two source-drain conductive layers stacked in sequence, and the plurality of shielding patterns are located in any one or any two of the at least two source-drain conductive layers.

[0016] In some embodiments, the multi-layer conductive layer further comprises: a light shielding layer and at least two gate conductive layers stacked sequentially on a side of the at least two source and drain conductive layers close to the substrate, wherein the first conductive layer is any one of the light shielding layer and the at least two gate conductive layers.

[0017] In some embodiments, the multi-layer conductive layer further comprises: at least two touch electrode layers stacked sequentially on a side of the at least two source / drain conductive layers away from the substrate, wherein the second conductive layer is any one of the at least two source / drain conductive layers and the at least two touch electrode layers.

[0018] On the other hand, a display device is provided, comprising: a display panel as described in any of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below should be considered schematic diagrams and are not intended to limit the actual dimensions, etc., of the products involved in the embodiments of the present disclosure.

[0020] FIG1 is a structural diagram of a display device according to some embodiments of the present disclosure;

[0021] FIG2 is a structural diagram of a display panel according to some embodiments of the present disclosure;

[0022] FIG3 is a structural diagram of a display substrate according to some embodiments of the present disclosure;

[0023] FIG4 is a structural diagram of a connection structure between a light-emitting device and a pixel driving circuit in a sub-pixel according to some embodiments of the present disclosure;

[0024] FIG5 is a structural diagram of another display substrate according to some embodiments of the present disclosure;

[0025] FIG6 is a structural diagram of another display panel according to some embodiments of the present disclosure;

[0026] FIG7 is a structural diagram of another display panel according to some embodiments of the present disclosure;

[0027] FIG8 is a partial structural diagram of a display panel according to some embodiments of the present disclosure;

[0028] FIG9 is a structural diagram of another display panel in a display substrate according to some embodiments of the present disclosure;

[0029] FIG10 is another partial structural diagram of a display panel according to some embodiments of the present disclosure;

[0030] FIG11 is another partial structural diagram of a display panel according to some embodiments of the present disclosure;

[0031] FIG12 is another partial structural diagram of a display panel according to some embodiments of the present disclosure;

[0032] FIG13 is another partial structural diagram of a display panel according to some embodiments of the present disclosure;

[0033] FIG14 is another partial structural diagram of a display panel according to some embodiments of the present disclosure;

[0034] FIG15 is another partial structural diagram of a display panel according to some embodiments of the present disclosure;

[0035] FIG16 is a cross-sectional structural diagram taken along the DD' direction in FIG15;

[0036] FIG17 is another partial structural diagram of a display panel according to some embodiments of the present disclosure;

[0037] FIG18 is another partial structural diagram of a display panel according to some embodiments of the present disclosure;

[0038] FIG19 is another partial structural diagram of a display panel according to some embodiments of the present disclosure;

[0039] FIG20 is another partial structural diagram of a display panel according to some embodiments of the present disclosure;

[0040] FIG21 is another partial structural diagram of a display panel according to some embodiments of the present disclosure;

[0041] FIG. 22 is another partial structural diagram of a display panel according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0042] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0043] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0044] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0045] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0046] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0047] As used herein, "perpendicular" and "equal" include the conditions described and conditions similar to the conditions described, where the range of the similar conditions is within an acceptable deviation range, where the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "perpendicular" includes absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range for approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, where the acceptable deviation range for approximate equality can be, for example, that the difference between the two equalities is less than or equal to 5% of either.

[0048] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0049] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0050] As shown in FIG1 , some embodiments of the present disclosure provide a display device 1000. The display device 1000 can be any display device 1000 that displays either motion (e.g., video) or fixed (e.g., still images) and text or images. More specifically, it is contemplated that the display device 1000 of the embodiments described can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., speedometer displays), navigation systems, cockpit controls and / or displays, camera view displays (e.g., displays for rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays for images of a piece of jewelry), etc.

[0051] The display device 1000 includes a display panel 200. In some examples, the display panel 200 is an organic light-emitting diode display (OLED) or a quantum dot light-emitting diode (QLED).

[0052] Based on this, the display device 1000 may further include an under-screen camera, an under-screen fingerprint recognition sensor, etc., so that the display device can realize a variety of different functions such as taking pictures, recording videos, and fingerprint recognition.

[0053] As shown in FIG2 , the display panel 200 includes a display substrate 100. For example, as shown in FIG2 , the display panel 200 may further include other functional film layers 211 located on the display side of the display substrate 100, such as a touch function layer, an anti-reflection layer, an anti-fingerprint layer, a hardening layer, and an encapsulation cover plate, so that the display panel 200 can achieve different functions.

[0054] The embodiment of the present disclosure does not further limit other functional film layers 211 of the display panel 200. The display substrate 100 is described below with an example.

[0055] 3 , the display substrate 100 includes a plurality of sub-pixels 101. The sub-pixels 101 are arranged in a plurality of columns along a first direction X and in a plurality of rows along a second direction Y.

[0056] In some examples, the first direction X and the second direction Y intersect.

[0057] Exemplarily, the first direction X is perpendicular to the second direction Y. For example, the first direction X is a horizontal direction, and the second direction Y is a vertical direction.

[0058] It can be understood that the sub-pixel 101 is the smallest unit for displaying a picture on the display substrate 100. Each sub-pixel 101 can display a single color, such as red, green, or blue. The display substrate 100 may include multiple red sub-pixels, multiple green sub-pixels, and multiple blue sub-pixels. By adjusting the brightness (grayscale) of the sub-pixels 101 of different colors, red light, green light, and blue light of different intensities can be obtained, and at least two of the red light, green light, and blue light of different intensities are superimposed to display more colors of light, thereby realizing full-color display of the display substrate 100.

[0059] As can be understood, as shown in FIG3 , the display substrate 100 has a display area AA and a fan-out area (full name: Fanout) BB, which is located on one side of the display area AA. The fan-out area BB is adjacent to at least one side edge of the display area AA. The display area AA is used to display image information, and a plurality of sub-pixels 101 are located in the display area AA of the display substrate 100.

[0060] It should be noted that the fan-out area BB is adjacent to at least one side edge of the display area AA. That is, the edge of the fan-out area BB close to at least one side edge of the display area AA overlaps with the edge of the display area AA close to at least one side edge of the fan-out area BB. In the drawings of the present disclosure, taking FIG. 3 as an example, the edge of the fan-out area BB is separated from the edge of the display area AA. This is merely for the convenience of illustrating the display area AA and the fan-out area BB, and does not further define the display area AA and the fan-out area BB.

[0061] In some examples, as shown in FIG. 3 , the fan-out area BB is located on one side of the display area AA along the second direction Y.

[0062] In some examples, as shown in FIG3 , the fan-out area BB is adjacent to the lower edge of the display area AA. That is, the fan-out area BB is located below the display area AA along the second direction Y.

[0063] For example, when the display panel 200 is used in a state perpendicular to or approximately perpendicular to the ground, the fan-out area BB is closer to the ground than the display area AA.

[0064] In some examples, each sub-pixel 101 includes a light-emitting device 300 and a pixel driving circuit, and the pixel driving circuit is electrically connected to the light-emitting device 300 to drive the light-emitting device 300 to emit light.

[0065] In some examples, as shown in Figure 4, the display panel 200 or display substrate 100 includes a substrate 102 and a plurality of conductive layers 103. The plurality of conductive layers 103 are located on the same side of the substrate 102. The plurality of conductive layers 103 are stacked.

[0066] In some examples, the substrate 102 is a flexible material, so that the display substrate 100 can be bent, thereby enabling the display panel 200 to achieve functions such as curved display, foldable display, or scrolling display. In other examples, the substrate 102 is a rigid material.

[0067] For example, the material of the substrate 102 may be any one of polyimide (PI), polycarbonate (PC), or polyvinyl chloride (PVC).

[0068] In some examples, an insulating layer IL (eg, a gate insulating layer and a buffer layer, an interlayer dielectric layer, a passivation layer, an organic layer, etc.) may be provided between the multiple conductive layers 103 . The insulating layer IL is used to electrically isolate two adjacent conductive layers 103 .

[0069] In some other examples, the insulating layer IL between the multiple conductive layers 103 does not include a passivation layer. Thus, the thickness of the display panel 200 can be reduced, which is conducive to achieving a lightweight and thin design of the display panel 200.

[0070] In some examples, the pixel driving circuit is provided in the multi-layer conductive layer 103. In some examples, as shown in FIG4 , the multi-layer conductive layer 103 includes a light shielding layer (not shown in the figure) that is sequentially away from the substrate 102, an active film layer 1034, at least one gate conductive layer Gate (such as a first gate conductive layer Gate1, a second gate conductive layer Gate2, and a third gate conductive layer (not shown in the figure, which may be located between the second gate conductive layer Gate2 and the first source-drain conductive layer SD1)), at least one source-drain conductive layer SD (such as a first source-drain conductive layer SD1, a second source-drain conductive layer SD2, and a third source-drain conductive layer (not shown in the figure, which may be located between the second source-drain conductive layer SD2 and the anode layer AND)), etc.

[0071] It is understood that when the display panel 200 includes a touch functional layer, the multi-layer conductive layer 103 in the display panel 200 further includes at least one touch electrode layer disposed on a side of the at least one source / drain conductive layer SD away from the substrate 102. Here, the at least one touch electrode layer constitutes the touch functional layer.

[0072] Exemplarily, as shown in FIG4 , the multilayer conductive layer 103 includes a first touch electrode layer TMA and a second touch electrode layer TMB disposed on a side of at least one source / drain conductive layer SD away from the substrate 102. If the display panel includes a light-emitting device, the first touch electrode layer TMA and the second touch electrode layer TMB are located on a surface of the light-emitting device away from the substrate 102. For example, the first touch electrode layer TMA includes a plurality of first touch electrodes, and the second touch electrode layer TMB includes a plurality of second touch electrodes.

[0073] The pixel driving circuit includes multiple thin film transistors (TFTs) and at least one capacitor. For example, the active film layer 1034 and the first gate conductive layer Gate1 can be used to form a portion of the multiple thin film transistors (one, two, or more), and the active film layer 1034 and the second gate conductive layer Gate2 can be used to form another portion of the multiple thin film transistors (one, two, or more). The first gate conductive layer Gate1 and the second gate conductive layer Gate2 can be used to form at least one capacitor.

[0074] It should be noted that the number of active film layers 1034 is not limited herein. For example, some embodiments of the present disclosure may include only one active film layer 1034, and the material of the active film layer may include metal oxide or low-temperature polysilicon. Alternatively, some embodiments of the present disclosure may include two active film layers 1034, wherein one active film layer 1034 includes a metal oxide and the other active film layer includes low-temperature polysilicon.

[0075] As can be seen from the above embodiments, the display substrate 100 further includes a light emitting device 300, and the pixel driving circuit is electrically connected to the light emitting device 300. The light emitting device 300 will be described below with reference to FIG4 .

[0076] In some examples, the light emitting device 300 is located on a side of the multilayer conductive layer 103 away from the substrate 102. It is understood that when the multilayer conductive layer 103 includes the at least one touch electrode layer, the light emitting device 300 is located between the at least one source-drain conductive layer SD and the at least one touch electrode layer.

[0077] Illustratively, the light emitting device 300 includes an anode layer AND, a light emitting layer EML, and a cathode layer CTD, which are sequentially arranged in a direction away from the substrate 102 .

[0078] In some examples, the light-emitting layer EML includes a plurality of effective light-emitting portions spaced apart, and it is understood that the effective light-emitting portion is used to emit light. For example, the effective light-emitting portion includes an electroluminescent material. It is understood that electroluminescence refers to the phenomenon that an organic semiconductor material, under the drive of an electric field (such as the electric field provided by the anode and cathode layers), injects and transports carriers, and combines electrons and holes to form excitons, and then radiates and recombine to cause light emission.

[0079] It is understood that a portion of the multiple effective light-emitting portions is used to emit red light, another portion is used to emit green light, and another portion is used to emit blue light. For example, different electroluminescent materials can be selected so that the effective light-emitting portions can emit light of different colors. It is understood that the number of effective light-emitting portions that emit red light, effective light-emitting portions that emit green light, and effective light-emitting portions that emit blue light can be the same or different.

[0080] For example, effective light-emitting portions emitting red light, effective light-emitting portions emitting green light, and effective light-emitting portions emitting blue light can be arranged in a mixed array. In this way, by controlling the luminous intensity of different effective light-emitting portions, red light, green light, and blue light of different intensities can be obtained. By mixing red light, green light, and blue light of different intensities, the display substrate 100 and the display panel 200 can display a color image.

[0081] It is understood that the pixel driving circuit can drive the light-emitting layer EML to emit light. In some examples, a pixel driving circuit is electrically connected to an effective light-emitting portion through the anode layer AND, so that each pixel driving circuit can provide a driving current to each effective light-emitting portion through the anode layer AND. In other words, multiple effective light-emitting portions are independently illuminated, reducing mutual interference between the multiple effective light-emitting portions and improving the display effect of the display substrate 100 and the display panel 200. It is understood that by adjusting the magnitude of the driving current provided by the pixel driving circuit to the effective light-emitting portion, the brightness of the light-emitting portion can be adjusted.

[0082] In some examples, the material of the anode layer AND includes a metal material, such as copper or silver. The material of the cathode layer CTD includes a light-transmitting material, such as light-transmitting indium tin oxide (ITO) or light-transmitting indium zinc oxide (IZO), so that light emitted by the effective light-emitting portion can be emitted through the cathode layer CTD. In this case, the display substrate 100 is a top-emitting display substrate.

[0083] In other examples, the material of the anode layer AND includes a transparent material, such as ITO or IZO, and the material of the cathode layer CTD includes a metal material, such as copper or silver, so that the light emitted by the effective light-emitting part can be emitted through the anode layer AND, that is, the display substrate 100 is a bottom-emitting display substrate.

[0084] In some other examples, the materials of the anode layer AND and the cathode layer CTD both include transparent materials, such as ITO or IZO, so that the light emitted by the effective light-emitting part can be emitted through the anode layer AND and the cathode layer CTD, that is, the display substrate 100 is a double-sided light-emitting display substrate.

[0085] In some examples, based on work function considerations, the anode layer AND is made of ITO or an ITO-Ag-ITO stack, enabling the anode layer AND to provide more holes. The cathode layer CTD is made of MgAg, enabling the CTD to provide more electrons. The CTD is thin and light-transmissive, enabling the display substrate 100 to achieve top emission.

[0086] In some examples, along the direction from the anode layer AND to the effective light-emitting portion, at least one of a hole injection layer (full name in English: Hole Inject Layer, English abbreviation: HIL), a hole transport layer (full name in English: Hole Transport Layer, English abbreviation: HTL), and an electron blocking layer (full name in English: Electron Blocking Layer, English abbreviation: EBL) is provided between the anode layer AND and the effective light-emitting portion. Along the direction from the cathode layer CTD to the effective light-emitting portion, at least one of an electron injection layer (full name in English: Electron Inject Layer, English abbreviation: EIL), an electron transport layer (full name in English: Electron Transport Layer, English abbreviation: ETL), and a hole blocking layer (full name in English: Hole Blocking Layer, English abbreviation: HBL) is provided between the cathode layer CTD and the effective light-emitting portion. The above-mentioned arrangement improves the luminous efficiency of the effective light-emitting portion.

[0087] FIG. 5 is a structural diagram of a display substrate according to some other embodiments.

[0088] In some examples, as shown in FIG5 , the display substrate 100 further includes an encapsulation layer 104. The encapsulation layer 104 is located on a side of the light-emitting device 300 away from the substrate 102 and can cover and encapsulate the light-emitting device 300 to prevent moisture and oxygen in the external environment from entering the light-emitting device 300, thereby protecting the light-emitting device 300.

[0089] Figure 6 illustrates the structure of a display panel according to yet other embodiments. As shown in Figure 6 , the multilayer conductive layer 103 includes, in addition to the pixel driver circuits, a plurality of data lines 110 and a plurality of fan-out lines 130. As will be appreciated, the plurality of data lines 110 are located in the display area AA and are electrically connected to the plurality of pixel driver circuits, transmitting drive signals to the pixel driver circuits so that the pixel driver circuits can drive the light-emitting devices 300 to emit light, thereby achieving display of different grayscales.

[0090] In some examples, as shown in FIG. 6 , multiple data lines 110 are spaced apart along a first direction X and extend along a second direction Y, the second direction Y intersecting the first direction X, and the first direction X and the second direction Y may be parallel to the substrate 102 .

[0091] In some examples, the first direction X is perpendicular or approximately perpendicular to the second direction Y. For example, as shown in FIG6 , the first direction X is a horizontal direction, and the second direction Y is a vertical direction.

[0092] As can be seen from the above, as shown in FIG3 , the plurality of sub-pixels 101 are arranged in a plurality of columns along the first direction X and in a plurality of rows along the second direction Y. That is, the pixel driving circuits in the plurality of sub-pixels 101 can be arranged in a multi-row and multi-column array along the first direction X and the second direction Y. As shown in FIG6 , the plurality of data lines 110 extend along the second direction Y. In this way, a data line 110 can be electrically connected to the pixel driving circuits in a column of sub-pixels 101 arranged along the second direction Y, thereby providing data voltages to the pixel driving circuits in the column of sub-pixels 101.

[0093] 7 , the plurality of data lines 110 include a plurality of first data lines 111 and a plurality of second data lines 112. The plurality of first data lines 111 are located in at least one edge region AA1 of the display area AA, and the plurality of second data lines 112 are located in a central region AA2 adjacent to the edge region AA1.

[0094] For example, as shown in FIG. 7 , there are two edge areas AA1 , which are located on both sides of the display panel 200 along the first direction X, and the center area AA2 is located between the two edge areas AA1 along the first direction X.

[0095] For example, the central area AA2 may be an area of ​​the display area AA that is directly or substantially directly opposite the fan-out area BB along the second direction Y. The edge area AA1 may be an area of ​​the display area AA that is not directly opposite the fan-out area BB along the second direction Y.

[0096] For example, along the first direction X, the widths of the two edge regions AA1 of the display area AA are the same or approximately the same. In some examples, as shown in FIG7 , the display area AA includes rounded corners, that is, two adjacent edges of the display area AA are connected in an arc shape or a substantially arc shape. The rounded corners are located within the edge region AA1 of the display area AA.

[0097] For example, the width of the edge area AA1 in the first direction X may be greater than or equal to the width of the rounded corner in the first direction X.

[0098] For example, the number of the first data lines 111 and the number of the second data lines 112 may be the same or different. Furthermore, the number of the first data lines 111 located in the two edge areas AA1 may be the same or different.

[0099] It should be noted that in various embodiments of the present disclosure, the first data line 111 and the second data line 112 are only used to distinguish the data line 110 located in the edge area AA1 and the center area AA2, and other aspects of the data line 110 are not further limited.

[0100] For example, the plurality of first data lines 111 and the plurality of second data lines 112 are located in the same conductive layer 103. For example, the plurality of first data lines 111 and the plurality of second data lines 112 are located on the first source-drain metal layer SD1. For another example, the plurality of first data lines 111 and the plurality of second data lines 112 are located on the second source-drain metal layer SD2. For another example, the plurality of first data lines 111 and the plurality of second data lines 112 may also be located on another conductive layer 103 (e.g., a third source-drain metal layer) in addition to the first source-drain metal layer SD1 and the second source-drain metal layer SD2.

[0101] As shown in FIG7 , the multi-layer conductive layer 103 further includes a plurality of connecting lines 120. A first end of a connecting line 120 (i.e., the end indicated by the arrow in FIG7 ) is located in the edge region AA1 of the display area AA and is electrically connected to a first data line 111. A second end of the connecting line 120 (i.e., the end opposite the end indicated by the arrow in FIG7 ) extends to the boundary between the central region AA2 of the display area AA and the fan-out region BB.

[0102] For example, as shown in FIG. 7 , the second end of any one of the plurality of connection lines 120 extends to the central area AA2 of the display area AA.

[0103] As can be seen from the above, the edge of the display area AA near the fan-out area BB can overlap with the edge of the fan-out area BB near the display area AA. The second end of the connecting line 120 extends to the junction of the central area AA2 and the fan-out area BB. It can be understood that the second end of the connecting line 120 can be located on the dividing line between the central area AA2 and the fan-out area BB; alternatively, there can be a small gap between the dividing line and the fan-out area BB, such as a gap of several microns. In this case, the second end of the connecting line 120 can be located on the side of the dividing line near the display area AA, or on the side of the dividing line near the fan-out area BB.

[0104] As shown in FIG. 7 , at least one connection line 120 crosses over at least one data line 110 (eg, the first data line 111 and / or the second data line 112 ) and is insulated from the data line 110 it crosses over.

[0105] It is understandable that, because the plurality of data lines 110 are arranged at intervals along the first direction X, the second ends of some connection lines 120 need to cross at least one data line 110 when extending to the boundary between the central area AA2 and the fan-out area BB. For example, at least one connection line 120 may cross both the first data line 111 and the second data line 112. In another example, at least one connection line 120 may only cross the first data line 111 (not shown). In another example, at least one connection line 120 may only cross the second data line 112 (not shown).

[0106] In addition, the display panel 200 may further include a connection line 120 that does not cross any data line 110 .

[0107] It can be understood that the connection line 120 crosses over at least one data line 110 , that is, the orthographic projection of the connection line 120 on the substrate 102 intersects with the orthographic projection of the at least one data line 110 on the substrate 102 .

[0108] In some examples, the connection line 120 and the data line 110 are located in different conductive layers 103 , so that the connection line 120 can be insulated from the data line 110 it crosses.

[0109] For example, the data line 110 is located in the first source-drain metal layer SD1, and the connection line 120 is located in the second source-drain metal layer SD2. Alternatively, the data line 110 is located in the second source-drain metal layer SD2, and the connection line 120 is located in the third source-drain metal layer.

[0110] For example, when the connecting line 120 and the data line 110 are located in different conductive layers 103, the first end of the connecting line 120 can be connected to the first data line 111 through a via. It is understood that the via penetrates the insulating layer between two adjacent conductive layers 103 in a direction perpendicular or approximately perpendicular to the substrate 102, thereby enabling electrical connection between the different conductive layers 103 and the conductive traces (e.g., the connecting line 120 and the data line 110) located on different conductive layers 103. For example, when the two conductive layers 103 are not adjacent, multiple vias can be used to electrically connect the conductive traces located on different conductive layers 103, thereby insulating the connecting line 120 from the data line 110 it crosses.

[0111] In other examples, the connecting line 120 includes a main body portion and a jumper portion. The main body portion and the jumper portion can be electrically connected through a via. The main body portion can be located in the same conductive layer 103 as the data line 110, that is, the main body portion and the data line 110 are arranged in the same layer, for example, the main body portion and the data line 110 are located in the first source-drain conductive layer in the multi-layer conductive layer 103, and the jumper portion can be located in two different conductive layers 103 than the data line 110, and the jumper portion and the data line 110 are arranged in different layers, for example, the data line 110 is located in the first source-drain conductive layer, and the jumper portion is located in the second source-drain conductive layer in the multi-layer conductive layer 103, and an insulating layer is provided between the first source-drain conductive layer and the second source-drain conductive layer, so that the jumper portion can cross at least one data line 110 and be insulated from the data line 110 it crosses.

[0112] 7 , the second end of at least one connecting line 120 is located between two adjacent second data lines 110. Thus, the second end of one connecting line 120 can be disposed between two adjacent second data lines 112, or the second ends of two or more connecting lines 120 can be disposed between two adjacent second data lines 112.

[0113] It is understandable that, as shown in FIG7 , between any two adjacent second data lines 112, one second end of the connecting line 120 may be provided, two or more second ends of the connecting lines 120 may be provided, or no second end of the connecting line 120 may be provided. The number of second ends of the connecting lines 120 provided between different adjacent second data lines 112 may be the same or different.

[0114] As shown in FIG. 7 , the second end of the connection line 120 is disposed between two adjacent second data lines 112 , so that the second end of the connection line 120 can pass through the gap between the two adjacent second data lines 112 and extend to the boundary between the central area AA2 and the fan-out area BB.

[0115] It is understood that the number of connection lines 120 and the number of first data lines 111 may be the same or different. In some examples, the number of connection lines 120 is the same as the number of first data lines 111. Multiple connection lines 120 are connected to multiple first data lines 111 in a one-to-one correspondence. In other examples, the number of connection lines 120 is less than the number of first data lines 111. In this case, all connection lines 120 may be connected to a portion of the first data lines 111 in a one-to-one correspondence, while another portion of the first data lines 111 may not be connected to the connection lines 120.

[0116] In some examples, as shown in FIG7 , the connection line 120 includes a first sub-connection line 121 and a second sub-connection line 122. One end of the first sub-connection line 121 is located in the edge area AA1 and is electrically connected to the first data line 111. The other end of the first sub-connection line 121 extends to the center area AA2. One end of the second sub-connection line 122 is electrically connected to the first sub-connection line 121 (for example, one end of the second sub-connection line 122 is connected to one end of the first sub-connection line 121, or one end of the second sub-connection line 122 is connected to the middle portion of the first sub-connection line 121), and the other end of the second sub-connection line 122 extends to the junction between the center area AA2 and the fan-out area BB. For example, the first sub-connection line 121 extends along the first direction X, and the second sub-connection line 122 extends along the second direction Y, and the first sub-connection line 121 and the second sub-connection line 122 are perpendicular or approximately perpendicular.

[0117] In the case where the connection line 120 includes a main portion and a jumper portion, as shown in FIG7 , in some examples, of the first sub-connection line 121 and the second sub-connection line 122 included in the connection line 120, the second sub-connection line 122 can be configured as the main portion, the main portion and the plurality of data lines 110 being located in the same conductive layer 103, while the first sub-connection line 121 can be configured as the jumper portion, the jumper portion and the plurality of data lines 110 being located in two different conductive layers 103. The first sub-connection line 121 can cross over at least one data line 110 and is insulated from the data line 110 it crosses. Furthermore, in other examples, the second sub-connection line 122 can be configured as the main portion, while the first sub-connection line 121 includes both the main portion and the jumper portion, wherein the jumper portion is configured to cross over the data lines 110.

[0118] In some examples, the jumper portion is farther away from the substrate 102 relative to the multiple data lines 110, which can reduce the parasitic capacitance generated between the jumper portion and the gate conductive layer Gate (for example, the first gate conductive layer Gate1, the second gate conductive layer Gate2 and the third gate conductive layer, etc.), thereby improving the signal transmission reliability.

[0119] For example, the data line fan-out method of adding the connection line 120 can be called display area fan-out (Fanout In AA, abbreviated as: FIAA display area fan-out) or panel fan-out (Fanout In Panel, abbreviated as: FIP).

[0120] In some examples, as shown in FIG. 7 , when the number of connection lines 120 is set to be the same as the number of first data lines 110 , the first data lines 111 are connected to the connection lines 120 in a one-to-one correspondence, and this setting method may be referred to as full FIAA.

[0121] In other examples, a portion of the first data lines 111 may be connected to the connection lines 120 in a one-to-one correspondence, while another portion of the first data lines 111 may not be connected to the connection lines 120. For example, like the second data lines 112, the first data lines 111 may be directly led out through fan-out lines (such as the second type of fan-out lines 132 described below). This configuration helps reduce the spacing between the multiple data lines 110, improve the pixel density of the display area AA, and enable the display panel 200 to achieve a high PPI (Pixels Per Inch). This configuration method may be referred to as partial FIAA.

[0122] As shown in FIG7 , the multi-layer conductive layer 103 further includes a plurality of fan-out lines 130 . The plurality of fan-out lines 130 are located in the fan-out area BB. One fan-out line 130 is connected to one connection line 120 or one second data line 112 .

[0123] For example, one end of a fan-out line 130 is connected to a corresponding first data line 111 via a connection line 120, or one end of a fan-out line 130 is connected to a second data line 112. Thus, multiple fan-out lines 130 are connected to multiple data lines 110 in a one-to-one correspondence. The other ends of the multiple fan-out lines 130 are electrically connected to a driver chip (IC). The driver IC inputs data signals to each pixel driver circuit through the multiple fan-out lines 130 and the multiple data lines 110.

[0124] As shown in FIG8 , the plurality of fan-out lines 130 includes a plurality of first-type fan-out lines 131. As shown in FIG9 and FIG10 , the first-type fan-out lines 131 include overlapping portions 1311. In the thickness direction of the substrate 102, the orthographic projections of the overlapping portions 1311 of at least two first-type fan-out lines 131 intersect on the substrate 102, such that the arrangement order of the at least two first-type fan-out lines 131 at their ends near the display area AA along the first direction X is different from the arrangement order of the at least two first-type fan-out lines 131 at their ends away from the display area AA along the first direction X.

[0125] It can be understood that the orthographic projection of the remaining part of a first-class fan-out line 131 except the overlapping part 1311 on the substrate 102 has no overlapping area with the orthographic projections of other fan-out lines 130 (the other fan-out lines 130 here can be other first-class fan-out lines 131 other than the above-mentioned first-class fan-out lines 131, and the second-class fan-out lines 132 mentioned below) on the substrate 102.

[0126] For example, as shown in Figure 10, the shape of the positive projection of the overlapping portion 1311 of the two first-class fan-out lines 131 on the substrate 102 can be or is approximately a "cross" shape. Thus, along the first direction X, the arrangement order of the two first-class fan-out lines 131 on one side of the overlapping portion 1311 and the arrangement order of the two first-class fan-out lines 131 on the other side of the overlapping portion 1311 are exchanged, that is, the order is changed. Therefore, the overlapping portion 1311 of the first-type fan-out line 131 can be used to achieve the reordering of the multiple first-type fan-out lines 131, so that the arrangement order of the ends of the multiple fan-out lines 130 away from the display area AA along the first direction X is the same as the arrangement order of the multiple data lines 110 connected to them along the first direction X. As a result, the arrangement order of the output end of the driver IC along the first direction X, the arrangement order of the ends of the multiple fan-out lines 130 away from the display area AA along the first direction X, and the arrangement order of the multiple data lines 110 along the first direction X can be the same. The output end of the driver IC can provide driving signals to the multiple data lines 110 in sequence, so that the driver IC can drive the multiple columns of sub-pixels 101 to emit light in sequence, without the need to redevelop the driver IC, thereby reducing the cost of the display substrate 100.

[0127] In one implementation, the overlapping portions 1311 of the two first-class fan-out lines 131 are respectively located in the first source-drain conductive layer SD1 and the second source-drain conductive layer SD2. The first source-drain conductive layer SD1 and the second source-drain conductive layer SD2 are adjacent conductive layers, so that the two overlapping portions 1311 are relatively close to each other in the thickness direction of the substrate 102. Therefore, when the data signals received by the two first-class fan-out lines 131 are different, the data signals transmitted by the two first-class fan-out lines 131 are prone to crosstalk with each other, and the two overlapping portions 1311 are prone to form parasitic capacitors, which makes the load of the first-class fan-out line 131 larger, resulting in larger loss of the data signal received by the data line 110 connected thereto, and poor accuracy and stability of the data signal, thereby affecting the image display quality of the display panel 200 and the display device 1000.

[0128] Based on this, in the embodiment of the present disclosure, as shown in Figures 9 and 10, the multi-layer conductive layer 103 includes at least a first conductive layer 1031, a second conductive layer 1032, and at least one third conductive layer 1033. The at least one third conductive layer 1033 is located between the first conductive layer 1031 and the second conductive layer 1032.

[0129] The relative positions of the first conductive layer 1031 and the second conductive layer 1032 can be set according to actual needs, and the embodiments of the present disclosure are not limited thereto.

[0130] For example, compared with the first conductive layer 1031 , the second conductive layer 1032 is closer to the substrate 102 .

[0131] For another example, as shown in FIG. 9 , compared to the second conductive layer 1032 , the first conductive layer 1031 is closer to the substrate 102 .

[0132] For example, when the first conductive layer 1031 is closer to the substrate 102 than the second conductive layer 1032, for example, among the multiple layers of third conductive layers 1033, one third conductive layer 1033A is located between the first conductive layer 1031 and the second conductive layer 1032, another two third conductive layers 1033B and 1033C are located on the side of the first conductive layer 1031 close to the substrate 102, and another third conductive layer 1033D is located on the side of the second conductive layer 1032 away from the substrate 102. For another example, among the multiple layers of third conductive layers 1033, at least two third conductive layers 1033A and 1033B are located between the first conductive layer 1031 and the second conductive layer 1032, and the remaining third conductive layers 1033 are located on the side of the first conductive layer 1031 close to the substrate 102. For another example, among the multiple layers of third conductive layer 1033 , at least two layers of third conductive layer 1033A and third conductive layer 1033B are located between the first conductive layer 1031 and the second conductive layer 1032 , and the remaining layers of third conductive layer 1033 are located on the side of the second conductive layer 1032 away from the substrate 102 .

[0133] As shown in FIG. 10 , the overlapping portions 1311 of the two intersecting first-type fan-out lines 131 are located in the first conductive layer 1031 and the second conductive layer 1032 , respectively.

[0134] Based on the above description, at least one third conductive layer 1033 is located between the first conductive layer 1031 and the second conductive layer 1032. Therefore, the distance between the two intersecting overlapping portions 1311 in the thickness direction of the substrate 102 (i.e., the third direction Z in Figure 10) is relatively large, and crosstalk is not likely to occur between the data signals transmitted by the two overlapping portions 1311. To a certain extent, the capacitance value of the parasitic capacitor between the two overlapping portions 1311 can be reduced, thereby reducing the load of the first type fan-out line 131 including the overlapping portion 1311, improving the accuracy and stability of the signal line transmitted by the first type fan-out line 131, and improving the image display quality of the display panel 200 and the display device 1000.

[0135] Moreover, the above-mentioned setting method disclosed in the present invention only improves the existing conductive layer 103 of the display panel 200, and does not add a new conductive layer. Therefore, there is no need to add a new mask plate and preparation process, etc., without increasing the preparation cost of the display panel 200, and improving the image display quality of the display panel 200 and the display device 1000.

[0136] In addition, in the process of preparing and forming two overlapping parts, an etching process is generally used to etch the conductive layer to form a conductive trace (the conductive trace can constitute a fan-out line, etc.), and etch the insulating layer to form a via to achieve the connection of the conductive traces in the two conductive layers (for example, conductive patterns of different layers, etc.). Since the spacing between the two intersecting overlapping parts 1311 in the above example of the present disclosure is relatively large, the probability of short-circuiting the two overlapping parts 1311 due to over-etching of the insulating layer under the film layer where the overlapping part 1311 is located near the substrate 102 can be reduced or even avoided, and over-etching connection caused by the large spacing between the two overlapping parts 1311 can be avoided, which is beneficial to improving the preparation yield of the display panel 200.

[0137] It will be appreciated that the above example is based on the case where the orthographic projections of the overlapping portions 1311 of two first-type fan-out lines 131 on the substrate 102 intersect. When the orthographic projections of the overlapping portions 1311 of three first-type fan-out lines 131 on the substrate 102 intersect, the three overlapping portions 1311 are located in different conductive layers 103. Specifically, see FIG. 12 , where the three overlapping portions 1311 are located in the first gate conductive layer Gate1, the first source-drain conductive layer SD1, and the second touch electrode layer TMB, respectively.

[0138] In some examples, as shown in Figure 10, the overlapping portion 1311 has a certain length, for example, the overlapping portion 1311 may be in the shape of a long strip in a top view. The extending directions of the two overlapping portions 1311 of the two first-type fan-out lines 131 intersect.

[0139] For example, of the two overlapping portions 1311, one overlapping portion 1311 may extend in the first direction X, and the other overlapping portion 1311 may extend in the second direction Y. For another example, of the two overlapping portions 1311, one overlapping portion 1311 may extend in the first direction X, and the other overlapping portion 1311 may extend in the third direction, where the third direction intersects both the first direction X and the second direction Y. For another example, as shown in FIG10 , of the two overlapping portions 1311, one overlapping portion 1311 may extend in the fifth direction, and the other overlapping portion 1311 may extend in the fourth direction, where the fifth direction intersects both the first direction X and the second direction Y, and the fourth direction intersects all the first direction X, the second direction Y, and the third direction.

[0140] Thus, the overlapping portion 1311 can be used to reorder the multiple first-type fan-out lines 131 to which it belongs, so that the arrangement order of the multiple fan-out lines 130 at one end away from the display area AA along the first direction X is the same as the arrangement order of the multiple data lines 110 connected to them along the first direction X, thereby reducing the cost of the display panel 200.

[0141] It is understandable that there are various structures of the first type fan-out line 131 , which can be configured according to actual conditions, and the present disclosure does not impose any limitation thereto.

[0142] In some examples, as shown in FIG11 , the first-type fan-out line 131 further includes at least one transition portion 1312. Within the same first-type fan-out line 131, the overlapping portion 1311 is located in the first conductive layer 1031, and the transition portion 1312 extends from any conductive layer along the thickness direction of the substrate 102 to the first conductive layer 1031 and is connected to the overlapping portion 1311.

[0143] Exemplarily, the conversion portion 1312 extends to the first conductive layer 1031 through a via hole on the insulating layer between any conductive layer and the first conductive layer 1031 .

[0144] For example, a portion of the conversion portion 1312 is located in the second conductive layer 1032 , and another portion extends from the second conductive layer 1032 through at least one third conductive layer 1033 to the first conductive layer 1031 to achieve connection with the overlapping portion 1311 .

[0145] For another example, as shown in FIG. 11 , a portion of the conversion portion 1312 is located in the third conductive layer 1033 , and another portion extends from the third conductive layer 1033 to the first conductive layer 1031 to achieve connection with the overlapping portion 1311 .

[0146] Thus, the connection between the conversion portion 1312 and the overlapping portion 1311 in the first type fan-out line 131 can be ensured, so that the first type fan-out line 131 can be switched from any conductive layer 103 to the first conductive layer 1031 .

[0147] 11 , in the same first-type fan-out line 131, the extension direction of the portion of the conversion portion 1312 located in the first conductive layer 1031 is different from the extension direction of the overlapping portion 1311. Therefore, the top view of the first-type fan-out line 131 is a zigzag shape or a substantially zigzag shape.

[0148] For example, the extending direction of the portion of the conversion portion 1312 located in the first conductive layer 1031 is the second direction Y, and the extending direction of the overlapping portion 1311 is the fourth direction.

[0149] This facilitates the sequence change of the first-type fan-out lines 131 .

[0150] For example, in the same first-type fan-out line 131, the extension direction of the portion of the conversion portion 1312 located in the first conductive layer 1031 may be the same as the extension direction of the overlapping portion 1311. Thus, the top view of the first-type fan-out line 131 is linear or substantially linear.

[0151] In other examples, as shown in Figure 12, the first-type fan-out line 131 further includes at least one connecting portion 1313. In the same first-type fan-out line 131, the connecting portion 1313 is connected to the overlapping portion 1311 and is disposed in the same layer.

[0152] For example, the overlapping portion 1311 and the connecting portion 1313 connected thereto are both located in the first conductive layer 1031 or the second conductive layer 1032 .

[0153] Therefore, the overlapping portion 1311 and the connecting portion 1313 can be made of the same layer and the same material, and the connecting portion 1313 and the overlapping portion 1311 can be formed in one manufacturing process, which is beneficial to simplifying the manufacturing process of the first type fan-out line 131 and the display panel 200.

[0154] It is understandable that the extension direction of the connecting portion 1313 and the extension direction of the overlapping portion 1311 can be set as needed, and the embodiments of the present disclosure are not limited to this.

[0155] 12 , the extending direction of the connecting portion 1313 is the same or substantially the same as the extending direction of the overlapping portion 1311. Therefore, the top view shape of the first type fan-out line 131 is a straight line or a substantially straight line.

[0156] 11 , the extending direction of the connecting portion 1313 is different from the extending direction of the overlapping portion 1311. Therefore, the top view shape of the first type fan-out line 131 is a zigzag line or substantially a zigzag line.

[0157] In some examples, as shown in FIG. 12 , the width W of the overlapping portion 1311 is greater than or equal to 1.0 μm.

[0158] Here, the width W of the overlapping portion 1311 refers to a dimension of the overlapping portion 1311 perpendicular to the extending direction thereof.

[0159] For example, the width W of the overlapping portion 1311 is greater than or equal to 1.5 μm.

[0160] For example, the width W of the overlapping portion 1311 may be 1.0 μm, 1.5 μm, 1.7 μm, 2.0 μm, or 2.5 μm.

[0161] In this way, the width of the overlapping portion 1311 can be ensured to be large, thereby avoiding defects such as breakage and short circuit in the overlapping portion 1311 and preventing the transmission of signals from being affected.

[0162] In some embodiments, as shown in FIG. 7 , the fan-out line 130 further includes a second-type fan-out line 132 .

[0163] For example, the second-type fan-out line 132 is connected to the second data line 112 .

[0164] The orthographic projections of the second type fan-out lines 132 on the substrate do not overlap with those of the other fan-out lines 130. For example, the second type fan-out lines 132 do not need to be reordered and are directly connected to the driver IC.

[0165] For example, along the first direction X, multiple first-type fan-out lines 131 and multiple second-type fan-out lines 132 are alternately arranged. For example, three first-type fan-out lines 131 can be a first group, and one second-type fan-out line 132 can be a second group. Then, the first group and the second group are alternately arranged (that is, the insertion sequence is 3-in-1). Of course, the embodiments of the present disclosure are not limited to this. For example, 2-in-1, 4-in-1, 4-in-2, etc. can also be used. On this basis, the portions of adjacent fan-out lines 130 (such as adjacent first-class fan-out lines 131 and second-class fan-out lines 132, or adjacent first-class fan-out lines 131, or two adjacent second-class fan-out lines 132) close to the display area can be located in different gate metal layers Gate. For example, the portion of one of the fan-out lines 130 close to the display area (as can be seen from the above, the entire fan-out line can be located in the same conductive layer or in different conductive layers. The portion of the first-class fan-out line close to the display area can be the conversion portion 1312 or the connection portion 1313 of the first-class fan-out line close to the display area) is located in the first gate metal layer Gate1, and the portion of the other fan-out line close to the display area is located in the second gate metal layer Gate2. This arrangement is conducive to reducing signal crosstalk between adjacent fan-out lines.

[0166] In some examples, as shown in FIG7 , the display panel 200 further includes a bending region CC and a chip-on-panel (COP) region, which are located sequentially away from the display area AA. The COP region is used to mount a driver IC. The fan-out region BB includes a first fan-out region BB1 and a second fan-out region BB2. The first fan-out region BB1 is located between the display area AA and the bending region CC, and the second fan-out region BB2 is located between the bending region CC and the chip-on-panel (COP) region.

[0167] The fan-out lines 130 extend from the first fan-out region BB1 through the bending region CC to the second fan-out region BB2, with the overlapping portion 1311 located in the second fan-out region BB2. Consequently, the end of the fan-out lines 130 near the driver IC has been reordered. The arrangement order of the fan-out lines 130 near the driver IC is the same as the arrangement order of the data lines 110. The driver IC can output data signals to each data line 110 according to the arrangement order of the data lines 110 along the first direction X.

[0168] In some examples, as shown in FIG7 , the display panel 200 further includes a cell test (CT) area. The CT area is used to test the display panel 200. In this case, the second fan-out area BB2 can be located between the CT area and the COP area. It should be noted that the spacing between the CT area and the bending area CC can be zero (i.e., there can be no intermediate fan-out area BB0 shown in FIG7 ) or non-zero (i.e., there can be an intermediate fan-out area BB0 shown in FIG7 ).

[0169] In addition, when the middle fan-out area BB0 is included, the middle fan-out area BB0 may be a part of the second fan-out area BB2 (not shown), or may not be a part of the second fan-out area BB2 (as shown in FIG. 7 ).

[0170] In some examples, the display substrate 100 further includes an inner lead bonding (ILB) region (not shown) and a flexible printed circuit on panel (FOP) region (not shown). The ILB region and the FOP region are located sequentially on the side of the COP region away from the second fan-out region BB2. In some examples, some pins of the driver IC can be electrically connected to pins in the FOP region via traces in the ILB region. The pins in the FOP region can then be used to connect to an external flexible printed circuit board.

[0171] In some examples, as shown in FIG7 , the display substrate 100 may further include a plurality of scan control signal lines 105 , which are arranged at intervals along the second direction Y and extend along the first direction X. In this way, one scan control signal line 105 can be electrically connected to the pixel driving circuits in a row of sub-pixels 101 arranged along the first direction X to control the operating states of the pixel driving circuits in the row of sub-pixels 101 .

[0172] In some examples, as shown in FIG7 and FIG13 , the display panel 200 further includes: at least one shielding pattern 140 . The shielding pattern 140 is located in the fan-out region BB and in the third conductive layer 1033 .

[0173] The shielding pattern 140 and the overlapping portion 1311 are provided in different layers. For example, along the thickness direction of the substrate 102, the shielding pattern 140 may be located in the third conductive layer 1033 above the two intersecting overlapping portions 1311 (see Figures 13 and 14), or located in the third conductive layer 1033 below the two intersecting overlapping portions 1311, or located in the third conductive layer 1033 between the two intersecting overlapping portions 1311 (see Figure 15).

[0174] The shielding pattern 140 receives a constant voltage signal. For example, the shielding pattern 140 may receive a first voltage signal VDD transmitted by a first voltage signal line, or receive a common voltage signal VSS transmitted by a common voltage signal line.

[0175] As shown in FIG. 13 , the overlapping area of ​​the orthographic projections of the two overlapping portions 1311 on the substrate 102 is located within the orthographic projection range of the shielding pattern 140 on the substrate 102 .

[0176] Thus, the shielding pattern 140 can be used to protect at least one overlapping portion 1311, thereby reducing interference caused by signals transmitted by conductive structures (such as signal lines, capacitors, etc.) located on the side of the shielding pattern 140 away from the overlapping portion 1311 on the signals of the overlapping portion 1311, thereby improving the stability of the signals transmitted by the first-type fan-out line 131. For example, when the shielding pattern 140 is located on the third conductive layer 1033 between two overlapping portions 1311 (see Figures 15 and 16), the shielding pattern 140 can shield the signals transmitted by the two overlapping portions 1311, reducing crosstalk and interference between the signals transmitted by the two overlapping portions 1311, and improving the accuracy of the signals transmitted by the first-type fan-out line 131.

[0177] In some examples, as shown in FIG. 7 , a plurality of shielding patterns 140 are located on the same third conductive layer 1033 and are connected to each other.

[0178] For example, among the plurality of shielding patterns 140 , one shielding pattern 140 is disposed corresponding to two intersecting overlapping portions 1311 .

[0179] Therefore, the difficulty of manufacturing the shielding pattern 140 and the display panel 200 can be reduced, and the shielding effect of the shielding pattern 140 can be improved.

[0180] As can be seen from the above, the multi-layer conductive layer 103 includes: at least two source-drain conductive layers SD stacked in sequence. Exemplarily, the plurality of shielding patterns 140 are located in any one or any two of the at least two source-drain conductive layers.

[0181] Exemplarily, the multi-layer conductive layer 103 includes a first source-drain conductive layer SD1 and a second source-drain conductive layer SD2 . A plurality of shielding patterns 140 are located in the first source-drain conductive layer SD1 (see FIG. 15 and FIG. 17 ) or the second source-drain conductive layer SD2 (see FIG. 14 ).

[0182] Exemplarily, the multilayer conductive layer 103 includes: a first source-drain conductive layer SD1, a second source-drain conductive layer SD2, and a third source-drain conductive layer SD3. For example, the plurality of shielding patterns 140 may be located in the first source-drain conductive layer SD1, the second source-drain conductive layer SD2 (see Figures 19, 20, and 21), or the third source-drain conductive layer SD3 (see Figure 22). In another example, a certain number of the plurality of shielding patterns 140 may be located in the first source-drain conductive layer SD1, while the remaining number of shielding patterns 140 may be located in the second source-drain conductive layer SD2. In another example, a certain number of the plurality of shielding patterns 140 may be located in the second source-drain conductive layer SD2, while a certain number of shielding patterns 140 may be located in the third source-drain conductive layer SD3.

[0183] As can be seen above, the multilayer conductive layer 103 further includes: a light shielding layer and at least two gate conductive layers, stacked sequentially on the side of the at least two source and drain conductive layers close to the substrate 102. In some examples, the first conductive layer 1031 is any one of the light shielding layer and the at least two gate conductive layers.

[0184] Exemplarily, the multilayer conductive layer 103 includes a light shielding layer, a first gate conductive layer Gate1, and a second gate conductive layer Gate2. The light shielding layer and the first conductive layer 1031 are the first gate conductive layer Gate1 or the second gate conductive layer Gate2. Thus, the overlapping portion 1311 of the first-type fan-out line 131 is located in the light shielding layer, the first gate conductive layer Gate1 (see Figures 11, 12, 15, and 17, etc.), or the second gate conductive layer Gate2 (see Figure 14).

[0185] Illustratively, the multilayer conductive layer 103 includes a light shielding layer, a first gate conductive layer Gate1, a second gate conductive layer Gate2, and a third gate conductive layer Gate3. The first conductive layer 1031 is the light shielding layer, the first gate conductive layer Gate1, the second gate conductive layer Gate2, or the third gate conductive layer Gate3. Thus, the overlapping portion 1311 of the first-type fan-out line 131 is located in the light shielding layer, the first gate conductive layer Gate1 (see Figures 15 and 17), the second gate conductive layer Gate2 (see Figure 14), or the third gate conductive layer Gate3.

[0186] As can be seen above, the multilayer conductive layer 103 further includes at least two touch electrode layers stacked sequentially on a side of the at least two source / drain conductive layers SD away from the substrate 102. In some examples, the second conductive layer 1032 is any one of the at least two source / drain conductive layers SD and the at least two touch electrode layers.

[0187] Exemplarily, the multilayer conductive layer 103 further includes: a first source-drain conductive layer SD1, a second source-drain conductive layer SD2, a first touch electrode layer TMA, and a second touch electrode layer TMB. The second conductive layer 1032 comprises the first source-drain conductive layer SD1, the second source-drain conductive layer SD2, the first touch electrode layer, or the second touch electrode layer TMB. Thus, the overlapping portion 1311 of the first-type fan-out line 131 is located in the first source-drain conductive layer SD1, the second source-drain conductive layer SD2, the first touch electrode layer, or the second touch electrode layer TMB (see Figures 21 and 22).

[0188] As a result, the overlapping portions 1311 of at least two intersecting first-type fan-out lines 131 can be located on two different conductive layers 103, with a larger spacing between the two conductive layers 103. This reduces crosstalk between the data signals transmitted by the at least two overlapping portions 1311, reduces the capacitance of the parasitic capacitor formed by the multiple overlapping portions 1311, reduces the load on the overlapping portions 1311, and improves the stability of the data signal received by the data line. Furthermore, the provision of the shielding pattern 140 further reduces crosstalk between the data signal transmitted by the overlapping portion 1311 and other conductive layers, effectively improving the stability of the data signal, and thereby enhancing the image quality of the display panel 200 and the display device 1000.

[0189] The structure of the first type of fan-out line 131 and the shielding pattern 140 in FIG. 13 to FIG. 22 are briefly introduced below.

[0190] For example, in FIG13 , one of the two first-type fan-out lines 131 includes two transition portions 1312 and an overlapping portion 1311. One transition portion 1312 extends from the second gate conductive layer Gate2 through a via in the insulating layer between the second gate conductive layer Gate2 and the first source and drain conductive layer SD1 to the first source and drain conductive layer SD1, and is connected to one end of an overlapping portion 1311 located on the first source and drain conductive layer SD1. The other end of the overlapping portion 1311 is connected to another transition portion 1312, which extends from the first source and drain conductive layer SD1 through a via between the first source and drain conductive layer SD1 and the first gate conductive layer Gate1 to the first gate conductive layer Gate1. The other first-type fan-out line 131 includes two connecting portions 1313 and an overlapping portion 1311, all of which are arranged on the same layer and located on the first gate conductive layer Gate1. The shielding pattern 140 is located on the second source and drain conductive layer SD2.

[0191] For example, in FIG14 , two first-class fan-out lines 131 each include two transition portions 1312 and an overlapping portion 1311. The two overlapping portions 1311 are located in the second gate conductive layer Gate2 and the first source and drain conductive layer SD1, respectively. One transition portion 1312 extends from the first source and drain conductive layer SD1 through a hole to the second gate conductive layer Gate2, connecting to the overlapping portion 1311 located in the second gate conductive layer Gate2. The other transition portion 1312 extends from the first gate conductive layer Gate1 through a hole to the first source and drain conductive layer SD1, connecting to the overlapping portion 1311 located in the first source and drain conductive layer SD1. The shielding pattern 140 is located in the second source and drain conductive layer SD2.

[0192] For example, in Figure 15, a first-type fan-out line 131 includes two transition portions 1312 and an overlapping portion 1311. The transition portion 1312 extends from the second gate conductive layer Gate2 through the hole to the first source-drain conductive layer SD1 and the second source-drain conductive layer SD2, connecting to the overlapping portion 1311 located in the second source-drain conductive layer SD2. Another first-type fan-out line 131 is located in the first gate conductive layer Gate1, and its overlapping portion 1311 is located in the first gate conductive layer Gate1. The shielding pattern 140 is located in the first source-drain conductive layer SD1.

[0193] 16 is a cross-sectional structural diagram taken along line DD′ in FIG15 . Along the third direction Z, the shielding pattern 140 is located between the two overlapping portions 1311 .

[0194] For example, in FIG17 , the conversion portion 1312 of a first-class fan-out line 131 extends from the second gate conductive layer Gate2 through a hole to the first source-drain conductive layer SD1, and is connected to the overlapping portion 1311 located in the first source-drain conductive layer SD1. The conversion portion 1312 of another first-class fan-out line 131 extends from the second gate conductive layer Gate2 through a hole sequentially to the first source-drain conductive layer SD1 and the second touch electrode layer TMB, and is connected to the overlapping portion 1311 located in the second touch electrode layer TMB. The connection portion 1313 and the overlapping portion 1311 of another first-class fan-out line 131 (the middle first-class fan-out line 131) are both located in the first gate conductive layer Gate1. The shielding pattern 140 is located in the second source-drain conductive layer SD2.

[0195] For example, in FIG18 , a conversion portion 1312 of a first-type fan-out line 131 extends from the second gate conductive layer Gate2 through a hole to the first source-drain conductive layer SD1, connecting to an overlapping portion 1311 located in the first source-drain conductive layer SD1. A conversion portion 1312 of another first-type fan-out line 131 extends from the first gate conductive layer Gate1 through a hole, sequentially to the first source-drain conductive layer SD1 and the third source-drain conductive layer SD3, connecting to an overlapping portion 1311 located in the third source-drain conductive layer SD3. A shielding pattern 140 is located in the second source-drain conductive layer SD2. Along the third direction Z, the shielding pattern 140 is located between the two overlapping portions 1311.

[0196] For example, in FIG19 , a conversion portion 1312 of a first-type fan-out line 131 extends from the second gate conductive layer Gate2 through the hole to the first source-drain conductive layer SD1 and the third source-drain conductive layer SD3 in sequence, and is connected to the overlapping portion 1311 located in the third source-drain conductive layer SD3. The connection portion 1313 and the overlapping portion 1311 of another first-type fan-out line 131 are both located in the first gate conductive layer Gate1. The shielding pattern 140 is located in the second source-drain conductive layer SD2. Along the third direction Z, the shielding pattern 140 is located between the two overlapping portions 1311. In this example, the shielding pattern 140 can be set in a variety of positions. For example, multiple shielding patterns 140 can be set in the first source-drain conductive layer SD1 and / or in the second source-drain conductive layer SD2.

[0197] For example, in FIG20 , a conversion portion 1312 of a first-type fan-out line 131 extends from the first gate conductive layer Gate1 through a hole to the first source-drain conductive layer SD1 and the second gate conductive layer Gate2, and is connected to the overlapping portion 1311 located in the second gate conductive layer Gate2. A conversion portion 1312 of another first-type fan-out line 131 extends from the second gate conductive layer Gate2 through a hole to the first source-drain conductive layer SD1 and the third source-drain conductive layer SD3, and is connected to the overlapping portion 1311 located in the third source-drain conductive layer SD3. The shielding pattern 140 is located in the second source-drain conductive layer SD2. In this example, the shielding pattern 140 can be disposed in a variety of locations. For example, multiple shielding patterns 140 can be disposed in the first source-drain conductive layer SD1 and / or in the second source-drain conductive layer SD2.

[0198] For example, in FIG21 , a conversion portion 1312 of a first-type fan-out line 131 extends from the first gate conductive layer Gate1 through a hole to the first source-drain conductive layer SD1, connecting to an overlapping portion 1311 located in the first source-drain conductive layer SD1. A conversion portion 1312 of another first-type fan-out line 131 extends from the second gate conductive layer Gate2 through a hole, sequentially to the first source-drain conductive layer SD1 and the second touch electrode layer TMB, connecting to an overlapping portion 1311 located in the second touch electrode layer TMB. A shielding pattern 140 is located in the second source-drain conductive layer SD2. Along the third direction Z, the shielding pattern 140 is located between the two overlapping portions 1311. In this example, the shielding pattern 140 can be disposed in a variety of locations. For example, multiple shielding patterns 140 can be disposed in the first source-drain conductive layer SD1 and / or in the second source-drain conductive layer SD2.

[0199] For example, in FIG22 , a conversion portion 1312 of a first-type fan-out line 131 extends from the first gate conductive layer Gate1 through a hole to the first source-drain conductive layer SD1 and the second source-drain conductive layer SD2, connecting to an overlapping portion 1311 located in the second source-drain conductive layer SD2. A conversion portion 1312 of another first-type fan-out line 131 extends from the first gate conductive layer Gate1 through a hole to the first source-drain conductive layer SD1 and the second touch electrode layer TMB, connecting to an overlapping portion 1311 located in the second touch electrode layer TMB. A connection portion 1313 of another first-type fan-out line 131 (the middle first-type fan-out line 131) is located on the second gate conductive layer Gate2 (the first source-drain conductive pattern SDT on this connection portion 1313 is provided to reduce the difference in film thickness between this first-type fan-out line 131 and the other fan-out lines), connecting to an overlapping portion 1311 located in the second gate conductive layer Gate2. The shielding pattern 140 is located on the third source-drain conductive layer SD3. In this example, the shielding pattern 140 can be positioned in various locations. For example, multiple shielding patterns 140 can be located on the first source-drain conductive layer SD1 and / or on the third source-drain conductive layer SD3. The shielding pattern 140 located on the first source-drain conductive layer SD1 can shield and protect the overlapping portion 1311 of the second gate conductive layer Gate2 and the overlapping portion 1311 of the second source-drain conductive layer SD2.

[0200] It is understandable that the structures of the first type of fan-out lines 131 and the shielding patterns 140 provided in the embodiments of the present disclosure are not limited to the structures shown in FIG. 13 to FIG. 22 .

[0201] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel comprising a display area and a fan-out area, wherein the fan-out area is located on one side of the display area; The display panel includes: A substrate and a plurality of conductive layers stacked on one side of the substrate; The multi-layer conductive layer includes: a plurality of data lines, a plurality of connection lines and a plurality of fan-out lines; The plurality of data lines are arranged at intervals along a first direction and extend along a second direction, the second direction intersecting the first direction; the plurality of data lines include a plurality of first data lines and a plurality of second data lines, the plurality of first data lines are located in at least one edge region of the display area, and the plurality of second data lines are located in a central region adjacent to the edge region; A first end of a connecting line is located in the edge region and is electrically connected to one of the first data lines, and a second end of the connecting line extends to a junction between the central region and the fan-out region; at least one of the connecting lines crosses over at least one data line and is insulated from the data line it crosses; The plurality of fan-out lines are located in the fan-out area; one of the fan-out lines is connected to one of the connection lines or one of the second data lines; The plurality of fan-out lines include: a plurality of first-type fan-out lines; the first-type fan-out lines include overlapping portions; in the thickness direction of the substrate, the overlapping portions of at least two first-type fan-out lines intersect with each other in an orthographic projection on the substrate, so that an arrangement order of the at least two first-type fan-out lines at one end close to the display area along the first direction is different from an arrangement order of the at least two first-type fan-out lines at one end away from the display area along the first direction; Among them, the multi-layer conductive layer includes: a first conductive layer, a second conductive layer and at least one third conductive layer; at least one third conductive layer is located between the first conductive layer and the second conductive layer; the overlapping parts of the two intersecting first-type fan-out lines are respectively located in the first conductive layer and the second conductive layer.

2. The display panel according to claim 1, wherein The extending directions of the two overlapping portions of the two first-type fan-out lines intersect.

3. The display panel according to claim 1, wherein: The first type fan-out line also includes: at least one transition portion; in the same first type fan-out line, the overlapping portion is located in the first conductive layer, and the transition portion extends from any layer of the conductive layer along the thickness direction of the substrate to the first conductive layer and is connected to the overlapping portion.

4. The display panel according to claim 3, wherein: An extending direction of a portion of the conversion portion located in the first conductive layer is different from an extending direction of the overlapping portion.

5. The display panel according to claim 1, wherein: The first type fan-out line further includes: at least one connecting portion; in the same first type fan-out line, the connecting portion is connected to the overlapping portion and is arranged in the same layer. The display panel according to claim 5 , wherein: An extending direction of the connecting portion is the same as or substantially the same as an extending direction of the overlapping portion.

7. The display panel according to claim 5, wherein: An extending direction of the connecting portion is different from an extending direction of the overlapping portion.

8. The display panel according to claim 1, wherein: The display panel further comprises a bending area and a chip mounting area that are sequentially away from the display area; the fan-out area comprises a first fan-out area and a second fan-out area, the first fan-out area is located between the display area and the bending area, and the second fan-out area is located between the bending area and the chip mounting area; The overlapping portion is located in the second fan-out area.

9. The display panel according to claim 1, wherein: The width of the overlapping portion is greater than or equal to 1.0 μm.

10. The display panel according to any one of claims 1 to 9, wherein: The display panel further includes: at least one shielding pattern; the shielding pattern receives a constant voltage signal; The shielding pattern is located in the fan-out area and in the third conductive layer; and the overlapping area of ​​the orthographic projections of the two overlapping portions on the substrate is located within the orthographic projection range of the shielding pattern on the substrate.

11. The display panel according to claim 10, wherein: The plurality of shielding patterns are located on the same third conductive layer and are connected to each other.

12. The display panel according to claim 10, wherein: The multi-layer conductive layer comprises: at least two source-drain conductive layers stacked in sequence; The plurality of shielding patterns are located in any one layer or any two layers of the at least two source / drain conductive layers.

13. The display panel according to claim 12, wherein: The multi-layer conductive layer further comprises: a light shielding layer and at least two gate conductive layers stacked in sequence on a side of the at least two source and drain conductive layers close to the substrate; The first conductive layer is any one of the light-shielding layer and the at least two gate conductive layers.

14. The display panel according to claim 12, wherein: The multi-layer conductive layer further comprises: at least two touch electrode layers stacked in sequence on a side of the at least two source and drain conductive layers away from the substrate; The second conductive layer is any one of the at least two source-drain conductive layers and the at least two touch electrode layers.

15. A display device comprising the display panel according to any one of claims 1 to 14.

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