Secure data transmission method and DMA controller

Abstract

Embodiments of the present disclosure provide a secure data transmission method and a DMA controller. The DMA controller comprises a plurality of DMA transmission channels, a cyclic redundancy check (CRC) unit, and a DMA scheduler. The secure data transmission method comprises: acquiring configuration parameters of the plurality of DMA transmission channels from a CPU; acquiring a plurality of secure data on the basis of the configuration parameters of the plurality of DMA transmission channels; in the CRC unit, performing CRC calculation on the plurality of secure data on the basis of the configuration parameters of the plurality of DMA transmission channels to obtain a plurality of CRC codes; and in the DMA scheduler, performing CRC processing on the plurality of secure data on the basis of the plurality of CRC codes.

Description

A secure data transmission method and a DMA controller

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure is based on Chinese patent application CN2024103084958, filed on March 18, 2024, entitled “A secure data transmission method and a DMA controller”, and claims the priority of the patent application, and all the contents disclosed therein are incorporated into this disclosure by reference. Technical Field

[0003] The embodiments of the present disclosure relate to the field of integrated circuits, and in particular to a secure data transmission method and a DMA controller. Background Art

[0004] Direct Memory Access (DMA) is a memory access and data transfer technology that can directly read and write system memory independently without the intervention of the Central Processing Unit (CPU). It can achieve direct data transfer from memory to memory, device to memory, memory to device, and device to device, thereby reducing the burden on the CPU. Data transfer through DMA can solve the problem of excessive CPU resource consumption due to data transfer, allowing the CPU to focus more on calculations, control, etc.

[0005] The secure data transmission process in related technologies is collaboratively completed by the CPU and DMA controller. During the sending process, the CPU uses a software or hardware CRC engine to calculate a cyclic redundancy check (CRC) on the secure data and adds the CRC to the end of the data to form a secure data packet. During the receiving process, the CPU also needs to use a software or hardware CRC engine to calculate the CRC of the secure data and compare it with the CRC at the end of the data to verify the correctness of the data. However, using software to calculate the CRC consumes a large amount of CPU resources, resulting in low CPU utilization; using a hardware CRC engine to calculate the CRC consumes double the transmission bandwidth, reducing bus utilization and increasing power consumption.

[0006] In related technologies, a technical solution has been proposed that uses a CRC hardware unit in conjunction with DMA to perform CRC calculations on security data. However, this solution requires returning the CRC code to the CPU for comparison, rather than performing data consistency verification directly on the hardware, nor does it involve multi-channel verification. In addition, when a CRC checksum code needs to be added to security data, the CRC code must first be read by the CPU and then written to the corresponding location, which further increases CPU intervention, especially in multi-channel and multi-task transmission, requiring more frequent CPU processing. Finally, in multi-channel transmission, equipping each channel with a CRC unit will increase area and power consumption.

[0007] In summary, there is no good solution to the problem that the secure data transmission process consumes a large amount of CPU resources in related technologies. Summary of the Invention

[0008] The embodiments of the present disclosure provide a secure data transmission method and a DMA controller to at least solve the problem in the related art that a secure data transmission process consumes a large amount of CPU resources.

[0009] According to one embodiment of the present disclosure, a secure data transmission method is provided, which is applied to a direct memory access (DMA) controller, wherein the DMA controller includes multiple DMA transmission channels, a cyclic redundancy check (CRC) unit, and a DMA scheduler. The method includes: obtaining configuration parameters of the multiple DMA transmission channels from a central processing unit (CPU); obtaining multiple pieces of security data based on the configuration parameters of the multiple DMA transmission channels; performing CRC calculation on the multiple pieces of security data in the CRC unit based on the configuration parameters of the multiple DMA transmission channels to obtain multiple CRC codes; and performing CRC processing on the multiple pieces of security data in the DMA scheduler based on the multiple CRC codes.

[0010] According to another embodiment of the present disclosure, a direct memory access (DMA) controller is provided, which includes multiple DMA transmission channels, a cyclic redundancy check (CRC) unit, and a DMA scheduler, wherein the multiple DMA transmission channels are configured to obtain configuration parameters of the multiple DMA transmission channels from a central processing unit (CPU), and obtain multiple security data based on the configuration parameters of the multiple DMA transmission channels; the CRC unit is configured to perform CRC calculation on the multiple security data based on the configuration parameters of the multiple DMA transmission channels to obtain multiple CRC codes; and the DMA scheduler is configured to perform CRC processing on the multiple security data based on the multiple CRC codes.

[0011] According to another embodiment of the present disclosure, a computer-readable storage medium is provided, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above method embodiments are executed.

[0012] According to another embodiment of the present disclosure, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any one of the above method embodiments.

[0013] According to another embodiment of the present disclosure, a computer program product is provided, including a computer program, which implements the steps in any of the above method embodiments when executed by a processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] FIG1 is a schematic structural diagram of a DMA transmission system according to an embodiment of the present disclosure;

[0015] FIG2 is a flow chart of a secure data transmission method according to an embodiment of the present disclosure;

[0016] FIG3 is a flow chart of a complete DMA data transfer according to an embodiment of the present disclosure;

[0017] FIG4 is a flow chart of a DMA controller automatically adding CRC check bits to security data in one embodiment of the present disclosure;

[0018] FIG5 is a flow chart of a DMA controller automatically performing consistency check on security data in one embodiment of the present disclosure;

[0019] FIG6 is a schematic structural diagram of a DMA controller according to an embodiment of the present disclosure;

[0020] FIG7 is a schematic diagram of a DMA transmission system in an embodiment of the present disclosure;

[0021] FIG8 is a schematic diagram of CRC calculation when multiple DMA channels share a CRC unit according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings and in conjunction with embodiments.

[0023] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0024] Cyclic Redundancy Check (CRC) is a commonly used error detection technology for data transmission in data communications. The sending end calculates a checksum based on the data using a specific algorithm. This checksum is then appended to the end of the data frame and sent to the receiving end. The receiving end verifies the received data and the checksum using the same algorithm to determine if the data is correct and complete.

[0025] To ensure data integrity during DMA transfers, related technologies combine CRC technology with DMA transfer technology to perform secure data DMA transfers. The secure data DMA transfer process is primarily implemented by the CPU and DMA controller.

[0026] A typical secure data transmission workflow is as follows:

[0027] 1. The CPU uses software (or hardware CRC engine) to calculate the CRC of the security data and adds the CRC to the end of the security data to form a security data packet;

[0028] 2. The CPU configures the DMA command control word and sends the configuration information such as source address, destination address, length, etc. to the DMA engine;

[0029] 3. CPU configures DMA transfer enable and starts DMA transfer;

[0030] 4. When the DMA engine completes the data transfer or an error occurs, it sends an interrupt to the CPU to inform the CPU that the data has been moved and that the next step can be processed.

[0031] A typical workflow for secure data reception and transmission is as follows:

[0032] 1. The CPU pre-configures the DMA command control words, such as source address, destination address, length, etc. to the DMA engine;

[0033] 2. The CPU configures DMA transfer enable (or an external device initiates a transfer request signal) and starts DMA transfer;

[0034] 3. When the DMA engine completes the data transfer or an error occurs, it sends an interrupt to the CPU to inform the CPU that the data has been moved and that the next step can be processed.

[0035] 4. The CPU uses software (or hardware CRC engine) to perform CRC calculation on the security data and compares the CRC calculation value with the CRC at the end of the security data to verify the correctness of the data.

[0036] In typical secure data transmission, the CPU is typically responsible for CRC calculation and processing. However, in the disclosed embodiments, CRC value calculation and CRC processing of secure data can be performed within the DMA controller, eliminating the need for CPU involvement or data interaction with the CPU, saving CPU resources and bus transmission bandwidth. Furthermore, multiple DMA transmission channels in the disclosed embodiments share a single CRC unit, achieving the technical benefits of reducing chip area and power consumption.

[0037] The method embodiments provided in the embodiments of the present disclosure can be executed in a DMA controller. The DMA controller can be regarded as an independent product, independent of the rest of the memory system and the processor. The DMA controller can also be used in a system on chip together with the processor.

[0038] In an exemplary embodiment, a DMA controller can be used as part of a DMA transmission system, combined with a CPU and a bus to implement a DMA transmission system. FIG1 is a schematic diagram of the structure of a DMA transmission system according to an embodiment of the present disclosure. As shown in FIG1 , the DMA transmission system includes the following structure:

[0039] DMA controller 10 , bus 20 , CPU 30 , storage unit 40 and external device 50 , wherein the DMA controller 10 is connected to the bus 20 , the CPU 30 is connected to the bus 20 , the storage unit 40 is connected to the bus 20 , and the external device 50 is connected to the bus 20 .

[0040] The DMA controller 10 is responsible for receiving data movement tasks sent by the CPU or triggered by external devices, scheduling and managing tasks, generating read and write control signals for the bus for data movement based on the tasks, and controlling whether to perform CRC check or add CRC check code to the moved data based on the tasks.

[0041] Bus 20 is responsible for providing a data transmission path between the CPU, storage unit and DMA controller. It can be implemented using a high-performance network-on-chip (NoC) bus topology structure. The communication protocol can adopt a high-performance bus protocol, such as the Advanced eXtensible Interface (AXI) protocol, the Advanced High Performance Bus (AHB) protocol, etc., which is not limited in this disclosure.

[0042] The CPU 30 is responsible for issuing the security data migration task and completing the interrupt control, and can be implemented by a high-performance CPU or a general-purpose CPU system.

[0043] The storage unit 40 is responsible for providing a cache for system data. For example, it can be implemented using an on-chip static random-access memory (SRAM), but the present disclosure is not limited thereto.

[0044] The external device 50 is responsible for protocol conversion and data transmission and reception between the system on chip (SoC) and the external device. The number of external devices can be one or more. For example, the type of external device can include low-latency CAN / LIN, I2C and other communication engines, or external storage units. The present disclosure does not limit this.

[0045] In the embodiment of the present disclosure, the DMA controller 10 is further configured to perform CRC processing on the moved data, eliminating the need for the CPU to perform CRC processing on the moved data, thereby achieving the technical effect of saving CPU resources.

[0046] In one embodiment of the present disclosure, a secure data transmission method is provided, which is applied to a direct memory access (DMA) controller. The DMA controller includes multiple DMA transmission channels, a cyclic redundancy check (CRC) unit, and a DMA scheduler. FIG2 is a flow chart of the secure data transmission method according to an embodiment of the present disclosure. As shown in FIG2 , the flow includes the following steps:

[0047] Step S202, obtaining configuration parameters of multiple DMA transmission channels from the central processing unit CPU;

[0048] Step S204, acquiring multiple pieces of security data according to the configuration parameters of the multiple DMA transmission channels;

[0049] Step S206, in the CRC unit, performing CRC calculation on the plurality of pieces of security data according to the configuration parameters of the plurality of DMA transmission channels to obtain a plurality of CRC codes;

[0050] Step S208: In the DMA scheduler, CRC processing is performed on the plurality of pieces of security data according to the plurality of CRC codes.

[0051] Through the disclosed embodiments, CRC processing of secure data can be performed within the DMA controller, ensuring the security and integrity of data DMA transmissions and saving CPU resources. This solves the problem of large CPU resource consumption during secure data transmission in related technologies. Furthermore, multiple DMA transmission channels in the disclosed embodiments share a single CRC unit, achieving the technical benefits of reducing chip area and power consumption.

[0052] The secure data transmission process in the embodiment of the present disclosure can be started by triggering the CPU or an external device and implemented within the DMA controller. The CRC unit can be implemented by software or hardware (such as a CRC engine), and the present disclosure does not limit this.

[0053] In some embodiments, the configuration parameters of the DMA transmission channel include: DMA transmission parameters and CRC processing parameters. Furthermore, the configuration parameters obtained from the CPU are equivalent to the transmission tasks assigned by the CPU to the DMA controller. In multi-channel transmission, the configuration parameters of the DMA transmission channel are equivalent to the subtasks assigned by the CPU to each transmission channel.

[0054] In some embodiments, the above step S202, obtaining the configuration parameters of the multiple DMA transmission channels from the central processing unit (CPU), may include the following steps:

[0055] Step S2022, receiving DMA transmission parameters of the multiple DMA transmission channels and CRC processing parameters of the multiple DMA transmission channels sent by the CPU;

[0056] Step S2024: The DMA transmission parameters of the multiple DMA transmission channels are respectively sent to the corresponding DMA transmission channels through the DMA scheduler, and the CRC processing parameters of the multiple DMA transmission channels are sent to the CRC unit.

[0057] In some embodiments, the above step S204, obtaining multiple pieces of security data according to the configuration parameters of the multiple DMA transmission channels, may include the following steps:

[0058] Step S2042: in each of the DMA transmission channels, generating a read data command according to the corresponding DMA transmission parameters;

[0059] Step S2044, scheduling the multiple read data commands generated by the multiple DMA transmission channels to a bus through the DMA scheduler;

[0060] Step S2046, acquiring the plurality of pieces of security data returned by the bus, wherein each piece of the security data corresponds to one of the read data commands;

[0061] Step S2048: Send the multiple pieces of security data to the corresponding DMA transmission channels respectively through the DMA scheduler.

[0062] In some embodiments, after performing CRC processing on the plurality of pieces of security data according to the plurality of CRC codes in the above step S208, the method further includes: step S209, sending the plurality of pieces of security data after CRC processing.

[0063] Specifically, step S209 may include the following steps:

[0064] Step S2092: In each of the DMA transmission channels, a write data command is generated according to the corresponding DMA transmission parameters;

[0065] Step S2094, scheduling the multiple write data commands generated by the multiple DMA transmission channels to the bus through the DMA scheduler;

[0066] Step S2096: Send the plurality of CRC-processed safety data to the bus, wherein the bus is configured to process the CRC-processed safety data according to the write data command.

[0067] In some embodiments, the DMA transfer parameters include: a DMA transfer channel number, a source address, a destination address, and the transfer length of the security data. The DMA transfer parameters are transfer tasks issued by the CPU to the DMA controller, instructing the DMA controller to read a certain amount of target data from the source address and then move the read data to the destination address. The source address and destination address can be addresses in a storage unit or an external device. Based on the DMA transfer channel number, the CPU can independently control the transfer subtasks of each transfer channel.

[0068] In some embodiments, before step S206, the method further includes: step S205, determining the DMA transmission channel number of each piece of the security data through the DMA scheduler, and sending the multiple pieces of security data and the corresponding DMA transmission channel number to the CRC unit.

[0069] In some embodiments, the above step S206 may include the following steps: in the CRC unit, determining the CRC processing parameters of each piece of the security data according to the DMA transmission channel number of the security data, and performing CRC calculation on the corresponding security data according to the CRC processing parameters to obtain the CRC code.

[0070] In some embodiments, the CRC processing parameters include: a CRC processing channel number and a CRC polynomial. The CRC processing parameters are transmission tasks sent by the CPU to the DMA controller, indicating whether CRC processing is required for the read security data, and the calculation method of the CRC code for each DMA transmission channel. Based on the CRC processing channel number, the CPU can set the CRC polynomial (i.e., the calculation method of the CRC code) for each transmission channel respectively. The CRC processing channel number here can only include the DMA transmission channels that need to be CRC processed, but the present disclosure is not limited to this.

[0071] In some embodiments, step S208 performs CRC processing on the plurality of pieces of security data according to the plurality of CRC codes, which may include the following steps:

[0072] Step S2082, sending the multiple CRC codes to the DMA scheduler through the CRC unit;

[0073] Step S2084: In the DMA scheduler, CRC processing is performed on each of the multiple pieces of security data according to the corresponding CRC code and CRC processing mode, wherein the CRC processing mode is included in the CRC processing parameters.

[0074] In the embodiment of the present disclosure, the complete DMA transmission process includes a data reading process and a data writing process. The CRC processing step in the above embodiment can occur in the data reading process or the data writing process, and the present disclosure does not limit this.

[0075] In some embodiments, step S2084 may include the following two situations: In situation one, when the CRC processing mode is the first processing mode, the DMA scheduler is used to add the CRC code to the security data according to the preset CRC position; in situation two, when the CRC processing mode is the second processing mode, the DMA scheduler is used to extract the CRC value to be checked from the security data according to the CRC position, and perform consistency check on the CRC value to be checked and the CRC code.

[0076] In some embodiments, the above situation one, when the CRC processing mode is the first processing mode, the DMA scheduler is used to add the CRC code to the security data according to a preset CRC position, which may include the following steps: in the DMA scheduler, a CRC code write command is constructed according to the CRC position and the CRC code; the CRC code write command is sent to the DMA transmission channel or the DMA write channel through the DMA scheduler, wherein the DMA transmission channel or the DMA write channel is set to add the CRC code to the security data according to the CRC code write command.

[0077] In an exemplary embodiment, if CRC processing occurs in the data read process of DMA transmission, the DMA scheduler may send a CRC code write command to the corresponding DMA transmission channel to complete the operation of adding the CRC code in the DMA transmission channel.

[0078] In another exemplary embodiment, if CRC processing occurs during the data write process of a DMA transfer, the DMA scheduler can send a CRC code write command to the DMA write channel, which then adds the CRC code and sends the processed data via the bus to the destination address. Alternatively, since the DMA write channel is the only channel through which the DMA controller writes data to the outside, the DMA write channel can also send the security data and the CRC code write command together via the bus to the destination address, which then adds the CRC code. This CRC processing also does not require CPU participation, thus achieving the technical effect of saving CPU resources.

[0079] In some embodiments, the method may further include the following processing: when the CRC processing mode is the third processing mode, scheduling multiple write data commands generated by the multiple DMA transfer channels to a bus via the DMA scheduler; and sending the multiple security data to the bus via the DMA write channel, wherein the bus is configured to process the security data according to the write data commands. The disclosed embodiments can accommodate situations where data does not require CRC processing, and the CRC processing mode is set separately for each DMA transfer channel, providing greater flexibility in the allocation and issuance of transmission tasks.

[0080] In some embodiments, the CRC processing parameters also include: a CRC processing channel number, a CRC position, and a CRC processing mode. The CRC processing parameter is a transmission task issued by the CPU to the DMA controller, which is used to indicate whether the read safety data needs to be CRC checked or CRC code added. Based on the CRC processing channel number, the CPU can control the CRC processing mode of each transmission channel. The CRC position is used to indicate the location where the CRC code is added, or the location where the CRC code is extracted. The CRC processing mode can include adding a CRC code, CRC checking, or not performing CRC processing, i.e., the first processing mode to the third processing mode mentioned above.

[0081] Through the disclosed embodiments, CRC processing of secure data can be performed within the DMA controller, ensuring the security and integrity of data DMA transmissions and saving CPU resources. This solves the problem of large CPU resource consumption during secure data transmission in related technologies. Furthermore, multiple DMA transmission channels in the disclosed embodiments share a single CRC unit, achieving the technical benefits of reducing chip area and power consumption.

[0082] In the disclosed embodiments, a complete DMA data transfer can be divided into two phases: a read data process and a write data process. The DMA controller reads security data from the source memory, caches the security data in the DMA transfer channel, and then writes the security data to the destination memory through the DMA transfer channel, thereby achieving the transfer of security data from the source memory to the destination memory. The step of performing CRC processing on the security data can be set after the data read is completed, or during the data write phase.

[0083] FIG3 is a flow chart of a complete DMA data transmission according to an embodiment of the present disclosure. As shown in FIG3 , a complete DMA transmission process includes the following steps:

[0084] Step S301, the CPU configures parameters for the DMA controller;

[0085] Step S302: The CPU starts DMA data transmission, or an external device triggers DMA data transmission;

[0086] Step S303, each DMA transmission channel generates a DMA transmission read data command according to the configuration;

[0087] Step S304: The DMA scheduler schedules the read data commands of each DMA transmission channel, and then reads the security data from the source memory through the bus;

[0088] In step S305 , the read security data is returned to the DMA caller through the bus, and the security data is distributed to the corresponding DMA transmission channel according to the ID of the transmission channel.

[0089] Step S306 , each DMA transmission channel caches the received security data and generates a write data command according to the configuration and data cache size;

[0090] Step S307: The DMA scheduler schedules the write data commands of each DMA transmission channel, and then transmits the write data commands to the destination memory via the bus.

[0091] Step S308, determine whether all data has been transmitted. If not, return to step S303, otherwise proceed to the next step;

[0092] Step S309: When the transmission is completed, an interrupt is generated to inform the CPU.

[0093] In this embodiment, the configuration parameters used in step S301 include DMA transmission parameters and CRC processing parameters. Furthermore, the configuration parameters may include: DMA transmission channel number, source address, destination address, transmission length, CRC location, CRC processing channel number, CRC polynomial, CRC processing mode, etc. The CRC processing mode includes adding a CRC code and CRC checksum, and the CRC polynomial may be a selectable range of polynomials or an identifier of a specific polynomial.

[0094] In this embodiment, the CRC processing can occur in the data reading process or the data writing process. The calculation operation of the CRC code of the security data can occur at any time after step S305 and before the CRC processing.

[0095] In an exemplary embodiment, the DMA scheduler also sends the security data to the CRC unit. The DMA scheduler can send all acquired security data to the CRC unit, which then determines whether to perform CRC processing. Alternatively, the DMA scheduler can directly determine whether the acquired security data requires CRC processing and send the security data requiring CRC processing to the CRC unit. Whether the security data requires CRC processing can be determined by comparing the CRC processing channel number with the channel number of the transmission channel corresponding to the security data. If they are consistent, it is necessary to iteratively calculate the CRC code based on the security data and the CRC polynomial corresponding to the transmission channel.

[0096] In an exemplary embodiment, if the CRC processing mode is to add a CRC code, the CRC unit may generate a corresponding CRC code write command and send the CRC code write command to the DMA scheduler, which then schedules the CRC code write command to a specified location.

[0097] Furthermore, if a CRC code is added to the data reading process, the operation can be performed in the corresponding DMA transmission channel, and the operation should be located between step S305 and step S306; if a CRC code is added to the data writing process, the operation can be performed in the data writing channel or the destination memory, and the operation can be located after step S307, in the process of the security data reaching the destination memory through the write channel and the bus.

[0098] In one exemplary embodiment, if the CRC processing mode is CRC check, the CRC unit sends the calculated CRC code to the DMA scheduler. Regardless of whether the data is read or written, the CRC check is performed by the DMA scheduler. If the check fails, the DMA scheduler generates an interrupt to notify the CPU of the check failure. In this embodiment, the CRC check can occur at any time after the DMA scheduler reads data from the read data channel and before writing data through the write data channel. This is not limited by the present disclosure.

[0099] FIG4 is a flow chart of a DMA controller automatically adding a CRC check bit to security data in an embodiment of the present disclosure. As shown in FIG4 , the flow includes the following steps:

[0100] Step S402, the CPU configures the transmission parameters of each DMA transmission channel;

[0101] Step S404, start DMA transmission and CRC calculation;

[0102] Step S406: secure data transmission is completed and CRC calculation is completed;

[0103] In step S408, the DMA scheduler constructs a check bit transmission command (equivalent to a CRC code write command).

[0104] In this embodiment, the transmission parameters of the DMA transmission channel include: DMA transmission parameters and CRC processing parameters. Further, the configuration parameters may include: DMA transmission channel number, source address, destination address, transmission length, CRC location, CRC processing channel number, CRC polynomial, CRC processing mode, etc. Among them, the CRC processing mode includes adding a CRC check bit, and the CRC polynomial can be an optional range of polynomials or the identifier of a specific polynomial.

[0105] In this embodiment, after starting DMA transmission and CRC calculation in step S404, the CRC unit receives data from the DMA read channel, and determines whether the ID of the data channel is consistent with the preset ID (such as the CRC processing channel number) for which CRC calculation needs to be performed. If consistent, the CRC polynomial is selected and the CRC value is iteratively calculated.

[0106] In this embodiment, step S408 specifically includes: when the CRC processing mode is to automatically add CRC check bits, the DMA scheduler will automatically construct a CRC code write command and AXI timing according to the CRC addition position and CRC polynomial, write the CRC to the corresponding position, and generate a completion interrupt.

[0107] Through the embodiments of the present disclosure, CRC check bits can be automatically added to security data within the DMA controller, ensuring the security and integrity of data DMA transmission, saving CPU resources, and thus solving the problem of large CPU resource consumption in the security data transmission process in related technologies.

[0108] FIG5 is a flow chart of a DMA controller automatically performing consistency check on security data in an embodiment of the present disclosure. As shown in FIG5 , the flow includes the following steps:

[0109] Step S502, the CPU configures the transmission parameters of each DMA transmission channel;

[0110] Step S504, start DMA transmission and CRC calculation;

[0111] Step S506: The secure data transmission is completed and the CRC calculation is completed;

[0112] Step S508: The DMA scheduler automatically checks the CRC value and reports the check result.

[0113] In this embodiment, the transmission parameters of the DMA transmission channel include: DMA transmission parameters and CRC processing parameters. Further, the configuration parameters may include: DMA transmission channel number, source address, destination address, transmission length, CRC location, CRC processing channel number, CRC polynomial, CRC processing mode, etc. Among them, the CRC processing mode includes data consistency checking, and the CRC polynomial can be an optional range of polynomials or the identifier of a specific polynomial.

[0114] In this embodiment, after starting DMA transmission and CRC calculation in step S504, the CRC unit receives data from the DMA read channel, and determines whether the ID of the data channel is consistent with the preset ID (such as the CRC processing channel number) for which CRC calculation needs to be performed. If consistent, the CRC polynomial is selected and the CRC value is iteratively calculated.

[0115] In this embodiment, step S508 specifically includes: when the secure data transmission mode is data consistency check, the DMA scheduler will automatically extract the CRC value according to the position of the CRC, and compare the extracted CRC value with the calculation result of the CRC unit. If they are inconsistent, an interrupt will be generated and the fault result will be reported to the CPU.

[0116] Through the embodiments of the present disclosure, automatic consistency verification of security data can be implemented inside the DMA controller, thereby ensuring the security and integrity of data DMA transmission, saving CPU resources, and thus solving the problem of large CPU resource consumption in the security data transmission process in related technologies.

[0117] In another embodiment of the present disclosure, a DMA controller is further provided. FIG6 is a schematic structural diagram of a DMA controller according to an embodiment of the present disclosure. As shown in FIG6 , the DMA controller 10 includes the following structure:

[0118] A plurality of DMA transmission channels 11 , a cyclic redundancy check CRC unit 12 and a DMA scheduler 13 .

[0119] The DMA transmission channel 11 is configured to obtain configuration parameters of the multiple DMA transmission channels from a central processing unit (CPU), and obtain multiple pieces of security data according to the configuration parameters of the multiple DMA transmission channels.

[0120] The CRC unit 12 is configured to perform CRC calculation on the plurality of safety data according to the configuration parameters of the plurality of DMA transmission channels to obtain a plurality of CRC codes.

[0121] The DMA scheduler 13 is configured to perform CRC processing on the plurality of pieces of security data according to the plurality of CRC codes.

[0122] Through the disclosed embodiments, CRC processing of secure data can be performed within the DMA controller, ensuring the security and integrity of data DMA transmissions and saving CPU resources. This solves the problem of large CPU resource consumption during secure data transmission in related technologies. Furthermore, multiple DMA transmission channels in the disclosed embodiments share a single CRC unit, achieving the technical benefits of reducing chip area and power consumption.

[0123] The secure data transmission process in the embodiment of the present disclosure can be started by triggering the CPU or an external device and implemented within the DMA controller. The CRC unit can be implemented by software or hardware (such as a CRC engine), and the present disclosure does not limit this.

[0124] In some embodiments, the configuration parameters of the DMA transmission channel include: DMA transmission parameters and CRC processing parameters.

[0125] In some embodiments, the DMA controller further includes a configuration channel, wherein the configuration channel is configured to receive DMA transmission parameters of the multiple DMA transmission channels and CRC processing parameters of the multiple DMA transmission channels sent by the CPU.

[0126] In some embodiments, the DMA scheduler is further configured to send the DMA transmission parameters of the multiple DMA transmission channels to the corresponding DMA transmission channels respectively, and send the CRC processing parameters of the multiple DMA transmission channels to the CRC unit.

[0127] In some embodiments, the DMA transmission channel is further configured to generate a read data command based on the respective corresponding DMA transmission parameters, and send the read data command to the DMA scheduler; the DMA scheduler is further configured to schedule multiple read data commands received from multiple DMA transmission channels to the bus.

[0128] In some embodiments, the DMA controller further includes a read data channel, wherein the read data channel is configured to obtain the plurality of security data returned by the bus, wherein each security data corresponds to a read data command.

[0129] Furthermore, the read data channel is used to send multiple pieces of security data to the DMA scheduler.

[0130] In some embodiments, the DMA scheduler is further configured to send multiple pieces of security data to corresponding DMA transmission channels respectively.

[0131] In some embodiments, the DMA transmission channel is configured to generate a write data command based on the corresponding DMA transmission parameters and send the write data command to the DMA scheduler; the DMA scheduler is configured to schedule the write data commands from multiple DMA transmission channels to the bus.

[0132] In some embodiments, the DMA controller further includes a write data channel, wherein the write data channel is configured to send multiple CRC-processed safety data to the bus, wherein the bus is configured to process the CRC-processed safety data according to a write data command.

[0133] In some embodiments, the DMA transfer parameters include: a DMA transfer channel number, a source address, a destination address, and the transfer length of the security data. The DMA transfer parameters are transfer tasks issued by the CPU to the DMA controller, instructing the DMA controller to read a certain amount of target data from the source address and then move the read data to the destination address. The source address and destination address can be addresses in a storage unit or an external device. Based on the DMA transfer channel number, the CPU can independently control the transfer subtasks of each transfer channel.

[0134] In some embodiments, the DMA scheduler is further configured to determine a DMA transmission channel number for each piece of the security data, and send the multiple pieces of security data and the corresponding DMA transmission channel numbers to the CRC unit.

[0135] In some embodiments, the CRC unit is further configured to determine the CRC processing parameters of each piece of the security data according to the DMA transmission channel number of the security data, and perform CRC calculation on the corresponding security data according to the CRC processing parameters to obtain the CRC code.

[0136] In some embodiments, the CRC processing parameters include: a CRC processing channel number and a CRC polynomial. The CRC processing parameters are transmission tasks sent by the CPU to the DMA controller, indicating whether CRC processing is required for the read security data, and the calculation method of the CRC code for each DMA transmission channel. Based on the CRC processing channel number, the CPU can set the CRC polynomial (i.e., the calculation method of the CRC code) for each transmission channel respectively. The CRC processing channel number here can only include the DMA transmission channels that need to be CRC processed, but the present disclosure is not limited to this.

[0137] In some embodiments, the CRC unit is further configured to send the multiple CRC codes to the DMA scheduler; the DMA scheduler is further configured to perform CRC processing on each of the multiple security data according to the corresponding CRC code and CRC processing mode, wherein the CRC processing mode is included in the CRC processing parameters.

[0138] In the embodiment of the present disclosure, the complete DMA transmission process includes a data reading process and a data writing process. The CRC processing step in the above embodiment can occur in the data reading process or the data writing process, and the present disclosure does not limit this.

[0139] In some embodiments, the DMA scheduler is further configured to, when the CRC processing mode is the first processing mode, add the CRC code to the security data according to a preset CRC position. Furthermore, the DMA scheduler is further configured to construct a CRC code write command based on the CRC position and the CRC code; and send the CRC code write command to the DMA transmission channel or the DMA write channel, wherein the DMA transmission channel or the DMA write channel is configured to add the CRC code to the security data according to the CRC code write command.

[0140] In some embodiments, the DMA scheduler is further configured to extract the CRC value to be checked from the security data according to the CRC position when the CRC processing mode is the second processing mode, and perform consistency check on the CRC value to be checked and the CRC code.

[0141] In an exemplary embodiment, if CRC processing occurs in the data read process of DMA transmission, the DMA scheduler may send a CRC code write command to the corresponding DMA transmission channel to complete the operation of adding the CRC code in the DMA transmission channel.

[0142] In another exemplary embodiment, if CRC processing occurs during the data write process of a DMA transfer, the DMA scheduler can send a CRC code write command to the DMA write channel, which then adds the CRC code and sends the processed data via the bus to the destination address. Alternatively, since the DMA write channel is the only channel through which the DMA controller writes data to the outside, the DMA write channel can also send the security data and the CRC code write command together via the bus to the destination address, which then adds the CRC code. This CRC processing also does not require CPU participation, thus achieving the technical effect of saving CPU resources.

[0143] In some embodiments, the DMA scheduler is further configured to, when the CRC processing mode is the third processing mode, send the multiple write data commands generated by the multiple DMA transmission channels to the DMA write channel; the DMA write channel is configured to send the multiple security data to the bus, wherein the bus is configured to process the security data according to the write data commands. Through the disclosed embodiments, it is compatible with situations where data does not require CRC processing, and the CRC processing mode is set separately for each DMA transmission channel, which increases the flexibility of allocating and issuing transmission tasks.

[0144] In some embodiments, the CRC processing parameters also include: a CRC processing channel number, a CRC position, and a CRC processing mode. The CRC processing parameter is a transmission task issued by the CPU to the DMA controller, which is used to indicate whether the read safety data needs to be CRC checked or CRC code added. Based on the CRC processing channel number, the CPU can control the CRC processing mode of each transmission channel. The CRC position is used to indicate the location where the CRC code is added, or the location where the CRC code is extracted. The CRC processing mode can include adding a CRC code, CRC checking, or not performing CRC processing, i.e., the first processing mode to the third processing mode mentioned above.

[0145] Through the disclosed embodiments, CRC processing of secure data can be performed within the DMA controller, ensuring the security and integrity of data DMA transmissions and saving CPU resources. This solves the problem of large CPU resource consumption during secure data transmission in related technologies. Furthermore, multiple DMA transmission channels in the disclosed embodiments share a single CRC unit, achieving the technical benefits of reducing chip area and power consumption.

[0146] FIG7 is a schematic diagram of a DMA transmission system in an embodiment of the present disclosure. As shown in FIG7 , the DMA transmission system includes the following structures:

[0147] DMA controller 10 , bus 20 , CPU 30 , storage unit 40 and external device 50 , wherein the DMA controller 10 is connected to the bus 20 , the CPU 30 is connected to the bus 20 , the storage unit 40 is connected to the bus 20 , and the external device 50 is connected to the bus 20 .

[0148] The DMA controller 10 includes the following structures: a plurality of DMA transmission channels 11 , a cyclic redundancy check (CRC) unit 12 , a DMA scheduler 13 , a configuration channel 14 , a read data channel 15 , and a write data channel 16 .

[0149] In this embodiment, the CPU sends the transmission parameters of the transmission channel to the DMA controller through the configuration channel, and the DMA scheduler distributes the transmission parameters to each transmission channel and sends the reference related to CRC calculation to the CRC unit.

[0150] In this embodiment, the DMA scheduler is responsible for receiving or caching data transfer tasks (including configuration parameters) issued by the CPU, and can also respond to DMA requests issued by external devices. The DMA scheduler can distribute configuration parameters to each DMA transfer channel or CRC unit, and can also perform interrupt aggregation and reporting.

[0151] In this embodiment, the configuration parameters can be divided into DMA transmission parameters and CRC processing parameters. The DMA transmission parameters are parameters required for data movement through the DMA controller, and the CRC processing parameters are parameters required for CRC processing of the moved data. For example, the DMA transmission parameters may include: source address, destination address, data length, and burst length. The CRC processing parameters may include CRC calculation parameters (such as CRC polynomial), the mapping relationship between CRC units and DMA channels (such as CRC processing channel number), CRC check type or CRC processing mode (such as adding CRC code, CRC check, or not performing CRC processing).

[0152] In this embodiment, the DMA transmission channel is responsible for receiving the transmission parameters assigned by the DMA scheduler, generating read and write commands according to the transmission parameters, and caching the read and written data.

[0153] In this embodiment, the CRC unit is responsible for judging the data channel ID of DMA read data or DMA write data, and judging whether the data channel ID is consistent with the preset channel that needs to perform CRC calculation. If consistent, CRC polynomial selection and iterative calculation of CRC value are performed, wherein the data channel ID is the ID of the DMA transmission channel to which the security data to be read and written by the DMA controller belongs, and the preset channel that needs to perform CRC calculation can be indicated by the CRC processing channel number.

[0154] In this embodiment, the CRC unit may be implemented using hardware (such as a CRC engine) or software, and this disclosure does not impose any limitations on this.

[0155] In this embodiment, the DMA transmission channel generates a read data command based on the transmission parameters and sends it to the DMA scheduler. The DMA scheduler schedules the read data commands from multiple DMA transmission channels, sequentially sending them to the bus via the write data channel. The bus then forwards the data to the source memory address, retrieves the data from it, and returns it. The data returns to the DMA scheduler via the bus and the read data channel. The DMA scheduler then distributes the data to the corresponding transmission channel, where the data is buffered, completing the data read process.

[0156] In this embodiment, the DMA scheduler also sends the data obtained from the read data channel to the CRC unit to calculate the CRC check code. The CRC check code calculation is performed separately for each transmission channel, and the CRC polynomials used by each transmission channel may be different.

[0157] In this embodiment, the DMA transmission channel will also generate a write data command based on the transmission parameters and send the write data command to the DMA scheduler. The DMA scheduler schedules the write data commands and data to be written of multiple DMA transmission channels, and sends them to the bus through the write data channel in turn, and then forwarded to the destination memory address by the bus, thereby completing the write data process.

[0158] In this embodiment, CRC processing can occur in the data reading process or the data writing process. The automatic addition of the CRC check code can occur in each DMA transmission channel, and the DMA scheduler schedules the CRC value returned by the CRC unit and the corresponding CRC code write command to the corresponding DMA transmission channel, or schedules the CRC value and the corresponding CRC code write command to the corresponding write data channel, and completes the automatic addition of the CRC code in the DMA transmission channel and the write data channel. The CRC check process is sent to the DMA scheduler. The DMA scheduler can obtain the calculated CRC value from the CRC unit, and extract the CRC code from the specified position of the security data to which the CRC check code has been added, and perform data consistency verification by comparing whether the two are consistent. If the verification is recognized, the DMA scheduler will also generate an interrupt to inform the CPU.

[0159] Through the disclosed embodiments, CRC processing of secure data can be performed within the DMA controller, ensuring the security and integrity of data DMA transmissions and saving CPU resources. This solves the problem of large CPU resource consumption during secure data transmission in related technologies. Furthermore, multiple DMA transmission channels in the disclosed embodiments share a single CRC unit, achieving the technical benefits of reducing chip area and power consumption.

[0160] FIG8 is a schematic diagram of CRC calculation for a CRC unit shared by multiple DMA channels in an embodiment of the present disclosure. As shown in FIG8 , the process includes the following steps:

[0161] Step S801, triggering multi-channel DMA transmission;

[0162] Step S802: The DMA scheduler obtains data to be read by each DMA channel;

[0163] Step S803, the DMA scheduler distributes data to each DMA channel;

[0164] Step S804, the DMA scheduler returns the data to the CRC unit;

[0165] Step S805, the CRC unit determines whether the channel ID of the data matches the CRC channel ID;

[0166] Step S806: If there is a match, the corresponding CRC polynomial is selected for iterative calculation;

[0167] Step S807: If there is no match, the CRC unit discards the data and does not perform CRC calculation.

[0168] In this embodiment, the CPU configures CRC-related parameters for each DMA channel, such as whether each DMA channel supports CRC processing (the need for CRC processing can be indicated by the CRC channel ID), the CRC code addition position, the CRC check mode, the selection of the CRC polynomial, etc.

[0169] In this embodiment, the DMA scheduler automatically sends a copy of all read data to the CRC unit. When CRC processing is required (including consistency check or adding CRC check code), the CRC check code is automatically calculated. The CRC check code calculated by the CRC unit can be combined with the CRC code write command generated by the DMA scheduler to automatically add the CRC check code at the specified position. The CRC check code calculated by the CRC unit can also be compared with the CRC code to be checked extracted by the DMA scheduler from the specified position of the data to be checked for consistency, to ensure data integrity during DMA transmission.

[0170] Through the embodiments of the present disclosure, CRC processing of secure data can be performed within the DMA controller, ensuring the security and integrity of data DMA transmissions, saving CPU resources, and thus resolving the problem of large CPU resource consumption during secure data transmission in related technologies. Furthermore, multiple DMA transmission channels in the present disclosure share a single CRC unit, achieving the technical effects of reducing chip area and power consumption.

[0171] An embodiment of the present disclosure further provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above method embodiments are executed.

[0172] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0173] An embodiment of the present disclosure further provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0174] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0175] An embodiment of the present disclosure further provides a computer program product, including a computer program, which implements the steps of any of the above method embodiments when executed by a processor.

[0176] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail here.

[0177] Obviously, those skilled in the art should understand that the modules or steps of the present disclosure described above can be implemented using a general-purpose computing device, they can be concentrated on a single computing device, or distributed across a network composed of multiple computing devices, they can be implemented using program code executable by the computing device, and thus, they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be performed in a different order than herein, or they can be fabricated into separate integrated circuit modules, or multiple modules or steps can be fabricated into a single integrated circuit module for implementation. Thus, the present disclosure is not limited to any particular combination of hardware and software.

[0178] The foregoing description is merely a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Those skilled in the art will readily appreciate that the present disclosure may be modified and varied in various ways. Any modifications, equivalent substitutions, or improvements made within the principles of the present disclosure shall be included within the scope of protection of the present disclosure.

Claims

1. A secure data transmission method, applied to a direct memory access (DMA) controller, wherein: The DMA controller includes multiple DMA transmission channels, a cyclic redundancy check (CRC) unit, and a DMA scheduler, wherein the method includes: Acquire configuration parameters of the multiple DMA transmission channels from a central processing unit (CPU); Acquire multiple pieces of security data according to configuration parameters of the multiple DMA transmission channels; In the CRC unit, CRC calculation is performed on the plurality of pieces of security data according to the configuration parameters of the plurality of DMA transmission channels to obtain a plurality of CRC codes; In the DMA scheduler, CRC processing is performed on the plurality of pieces of safety data according to the plurality of CRC codes.

2. The method according to claim 1, wherein The configuration parameters of the DMA transmission channel include: DMA transmission parameters and CRC processing parameters.

3. The method according to claim 2, wherein: The configuration parameters of the plurality of DMA transmission channels are obtained from a central processing unit (CPU), including: receiving DMA transmission parameters of the plurality of DMA transmission channels and CRC processing parameters of the plurality of DMA transmission channels sent by the CPU; The DMA transmission parameters of the multiple DMA transmission channels are respectively sent to the corresponding DMA transmission channels through the DMA scheduler, and the CRC processing parameters of the multiple DMA transmission channels are sent to the CRC unit.

4. The method according to claim 2, wherein: Acquiring multiple pieces of security data according to configuration parameters of the multiple DMA transmission channels, including: In each of the DMA transmission channels, generating a read data command according to the corresponding DMA transmission parameters; Dispatching the plurality of read data commands generated by the plurality of DMA transmission channels to a bus through the DMA scheduler; Acquire the plurality of pieces of security data returned by the bus, wherein each piece of the security data corresponds to one of the read data commands; The multiple pieces of security data are sent to the corresponding DMA transmission channels respectively through the DMA scheduler.

5. The method according to claim 4, wherein After performing CRC processing on the plurality of pieces of security data according to the plurality of CRC codes, the method further includes: In each of the DMA transmission channels, generating a write data command according to the corresponding DMA transmission parameters; Dispatching the plurality of write data commands generated by the plurality of DMA transmission channels to the bus through the DMA scheduler; A plurality of pieces of safety data processed by CRC are sent to the bus, wherein the bus is used to process the safety data processed by CRC according to the write data command.

6. The method according to any one of claims 2 to 5, The DMA transfer parameters include: DMA transmission channel number, source address, destination address and transmission length of the security data.

7. The method according to claim 2, wherein: Before performing CRC calculation on the plurality of pieces of security data according to the configuration parameters of the plurality of DMA transmission channels to obtain a plurality of CRC codes, the method further includes: The DMA scheduler determines the DMA transmission channel number of each piece of the safety data, and sends the multiple pieces of safety data and the corresponding DMA transmission channel number to the CRC unit.

8. The method according to claim 7, wherein: In the CRC unit, CRC calculation is performed on the multiple pieces of security data according to the configuration parameters of the multiple DMA transmission channels to obtain multiple CRC codes, including: In the CRC unit, CRC processing parameters of each piece of the security data are determined according to the DMA transmission channel number of the security data, and CRC calculation is performed on the corresponding security data according to the CRC processing parameters to obtain the CRC code.

9. The method according to any one of claims 7 to 8, The CRC processing parameters include: The CRC handles the channel number and the CRC polynomial.

10. The method according to claim 2, wherein: Performing CRC processing on the plurality of pieces of security data according to the plurality of CRC codes includes: sending the plurality of CRC codes to the DMA scheduler through the CRC unit; In the DMA scheduler, CRC processing is performed on each of the plurality of pieces of safety data according to the corresponding CRC code and CRC processing mode, wherein the CRC processing mode is included in the CRC processing parameters.

11. The method according to claim 10, wherein: In the DMA scheduler, performing CRC processing on each of the plurality of pieces of security data according to the corresponding CRC code and CRC processing mode, including: When the CRC processing mode is the first processing mode, adding the CRC code to the security data according to a preset CRC position by the DMA scheduler; When the CRC processing mode is the second processing mode, the DMA scheduler extracts the CRC value to be checked from the security data according to the CRC position, and performs a consistency check on the CRC value to be checked and the CRC code.

12. The method according to claim 11, wherein When the CRC processing mode is the first processing mode, adding the CRC code to the security data according to a preset CRC position by the DMA scheduler includes: In the DMA scheduler, constructing a CRC code write command according to the CRC position and the CRC code; The CRC code write command is sent to the DMA transmission channel or the DMA write channel through the DMA scheduler, wherein the DMA transmission channel or the DMA write channel is used to add the CRC code to the security data according to the CRC code write command.

13. The method according to claim 10, further comprising: When the CRC processing mode is the third processing mode, scheduling the multiple write data commands generated by the multiple DMA transmission channels to a bus through the DMA scheduler; The plurality of pieces of security data are sent to the bus through a DMA write channel, wherein the bus is used to process the security data according to the write data command.

14. The method according to any one of claims 10 to 13, The CRC processing parameters also include: CRC processing channel number, CRC position, and CRC processing mode.

15. A direct memory access (DMA) controller, wherein: The DMA controller includes multiple DMA transmission channels, a cyclic redundancy check (CRC) unit, and a DMA scheduler, wherein: The multiple DMA transmission channels are configured to obtain configuration parameters of the multiple DMA transmission channels from a central processing unit (CPU), and obtain multiple pieces of security data according to the configuration parameters of the multiple DMA transmission channels; The CRC unit is configured to perform CRC calculation on the plurality of safety data according to the configuration parameters of the plurality of DMA transmission channels to obtain a plurality of CRC codes; The DMA scheduler is configured to perform CRC processing on the plurality of pieces of security data according to the plurality of CRC codes.

16. A computer-readable storage medium storing a computer program, wherein: When the computer program is executed by a processor, the method according to any one of claims 1 to 14 is executed.

17. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the method according to any one of claims 1 to 14.

18. A computer program product comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements the steps of the method according to any one of claims 1 to 14.

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