Processor-controlled converter circuit with improved response time

Abstract

The invention relates to a processor-controlled converter circuit in which an external flip-flop circuit is used for increasing resolution and event response time of a standard low-cost processor-controlled converter.

Description

[0001] PROCESSOR-CONTROLLED CONVERTER CIRCUIT WITH IMPROVED RESPONSE

[0002] TIME

[0003] FIELD OF THE INVENTION

[0004] The invention relates to the field of converter circuits for drivers for different types of loads, such as - but not limited to - luminaires of lighting systems, for use in various different applications for home, office, retail, street lightings, hospitality and industry.

[0005] BACKGROUND OF THE INVENTION

[0006] Output converters for switched-mode power supplies of luminaire drivers (e.g., light emitting diode (LED) drivers) or drivers of other types of loads can be based on several control schemes. A commonly used control scheme uses a fast peak current controlled cycle-by-cycle inner control loop and a relatively slow average control outer control loop to regulate the output current.

[0007] Increased miniaturization and use of wide bandgap switches (e.g., GaN switches) require high-frequency operation of switched-mode power supplies.

[0008] Recently, (micro)processor-controlled drivers have become available. However, when low-cost microcontrollers (microprocessors) are used for peak current control, the following limitations are faced:

[0009] The microcontroller is configured to take decisions based on a time discrete processing steps. This may lead to a 10ns time resolution (related to the clock frequency) for commonly used microcontrollers. When trying to operate a peak current controlled converter at high frequency (>200kHz) all kinds of delays may cause problems. Also delays and discrete time steps in lOths of nanoseconds may cause big steps in energy transfer from the input to the output of the converter. Thus, when using a high converter operation frequency, time discrete processing steps can lead to a problem that a required average output current cannot be achieved with a discrete step so that continuous jumping between steps can occur. If the steps are too big, this can lead to an unstable behavior and flickering of the light output.

[0010] Timer peripherals inside the microcontroller may also be working in a time discrete manner so that input events need to be synchronized to a clock frequency. As a result, processing of event input signals to a responsive output may take multiple clock cycles (which may easily amount to 50-100ns). When using a high converter operating frequency this response time may degrade cycle-by-cycle performance.

[0011] SUMMARY OF THE INVENTION

[0012] It is an object of the present invention to provide a processor-controlled converter circuit with reduced response time.

[0013] This object is achieved by a control circuit as claimed in claim 1, a driver as claimed in claim 12, a luminaire as claimed in claim 13 and a method as claimed in claim 14.

[0014] According to a first aspect, a control circuit is provided for controlling a driver of a load, the control circuit comprising: a comparator for comparing a peak current reference value with a value of a sensed switching current of a converter switching element; a flip-flop circuit configured to be triggered by an output signal of the comparator, wherein an output signal of the flip-flop circuit is used to control a switching state of the converter switching element; and a microprocessor configured to control generation of the peak current reference value based on a comparison of an output reference value with a sensed value of the output signal at the load, wherein the microprocessor comprises an internal on-timer configured to control the flip-flop circuit to determine one or more of a maximum on-time of the converter switching element, a minimum on-time of the converter switching element, and a switch-on moment of the converter switching element, wherein the microprocessor is configured to apply to the flip-flop circuit a first control signal as a start pulse for setting the flip-flop circuit to an active state, and to apply a second control signal to a reset input of the flip-flop circuit to control a reset state of the flip-flop circuit.

[0015] Furthermore, according to a second aspect, a driver is provided, which comprises the control circuit of the first aspect.

[0016] Additionally, according to a third aspect, a luminaire is provided, which comprises the driver of the second aspect.

[0017] Moreover, according to a fourth aspect, a method of controlling a driver of a load is provided, wherein the method comprises: comparing a peak current reference value with a value of a sensed switching current of a converter switching element; triggering a flip-flop circuit by an output of the comparison step; using an output signal of the flip-flop circuit to control a switching state of the converter switching element; and configuring a microprocessor to control generation of the peak current reference value based on a comparison of an output reference value with a sensed value of the output signal at the load.

[0018] Accordingly, resolution and event response time of the converter can be increased by using the flip-flop circuit for fast signal processing, wherein the flip-flop circuit receives a peak current event of the converter switching element as a trigger and provides at its output a switch control signal for the converter switching element. Moreover, the proposed use of the flip-flop circuit in combination with the microprocessor allows to benefit from using the microprocessor while combining this with the benefits of the analogue control techniques offered by the flip-flop circuit.

[0019] According to a first option that may be combined with any one of the first to fourth aspects, the switching current through the converter switching element may be sensed by a sensing resistor connected in series to the converter switching element, wherein a voltage value across the sensing resistor may be fed back to the comparator.

[0020] According to a second option that may be combined with the first option or any one of the first to fourth aspects, the output signal of the comparator may be supplied to a trigger input, particularly a clock input, of the flip-flop circuit, particularly a D-type or RS- type flip-flop or latch, wherein the output signal of the flip-flop circuit may be applied as a switch control signal to a control terminal of the converter switching element.

[0021] According to a third option that may be combined with the first or second option or any one of the first to fourth aspects, the microprocessor may be configured to generate the peak current reference value based on the comparison of the output reference value with the sensed value of the output signal to adjust the output signal at the load.

[0022] According to a fourth option that may be combined with any one of the first to third options, the microprocessor may be configured to generate and supply the output reference value to an error amplifier which compares the sensed value of the output signal with the output reference value and generates the load peak current reference value to adjust the output signal at the load.

[0023] According to a seventh option, a transistor switch may be provided, that is controlled by the output signal of the comparator and connected between the reset input of the flip-flop circuit and a reference potential to forcedly activate an asynchronous reset of the flip-flop circuit in response to the output signal of the comparator. According to an eighth option that may be combined with any one of the first to seventh options or any one of the first to fourth aspects, the output signal of the flip-flop circuit may be fed back to the microprocessor to indicate a peak current event.

[0024] According to a ninth option that may be combined with any one of the first to eighth options or any one of the first to fourth aspects, a data input of the flip-flop circuit may be connected to a fixed reference potential and the output signal of the comparator may be directly applied to an edge-sensitive clock input of the flip-flop circuit.

[0025] According to a tenth option that may be combined with any one of the first to ninth options or any one of the first to fourth aspects, the flip-flop circuit may be an SR flipflop circuit and the output signal of the comparator may be applied to a reset input of the flipflop circuit.

[0026] It shall be understood that the control circuit of claim 1, the driver of claim 12, the luminaire of claim 13 and the method of claim 14 may have similar and / or identical preferred embodiments, in particular, as defined in the dependent claims.

[0027] It shall be understood that a preferred embodiment of the invention can also be any combination of the dependent claims or above embodiments with the respective independent claim.

[0028] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.

[0029] BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In the following drawings:

[0031] Fig. 1 shows schematically a block diagram of a processor-controlled LED driver with accelerating flip-flop circuit according to various embodiments;

[0032] Fig. 2 shows schematically an exemplary circuit diagram of an LED driver with accelerating D-type flip-flop circuit according to a first embodiment; and

[0033] Fig. 3 shows schematically an exemplary circuit diagram of an LED driver with accelerating SR-type flip-flop circuit according to a second embodiment.

[0034] DETAILED DESCRIPTION OF EMBODIMENTS

[0035] Various embodiments of the present invention are now described, which are applicable to drivers for luminaires of a solid-state lighting system, such as semiconductor LEDs, semiconductor lasers, vertical -cavity surface emitting lasers (VCSELs), organic light- emitting diodes (OLED), or polymer light-emitting diodes (PLED) as sources of illumination or light sources in visible or non-visible light spectra.

[0036] It is noted that - throughout the present disclosure - only those structural elements and functions are shown and described, which are useful to understand the embodiments. Other structural elements and functions are omitted for brevity reasons. Furthermore, the structure and / or function of blocks with identical reference numbers that have been described before are not described again, unless an additional specific functionality is involved.

[0037] The following embodiments are directed to a driver for LED loads such as luminaires with one or more LED light sources that are controlled by a separate or integrated driver circuit or module. They can be implemented in connection with any type of luminaire module or board and are applicable to various kinds of luminaire drivers or converters of luminaires.

[0038] Fig. 1 shows schematically a block diagram of a processor-controlled LED driver with reduced response time, according to various embodiments. The LED driver may be used for various applications like automotive lighting, street lighting, household lighting, commercial lighting and many others.

[0039] An input voltage of the driver may be generated by an AC power supply circuit e.g. from a power grid voltage of 110 V or 220 V at a mains frequency of 50 Hz or 60 Hz. The power supply circuit may comprise an electromagnetic interference (EMI) filter 10 for attenuating electromagnetic interference from the power system to limit the noise in the system and lower a risk of malfunctioning of the driver. The filtered AC voltage may then be supplied to a rectifier stage (RECT) 20 which is an electronic device that converts the filtered AC voltage into the DC voltage by using one or more rectifying elements (e.g., diodes or other valve elements) that allow current to flow in a single direction only. In an example, the rectifier stage may be a full-bridge rectifier stage.

[0040] The rectified voltage is supplied to a converter stage (CONV) 30 of the driver, that may be configured as an isolating or non-isolating power converter and may further comprise magnetics (inductor(s) / transformer), a converter output part (rectifying part) and a microprocessor (CC) 50 of the converter stage 30. In such power converters, a switching circuit of the converter stage 30 may be configured to control the converter output part of the converter stage 30 (e.g., via an electronic transformer in the isolated case) to supply a desired power level to an LED load (LED) 40, e.g., a luminaire comprising one or more LEDs or Led strings. In the example of Fig. 1, a buck converter with a faster peak-current controlled inner current control loop and a slower external current control loop are used.

[0041] There are several other converter topologies possible (besides the above buck topology). The converter stage 30 may alternatively be configured as a boost converter, a buck-boost converter, a flyback converter, a half-bridge converter, a full bridge converter, a forward converter, a push-pull converter, a resonant converter, or combinations of these. They all can be implemented in connection with the peak-current controlled design of proposed embodiments. The switching circuit of the converter stage 30 may be configured to use one or more switching elements (S) to transform the DC voltage into a pulsed waveform. The switching element(s) may be (a) semiconductor switch(es), such as (a) metal oxide semiconductor field effect transistor(s) (MOSFET(s)) or bipolar junction transistor(s) (BJT(s)). In examples, the output voltage at the LED load 40 can be controlled by switching the switching element on and off at a constant frequency, wherein the duty cycle of the switching control signal can be used to adjust the output voltage (e.g., by a pulse width modulation (PWM) scheme).

[0042] The converter stage 30 may be configured to operate as an electrical power converting device that controls (e.g., regulates) the power to the LED load 40 and that may respond to changing needs of the LED load 40 by supplying a constant amount of power to the LED load 40, as its electrical properties may change e.g. with temperature. Thereby, the LED load 40 can be provided with a very specific electrical power in order to operate properly.

[0043] More specifically, the converter stage 30 may be configured to control the output voltage / current at / through the LED load 40 depending on the power needs of the LED load 40. If multiple LED chips are connected in series, the output voltage of the converter stage 30 should supply at least the total forward voltage of the LEDs of the LED load 40, regardless of voltage variations in the AC power supply. Therefore, in switched-mode drivers, voltage feedback and / or current feedback may be implemented at least partly by the microprocessor 50 to provide a stable operation of the LED load 40.

[0044] In embodiments, peak current mode control may be implemented as current mode control technique, wherein current control may be combined with over-voltage protection.

[0045] The peak current mode control may comprise current feedback (via a feedback load current ILED) to the microprocessor 50 for an outer loop control function and switching current feedback (via feedback current IFB) for an inner loop control function. In the embodiment shown in Fig. 1, a MOSFET is used as switching element (S) of the converter stage 30. The drain-source current through the MOSFET is sensed by a sensing resistor (e.g., shunt resistor) Rs connected in series to the source terminal of the MOSFET, wherein the voltage value across the sensing resistor Rs (that directly corresponds to the sensed current) is then fed back as feedback current value IFB and compared with a reference current value IREF (generated / calculated by the microprocessor circuit 50) at a peak current comparator 70. The result of comparison, i.e., the output signal Ip of the peak current comparator 70, is then supplied to a trigger input (e.g., clock or set / reset input) of a flip-flop circuit (FF) 60 which is used to generate a switch control signal (G) (e.g., PWM control signal) applied to the control terminal (e.g., gate terminal of a MOSFET of Fig. 1) of the switching element.

[0046] The flip-flop circuit 60 is to be understood as a circuit or latch that has two stable states (e.g., high state and low state) that can store state information, sometimes also referred to as bistable multivibrator. Clocked flip-flops are specially designed for synchronous systems. Such devices ignore their inputs except at the transition of a dedicated trigger or clock signal (known as clocking, pulsing, or strobing). Clocking causes the flipflop either to change or to retain its output signal at its output Q based upon the values of the input signals at the transition. Some flip-flops change their output state on the rising edge of a clock signal applied to their clock input, others on the falling edge. Flip-flops and latches can be divided into various types including SR ("set-reset"), D ("data" or “delay”), T ("toggle"), and JK. The behavior of each particular type can be described by what is termed the characteristic equation, which defines the "next" (i.e., after the next clock pulse) output Qnext in terms of the present input signal(s) and / or the present output. Inputs S and R designate set and reset, meaning a high state at the set input (e.g., S=l) sets the binary state of the flip-flop to high state (e.g., 1) and a high state at the reset input (e.g., R=l) sets the binary state of the flip-flop to low state (e.g., 0). Negated input and output terminals may be indicated by an upper dash.

[0047] The flip-flop circuit 60 can be made to change state by signals applied to one or more control inputs (including a trigger or clock input and a set and reset input) and will output its state at its output terminal (e.g., Q terminal).

[0048] According to embodiments, a direct generation of the switch control signal via the comparator 70 and the flip-flop circuit 60 (i.e., without involvement of the microprocessor 50) substantially reduces the delay time that would occur if the switch control signal were generated via the microprocessor 50. The reference current value IREF may be generated (calculated), e.g., based on the outer control loop, and output by the microprocessor 50. By controlling the reference current IREF value, the output current through the LED load 40 can be adjusted.

[0049] In an example where the converter stage 30 comprises one or more inductors respectively arranged before and / or after the switching element, the switched current through the switching element may be equal to sum of the inductors’ current, when the switching element is closed in the converter stage 30. Therefore, controlling the switch peak current value via the peak current comparator 70 provides control of the output current as well.

[0050] As a result of the accelerated peak current mode control via the peak current comparator 70 and the flip-flop circuit 60, smaller current peak voltages across the sensing resistor Rs will lead to an accelerated earlier switch-off of the switching element and will result in smaller duty cycles, and vice versa. Moreover, the output current ILED through the LED load 40 can be controlled even at faster switching frequencies by properly adjusting the reference current value IREF generated by the microprocessor 50 on the basis of the outer feedback loop.

[0051] According to embodiments, the microprocessor 50 may be configured to control a part of the timing of the converter stage 30 (as long as its discrete time steps do not give negative effects). Additionally, the flip-flop circuit 60 (which may be a latch circuit) may be configured to take over time-critical parts of the timing of the converter stage 30, e.g., by allowing switch-off of the control terminal (e.g., gate) of the switching element when the overcurrent event is detected by the peak current comparator 70 (e.g., in an asynchronous moment).

[0052] In the example of Fig. 1, the buck circuit (configured by the upper mesh of diode, capacitor and inductor of the converter stage 30 in Fig. 1) may be operated in critical conduction mode. In this case the, the microprocessor 50 starts switching the control terminal (e.g., gate) of the switching element by generating a set pulse (S) on a set input of the flipflop circuit 60 (to start an on-time of the switching element of the converter stage 30).

[0053] At the same time, a reset output (R) of the microprocessor 50 is deactivated (e.g., set to low level) so that the flip-flop circuit 60 gets out of a reset state allowing its output to be activated (e.g., switched to a high level). The microprocessor 50 can thus force a minimum on-time of the switching element of the converter stage 30 by extending the length of the set pulse.

[0054] In the example of Fig. 1, the set input is dominant (has priority) over the reset input. When the peak current Ip is detected at the peak current comparator 70 by comparing the reference current IREF to the measured value IFB measured at the source resistor Rs, the flip-flop circuit 60 will be set immediately and switch its output (e.g., Q) and thus the control voltage of the switching element of the converter stage 30 to low voltage level.

[0055] Due to the proposed circuit configuration of Fig. 1, the time delay between the detection of the peak current Ip and the change of the state of the control signal of the switching element of the converter stage 30 is not determined by the time resolution (processing steps) of the microprocessor 50 and resulting delay of the microprocessor 50.

[0056] The output G of the flip-flop circuit 60 may also be used to inform the microprocessor 50 about the detection of the current peak Ip via a related input (IP UC) at or parameter of the microprocessor circuit 50, which may thus stop an internal on-timer in response to the signaled event that the peak current has been reached.

[0057] The on-timer may serve to determine and set a maximum on-time of the switching element of the converter stage 30 by controlling (activating) the reset output of the microprocessor 50 when the peak current event has been missed occasionally.

[0058] Moreover, the microprocessor 50 may be configured to step over from the on- timer to an off-timer which counts a time during which the microprocessor 50 waits until the current through the inductor of the converter stage 30 is reduced to zero. According to the example of Fig. 1, this can be achieved by sensing / detecting the voltage at the drain terminal of the switching element of the converter stage 30 via an input DRN DET of the microprocessor 50. Detection of a predetermined drain voltage (that reflects a zero inductor current) at the input DRN DET may then result in a control of the flip-flip circuit 60 to switch the output G of the flip-flop circuit 60 to a high voltage state again, to start a new switching cycle. The sensing signal of the drain voltage may be supplied via an RC lowpass filter to prevent to prevent high-frequency noise from reaching the input DRN DET.

[0059] As already mentioned above, in the example of Fig. 1, the slow current control loop is provided by the microprocessor 50 by sampling the output current ILED through the LED load 40 and adjusting the reference current IREF to obtain a desired output current ILED. In an example, the reference current value IREF may be obtained as the output value of a comparison (e.g., via another comparator implemented by or integrated in the microprocessor 50) of the output current ILED of the outer loop control with a predetermined reference current. Thus, when the output current at the LED load 40 increases, the reference current value IREF decreases leading to an earlier switch-off of the switching element and smaller duty cycles so that the output voltage decreases again, and vice versa. Alternatively or additionally, the reference current value IREF may be generated by a separate source e.g. based on a manual adjustment or other criteria.

[0060] In an alternative embodiment, slow current control may also be implemented in an analogue way by providing a separate error amplifier for setting / resetting the flip-flop circuit 60 and configuring the microprocessor 50 to define a setpoint for the output current ILED. More specifically, the measured output signal (e.g., output currents ILED) may be fed to an error amplifier with feedback compensation. The measured output signal is then compared by the error amplifier with the reference output value (i.e., the setpoint generated by the microprocessor 50) and the error amplifier outputs the needed reference current value IREF (supplied to the peak current comparator 70) to obtain a desired average output signal.

[0061] A benefit of configuring the microprocessor 50 to provide control over set and reset of the flip-flop circuit 60 is that it can have full control over the time periods or cases where the peak detection process / circuits should not be sensitive for its inputs (i.e., blanking). Thereby, unwanted detection signals (which may occur when the converter stage 30 is operated in a noisy environment) can be masked and malfunctions can be prevented.

[0062] The feedback of the outer control loop via the feedback current ILED may also be used for overvoltage protection. With the proposed control strategy, the amount of current flowing through the LED load 40 naturally determines the output voltage and may therefore prevent overvoltage as well.

[0063] In addition, to prevent huge spikes in the current waveform while sensing the switch current, a simple lowpass filter (e.g., RC filter) may be used (e.g., connected into the sensing path between the sensing resistor Rs and the peak current comparator 70).

[0064] Thus, according to embodiments, time discrete timers and event processing inside the microprocessor 50 can be used in combination with the external flip-flop circuit 60 to increase resolution and decrease event response time of the LED driver.

[0065] In embodiments, the microprocessor 50 may be configured (e.g., by sensing / controlling the flip-flop circuit 60) to determine one or more of a maximum on-time of the switching element (e.g., by a time-out condition of a timer), a minimum on-time of the switching element (e.g., by a length of a “start pulse”), a switch-on moment (e.g., by the start of a timer), or a step-over to the next timer state (e.g., by sensing an output (e.g., Q) of the flip-flop circuit 60).

[0066] In embodiments, the external flip-flop circuit 60 may be configured to achieve one or more of a minimum possible response time (e.g., clock response) from an over-current event to the responsive switching moment (e.g., set the flip-flop output to a low state in response to an over-current event signaled (e.g., by the peak current comparator 70) to the trigger input (e.g., clock input) of the flip-flop circuit 60), a fast (time-indiscrete) switch-off moment based on a detected overcurrent event, or an event masking (e.g., by pulling a reset input to a low state).

[0067] Fig. 2 shows schematically an exemplary circuit diagram of a luminaire driver with accelerating D-type flip-flop circuit and microprocessor (i.e., control circuit (CC)) 50 according to a first embodiment.

[0068] The implementation of Fig. 2 is based on delay or data flip-flop (D-type flipflop (D-FF)) 60 that comprises a clock input Clk, a negated set input S (i.e., a low input state (0) leads to a high output state (1)), a negated reset input R (i.e., a low input state (0) leads to a low output state (0)), a data input D, an output Q and a negated output Q. The pulse-shaped output signal at the output Q is supplied as switch control signal G to the control terminal (e.g., gate) of the switching element (e.g., MOSFET) of the converter stage (e.g., converter stage 30 of Fig. 1). Optionally, as shown as a dashed arrow in Fig. 2, the output signal of the D flip-flop 60 may also be fed back to the microprocessor 50 as a signal that indicates that a peak current event has taken place. This may be used to synchronize the peripheral of the microprocessor 50 and let the timers step over to the next timer state.

[0069] Thus, the D flip-flop 60 is used to obtain an accelerated (processorindependent) output triggered in synchronism with a clock signal directly (instantaneously) derived from a peak current detection event. E.g., when the clock input of the D flip-flop 60 rises from 0 to 1, the value remembered by the flip-flop (e.g., value at data input D) becomes the value at the output Q at that instant. Thereby, a low response time of the converter stage to a detected peak current situation can be achieved.

[0070] In the example of Fig. 2, the data input D of the D flip-flop 60 is connected to ground or another reference potential, which corresponds to a continuous low input state.

[0071] Similar to Fig. 1, a peak current comparator 70 is used to compare the feedback current value IFB measured at the switching element (e.g., MOSFET) of the converter stage with a current refence value IRF generated (e.g., based on the outer loop control function of the driver) and output from the microprocessor 50. A peak current detection signal Ip at the output of the peak current comparator 70 is directly supplied to the clock input Clk of the D flip-flop 60. The clock input Clk is edge sensitive. That is, when it detects an edge of a signal at the clock input Clk, the state (low) of the D input is clocked to the Q output and the control terminal (e.g., gate) of the switching element (e.g., MOSFET) of the converter (e.g., converter stage 30 of Fig. 1) is turned off. The edge is generated by the peak current comparator 70. The reference current IREF applied by the microprocessor 50 to the peak current comparator 70 may be generated with a resolution needed to obtain enough granularity of peak current levels.

[0072] Additionally, in the embodiment, a first control signal UGS may be output from the microprocessor 50 and supplied to the negated set input S of the D flip-flop 60. The input of the negated set input S is pulled up to a DC voltage by a resistor R3 so that the set input of the D flip-flop is not activated as long as the first control signal UGS is not active. The first control signal UGS corresponds to a start pulse used to directly set the flip-flop output Q to a high state in an asynchronous manner (i.e., irrespective of the clock input). Thereby, the switching element of the converter stage can be switched on asynchronously via the first control signal UGS. The pulse duration of the first control signal UGS defines a minimum switch-on time of the switching element of the converter stage, as a switch-off via the clock input Clk is only possible when the set input is not activated and as the set input is dominant (has priority) over the reset input.

[0073] Furthermore, a second control signal UCG may be output from the microprocessor 50 and supplied to the negated reset input R of the D flip-flop 60 via a resistor R1. The input of the negated reset input R is pulled down to ground by a resistor R2 so that the reset input of the D flip-flop 60 is continuously activated when the second control signal UCG is not active. Thus, the second control signal UCG determines when the D flipflop 60 is not reset and the control terminal (e.g., gate) of the switching element of the converter stage can be switched on via the output Q of the D flip-flop 60. Thus, the pulse duration of the second control signal UCG determines a maximum switch-on time (window) of the switching element of the converter stage.

[0074] An external transistor switch (e.g., MOSFET) Ml serves to prevent that the control terminal (e.g., gate) of the switching element of the converter stage stays unwanted in the on-state. It will cover the situation that the start pulse (first control signal UGS) is "blocking" the sensitivity for the edge at the clock input Clk. This may result when an event edge at the output of the peak current comparator 70 is missed. Although the “start pulse” of the first control signal UGS is very short, it may still block an early peak current detection signal Ip so that the switch-on duration corresponds to the maximum switch-on duration programmed in the microprocessor 50. The transistor switch Ml is connected to forcedly activate a reset (by pulling the reset input of the D flip-flop 60 to ground) when the peak current detection signal Ip at the output of the peak current comparator 70 is activated (e.g., high state). As a result, the switch-on time of the switching element of the converter stage is shortened.

[0075] Fig. 3 shows schematically an exemplary circuit diagram of an LED driver with accelerating SR-type flip-flop circuit 60 according to a second embodiment.

[0076] The second embodiment is similar to the first embodiment of Fig. 2 but simplified by using a non-clocked SR flip-flop circuit (SR latch) 60 instead of a clocked D- flip-flop circuit. Thus, a clock input is no longer provided, and the peak current Ip is only processed based on a level (i.e., no event-based trigger of the flip-flop circuit 60).

[0077] The SR flip-flop circuit 60 comprises a set input (S), a reset input (R) and an output (Q) at which the control signal G for the switching element of the converter stage 30 of Fig. 1 is generated. The switching element of the converter stage 30 can be controlled by the microprocessor (CC) 50 e.g. by generating a short start pulse at the UGS output and supplying it to the set input of the SR flip-flop circuit 60 to set the SR flip-flop circuit 60 (activate the output). Thus, the pulse time of the output signal at the UGS output determines the minimum on-time of the switching element of the converter stage 30.

[0078] At the same time, the microprocessor 50 will be configured to switch its UCG output to a low state to prevent the SR flip-flop circuit 60 from being switched into the reset state (which will end an initial blanking time and enable a reaction to a peak current event detected by the peak current converter 70).

[0079] Then, when the peak current Ip is detected by the peak current comparator 70, the reset input of the SR flip-flop circuit 60 will be pulled high via a decoupling diode D and the output of the SR flip-flop circuit 60 will be pulled low (control signal G will switch off the switching element of the converter stage 30).

[0080] Otherwise, when no peak current event is detected for whatever reason, the microprocessor 50 may be configured to pull the output of the SR flip-flop circuit 60 to the low state by setting its UCG output to a high state and thereby resetting the SR flip-flop circuit 60 via a voltage divider R1 and R2, while the reset input is otherwise pulled down via the resistor R2.

[0081] Thus, according to the above embodiments, resolution and event response time of a standard low-cost microprocessor-controlled converter can be increased by using an external flip-flop, wherein the external flip-flop is used for fast signal processing (e.g., inner loop control), wherein the microprocessor is used for slow signal processing (e.g., outer loop control), and wherein the flip-flop receives the peak current of the converter for the clock signal and provides at its output a drive / control signal for the switching element of the converter.

[0082] To summarize, a processor-controlled converter circuit has been described, in which an external flip-flop circuit is used for increasing resolution and event response time of a standard low-cost processor-controlled converter.

[0083] While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive. The invention is not limited to the disclosed embodiments concerning solid-state luminaires (e.g., LED luminaires). The proposed processor-controlled converter circuit can be applied in connection with any type of load.

[0084] Furthermore, the driver circuit of the above embodiments with at least one of the converter stage 20, the microprocessor 50, the flip-flop circuit 60 and the comparator 70 may be integrated in a circuit board or module of the LED load 40 or another load.

[0085] Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure and the appended claims. In the claims, the word “comprising” does not exclude other elements or steps, and the indefinite article “a” or “an” does not exclude a plurality. A single processor or other unit may fulfil the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. The foregoing description details certain embodiments of the invention. It will be appreciated, however, that no matter how detailed the foregoing appears in the text, the invention may be practiced in many ways, and is therefore not limited to the embodiments disclosed. It should be noted that the use of particular terminology when describing certain features or aspects of the invention should not be taken to imply that the terminology is being re-defined herein to be restricted to include any specific characteristics of the features or aspects of the invention with which that terminology is associated.

[0086] A single unit or device may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

CLAIMS:

1. A control circuit for controlling a driver of a load (40), the control circuit comprising: a comparator (70) for comparing a peak current reference value (IREF) with a value (IFB) of a sensed switching current of a converter switching element; a flip-flop circuit (60) configured to be triggered by an output signal (Ip) of the comparator (70), wherein an output signal of the flip-flop circuit (60) is used to control a switching state of the converter switching element; and a microprocessor (50) configured to control generation of the peak current reference value (IREF) based on a comparison of an output reference value with a sensed value (IFB) of the output signal at the load (40), wherein the microprocessor (50) comprises an internal on-timer configured to control the flip-flop circuit (60) to determine one or more of a maximum on-time of the converter switching element, a minimum on-time of the converter switching element, and a switch-on moment of the converter switching element, wherein the microprocessor (50) is configured to apply to the flip-flop circuit (60) a first control signal (UGS) as a start pulse for setting the flip-flop circuit (60) to an active state, and to apply a second control signal (UCG) to a reset input of the flip-flop circuit (60) to control a reset state of the flip-flop circuit (60).

2. The control circuit according to claim 1, wherein the switching current through the converter switching element is sensed by a sensing resistor (Rs) connected in series to the converter switching element, and wherein a voltage value across the sensing resistor (RS) is fed back to the comparator (70).

3. The control circuit according to claim 1 or 2, wherein the output signal (Ip) of the comparator (70) is supplied to a trigger input, particularly a clock input, of the flip-flop circuit (60), particularly a D-type flip-flop, and wherein the output signal of the flip-flop circuit (60) is applied as a switch control signal (G) to a control terminal of the converter switching element.

4. The control circuit according to any one of the preceding claims, wherein the microprocessor (50) is configured to generate and supply the output reference value to an error amplifier which compares the sensed value (IFB) of the output signal with the output reference value and generates the load peak current reference value (IREF) to adjust the output signal at the load (40).

5. The control circuit according to claim 1, further comprising a transistor switch (Ml) controlled by the output signal (Ip) of the comparator (70) and connected between the reset input of the flip-flop circuit (60) and a reference potential to forcedly activate an asynchronous reset of the flip-flop circuit (60) in response to the output signal (Ip) of the comparator (70).

6. The control circuit according to any one of the preceding claims, wherein the output signal of the flip-flop circuit (60) is fed back to the microprocessor (50) to indicate a peak current event.

7. The control circuit according to any one of the preceding claims, wherein a data input (D) of the flip-flop circuit (60) is connected to a fixed reference potential and the output signal (Ip) of the comparator (70) is directly applied to an edge-sensitive clock input (Clk) of the flip-flop circuit (60).

8. The control circuit according to any one of claims 1 to 6, wherein the flip-flop circuit (60) is an SR flip-flop circuit and the output signal (Ip) of the comparator (70) is directly applied to a reset input of the flip-flop circuit (60).

9. A driver comprising the control circuit of any one of the preceding claims.

10. A luminaire (40) comprising the driver of claim 9.

11. A method of controlling a driver of a load (40), the method comprising: comparing a peak current reference value (IREF) with a value (IFB) of a sensed switching current of a converter switching element; triggering a flip-flop circuit (60) by an output of the comparison step;using an output signal of the flip-flop circuit (60) to control a switching state of the converter switching element; and configuring a microprocessor (50) to control generation of the peak current reference value (IREF) based on a comparison of an output reference value with a sensed value (ILED) of the output signal at the load (40).

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