Bus transaction control device, bus transaction control method, and bus transaction control program

Abstract

A bus transaction control device (10) controls, in accordance with an interrupt from a periodic timer (100), access by a plurality of bus masters (120) that start periodic processing following access to a device (200) connected to a bus (150). A priority setting unit (130) sets a priority for access from each of the plurality of bus masters (120) to the device (200) in accordance with a value on the periodic timer (100). When the plurality of bus masters (120) compete to gain access, an arbitration unit (140) performs arbitration on the basis of the priorities set by the priority setting unit (130).

Description

BUS TRANSACTION CONTROL DEVICE, BUS TRANSACTION CONTROL METHOD, AND BUS TRANSACTION CONTROL PROGRAM

[0001] The present disclosure relates to a technique for controlling the priority of bus transactions.

[0002] When access from multiple bus masters conflicts, control is performed based on priority. Patent Document 1 describes monitoring the capacity of a storage unit and increasing the priority of a local bus master when free space is low. Other technologies determine priority based on past performance, such as measurement results or calculation results, or the access destination.

[0003] JP 2014-211842 A

[0004] FA systems incorporate FA controllers that control the movement of equipment or machinery according to sequences or conditions defined in a program. FA stands for Factory Automation. FA controllers are characterized by the fact that the frequency of bus access varies significantly during periodic processing. In devices with such characteristics, conventional priority setting methods make it difficult to keep up with the changing frequency of bus accesses in managing bus priority rights. The present disclosure aims to enable appropriate access control when the frequency of bus access varies significantly during periodic processing.

[0005] The bus transaction control device according to the present disclosure is a bus transaction control device that controls accesses of multiple bus masters that start periodic processing involving access to devices connected to a bus in response to an interrupt from a periodic timer, and includes: a priority setting unit that sets a priority for accesses from each of the multiple bus masters to the device according to the value of the periodic timer; and an arbitration unit that performs arbitration based on the priority set by the priority setting unit when accesses from the multiple bus masters conflict.

[0006] In the present disclosure, priority is set according to the value of the periodic timer, which allows appropriate access control when the frequency of access to the bus changes significantly during periodic processing.

[0007] FIG. 1 is a configuration diagram of a bus transaction control device 10 according to a first embodiment. FIG. 2 is a flowchart showing the processing flow of a priority setting unit 130 according to the first embodiment. FIG. 3 is a diagram showing a specific example of priority transition according to the first embodiment. FIG. 4 is a configuration diagram of a bus transaction control device 10 according to a second embodiment. FIG. 5 is a flowchart showing the processing flow of a priority setting unit 130 according to the second embodiment. FIG. 6 is a diagram showing a specific example of priority transition according to the second embodiment. FIG. 7 is a configuration diagram of a bus transaction control device 10 according to a third embodiment. FIG. 8 is a flowchart showing the processing flow of a priority setting unit 130 according to the third embodiment. FIG. 9 is a diagram showing a specific example of priority transition according to the third embodiment.

[0008] First Embodiment *** Description of Configuration *** The configuration of a bus transaction control device 10 according to the first embodiment will be described with reference to Figure 1. Here, the bus transaction control device 10 is an FA controller. The bus transaction control device 10 includes a periodic timer 100, a CPU 110, multiple bus masters 120, a priority setting unit 130, an arbitration unit 140, a bus 150, and multiple devices 200. In Figure 1, the multiple devices 200 include a main memory 201, a bus slave 202, and a bus slave 203.

[0009] The periodic timer 100 is a timer for performing periodic processing. The periodic timer 100 outputs a periodic interrupt 31, which is the starting point of the periodic processing, to the CPU 110, each bus master 120, and the priority setting unit 130. The periodic timer 100 outputs the current timer value 32 to the priority setting unit 130 as needed.

[0010] The CPU 110 has a read channel 111 for reading data etc. from the device 200, and a write channel 112 for writing data etc. to the device 200. The read channel 111 outputs a read priority 1a to the bus 150, and is connected to the bus 150 by a read bus signal 2a. The read priority 1a is the priority for reading data etc. by the CPU 110. The read bus signal 2a is a signal for the CPU 110 to process a read request. The write channel 112 outputs a write priority 3a to the bus 150, and is connected to the bus 150 by a write bus signal 4a. The write priority 3a is the priority for writing data etc. by the CPU 110. The write bus signal 4a is a signal for the CPU 110 to process a write request.

[0011] Each bus master 120 is a circuit that starts periodic processing involving access to a device 200 connected to the bus 150 in response to a periodic interrupt 31 from the periodic timer 100. Like the CPU 110, each bus master 120 has a read channel 121 for reading data, etc. from the device 200 and a write channel 122 for writing data, etc. to the device 200. The read channel 121 of each bus master 120 is connected to the bus 150 by a read bus signal 2b. The read bus signal 2b is a signal used by the bus master 120 to process a read request. The write channel 122 of each bus master 120 is connected to the bus 150 by a write bus signal 4b. The write bus signal 4b is a signal used by the bus master 120 to process a write request.

[0012] The priority setting unit 130 is a circuit that sets priorities for accesses from each of the multiple bus masters 120 to the device 200 in accordance with the value of the periodic timer 100, on behalf of each of the multiple bus masters 120. The priority setting unit 130 includes multiple register sets 131 corresponding to each of the multiple bus masters 120, and a priority output register 132. Each register set 131 has an enable register 133, a range lower limit register 134, a range upper limit register 135, and a priority register 136. The enable register 133 is set to enabled or disabled. The range lower limit register 134 is set to the lower limit of a value range. The range upper limit register 135 is set to the upper limit of a value range. The priority register 136 is set to a specified priority value. The priority output register 132 outputs the priorities set by each register set 131 to the bus 150 as a read priority 1b and a write priority 3b. The read priority 1b is the priority for reading data, etc., by the bus master 120. The write priority 3b is the priority of the bus master 120 writing data or the like.

[0013] The arbitration unit 140 is a circuit that arbitrates accesses from multiple bus masters 120 based on the priorities set by the priority setting unit 130 when the accesses conflict with each other. The arbitration unit 140 arbitrates accesses from the CPU 110 and multiple bus masters 120 by dividing them into read requests and write requests based on read priorities 1a and 1b and write priorities 3a and 3b.

[0014] Each device 200 has a read channel 211 for processing read requests and a write channel 212 for processing write requests. The read channel 211 of each device 200 receives a read priority of 5 and is connected to the bus 150 by a read bus signal 6. The write channel 212 of each device 200 receives a write priority of 7 and is connected to the bus 150 by a write bus signal 8.

[0015] ***Description of Operation*** The operation of the bus transaction control device 10 according to the first embodiment will be described with reference to Figures 2 and 3. The operating procedure of the bus transaction control device 10 according to the first embodiment corresponds to the bus transaction control method according to the first embodiment. Furthermore, the program that realizes the operation of the bus transaction control device 10 according to the first embodiment corresponds to the bus transaction control program according to the first embodiment.

[0016] The flow of processing by the priority setting unit 130 according to the first embodiment will be described with reference to Fig. 2. The priority setting unit 130 performs the processing shown in Fig. 2 with each register set 131 as the target register set 131.

[0017] (Step S101: Validity Determination Process) The priority setting unit 130 determines whether the enable register 133 included in the target register set 131 is valid. If the enable register 133 is valid, the priority setting unit 130 proceeds to step S102. On the other hand, if the enable register 133 is invalid, the priority setting unit 130 ends the process for the target register set 131.

[0018] (Step S102: Lower Limit Determination Process) The priority setting unit 130 determines whether the current value 32 of the period timer 100 is equal to or greater than the value set in the range lower limit register 134 included in the target register set 131. If the current value 32 is equal to or greater than the value set in the range lower limit register 134, the priority setting unit 130 proceeds to step S103. On the other hand, if the current value 32 is less than the value set in the range lower limit register 134, the priority setting unit 130 ends the process for the target register set 131.

[0019] (Step S103: Upper Limit Determination Process) The priority setting unit 130 determines whether the current value 32 of the period timer 100 is less than the value set in the range upper limit register 135 included in the target register set 131. If the current value 32 is less than the value set in the range upper limit register 135, the priority setting unit 130 proceeds to step S104. On the other hand, if the current value 32 is equal to or greater than the value set in the range upper limit register 135, the priority setting unit 130 ends the process for the target register set 131.

[0020] (Step S104: Priority Setting Process) The priority setting unit 130 sets the priority set in the priority register 136 in the priority output register 132. Then, the priority output register 132 outputs the set priorities to the bus 150 as read priority 1b and write priority 3b. As a result, read priority 1b and write priority 3b that give priority to the bus master 120 corresponding to the target register set 131 are set.

[0021] A specific example of priority transition according to the first embodiment will be described with reference to FIG. 3. As a prerequisite for FIG. 3, the period of the period timer 100 is assumed to be t3. The enable registers 133 of the register sets 131a to 131c are set to enabled. The other registers are set as follows: Register set 131a: Priority register 136 = p1, range lower limit register 134 = 0, range upper limit register 135 = t1. Register set 131b: Priority register 136 = p2, range lower limit register 134 = t1, range upper limit register 135 = t2. Register set 131c: Priority register 136 = p3, range lower limit register 134 = t2, range upper limit register 135 = t3. Furthermore, 0 < t1 < t2 < t3.

[0022] When the value t, which is the current value 32 of the periodic timer 100, is 0≦t<t1, p1 is set in the priority output register 132 in accordance with register set 131a. When the value t, which is the current value 32 of the periodic timer 100, is t1≦t<t2, p2 is set in the priority output register 132 in accordance with register set 131b. When the value t, which is the current value 32 of the periodic timer 100, is t2≦t<t3, p3 is set in the priority output register 132 in accordance with register set 131c. When the value t, which is the current value 32 of the periodic timer 100, becomes 0 in accordance with the period, when it reaches t3. In other words, t3=0. Therefore, the same operation is repeated thereafter.

[0023] As described above, arbitration is performed by the arbitration unit 140 according to the read priority 1b and write priority 3b set by the priority setting unit 130. The arbitration unit 140 gives priority to granting access rights to the bus master 120 for which the corresponding priorities are set. For example, if p2 is set for the read priority 1b and write priority 3b, priority is given to granting access rights to the bus master 120 corresponding to the register set 131b.

[0024] ***Effects of First Embodiment*** As described above, bus transaction control device 10 according to the first embodiment sets priorities according to the value of periodic timer 100. This makes it possible to perform appropriate access control when the frequency of access to bus 150 changes significantly during periodic processing.

[0025] ***Other Configurations*** <Variation 1> In the first embodiment, the priority setting unit 130 and the arbitration unit 140 are realized by hardware. However, the priority setting unit 130 and the arbitration unit 140 may be realized by software. In this case, the priority setting unit 130 and the arbitration unit 140 are realized by the CPU 110 reading a program that realizes the functions of the priority setting unit 130 and the arbitration unit 140. Furthermore, one of the priority setting unit 130 and the arbitration unit 140 may be realized by hardware, and the other may be realized by software.

[0026] Embodiment 2. Embodiment 2 differs from embodiment 1 in that a read priority 1b and a write priority 3b are set separately. In embodiment 2, this difference will be explained, and explanation of the same points will be omitted.

[0027] ***Description of Configuration*** The configuration of a bus transaction control device 10 according to the second embodiment will be described with reference to Figure 4. The bus transaction control device 10 differs from the bus transaction control device 10 shown in Figure 1 in the following respects. The priority setting unit 130 includes multiple register sets 131 provided corresponding to the read channels and write channels for each of the multiple bus masters 120. Each register set 131 includes a channel designation register 137 in which the read channel or write channel is set. The priority setting unit 130 includes a read output register 138 and a write output register 139 instead of the priority output register 132.

[0028] ***Description of Operation*** The operation of the bus transaction control device 10 according to the second embodiment will be described with reference to FIGS.

[0029] The processing flow of the priority setting unit 130 according to the second embodiment will be described with reference to Fig. 5. The priority setting unit 130 performs the processing shown in Fig. 5 with each register set 131 as the target register set 131. The processing from step S201 to step S203 is the same as the processing from step S101 to step S103 in Fig. 2.

[0030] (Step S204: Priority Setting Process) The priority setting unit 130 determines whether a read channel or a write channel is set in the channel specification register 137 included in the target register set 131. This determines whether the target register set 131 corresponds to a read channel or a write channel. If a read channel is set in the channel specification register 137, the priority setting unit 130 sets the priority set in the priority register 136 in the read output register 138. The read output register 138 then outputs the set priority to the bus 150 as read priority 1b. This sets read priority 1b, which prioritizes the read request of the bus master 120 corresponding to the target register set 131. On the other hand, if a write channel is set in the channel specification register 137, the priority setting unit 130 sets the priority set in the priority register 136 in the write output register 139. The write output register 139 then outputs the set priority to the bus 150 as write priority 3b. As a result, a write priority 3b is set that prioritizes the write request of the bus master 120 corresponding to the target register set 131.

[0031] A specific example of priority transition according to the first embodiment will be described with reference to FIG. 6. As a prerequisite for FIG. 6, the period of the period timer 100 is set to t5. The enable registers 133 of the register sets 131a to 131f are set to enabled. The other registers are set as follows: Register set 131a: Priority register 136 = p1, range lower limit register 134 = 0, range upper limit register 135 = t1, channel designation register 137 = read channel. Register set 131b: Priority register 136 = p2, range lower limit register 134 = t1, range upper limit register 135 = t3, channel designation register 137 = read channel. Register set 131c: Priority register 136 = p3, range lower limit register 134 = t3, range upper limit register 135 = t5, channel designation register 137 = read channel. Register set 131d: priority register 136 = p4, range lower limit register 134 = 0, range upper limit register 135 = t2, channel designation register 137 = write channel. Register set 131e: priority register 136 = p5, range lower limit register 134 = t2, range upper limit register 135 = t4, channel designation register 137 = write channel. Register set 131f: priority register 136 = p6, range lower limit register 134 = t4, range upper limit register 135 = t5, channel designation register 137 = write channel. Also, 0 < t1 < t2 < t3 < t4 < t5.

[0032] When the value t, which is the current value 32 of periodic timer 100, is 0≦t<t1, p1 is set in read output register 138 in accordance with register set 131a. When the value t, which is the current value 32 of periodic timer 100, is t1≦t<t3, p2 is set in read output register 138 in accordance with register set 131b. When the value t, which is the current value 32 of periodic timer 100, is t3≦t<t5, p3 is set in read output register 138 in accordance with register set 131c. When the value t, which is the current value 32 of periodic timer 100, is 0≦t<t2, p4 is set in write output register 139 in accordance with register set 131d. When the value t, which is the current value 32 of periodic timer 100, is t2≦t<t4, p5 is set in write output register 139 in accordance with register set 131e. When the value t, which is the current value 32 of the periodic timer 100, is in the range t4≦t<t5, p6 is set in the write output register 139 according to the register set 131f. When the value t, which is the current value 32 of the periodic timer 100, reaches t5, it becomes 0 according to the period. In other words, t5=0. Therefore, the same operation is repeated thereafter.

[0033] As described above, arbitration is performed by the arbitration unit 140 according to the read priority 1b and write priority 3b set by the priority setting unit 130. The arbitration unit 140 gives priority to the bus master 120 to which the corresponding read priority 1b is set and grants access rights to the read request. The arbitration unit 140 also gives priority to the bus master 120 to which the corresponding write priority 3b is set and grants access rights to the write request.

[0034] ***Effects of Second Embodiment*** As described above, bus transaction control device 10 according to the second embodiment sets read priority 1 and write priority 3 separately according to the value of period timer 100. There are cases where the read and write latencies of device 200 differ significantly, or the number of read and write accesses differ significantly. Even in these cases, it is possible to set optimal priorities according to the operation of bus master 120 that the system designer envisioned during system design.

[0035] Embodiment 3. Embodiment 3 differs from embodiments 1 and 2 in that the priority value is changed according to the value of the periodic timer. In embodiment 3, this difference will be explained, and explanation of the same points will be omitted. In embodiment 3, a case where a function is added to embodiment 1 will be explained. However, it is also possible to add a function to embodiment 2.

[0036] ***Description of Configuration*** The configuration of a bus transaction control device 10 according to the third embodiment will be described with reference to FIG. 7. The bus transaction control device 10 differs from the bus transaction control device 10 shown in FIG. 1 in the following respects. Each register set 131 includes a change method register 160. The change method register 160 registers a change method indicating how to change the priority value according to the value of the period timer 100. The change method register 160 includes a mode register 161, a period register 162, an increment / decrement value register 163, a lower limit value register 164, and an upper limit value register 165. The mode register 161 is set to either fixed or variable. The period register 162 is set to the interval for changing the value. The increment / decrement value register 163 is set to a positive or negative value as the increment / decrement value. The lower limit value register 164 is set to the lower limit value of the priority. The upper limit value register 165 is set to the upper limit value of the priority.

[0037] ***Description of Operation*** The operation of the bus transaction control device 10 according to the third embodiment will be described with reference to FIGS.

[0038] The processing flow of the priority setting unit 130 according to the third embodiment will be described with reference to Fig. 8. The priority setting unit 130 performs the processing shown in Fig. 8 with each register set 131 as the target register set 131. The processing from step S301 to step S303 is the same as the processing from step S101 to step S103 in Fig. 2. The processing from step S305 is the same as the processing from step S104 in Fig. 2.

[0039] (Step S304: Mode Determination Process) The priority setting unit 130 determines whether the mode register 161 included in the target register set 131 is set to fixed or variable. If the mode register 161 is set to fixed, the priority setting unit 130 proceeds to step S305. On the other hand, if the mode register 161 is set to variable, the priority setting unit 130 proceeds to step S306.

[0040] (Step S306: Temporary Priority Setting Process) As in step S305, the priority setting unit 130 sets the priority set in the priority register 136 in the priority output register 132. Then, the priority output register 132 outputs the set priorities to the bus 150 as read priority 1b and write priority 3b. As a result, read priority 1b and write priority 3b that give priority to the bus master 120 corresponding to the target register set 131 are set.

[0041] (Step S307: Period Determination Process) The priority setting unit 130 determines whether the value of the period timer 100 has elapsed for the period set in the period register 162. If the value of the period timer 100 has elapsed for the period set in the period register 162, the priority setting unit 130 proceeds to step S308. In other words, after the process proceeds to step S307, the priority setting unit 130 waits until the value of the period timer 100 has elapsed for the period set in the period register 162.

[0042] (Step S308: Priority increase / decrease process) The priority setting unit 130 adds the increase / decrease value set in the increase / decrease value register 163 to the current priority. A positive or negative value is set as the increase / decrease value in the increase / decrease value register 163. Therefore, adding the increase / decrease value to the priority increases or decreases the priority value.

[0043] (Step S309: Upper limit determination process) The priority setting unit 130 determines whether the value obtained by adding the increase / decrease value to the priority in step S308 is greater than the upper limit set in the upper limit register 165. If the value obtained by the addition is equal to or less than the upper limit, the priority setting unit 130 proceeds to step S310. On the other hand, if the value obtained by the addition is greater than the upper limit, the priority setting unit 130 proceeds to step S312.

[0044] (Step S310: Lower Limit Determination Process) The priority setting unit 130 determines whether the value obtained by adding the increase / decrease value to the priority in step S308 is smaller than the lower limit set in the lower limit register 164. If the value obtained by the addition is equal to or greater than the lower limit, the priority setting unit 130 proceeds to step S311. On the other hand, if the value obtained by the addition is smaller than the lower limit, the priority setting unit 130 proceeds to step S313.

[0045] (Step S311: Result output process) The priority setting unit 130 outputs the value obtained by adding the increase / decrease value to the priority in step S308 to the priority output register 132. As a result, the value obtained by the addition is output to the bus 150 as read priority 1b and write priority 3b.

[0046] (Step S312: Upper limit value output process) The priority setting unit 130 outputs the upper limit value set in the upper limit value register 165 to the priority output register 132. As a result, the upper limit values ​​are output to the bus 150 as read priority 1b and write priority 3b.

[0047] (Step S313: Lower Limit Output Process) The priority setting unit 130 outputs the lower limit set in the lower limit register 164 to the priority output register 132. As a result, the lower limit values ​​are output to the bus 150 as read priority 1b and write priority 3b.

[0048] (Step S314: Upper Limit Determination Process) As in step S303, the priority setting unit 130 determines whether the current value 32 of the period timer 100 is less than the value set in the range upper limit register 135 included in the target register set 131. If the current value 32 is less than the value set in the range upper limit register 135, the priority setting unit 130 returns the process to step S307. On the other hand, if the current value 32 is equal to or greater than the value set in the range upper limit register 135, the priority setting unit 130 ends the process for the target register set 131.

[0049] A specific example of priority transition according to the first embodiment will be described with reference to FIG. 9 . As a prerequisite for FIG. 9 , the period of the period timer 100 is assumed to be t3. The enable registers 133 of the register sets 131a to 131c are set to enabled. The other registers are set as follows: Register set 131a: Priority register 136 = p1, range lower limit register 134 = 0, range upper limit register 135 = t1, mode register 161 = fixed. Register set 131b: Priority register 136 = p2, range lower limit register 134 = t1, range upper limit register 135 = t2, mode register 161 = variable, period register 162 = Δt, increment / decrement value register 163 = Δp, lower limit value register 164 = 0, upper limit value register 165 = p3. Register set 131c: Priority register 136 = p3, range lower limit register 134 = t2, range upper limit register 135 = t3, mode register 161 = fixed. In addition, 0<t1<t2<t3.

[0050] When the value t, which is the current value 32 of the periodic timer 100, is 0≦t<t1, p1 is set in the priority output register 132 according to the register set 131a. When the value t, which is the current value 32 of the periodic timer 100, is t1≦t<t2, p2 is first set in the priority output register 132 according to the register set 131b. Thereafter, every time Δt elapses, Δp is added to the priority output register 170. When the value t, which is the current value 32 of the periodic timer 100, is t2≦t<t3, p3 is set in the priority output register 132 according to the register set 131c. When t, which is the current value 32 of the periodic timer 100, becomes 0 according to the period at t3. In other words, t3=0. Therefore, the same operation is repeated thereafter.

[0051] As described above, arbitration is performed by the arbitration unit 140 in accordance with the read priority 1b and write priority 3b set by the priority setting unit 130. The arbitration unit 140 gives access rights preferentially to the bus master 120 for which the corresponding priority is set. In particular, when the mode register 161 is set to variable, the priority value is changed according to the value of the period timer 100. Therefore, the arbitration unit 140 can control which bus master 120 is given access rights preferentially based on the priority value. For example, the priority value can be gradually increased to gradually raise the priority, making it easier to grant access rights. Conversely, the priority value can be gradually decreased to gradually lower the priority, making it harder to grant access rights.

[0052] ***Effects of Third Embodiment*** As described above, bus transaction control device 10 according to the third embodiment changes the priority value according to the value of the periodic timer. This makes it possible to set the optimal priority according to the operation of bus master 120, as envisioned by the system designer at the time of system design, with a small number of register settings.

[0053] The embodiments and modifications of the present disclosure have been described above. Some of these embodiments and modifications may be combined and implemented. Furthermore, one or more of them may be implemented partially. Note that the present disclosure is not limited to the above embodiments and modifications, and various modifications are possible as needed.

[0054] 10 bus transaction control device, 100 period timer, 110 CPU, 111 read channel, 112 write channel, 120 bus master, 121 read channel, 122 write channel, 130 priority setting unit, 131 register set, 132 priority output register, 133 enable register, 134 range lower limit register, 135 range upper limit register, 136 priority register, 137 channel designation register, 138 read output register, 139 write output register, 140 arbitration unit, 150 bus, 160 change method register, 161 mode register, 162 period register, 163 increase / decrease value register, 164 lower limit value register, 165 upper limit value register, 200 device, 201 main memory, 202 bus slave, 203 bus slave, 211 read channel, 212 write channel, 1 read priority, 2 Read bus signal, 3 Write priority, 4 Write bus signal, 5 Read priority, 6 Read bus signal, 7 Write priority, 8 Write bus signal, 31 Periodic interrupt, 32 Current value.

Claims

1. A bus transaction control device that controls accesses by multiple bus masters that start periodic processing involving access to devices connected to a bus in response to an interrupt from a periodic timer, the bus transaction control device comprising: a priority setting unit that sets a priority for accesses to the device from each of the multiple bus masters according to the value of the periodic timer; and an arbitration unit that arbitrates based on the priorities set by the priority setting unit when accesses from the multiple bus masters conflict.

2. The bus transaction control device according to claim 1, wherein the priority setting unit identifies a register set provided corresponding to each of the plurality of bus masters, from among the register sets in which a value range is registered, the register set in which the value of the periodic timer falls within the value range, and sets a priority that gives priority to the bus master corresponding to the identified register set.

3. A bus transaction control device as described in claim 1, wherein the priority setting unit sets a read priority, which is the priority for read requests, and a write priority, which is the priority for write requests, for accesses to the device from each of the multiple bus masters according to the value of the periodic timer, and the arbitration unit arbitrates the accesses from the multiple bus masters by dividing them into read requests and write requests based on the read priority and the write priority.

4. The bus transaction control device according to claim 3, wherein the priority setting unit identifies a register set, which is provided for each of the plurality of bus masters in correspondence with a read channel and a write channel, from among the register sets in which a value range is registered, a register set in which the value of the periodic timer is within the value range, and if the identified register set corresponds to the read channel, sets a read priority that gives priority to the bus master corresponding to the identified register set, and if the identified register set corresponds to the write channel, sets a write priority that gives priority to the bus master corresponding to the identified register set.

5. A bus transaction control device as described in claim 2, wherein at least some of the register sets have registered therein a change method indicating how to change the priority value depending on the value of the periodic timer, and the priority setting unit changes and sets the priority value in accordance with the change method registered in the specified register set.

6. A bus transaction control device according to claim 5, wherein the change method indicates a period and an increment / decrement value, and the priority setting unit changes the priority by the value indicated by the increment / decrement value for each period indicated by the change method.

7. A bus transaction control method for controlling accesses by multiple bus masters that start periodic processing involving access to a device connected to a bus in response to an interrupt from a periodic timer, wherein a computer sets a priority for access to the device from each of the multiple bus masters according to the value of the periodic timer, and when accesses from the multiple bus masters conflict, the computer arbitrates based on the priority.

8. A bus transaction control program that controls accesses by multiple bus masters that start periodic processing involving access to devices connected to a bus in response to an interrupt from a periodic timer, the program causing a computer to function as a bus transaction control device that performs a priority setting process that sets a priority for accesses from each of the multiple bus masters to the device according to the value of the periodic timer, and an arbitration process that arbitrates based on the priorities set by the priority setting process when accesses from the multiple bus masters conflict.

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