Product-sum calculating device and integrated circuit

Abstract

A product-sum calculating device according to one embodiment of the present technology is provided with a ring buffer and a product-sum calculating unit. The ring buffer is composed of a plurality of RAMs. The product-sum calculating unit simultaneously reads two or more pieces of data from the ring buffer in such a way that the RAMs in which the pieces of data are stored do not overlap, and subjects the read data to product-sum calculation one or more times. In the product-sum calculating device, two or more pieces of data are read simultaneously from the ring buffer composed of the plurality of RAMs. At this time, reading is performed in such a way that two or more read addresses for reading do not access the same RAM. The two or more read pieces of data are subjected to product-sum calculation processing by the product-sum calculating unit. A high-quality product-sum calculation can thus be achieved.

Description

Multiply-accumulate device and integrated circuit

[0001] The present technology relates to a multiply-accumulate device and an integrated circuit.

[0002] Patent Document 1 discloses a ring buffer circuit capable of writing and reading in a FIFO (First In First Out) format. This ring buffer circuit is capable of performing ring counting across one or more use areas set at any address location in RAM (Random Access Memory). This allows for highly flexible operation.

[0003] Japanese Patent Application Publication No. 5-341957

[0004] There is a demand for a high-quality product-sum calculation device that uses such a ring buffer.

[0005] In view of the above circumstances, an object of the present technology is to provide a high-quality product-sum calculation device and an integrated circuit that makes it possible to realize such a product-sum calculation device.

[0006] In order to achieve the above object, a multiply-accumulate operation device according to one embodiment of the present technology includes a ring buffer and a multiply-accumulate operation unit. The ring buffer is configured with a plurality of RAMs. The multiply-accumulate operation unit simultaneously reads two or more pieces of data from the ring buffer so that the RAMs, which are storage destinations, do not overlap, and performs a multiply-accumulate operation on the read data one or more times.

[0007] In this multiply-and-accumulate device, two or more pieces of data are simultaneously read from a ring buffer composed of multiple RAMs. At this time, reading is performed so that two or more read addresses for reading do not access the same RAM. A multiply-and-accumulate operation is performed on the two or more pieces of read data by a multiply-and-accumulate operation unit. This makes it possible to achieve high-quality multiply-and-accumulate operations.

[0008] The product-sum operation process may include a multiplication process that generates two or more product data by multiplying each of the data by a predetermined coefficient, and an addition process that adds up the two or more product data to generate sum data.

[0009] The sum-of-products operation unit may have a sum-of-products operation circuit including two or more multipliers that perform the multiplication process and one or more adders that perform the addition process.

[0010] The multiplication process may be a process in which the product data is generated by a different multiplier for each of the data in a predetermined number of times of the product-sum operation process.

[0011] The addition process may be a process in which, when there are three or more pieces of product data in a predetermined round of product-sum calculation process, the product data that has not been added in the predetermined round is repeatedly added to one piece of product data by the adder that has not performed addition in the predetermined round.

[0012] When part or all of the data stored in the ring buffer is used as target data, the product-sum operation unit may perform the product-sum operation process only once for all of the target data throughout all rounds.

[0013] The multiply-accumulate operation unit may refer to different pieces of target data in a predetermined number of reads. In this case, if there is duplicate data among the plurality of referenced target data that is stored in the RAM, the duplicate data may be excluded from the multiply-accumulate operation performed in the predetermined number of reads.

[0014] The multiply-accumulate operation unit may refer to different pieces of target data in a predetermined number of reads. In this case, if there is data among the plurality of target data that has already been subjected to the multiply-accumulate operation in a number of times other than the predetermined number of times, the data that has already been subjected to the multiply-accumulate operation may be excluded from the target of the multiply-accumulate operation in the predetermined number of times.

[0015] The sum-of-products operation unit may perform the sum-of-products operation process on non-duplicate data among the plurality of target data that are referenced and whose storage destinations are not overlapped in the RAM in the predetermined round. In this case, the sum-of-products operation process may be performed on the duplicate data after all rounds of the sum-of-products operation process on the non-duplicate data have been completed.

[0016] When new data is provided, the ring buffer may store the new data by overwriting the oldest data stored in the ring buffer.

[0017] The ring buffer may store the new data at an address adjacent to an address at which the next newest data is stored.

[0018] The difference between the total number of addresses of each of the plurality of RAMs may be smaller than the number of the plurality of RAMs.

[0019] The product-sum calculation device may further include a coefficient RAM for storing the predetermined coefficients.

[0020] An integrated circuit according to one aspect of the present technology includes a product-sum operation circuit that receives as input two or more pieces of data that are simultaneously read out from a ring buffer configured with a plurality of RAMs so that the RAMs that are storage destinations do not overlap.

[0021] FIG. 1 is a schematic diagram showing an example of the configuration of a product-sum calculation device 1 according to an embodiment of the present technology; FIG. 2 is a conceptual diagram showing an example of the configuration of a data RAM 2; FIG. 3 is a schematic diagram showing a change state of a write address 13; FIG. 4 is a schematic diagram showing a change state of a read address 14; FIG. 5 is a schematic diagram showing a read order of target data; FIG. 6 is a conceptual diagram of a product-sum calculation process of this embodiment; FIG. 7 is a schematic diagram showing a state of address overlap; FIG. 8 is a schematic diagram showing a processing order when duplicate data exists; FIG. 9 is a schematic diagram showing the configuration of a RAM 20 according to a comparative example; FIG. 10 is a schematic diagram showing a write state in the present technology and the comparative example; FIG. 11 is a schematic diagram showing a read state in the present technology and the comparative example; FIG. 12 is a schematic diagram showing the presence or absence of address overlap; FIG. 13 is a diagram showing variations in the number of parallel RAMs;

[0022] Hereinafter, embodiments of the present technology will be described with reference to the drawings. [Product-sum Calculation Device] Fig. 1 is a schematic diagram showing an example of the configuration of a product-sum arithmetic device 1 according to an embodiment of the present technology. The product-sum arithmetic device 1 has a data RAM 2, a coefficient RAM 3, and a product-sum arithmetic circuit 4. In this embodiment, these mechanisms function as a digital filter, and product-sum arithmetic is performed on input data (signals).

[0023] The data RAM 2 is a RAM for storing data. In Fig. 1, the data RAM 2 is conceptually illustrated as one block.

[0024] 2 is a conceptual diagram showing an example of the configuration of the data RAM 2. As shown in FIG. 2, in this technology, one data RAM 2 is configured as a ring buffer 5 using three RAMs 2a to 2c. A ring buffer is a buffer area that temporarily stores data, the end and beginning of which are logically linked and used in a circular manner. The ring buffer 5 is also called a circular buffer.

[0025] RAM 2a has 1366 addresses. In other words, RAM 2a can cache (temporarily store) 1366 pieces of data by itself. RAM 2b also has 1366 addresses. RAM 2c has 1364 addresses, two fewer than RAMs 2a and 2b.

[0026] When the three RAMs 2a to 2c are logically linked, a ring buffer 5 (data RAM 2) having a total of 4096 (1366 + 1366 + 1364) addresses is formed. Therefore, the ring buffer 5 has 4096 addresses from 0 to 4095, and can cache a total of 4096 pieces of data.

[0027] In the following description, the addresses of the ring buffer 5 corresponding to RAM 2a will be addresses 0 to 1365, the addresses corresponding to RAM 2b will be addresses 1366 to 2731, and the addresses corresponding to RAM 2c will be addresses 2732 to 4095. In Figure 2, each address is shown in a separate diagram.

[0028] The end (highest numbered address) of each of RAMs 2a to 2c is continuous with the beginning (lowest numbered address) of any of the other RAMs 2a to 2c. For example, address 1365, which is the end of RAM 2a, and address 1366, which is the beginning of RAM 2b, are continuous because the difference in address numbers is 1. Also, because the addresses of the ring buffer 5 are cyclic, addresses 4095 and 0 are also included in the continuous addresses. In other words, the end of RAM 2c and the beginning of RAM 2a are continuous.

[0029] Returning to FIG. 1 , the coefficient RAM 3 is a RAM that holds coefficients used in multiplication during the sum-of-products operation. Predetermined coefficients are stored in the coefficient RAM 3 before the sum-of-products operation device 1 starts operating. The specific configuration of the coefficient RAM 3 is not limited, and for example, only one coefficient RAM 3 may be configured, or multiple RAMs may be connected together to form a ring buffer. Alternatively, the coefficient RAM 3 may be configured by configuring one ring buffer per RAM, and connecting the multiple ring buffers via shift registers.

[0030] The product-sum operation circuit 4 is a circuit configured as an integrated circuit, and is sometimes called a multiplication-addition circuit. The product-sum operation circuit 4 has three multipliers 6 (6i, 6j, 6k), two adders 7 (7a, 7b), and an accumulator 8. In this example, product-sum operation processing including multiplication processing by the multiplier 6 and addition processing by the adder 7 is performed.

[0031] The multiplier 6 is a multiplication circuit that receives one piece of data stored in the data RAM 2 (ring buffer 5) and one coefficient stored in the coefficient RAM 3, performs multiplication processing by multiplying the data by the coefficient, and outputs multiplied data. Hereinafter, the multiplied data may be referred to as product data.

[0032] The adder 7 is an addition circuit that receives two pieces of product data output from two different multipliers 6, performs an addition process to add the two pieces of product data together, and outputs added data. Hereinafter, the added data may be referred to as sum data.

[0033] The adder 7a adds the product data output from the multipliers 6i and 6j. The adder 7b adds the sum data output from the adder 7a and the product data output from the multiplier 6k. In other words, the sum data output from the adder 7b can be said to be the sum of the three product data output from the multipliers 6i, 6j, and 6k.

[0034] The accumulator 8 has an adder 9 and a flip-flop (FF) 10. The adder 9 adds the sum data output from the adder 7b and the sum data output from the flip-flop 10 to generate and output new sum data. The flip-flop 10 holds the sum data output from the adder 9. The flip-flop 10 also outputs the held sum data to the outside of the adder 9 and the product-sum calculation unit 1.

[0035] When new sum data is output from adder 7b to accumulator 8 while flip-flop 10 is holding sum data, flip-flop 10 first outputs the sum data it is holding to adder 9. Next, adder 9 adds the sum data output from adder 7b and the sum data output from flip-flop 10. As a result, new sum data is generated by adding the sum data output from adder 7b to the existing sum data.

[0036] The new sum data is output from the adder 9 to the flip-flop 10 and is held by the flip-flop 10. In this way, a plurality of sum data are repeatedly output from the adder 7b, and these plurality of sum data are accumulated in the form of being added together in the flip-flop 10.

[0037] The sum-of-products calculation circuit 4 corresponds to an embodiment of a sum-of-products calculation unit according to the present technology.

[0038] 3 is a schematic diagram showing the state of change of the write address 13. The writing of data to the ring buffer 5 will be described. The ring buffer 5 stores data so that when the newest data is stored in a certain address, the second newest data is stored in an address one number smaller than the newest data.

[0039] Furthermore, the third most recent data is stored in an address one number smaller than the address where the second most recent data is stored, and so on, with the previous (older) data being stored in an address one number smaller. Note that address 4095 is one number smaller than address 0.

[0040] If data continues to be stored according to this rule, the oldest data will be stored in an address one number higher than the address of the newest data. For example, if the newest data is stored in address 1000, the second newest data will be stored in address 999. Also, the oldest data will be stored in address 1001.

[0041] To achieve storage according to such rules, when new data is given to the ring buffer 5, the new data is stored by overwriting the oldest data stored in the ring buffer 5. The new data is also stored at an address adjacent to the address at which the next newest data is stored.

[0042] As an example, consider a situation in which the latest data is stored at address 1 and the oldest data is stored at address 2. If new data is given in this situation, the new data will overwrite the oldest data, and therefore the data stored at address 2. Specifically, when write address 13 (Write address) specifies address 2, the data at address 2 is overwritten.

[0043] Furthermore, when new data is given, the next newest data can be said to be the data stored at address 1, so it can also be said that the new data is stored at an address adjacent to the address where the next newest data is stored (an address one number apart).

[0044] After the new data is stored, the latest data will be stored at address 2. Also, since the oldest data originally stored at address 2 has been deleted by being overwritten by the latest data, the data stored at address 3 will next become the oldest data.

[0045] Even after the new data is stored, the condition that "the previous data is stored in the address with the next smaller number" is still satisfied. In other words, by writing new data in the above manner, it is possible to maintain this condition.

[0046] If new data is subsequently given, the new data overwrites the data stored at address 3. Specifically, the write address 13, which had specified address 2, is incremented by one, and address 3 is now specified. In this way, the write address is incremented by one each time new data is given, and writing is performed such that the write address 13 moves clockwise on the ring buffer 5.

[0047] 4 is a schematic diagram showing the state of change of the read address 14. In this embodiment, "reading one or more data from the ring buffer 5 and performing a product-sum operation on each of the read data" is counted as one operation, and the process is performed multiple times.

[0048] In this example, through multiple multiply-and-accumulate operations, the multiply-and-accumulate operation is performed on all of the data stored in the ring buffer 5, including the latest data (the data most recently written at the time of reading), data four data points earlier than the latest data, data eight data points earlier, ..., 4092 data points earlier. In other words, the multiply-and-accumulate operation is performed on each of a total of 1024 data points, spaced apart by four data points (thinning number 4). Hereinafter, the data that is the target of the multiply-and-accumulate operation may be referred to as target data.

[0049] On the other hand, data one, two, three, five, ..., 4095 data items past the most recent data are not the target data, and product-sum calculation processing is not performed on these data items.

[0050] For each read, three target data are simultaneously read from the ring buffer 5. Specifically, as shown in Fig. 4, three read addresses 14 (14i, 14j, 14k) (read addresses) each specify a different address, so that the three target data are simultaneously read.

[0051] 5 and 6 are schematic diagrams showing the read order of target data. The product-sum calculation unit 1 executes each read and product-sum calculation process in response to the clock signal shown in FIG. 5. As shown in FIGS. 4A and the area enclosed by the dashed lines in FIG. 5, and as shown in FIG. 6, in the first read of the product-sum calculation process, the address where the latest data is stored is specified by read address 14i. Furthermore, coefficients are read in three parallel fashion starting from b0, b342, and b648. Therefore, corresponding to each coefficient, read address 14j specifies 1368 (=342×4) pieces of past data, and read address 14k specifies 2736 (=648×4) pieces of past data.

[0052] In this example, it is assumed that the latest data is stored at address 10 (index: 10). Therefore, read address 14i specifies address 10. Read address 14j specifies address 2738 as the address of 1368 pieces of data from the past. Read address 14k specifies address 1370 as the address of 2736 pieces of data from the past. Note that in FIG. 4, read address 14i is shown at the fifth scale mark even though it specifies address 10, but this is merely to schematically indicate the position of read address 14i. The same is true for read addresses 14j and 14k, and they may be shown in this manner in subsequent figures.

[0053] That is, in the first read, a plurality of different target data including the latest data is referenced. Here, "reference" means that the read address 14 specifies an address in the ring buffer 5 before the data is actually read.

[0054] Since address 10 belongs to RAM 2a, address 2738 belongs to RAM 2c, and address 1370 belongs to RAM 2b, each of the read addresses 14i, 14j, and 14k designates a different RAM 2a, 2c, and 2b, respectively. In other words, the same RAM 2a, 2c, and 2b are not designated by multiple read addresses 14.

[0055] In the second read, as shown in Figures 4B, 5, and 6, each read address 14 is decremented by four. In Figure 4B, each read address 14 is rotated slightly counterclockwise compared to Figure 4A. As a result, read address 14i specifies address 6, which is the address of data four blocks back. Read address 14j specifies address 2734, which is the address of data 1372 blocks back. Read address 14k specifies address 1366, which is the address of data 2740 blocks back.

[0056] In this case, the read addresses 14i, 14j, and 14k each specify a different RAM 2a, 2c, or 2b, so that the same RAM 2a, 2c, or 2b is not specified by a plurality of read addresses 14.

[0057] Thereafter, each read address 14 is decremented by four for each read, and the read address 14 moves counterclockwise on the ring buffer 5, so that all 1,024 pieces of target data are read a total of 342 times.

[0058] That is, in the readout following the predetermined number of times, the next oldest target data after the target data referenced in the predetermined number of times is referenced, and this is repeated each time. For example, in the first readout, the latest data, 1368 pieces of data from the past, and 2736 pieces of data from the past are referenced, while in the second readout, the next oldest target data after the latest data, which is 4 pieces of data from the past, the next oldest target data after the 1368 pieces of data from the past, which is 1372 pieces of data from the past, and the next oldest target data after the 2736 pieces of data from the past, which is 2740 pieces of data from the past, are referenced.

[0059] As shown in Figure 6, in this example, in the third read, RAM 2a is specified by both read addresses 14i and 14k. However, since single read / write RAMs 2a to 2c are used in this embodiment, two pieces of data cannot be read from RAM 2a at the same time. In such a case, an exclusion process, which will be described later, is performed.

[0060] Furthermore, since read address 14k specifies address 14 in the 340th read, it specifies address 10 in the 341st read, and address 6 in the 342nd read. However, the data at address 10 has already been read in the first read, and the data at address 6 has been read in the second read, and both have undergone product-sum operations. Therefore, there is no need to read the data at addresses 10 and 6 again. In such cases, the exclusion process described below is also performed.

[0061] [Product-Sum Operation Processing] The product-sum operation processing by the product-sum operation circuit 4 will be described. As shown in FIG. 1, three pieces of data read from the ring buffer 5 in a given round will be referred to as di, dj, and dk. In accordance with the data read from the ring buffer 5, the corresponding coefficients bi, bj, and bk are read from the coefficient RAM 3. In this example, 1024 pieces of data are read in three parallel steps, but when 1024 is divided by 3, the remainder is carried over to 342. Therefore, in the first round of processing, as shown in FIG. 5, the coefficients b0, b342, which is 342 steps ahead, and b684, which is 342 steps ahead, are read out simultaneously.

[0062] Of these, data di and coefficient bi are input to multiplier 6i, which then performs a multiplication process to generate product data di × bi. Similarly, data dj and coefficient bj are input to multiplier 6j, which generates product data dj × bj. Data dk and coefficient bk are input to multiplier 6k, which generates product data dk × bk.

[0063] That is, in this embodiment, product data is generated by different multipliers 6i, 6j, and 6k for each of data di, dj, and dk. On the other hand, for example, when multiplication processes for data di and dj are both performed by the same multiplier 6i, this does not include the case where product data is generated by different multipliers for each of data.

[0064] Next, the product data di×bi and dj×bj are input to the adder 7a, which performs an addition process to generate the sum data di×bi+dj×bj. Then, the sum data di×bi+dj×bj and the product data dk×bk are input to the adder 7b, which generates the sum data di×bi+dj×bj+dk×bk.

[0065] That is, in this embodiment, when there are three or more pieces of product data, the product data that have not yet been added to one piece of product data are repeatedly added by an adder 7 that has not yet performed addition. For example, in this example, the product data dj×bj that have not yet been added to one piece of product data di×bi are added by an adder 7a that has not yet performed addition. Then, the product data dj×bj that have not yet been added are added by an adder 7b that has not yet performed addition.

[0066] As a result of the first product-sum operation, sum data di×bi+dj×bj+dk×bk is accumulated in the accumulator 8. Similarly, sum data is generated in each of the second to 342nd product-sum operation processes and accumulated in the accumulator 8. As a result, a total of 1024 pieces of product data are generated for each of the 1024 pieces of target data, and sum data that is the sum of all of these pieces of product data is generated.

[0067] 7 is a conceptual diagram of the sum-of-products operation according to this embodiment. In this embodiment, the read process and sum-of-products operation described above are performed 342 times each time new data is written to the ring buffer 5. This allows the sum-of-products operation to be performed on all 1048 pieces of target data.

[0068] "z" in Figure 7 －１ The block 17 marked with "" represents a logic element that outputs the data immediately prior to the input data. The triangular block represents a logic element that multiplies the input data by a coefficient bi and outputs the result, and the block marked with "+" represents a logic element that adds two input data and outputs the result.

[0069] In the following explanation, n pieces of past data are referred to as dn. When the latest data d0 is input from the left side, d0 is multiplied by a coefficient b0 in one direction (branching downwards) to become product data d0b0. In addition, "z" is added to d0 in the other direction (branching rightwards). －１ Block 17 operates four times, resulting in d4, which is four data points earlier than d0.

[0070] Similarly, for d4, in one branch (branching downward), d4 is multiplied by coefficient b1 to obtain product data d4b1. In the other branch (branching right), d8, which is four data points earlier than d4, is obtained. This process is repeated in the upper part of Figure 7.

[0071] In the lower stage, the process of adding each piece of product data is repeated. That is, d4b1 is added to the first piece of product data d0b0, ​​then d8b2 is added, and so on, and the process is repeated until the sum of all the product data, d0b0+d4b1+d8b2+...+d4084b1021+d4088b1022+d4092b1023, is finally output. The product-sum calculation device 1 of the present technology performs pipeline processing by dividing such product-sum calculations into three calculations at a time, 342 times.

[0072] In this embodiment, if the "read and multiply-and-accumulate process" is considered to be a single process, the multiply-and-accumulate device 1 continues to operate by repeating the above "process" 342 times each time one new data item is written to the ring buffer 5.

[0073] [Exclusion Processing] Fig. 8 is a schematic diagram showing the state of address overlap. As shown in Figs. 5, 6, and 8, in the third read, the read address 14i specifies address 2, and the read address 14k specifies address 1362. In other words, both the read addresses 14i and 14k specify the same RAM 2a (the shaded portion in Fig. 8).

[0074] Therefore, if the target data referenced by the three read addresses 14i, 14j, and 14k are di, dj, and dk, di and dk are duplicate data stored in RAM 2a. Hereinafter, the state in which duplicate data occurs may be referred to as address overlap. On the other hand, dj is non-duplicate data stored in RAM 2b.

[0075] Since each of the RAMs 2a to 2c is a single-read type, the duplicate data di and dk cannot be read simultaneously. In this embodiment, in such a case, the duplicate data di and dk are excluded from the target of the multiply-and-accumulate operation for that round. In other words, in the third round of processing, the multiply-and-accumulate operation is performed only on the non-duplicate data dj.

[0076] For example, the exclusion process is performed by turning off the multipliers 6i and 6k corresponding to the duplicate data di and dk. As a result, only the multiplier 6j that processes the non-duplicate data dj operates, and only the multiplication process for the non-duplicate data dj is performed. Then, the sum data dj × bk, which does not include the duplicate data di and dk but only includes the non-duplicate data dj, is accumulated in the accumulator 8.

[0077] Alternatively, the exclusion process may be performed by a method that does not involve reading out the duplicate data di and dk. That is, the duplicate data di and dk are not read out from the ring buffer 5, and only the non-duplicate data dj is read out and input to the product-sum operation circuit 4. Then, the multipliers 6i and 6k do not operate because there is no input data, and only the multiplier 6j operates. As a result, only the product-sum operation is performed on the non-duplicate data dj.

[0078] Alternatively, the exclusion process may be performed by a method that does not read out the coefficients bi and bk corresponding to the duplicated data di and dk. That is, the coefficients bi and bk are not read out from the coefficient RAM 3, and only the coefficient bj corresponding to the non-duplicate data dj is read out and input to the product-sum operation circuit 4. Then, the multipliers 6i and 6k do not operate because there are no input coefficients, and only the multiplier 6j operates. As a result, only the product-sum operation is performed on the non-duplicate data dj.

[0079] Two or more of the above methods may be used in combination. Furthermore, similar processing may be performed when three or more duplicate data items exist in a single read. The specific content of the exclusion processing is not limited.

[0080] 9 is a schematic diagram showing the processing order when duplicate data exists. The product-sum operation circuit 4 performs product-sum operation on the duplicate data after all rounds of product-sum operation on non-duplicate data have been completed. In this example, addresses 2 and 2730 are specified in the third round of operation, and the data stored at these addresses is duplicate data.

[0081] As mentioned above, these duplicate data are excluded from the third processing. Instead, the data at address 2 is processed in the 343rd processing, and the data at address 2730 is processed in the 344th processing. In other words, the product-sum operation processing for all non-duplicate data is completed in the first through 342nd processing, and then processing for duplicate data begins. In other words, the duplicate data is processed later.

[0082] By using this method, it is possible to read data from the ring buffer 5 without overlapping it with the RAMs 2a to 2c as storage destinations, and to perform product-sum operations on the read data.

[0083] Although only two duplicate data items are generated in this example, three or more duplicate data items may be generated depending on how the read address 14 is determined, etc. If there is duplicate data among these three or more duplicate data items that belong to different RAMs 2a to 2c, two or three pieces of data that belong to different RAMs 2a to 2c may be processed in one process at the stage of processing the duplicate data (the 343rd or later stage in FIG. 9).

[0084] By implementing the logic of "Are there any sets of three or more duplicate data that belong to different RAMs 2a to 2c?", such parallel processing is possible even in postponed processing. On the other hand, by processing duplicate data one by one in postponed processing, there is also the advantage that there is no need to implement such logic.

[0085] Furthermore, in this embodiment, if there is calculated data that has already undergone product-sum operation processing in an operation other than the specified operation among the multiple target data referenced in a specified operation, the product-sum operation circuit 4 excludes the calculated data from the target of product-sum operation processing in the specified operation.

[0086] In the 341st processing shown in Figure 9, data at address 10 is referenced by read address 14k, but a multiply-and-accumulate operation has already been performed on that data in the first processing. In other words, the data at address 10 is already calculated data, and if a multiply-and-accumulate operation is performed on the data at address 10 in the 341st processing, it will result in redundant processing. Therefore, the data at address 10 is excluded from the target of the multiply-and-accumulate operation in the 341st processing. Similarly, in the 342nd processing, the data at address 6 is already calculated data and is therefore excluded from the target of the multiply-and-accumulate operation.

[0087] The exclusion process may be realized by any method, such as turning off the multiplier 6 corresponding to the calculated data, not reading the calculated data, or not reading the coefficients corresponding to the calculated data.

[0088] Through the above-described "processing for excluding duplicate data," "processing for postponing duplicate data," and "processing for excluding already-operated data," the product-sum operation circuit 4 performs product-sum operation processing only once for all target data throughout all cycles. In other words, there is no case where a certain target data is not processed even once, and no case where it is processed more than once.

[0089] As described above, in the product-sum calculation device 1 according to this embodiment, two or more pieces of data are simultaneously read from the ring buffer 5, which is made up of a plurality of RAMs 2a to 2c. At this time, reading is performed so that two or more read addresses for reading do not access the same RAMs 2a to 2c. The product-sum calculation circuit 4 performs product-sum calculation processing on the two or more pieces of read data. This makes it possible to realize a high-quality product-sum calculation device 1.

[0090] From the viewpoint of calculation speed, it may be necessary to execute three multiply-and-accumulate operations in parallel. In such a case, three pieces of data must be read simultaneously from the RAM, but because each RAM is a single-read type, three RAMs must be prepared. In such a case, a configuration in which three RAMs are connected by a shift register can be considered (hereinafter, a comparative example).

[0091] 10 is a schematic diagram showing the configuration of a RAM 20 according to a comparative example. In the comparative example, data is cached by three RAMs 20 (20a, 20b, 20c). The RAMs 20a and 20b each have 1366 addresses from address 0 to address 1365. The RAM 20c has 1364 addresses from address 0 to address 1363. In other words, the three RAMs 20 can cache a total of 4096 pieces of data (1366 + 1366 + 1364), similar to the present technology.

[0092] The RAMs 20a and 20b are connected by a shift register 21a. The shift register 21a is capable of reading and holding data stored in the RAM 20a and writing the data to the RAM 20b. The RAMs 20b and 20c are connected by a shift register 21b. Similarly, the shift register 21b is capable of reading and holding data stored in the RAM 20b and writing the data to the RAM 20c.

[0093] 11A and 11B are schematic diagrams showing write states in the present technology and a comparative example. Fig. 11A illustrates a write state to the ring buffer 5 in the present technology. As described above, in the present technology, when new data is provided, the new data is written over the oldest data in the ring buffer 5. This write is performed while the write address 13 is incremented by one.

[0094] 11B illustrates the state of writing to the RAM 20 in the comparative example. In the comparative example, when new data is given, the oldest data in the RAM 20a is first held by the shift register 21a. At the same time, the new data is overwritten on the oldest data in the RAM 20a.

[0095] Next, the oldest data in RAM 20b is held by shift register 21b. At the same time, the oldest data in RAM 20b is overwritten with the data held by shift register 21a. After that, the oldest data in RAM 20c is overwritten with the data held by shift register 21b.

[0096] That is, new data is written to RAM 20a, the oldest data in RAM 20a is pushed to RAM 20b, the oldest data in RAM 20b is pushed to RAM 20c, and the oldest data in RAM 20c is deleted from RAM 20c.

[0097] Such writing is performed while the write addresses 22 (22i to 22k) present in each RAM 20 (20a to 20c) are incremented by 1. This maintains a state in which the latest data to 1365 samples of data are aligned and stored in RAM 20a, data from 1366 to 2731 samples of data are aligned and stored in RAM 20b, and data from 2732 to 4095 samples of data are aligned and stored in RAM 20c.

[0098] However, in the comparative example, each time new data is provided ("one operation" in the figure), a total of three writes to RAMs 20a to 20c are required, which consumes power. Also, a shift register 21 is required to connect RAMs 20, which increases the overall circuit area.

[0099] By using the ring buffer 5 according to the present technology, it is possible to limit writing of new data to one time, thereby reducing the power required for the write process. Furthermore, the shift register 21 connecting the RAMs 2a to 2c is no longer necessary, making it possible to reduce the number of flip-flops, for example, 24 bits x 24. Therefore, it is possible to reduce the area of ​​the sum-of-products operation circuit 4. These features enable the realization of a high-quality sum-of-products operation device 1.

[0100] 12A and 12B are schematic diagrams showing read states in the present technology and a comparative example. Fig. 12A shows the read state in the ring buffer 5 of the present technology. As described above, in the present technology, reading is performed while decrementing each of the three read addresses 14i to 14k by four.

[0101] 12B illustrates the read state in the comparative example RAM 20. In RAM 20a, reading is performed while one read address 23i is decremented by four. Similarly, in RAMs 20b and 20c, reading is performed while one read address 23j and one read address 23k are decremented by four, respectively.

[0102] In this way, in both the present technology and the comparative example, 1024 read operations are performed each time new data is provided ("one operation" in the drawing), and there is generally no difference in power consumption.

[0103] In addition, in this technology, the product-sum operation includes a multiplication process in which each piece of data is multiplied by a predetermined coefficient, and an addition process in which the product data is added together. The product-sum operation circuit 4 also includes a multiplier 6 that performs multiplication and an adder 7 that performs addition. This allows for highly accurate product-sum operation.

[0104] Furthermore, in a predetermined number of product-sum calculation processes, product data is generated for each data by a different multiplier 6. This makes it possible to simultaneously perform multiplication processes on a plurality of different data, thereby speeding up the multiplication process.

[0105] Furthermore, in a predetermined number of product-sum calculation processes, a process is repeatedly performed in which product data that has not been added in the predetermined number of times is added by the adder 7 that has not performed addition in the predetermined number of times, thereby achieving highly accurate addition processing.

[0106] Furthermore, the product-sum operation circuit 4 performs the product-sum operation only once for all target data throughout all rounds. This prevents the product-sum operation from being omitted for some target data or from being performed more than once, thereby realizing highly accurate product-sum operation.

[0107] Furthermore, multiple target data stored in the ring buffer 5 are referenced, and if duplicate data exists, the duplicate data is excluded from the targets of that round of product-sum operation processing. A configuration in which RAMs 2a to 2c are linked to form the ring buffer 5 is advantageous in terms of power saving and area saving compared to a configuration in which RAMs 20 are linked by a shift register 21, but it creates a new, unique problem of address overlap. By performing a process to exclude duplicate data as in the present technology, it is possible to solve the problem of address overlap.

[0108] Furthermore, when multiple target data stored in the ring buffer 5 are referenced and there is already-operated data, the already-operated data is excluded from the target of the multiply-and-accumulate operation in that round. This prevents the multiply-and-accumulate operation from being performed on a given target data more than once, thereby realizing highly accurate multiply-and-accumulate operation.

[0109] Furthermore, the elimination is performed by one or more of the following methods: turning off the multipliers 6 corresponding to the duplicated data; not reading out the duplicated data; and not reading out the coefficients corresponding to the duplicated data. This makes it possible to efficiently eliminate duplicated data.

[0110] Furthermore, among the target data referenced in a predetermined round, the non-duplicate data undergoes a multiply-and-accumulate operation in that predetermined round, and the duplicate data undergoes a multiply-and-accumulate operation after all rounds of the multiply-and-accumulate operation on the non-duplicate data have been completed, thereby ensuring that the duplicate data is processed reliably and preventing omissions.

[0111] Furthermore, in the first read, a plurality of different target data are referenced, including the most recent data stored in the ring buffer 5. This allows the newest data to be read first, making it possible to perform reads efficiently.

[0112] Furthermore, in the reading cycle following the predetermined cycle, the next oldest target data after each of the plurality of target data referenced in the predetermined cycle is referenced, and this is repeated each time. This allows the target data to be read in chronological order, making it possible to perform reading efficiently.

[0113] Furthermore, when new data is given to the ring buffer 5, the new data is stored by overwriting the oldest data stored in the ring buffer 5. This makes it possible to efficiently delete the oldest data in the ring buffer 5.

[0114] The ring buffer 5 also stores new data in an address adjacent to the address of the storage destination for the next newest data, thereby enabling data to be efficiently stored in chronological order.

[0115] The product-sum calculation unit 1 also has a coefficient RAM 3 for storing coefficients, which allows for efficient storage and reading of coefficients.

[0116] Other Embodiments The present technology is not limited to the above-described embodiments, and various other embodiments can be realized.

[0117] [Configuration of Number of RAMs, etc.] In the example of FIG. 2 etc., the target data was set so that the address intervals in the ring buffer 5, where it was stored, were equal. That is, the target data was set so that the address intervals were four, with the most recent data being the target data, the four most recent data, etc. Furthermore, the same number of target data was referenced in every read. That is, three target data were always referenced by the three read addresses 14i to 14k. Furthermore, the number of RAMs 2a to 2c was three, which is the same as the number of references to the target data.

[0118] The inventor has found that, as in this example, when addresses are spaced equally apart, the same number of target data are always referenced, the number of RAMs is equal to the number of references, and the start position of read address 14i is index:10, address overlap will occur if the following conditions are met: "the total number of addresses in ring buffer 5 is A x B, and A x B is not divisible by C." Here, A is the number of target data read throughout all cycles, B is the interval between address addresses of the target data, and C is the number of references to the target data in each cycle.

[0119] In this example, if the "read and multiply-and-accumulate process" is performed once, 1024 pieces of target data are read across all the processes, so A = 1024. Also, the address interval between the target data is 4, so B = 4. Furthermore, three pieces of target data are referenced each time, so C = 3.

[0120] Therefore, A x B = 4096, which is equal to the total number of addresses in the ring buffer 5. Also, 4096 is not divisible by 3. Therefore, since the above condition is met, address overlapping will occur at some point. In fact, in Figure 6, for example, address overlapping occurs during the third read.

[0121] In addition, for example, if the number of target data is 1024, the address interval between the target data is 4, five target data are referenced at a time, and the number of RAMs is 5, the condition is met and address overlap occurs.On the other hand, for example, if the start position of read address 14i is index:6, the number of target data is 1024, the address interval between the target data is 8, three target data are referenced at a time, and the number of RAMs is 3, address overlap does not occur.

[0122] 13A is a schematic diagram showing whether or not address overlap occurs. Fig. 13A shows the ring buffer 5 shown in Fig. 2 etc. In this example, since the above conditions are met, address overlap occurs as shown on the right side of the figure.

[0123] 13B shows an example in which address overlap does not occur. In this example, the ring buffer 26 is composed of four RAMs 27 (27a to 27d). Each of the RAMs 27a to 27d has 1024 addresses. Therefore, the ring buffer 26 has 4096 addresses, the same as the ring buffer 5 in FIG. 2 etc.

[0124] Consider a case in which target data is set at intervals of four in such a ring buffer 26, similar to the ring buffer 5 in FIG. 2, and four data are referenced at a time for each read. In this case, A = 1024, B = 4, and C = 4, but A x B = 4096 is divisible by 4, so the condition is not met. Therefore, no address overlap occurs, as shown on the right side of FIG. 13B.

[0125] Specifically, for example, when the read address 28i is moved to the next RAM 27, the other read addresses 28j, 28k, and 28l are also simultaneously moved to the next RAM 27, so that no address overlap occurs.

[0126] 14A shows variations in the number of parallel RAMs. The ring buffer 29 shown in FIG. 14A is configured with two RAMs 30 (30a, 30b), so the number of parallel RAMs is two. For example, if the total number of addresses in each RAM 30 is 2048, the total number of addresses in the ring buffer 29 is 4096. In such a two-parallel ring buffer 29, if the number of target data is 1024, the address interval between the target data is 4, and two target data are referenced at a time, the condition is not met and no address overlap occurs.

[0127] 14B shows a three-parallel ring buffer 5, and FIG. 14C shows a four-parallel ring buffer 26. There are no specific restrictions on the number of parallel RAMs, and the number of parallel RAMs may be five or more. For example, if address overlap occurs, the pipeline processing sequence becomes complicated and the usability of the product-sum calculation unit 1 deteriorates. Therefore, the number of parallel RAMs is determined taking into consideration whether or not address overlap occurs. Area and power consumption are also taken into consideration.

[0128] Furthermore, in the ring buffer 5, the difference in the total number of addresses among the multiple RAMs 2a to 2c is smaller than the number of RAMs 2a to 2c. That is, the total number of addresses among RAMs 2a and 2b is 1,366, and the total number of addresses among RAM 2c is 1,364, so the difference in the total number of addresses among the multiple RAMs 2a to 2c is 0 or 2, which is smaller than the number of RAMs 2a to 2c, which is 3. In other words, the total number of addresses among RAMs 2a to 2c is equal, excluding any remainders. This makes it possible to reduce the number of address overlaps.

[0129] However, the total number of addresses of each of the RAMs 2a to 2c may be any number within the scope of feasibility of the present technology. For example, there may be a certain difference in the total number of addresses, such as the difference between the total number of addresses of any of the RAMs 2a to 2c being equal to or greater than the number of RAMs 2a to 2c.

[0130] In the ring buffer 5, the same number of target data items are referenced (specified by the read addresses 14) in every read operation, but if the present technology is feasible, different numbers of target data items may be referenced in each read operation. For example, three target data items may be referenced in one read operation and two target data items may be referenced in another read operation.

[0131] 6, the interval between the addresses designated by the read addresses 14i and 14j is 1368, and the interval between the read addresses 14j and 14k is 1368, and the interval between the read addresses 14k and 14i is 1360, so the intervals are roughly the same. By minimizing the difference in the intervals in this way, it is possible to reduce the number of address overlaps. However, the specific addresses designated by each read address 14 are not limited. For example, there may be some difference in the intervals between the addresses.

[0132] There is no limitation as to which address in the ring buffer 5 the data is set as the target data. In the ring buffer 5, the target data is read out with a thinning number of 4, but other thinning numbers such as 3 may be used, and the thinning number may not be constant. Also, all data stored in the ring buffer 5 may be set as the target data without thinning.

[0133] The specific configurations of the multipliers 6 and the adders 7 are not limited. For example, the number of multipliers 6 may be any number equal to or greater than two, matching the number of reads per operation. The number and arrangement of the adders 7 are also not limited. For example, if four pieces of product data A to D are generated at one time, it is conceivable to arrange the adders 7 so that A+B is processed, then (A+B)+C is processed, and finally (A+B+C)+D is processed. This type of addition processing is included in "repeated processing of adding, for one piece of product data, product data that has not been added in a predetermined number of times by an adder that has not been added in a predetermined number of times." On the other hand, addition processing may be performed such that A+B is processed, then C+D is processed, and finally (A+B)+(C+D) is processed.

[0134] The use of the product-sum calculation device 1 of the present technology is not limited. For product-sum calculations and the like in which the output does not change depending on the calculation order, the product-sum calculation device 1 of the present invention can be used to save area and power. For example, it is conceivable to apply the product-sum calculation device 1 to convolution calculations such as CNN (Convolutional Neural Network). Furthermore, the product-sum calculation circuit 4 is typically configured as an FIR (Finite Impulse Response) filter, but the specific configuration thereof is not limited.

[0135] The configurations of the product-sum calculation device, data RAM, coefficient RAM, product-sum calculation circuit, ring buffer, multiplier, and adder described with reference to the drawings are merely one embodiment and can be arbitrarily modified without departing from the spirit of the present technology. In other words, any other configurations, algorithms, etc. for implementing the present technology may be adopted.

[0136] In this disclosure, when the word "approximately" is used, this is used merely to facilitate understanding of the description, and the use or non-use of the word "approximately" does not have any special meaning. In other words, in this disclosure, concepts defining size, positional relationship, state, etc., such as "center," "central," "uniform," "equal," "same," "orthogonal," "parallel," "symmetrical," "extended," and "axial direction," are concepts that include "substantially centered," "substantially central," "substantially uniform," "substantially equal," "substantially the same," "substantially orthogonal," "substantially parallel," "substantially symmetrical," "substantially extended," and "substantially axial direction," etc. For example, states that fall within a predetermined range (e.g., a range of ±10%) based on "completely centered," "completely central," "completely uniform," "completely equal," "completely the same," "completely orthogonal," "completely parallel," "completely symmetrical," "completely extended," "completely axial direction," etc., are also included. Therefore, even if the word "approximately" is not added, a concept expressed with the addition of "approximately" may be included. Conversely, a state expressed with the addition of "approximately" does not exclude a perfect state.

[0137] In the present disclosure, expressions using "than", such as "greater than A" and "smaller than A", are expressions that comprehensively include both concepts that include the case where it is equivalent to A and concepts that do not include the case where it is equivalent to A. For example, "greater than A" is not limited to cases that do not include equivalent to A, but also includes "A or greater". Furthermore, "smaller than A" is not limited to "less than A" but also includes "A or less". When implementing the present technology, specific settings and the like can be appropriately adopted from the concepts included in "greater than A" and "smaller than A" so that the effects described above can be achieved.

[0138] It is also possible to combine at least two of the features of the present technology described above. That is, the various features described in each embodiment may be arbitrarily combined without distinguishing between the embodiments. Furthermore, the various effects described above are merely examples and are not intended to be limiting, and other effects may also be achieved.

[0139] The present technology can also be configured as follows. (1) A product-sum calculation device comprising: a ring buffer composed of a plurality of RAMs; and a product-sum calculation unit that performs one or more of the following operations: simultaneously reading two or more pieces of data from the ring buffer so that the RAMs that are storage destinations do not overlap, and performing product-sum calculation processing on the read data. (2) The product-sum calculation device according to (1), wherein the product-sum calculation processing includes a multiplication processing that generates two or more pieces of product data by multiplying each piece of data by a predetermined coefficient, and an addition processing that adds the two or more pieces of product data to generate sum data. (3) The product-sum calculation device according to (2), wherein the product-sum calculation unit has a product-sum calculation circuit including two or more multipliers that perform the multiplication processing and one or more adders that perform the addition processing. (4) The product-sum calculation device according to (3), wherein the multiplication processing is processing that generates the product data by a different multiplier for each piece of data in a predetermined round of the product-sum calculation processing. (5) The product-sum calculation device according to (3) or (4), wherein the addition process is a process in which, when there are three or more pieces of product data in a predetermined round of the product-sum calculation process, the product data that has not been added in the predetermined round is repeatedly added to one of the product data by the adder that has not performed addition in the predetermined round. (6) The product-sum calculation device according to any one of (1) to (5), wherein, when some or all of the data stored in the ring buffer are target data, the product-sum calculation unit performs the product-sum calculation process only once on all of the target data throughout all rounds. (7) The product-sum calculation device according to (6), wherein the product-sum calculation unit references different pieces of target data in the reading in a predetermined round, and when there is duplicate data that is stored in the RAM as a destination of the referenced piece of target data, the product-sum calculation unit excludes the duplicate data from the product-sum calculation process in the predetermined round.(8) The product-sum calculation device according to (6) or (7), wherein the product-sum calculation unit refers to different pieces of target data in the reading at a predetermined time, and if there is operated data that has already been subjected to the product-sum calculation at a time other than the predetermined time among the referenced pieces of target data, the product-sum calculation unit excludes the operated data from being a target of the product-sum calculation at the predetermined time. (9) The product-sum calculation device according to (7), wherein the product-sum calculation unit performs the product-sum calculation at the predetermined time on non-duplicate data that does not overlap in the RAM as a storage destination among the referenced pieces of target data, and performs the product-sum calculation on the duplicate data after all times of performing the product-sum calculation on the non-duplicate data have been completed. (10) The product-sum calculation device according to (1) to (9), wherein when new data is given, the ring buffer overwrites the oldest data stored in the ring buffer with the new data. (11) The product-sum calculation device according to (10), wherein the ring buffer stores the new data at an address adjacent to an address at which the next most recent data after the new data is stored. (12) The product-sum calculation device according to (1) to (11), wherein a difference between the total number of addresses of the plurality of RAMs is smaller than the number of the plurality of RAMs. (13) The product-sum calculation device according to (2) to (12), further comprising a coefficient RAM for storing the predetermined coefficient. (14) An integrated circuit comprising a product-sum calculation circuit that receives as input two or more pieces of data simultaneously read from a ring buffer composed of a plurality of RAMs so that the RAMs that are storage destinations do not overlap.

[0140] REFERENCE SIGNS LIST 1... sum-of-products calculation device 2... data RAM 2a to 2c... RAM 3... coefficient RAM 4... sum-of-products calculation circuit 5... ring buffer 6... multiplier 7... adder

Claims

1. A multiply-and-accumulate device comprising: a ring buffer composed of multiple RAMs; and a multiply-and-accumulate operation unit that simultaneously reads two or more pieces of data from the ring buffer so that the RAMs that store the data do not overlap, and performs multiply-and-accumulate operation processing on the read data one or more times.

2. A product-sum calculation device according to claim 1, wherein the product-sum calculation process includes a multiplication process that generates two or more pieces of product data by multiplying each piece of data by a predetermined coefficient, and an addition process that adds up the two or more pieces of product data to generate sum data.

3. A product-sum calculation device according to claim 2, wherein the product-sum calculation unit has a product-sum calculation circuit including two or more multipliers that perform the multiplication process and one or more adders that perform the addition process.

4. A product-sum calculation device according to claim 3, wherein the multiplication process is a process in which the product data is generated by a different multiplier for each of the data in a predetermined number of product-sum calculation processes.

5. A product-sum calculation device according to claim 3, wherein the addition process is a process in which, when there are three or more pieces of product data in a predetermined round of product-sum calculation processing, the product data that has not been added in the predetermined round is repeatedly added to one piece of product data by the adder that has not performed addition in the predetermined round.

6. A product-sum calculation device according to claim 1, wherein, when part or all of the data stored in the ring buffer is used as target data, the product-sum calculation unit performs the product-sum calculation process on all of the target data only once throughout all cycles.

7. A product-sum calculation device according to claim 6, wherein the product-sum calculation unit refers to different target data in a predetermined number of reads, and if there is duplicate data among the referenced target data that is stored in the RAM, the duplicate data is excluded from the target of the product-sum calculation process in the predetermined number of reads.

8. A product-sum calculation device according to claim 6, wherein the product-sum calculation unit refers to different target data in a predetermined number of reads, and if there is data among the referenced target data that has already been subjected to the product-sum calculation process in a number of times other than the predetermined number of times, the product-sum calculation unit excludes the calculated data from the target of the product-sum calculation process in the predetermined number of times.

9. A product-sum calculation device according to claim 7, wherein the product-sum calculation unit performs the product-sum calculation process in the specified number of times on non-duplicate data among the plurality of target data referenced, the non-duplicate data being stored in the RAM, and performs the product-sum calculation process on the duplicated data after all times of performing the product-sum calculation process on the non-duplicate data have been completed.

10. A product-sum calculation device according to claim 1, wherein when new data is given, the ring buffer overwrites the oldest data stored in the ring buffer with the new data.

11. A product-sum calculation device according to claim 10, wherein the ring buffer stores the new data at an address adjacent to an address at which the next newest data is stored.

12. A product-sum calculation device according to claim 1, wherein the difference between the total number of addresses of each of said plurality of RAMs is smaller than the number of said plurality of RAMs.

13. A product-sum calculation device according to claim 2, further comprising a coefficient RAM for storing said predetermined coefficients.

14. An integrated circuit having a multiply-and-accumulate circuit that receives as input two or more pieces of data simultaneously read from a ring buffer made up of multiple RAMs so that the RAMs that are the storage destinations do not overlap.

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