Selection device and selection method

Abstract

This selection device (100) is connected to: a plurality of processors (for example, targets (210), (220), and (230)); and a debugger (for example, a host (400)) that executes debugging of the plurality of processors, the debugger being connected to the plurality of processors via a multi-drop connection. The selection device is provided with: a first holding circuit (for example, a first register (110)) that holds first identification information indicating any one of the plurality of processors; and a selection circuit (120) that outputs, to the debugger, among one or more pieces of data output from one or more processors among the plurality of processors, only the data output from one processor indicated by the first identification information.

Description

Selection device and selection method

[0001] The present disclosure relates to a selection device and a selection method.

[0002] Conventionally, there are systems for debugging multiple processors. Patent Document 1 discloses a system in which a debugger executes debugging of multiple cores provided in a multiprocessor. The multiple cores disclosed in Patent Document 1 are connected in a ring shape.

[0003] JP 2018-88048 A

[0004] A debugger that debugs multiple processors arranged on a single chip may be connected to the multiple processors in a multi-drop configuration. Even in such a connection configuration, it is desirable for the debugger to be able to properly debug the multiple processors.

[0005] The present disclosure provides a selection device and the like that can reduce the possibility that a debugger will not be able to properly debug a processor.

[0006] A selection device according to one aspect of the present disclosure comprises a plurality of processors and a debugger that performs debugging of the plurality of processors, the selection device being connected to the debugger in a multi-drop connection with the plurality of processors, and comprising: a first holding circuit that holds first identification information indicating one of the plurality of processors; and a selection circuit that outputs to the debugger only data output from one processor indicated by the first identification information, out of one or more data output from one or more processors among the plurality of processors.

[0007] A selection method according to one aspect of the present disclosure is a selection method performed by a selection device connected to a debugger that performs debugging of multiple processors and that is multi-drop connected to the multiple processors, the selection device holding first identification information indicating any one of the multiple processors, and outputting to the debugger only data output from one processor indicated by the first identification information out of one or more data output from one or more processors among the multiple processors.

[0008] A selection device according to one aspect of the present disclosure can reduce the possibility that a debugger will not be able to properly debug a processor.

[0009] FIG. 1 is a block diagram showing a configuration of a debugging system according to an embodiment. FIG. 2 is a diagram for explaining a debugging interface provided in a host according to an embodiment. FIG. 3 is a diagram for explaining a debugging interface provided in a target according to an embodiment. FIG. 4 is a sequence diagram showing a first example of a processing procedure of the debugging system according to an embodiment. FIG. 5 is a sequence diagram showing a second example of a processing procedure of the debugging system according to an embodiment. FIG. 6 is a flowchart showing a specific example of a processing procedure of a selection device according to an embodiment. FIG. 7 is a flowchart showing a selection method according to an embodiment.

[0010] (Background to the Disclosure) In recent years, the development of wearable devices has led to an increasing demand for smaller and thinner devices. In addition, systems tend to become more complex, and the number of LSIs (Large Scale Integrations) equipped with multiple processors such as CPUs (Central Processing Units) mounted on devices has been increasing in recent years.

[0011] Such processors have an interface (access port) for debugging. One example of such an interface (also called a debug interface) is JTAG (Joint Test Action Group). Another example of a debug interface is SWD (Serial Wire Debug).

[0012] SWD is an interface that uses a serial communication method and has fewer terminals than JTAG, while still providing the same debugging functionality as JTAG. Because SWD has fewer terminals than JTAG, it is expected to be smaller in area (i.e., more compact) than LSIs that use JTAG.

[0013] A multi-drop connection (multi-drop connection method) is defined as a connection method for SWDs that connects to multiple processors. This makes it possible to debug multiple processors in an LSI without increasing the number of terminals on the LSI.

[0014] The multi-drop connection in the SWD makes it easy to design and verify the processor, and also provides a high degree of freedom in terms of memory map configuration and debug connection control for each core.

[0015] However, the specifications for the SWD multi-drop connection do not provide a way to avoid a race condition that occurs when responses are returned simultaneously from multiple processors due to an unexpected failure caused by noise or the like (for example, an abnormality in the debug path).

[0016] Therefore, the inventors of the present invention have come up with the present invention.

[0017] Specifically, according to the present disclosure, even when a multi-drop connection of SWDs is adopted within an LSI, it is possible to easily establish a connection (debug access) between any processor (specifically, a processor core) in a multiprocessor system and a debugger even if a fault occurs. Furthermore, for example, according to the present disclosure, an abnormality monitoring function for detecting a processor in which a fault has occurred can be realized.

[0018] The failures referred to here include, for example, unexpected failures due to noise, insufficient output protection when the power is cut off, the same identifier being assigned to two or more processors, the existence of a processor that does not support multi-drop connection, the existence of wiring to a processor that is subject to severe noise, or the existence of a processor that behaves in an unexpected manner.

[0019] Hereinafter, the embodiments will be specifically described with reference to the drawings.

[0020] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component placement and connection configurations, steps, and step order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components that are not described in the independent claims of the present disclosure are described as optional components.

[0021] Furthermore, unless otherwise specified, ordinal numbers such as "first" and "second" do not refer to the number or order of components, but are used to avoid confusion and distinguish between components of the same type.

[0022] (Embodiment) [Configuration] FIG. 1 is a block diagram showing the configuration of a debugging system 10 according to an embodiment.

[0023] The debug system 10 is a system for debugging a plurality of processors (specifically, programs executed by a plurality of processor cores). In this embodiment, the debug system 10 includes a host 400 and an LSI 300, and the host 400 debugs n targets included in the LSI 300. Note that n may be 2 or greater. In this embodiment, the LSI 300 includes three targets, 210, 220, and 230. The host 400 debugs the targets 210, 220, and 230 included in the LSI 300.

[0024] The host 400 is a computer that executes debugging. The host 400 is realized by, for example, a non-volatile memory that stores a program, a volatile memory that is a temporary storage area for executing the program, and a processor that executes the program. The host 400 also includes a debug interface for executing debugging of the targets 210, 220, and 230 included in the LSI 300.

[0025] FIG. 2 is a diagram for explaining a debug interface provided in the host 400 according to the embodiment.

[0026] For example, the host 400 includes a debug interface having a port for communicating a clock signal (CLK shown in FIG. 2) for synchronizing with the targets 210, 220, and 230, and a port for communicating data for executing debugging (DIO shown in FIG. 2). The debug interface included in the host 400 is serially connected to, for example, a port unit 310 included in the LSI 300. This allows serial communication between the host 400 and the LSI 300.

[0027] The host 400 is an example of a debugger.

[0028] Although not shown, the clock generator may be realized by any component.

[0029] The LSI 300 is an LSI that includes multiple processors that are the targets of debugging executed by the host 400. The LSI 300 is realized, for example, on one chip (i.e., one semiconductor substrate). The LSI 300 includes a selection device 100, targets 210, 220, and 230, and a port unit 310. The selection device 100, targets 210, 220, and 230, and port unit 310 are provided on one chip. In other words, for example, the selection circuit 120 and targets 210, 220, and 230 are provided on one chip.

[0030] The targets 210, 220, and 230 are processors (specifically, processor cores of a CPU) that are the targets of debugging executed by the host 400. The targets 210, 220, and 230 each include a debug interface that enables the host 400 to debug the targets 210, 220, and 230.

[0031] FIG. 3 is a diagram for explaining a debug interface provided in the target 200 according to the embodiment.

[0032] The targets 210, 220, and 230 have the same configuration as the debug interface provided in the target 200 shown in Fig. 3. In the following, descriptions common to the targets 210, 220, and 230 may be described as the target 200.

[0033] The target 200 includes a debug interface having, for example, a port for communicating a clock signal for synchronization with the host 400, a port for inputting data from the host 400 (DI shown in FIG. 3), a port for outputting data to the host 400 (DO shown in FIG. 3), and a debug access port including a port for outputting an enable signal (EN shown in FIG. 3). The data and enable signal output from the target 200 are output to the host 400 via the selection device 100 and the port unit 310.

[0034] The host 400 is multi-drop connected to the targets 210, 220, and 230. Therefore, data output by the host 400 is input to each of the targets 210, 220, and 230. For example, the data output by the host 400 includes a target ID (Identifier) ​​indicating one of the targets 210, 220, and 230. Each of the targets 210, 220, and 230 pre-stores a target ID indicating its own target, and based on the acquired target ID, if the target indicated by the target ID is its own target, it outputs data and an enable signal corresponding to the acquired data to the host 400, but if the target indicated by the target ID is not its own target, it does not output the data or enable signal to the host 400.

[0035] By performing such processing, when the host 400 debugs, for example, one of the targets 210, 220, and 230, it outputs data including the target ID of the target to be debugged, thereby establishing one-to-one communication with one target and performing the debugging.

[0036] The port unit 310 is a port that is serially connected to the host 400. The port unit 310 includes, for example, two ports: a port for communicating a clock signal and a port through which data is communicated. The data and enable signal output from the target 200 are each output to the host 400, for example, from the port of the port unit 310 through which data is communicated. Specifically, data input to the selection circuit 120 from the target 210, 220, or 230 is output to the host 400 from the port through which data is communicated, using an enable signal to switch to prevent a collision between input and output in the host 400, only when the host 400 is not using the data line.

[0037] The selection device 100 is an electronic circuit connected to the host 400 and the targets 210, 220, and 230. Specifically, the selection device 100 is connected to the targets 210, 220, and 230 via independent buses, and outputs data and enable signals output from the targets 210, 220, and 230 to the host 400 via a port unit 310. The selection device 100 includes a first register 110 and a selection circuit 120.

[0038] The first register 110 is a register that holds (stores) a target ID (also referred to as a first target ID) that indicates one of the targets 210, 220, and 230. The first register 110 is an example of a first holding circuit. The first target ID is an example of first identification information. The first register 110 is realized, for example, by a latch circuit, but may be realized by any other configuration such as a flip-flop circuit.

[0039] For example, the first register 110 holds a target ID included in data output from the host 400 to the targets 210, 220, and 230. For example, when the host 400 starts debugging one of the targets 210, 220, and 230, it first outputs the target ID and a request (also called a debug request). For example, the first register 110 latches the target ID output at this time. The request is an example of data output by the host 400.

[0040] The LSI 300 may include a port for receiving the output of the target ID to the first register 110. The port is connected to, for example, the first register 110 and an external computer. The external computer may output the target ID to cause the first register 110 to hold the target ID. As a result, the first register 110 may hold the target ID. The external computer here may be the host 400, or may not be the host 400.

[0041] The selection circuit 120 is an electronic circuit that outputs data output by the targets 210, 220, and 230 to the host 400. For example, the selection circuit 120 outputs acknowledgment and enable signals, which are responses to requests output by the targets 210, 220, and 230, to the host 400. The acknowledgment and enable signals are an example of data output by the targets 210, 220, and 230.

[0042] As described above, normally, targets 210, 220, and 230 output an ACK to host 400 if the target indicated by the target ID is their own target, and do not output an ACK to host 400 if the target indicated by the target ID is not their own target. In other words, even if a request is output to targets 210, 220, and 230, normally only one of targets 210, 220, and 230 outputs an ACK.

[0043] Assume now that an abnormality (fault) has occurred in at least one of the targets 210, 220, and 230. An example of the abnormality is an unexpected fault due to noise or the like. Another example of the abnormality is when the same target ID is erroneously assigned to two or more targets. Another example of the abnormality is when an output value is incorrectly fixed in at least one of the targets 210, 220, and 230 when power is cut off. Another example of the abnormality is when at least one of the targets 210, 220, and 230 includes a target that operates according to a standard that does not support multi-drop connections. Another example of the abnormality is when an unexpected malfunction occurs in at least one of the targets 210, 220, and 230. When such an abnormality occurs, an unintended target, i.e., a target other than the target indicated by the target ID, may output an ACK to the host 400. In such a case, the host 400 may not be able to properly debug.

[0044] Therefore, when a conflict occurs in which, for example, two or more of the multiple targets 200 simultaneously output ACKs in response to a debug request output by the host 400 in order to perform debugging, the selection circuit 120 outputs only the ACK obtained from one target 200 indicated by the target ID to the host 400. In this way, the selection circuit 120 outputs only the data output from one target indicated by the target ID to the host 400, of the one or more data (e.g., ACKs and enable signals) output from one or more of the targets 210, 220, and 230.

[0045] The selection device 100 may further include a detection circuit 130 and a second register 140 .

[0046] The detection circuit 130 is an electronic circuit that detects a conflict state in which data is output from multiple targets at the same time. Specifically, when a conflict state occurs in which data is output from two or more targets 200 among the targets 210, 220, and 230, the detection circuit 130 stores conflict information regarding the conflict state in the second register 140.

[0047] The second register 140 is a register that holds (stores) conflict information. The second register 140 is realized by, for example, a latch circuit, but may be realized by any other configuration such as a flip-flop circuit. The second register 140 is an example of a second holding circuit.

[0048] The conflict information may be, for example, the enable signals output by the two or more targets. For example, the detection circuit 130 stores the enable signals output by the targets 210, 220, and 230 in the second register 140.

[0049] Furthermore, for example, the conflict information is a target ID (second target ID) indicating two or more targets. The second target ID is an example of second identification information. For example, the detection circuit 130 stores in the second register 140 a target ID indicating a target among the targets 210, 220, and 230 that has output data to the selection circuit 120. For example, the selection device 100 may store the target IDs of the targets 210, 220, and 230 in advance in a memory (not shown), and the detection circuit 130 may use the memory to identify the target ID indicating the target that output the data when data is output from the target, and store the identified target ID in the second register 140 as conflict information.

[0050] Of course, the detection circuit 130 may store in the second register 140 both the target IDs of the two or more targets and the enable signals output by the two or more targets.

[0051] The host 400 and the second register 140 may be connected to be able to communicate with each other. Specifically, the second register 140 may be configured so that the host 400 can access the conflict information. For example, the host 400 communicates with the second register 140 via a bus that is used when a component such as a CPU included in the LSI 300 accesses the second register 140. The conflict information stored in the second register 140 may be located in an address space or memory space accessible from the host 400. The conflict information may be located in an address space or memory space accessible only from the host 400, or in an address space or memory space accessible from devices other than the host 400.

[0052] [Processing Procedure] Next, a processing procedure of the debugging system 10 according to the embodiment will be described. In the first and second examples described below, the processing procedure will be described when debugging of the target 210 among the targets 210, 220, and 230.

[0053] 4 is a sequence diagram showing a first example of the processing procedure of the debugging system 10 according to the embodiment. The first example is a processing procedure of the debugging system 10 when no conflict state occurs.

[0054] First, the host 400 outputs a target ID (specifically, a target ID indicating the target 210) and a request (debug request) to the LSI 300 (S110). As a result, the target ID and the request are output to each of the targets 210, 220, and 230.

[0055] Examples of methods for the host 400 to connect to one target (also called a debug connection) in order to debug the target include a reset vector catch connection and an attach connection.

[0056] The reset vector catch connection is a connection method in which the reset negation timing is controlled by the host 400 and a break occurs when the reset vector is fetched. The reset vector catch connection is used, for example, when it is desired to debug the target program from the beginning (startup).

[0057] An attach connection is a method in which the host 400 connects to a target while the target is already executing a program. In this connection method, for example, the program being executed by the target will not stop until a break operation is performed. Note that in an attach connection, the host 400 may break during a debug connection.

[0058] Either the reset vector catch connection or the attach connection may be used in the debug system 10. When the reset vector catch connection is used, for example, after the power is turned on (power-on reset), the debug connection is started before the reset is released and the boot sequence is started (that is, the target ID and the request are output).

[0059] When the target ID and the request are output in step S110, the selecting device 100 holds the output target ID (S120).

[0060] Furthermore, the target 210 outputs an ACK in response to the request (S130). Specifically, the target 210 outputs an ACK and an enable signal.

[0061] Also, in this example, targets 220 and 230 do not output acknowledgments.

[0062] The selecting device 100 outputs the ACK received from the target 210 as is (S140). As a result, the host 400 receives the ACK from the target 210, a debug connection is established between the host 400 and the target 210, and debugging of the target 210 begins (S150).

[0063] Note that in the communication between the host 400 and the target 210 when debugging is performed from step S150 onwards, the host 400 may or may not output a target ID. Furthermore, in this communication, if a target ID is output from the host 400, the selecting device 100 may not retain the target ID. Furthermore, in this communication, the selecting device 100 may or may not determine whether to output data for debugging to the host 400 based on the target ID. For example, when the selecting device 100 acquires data for debugging from a target indicated by the target ID, the selecting device 100 may output the data to the host 400, and when the selecting device 100 acquires data for debugging from a target other than the target indicated by the target ID, the selecting device 100 may not output the data to the host 400.

[0064] 5 is a sequence diagram showing a second example of the processing procedure of the debugging system 10 according to the embodiment. The second example is a processing procedure of the debugging system 10 when a conflict state occurs. In the description of each step in the second example, steps that are substantially the same as those in the first example are denoted by the same reference numerals, and the description may be simplified or omitted.

[0065] First, the host 400 outputs a target ID indicating the target 210 and a request to the LSI 300 (S110).

[0066] Next, the selection device 100 holds the output target ID (S120).

[0067] Furthermore, the target 210 outputs an ACK in response to the request (S130).

[0068] In this example, it is assumed that some abnormality has occurred in the target 230 and that the target 230 has output an ACK (specifically, an ACK and an enable signal) in response to the request (S210). In this case, the selecting device 100 simultaneously receives ACKs from both the target 210 and the target 230.

[0069] In this case, the selecting device 100 outputs only the ACK acquired from the target indicated by the target ID held in step S120, out of the two acquired ACKs, to the host 400 (S220). Specifically, the selecting device 100 outputs only the ACK and enable signal acquired from the target 210 to the host 400.

[0070] As a result, the host 400 receives only the acknowledgment of the target 210, a debug connection is established between the host 400 and the target 210, and debugging of the target 210 begins (S150).

[0071] The selection device 100 also stores the conflict information (S230). For example, the detection circuit 130 stores the two enable signals output together with the two ACKs in the second register 140 as conflict information.

[0072] For example, when the selection device 100 acquires only one ACK, if the target that has output the ACK is not the target indicated by the target ID, the selection device 100 may or may not output the ACK to the host 400. In this case, the enable signal that the target that has output the ACK wants to output and / or the target ID indicating the target may be stored in the second register 140 or the like.

[0073] <Processing Procedure of Selection Device> FIG. 6 is a flowchart showing a specific example of the processing procedure of the selection device 100 according to the embodiment.

[0074] First, the selecting device 100 holds the target ID output by the host 400 (S310).

[0075] Next, the selection device 100 acquires an acknowledgment from at least one of the targets 210, 220, and 230 (S320).

[0076] Next, the selection device 100 determines whether the number of ACKs acquired in step S320 is two or more (S330).

[0077] If the selection device 100 determines that the number of acquired ACKs is not two or more (No in S330), that is, if the number of acquired ACKs is one, it outputs the acquired ACK to the host 400 (S340).

[0078] On the other hand, if the selection device 100 determines that the number of acquired ACKs is two or more (Yes in S330), that is, if it determines that a conflict state has occurred, it outputs to the host 400 only the ACK output from the target indicated by the target ID, out of the two or more acquired ACKs, based on the target ID retained in step S310 (S350).

[0079] Furthermore, the selection device 100 holds, for example, two or more enable signals acquired together with two or more ACKs as contention information (S360).

[0080] Note that the process of step S330 does not have to be executed. In this case, for example, after step S320, the selecting device 100 determines whether the target that output the acquired ACK is the target indicated by the target ID. For example, if the target is the target indicated by the target ID, the selecting device 100 transfers the acquired ACK to the host 400, and if the target is not the target indicated by the target ID, the selecting device 100 does not transfer the acquired ACK to the host 400.

[0081] Representative Example Fig. 7 is a flowchart illustrating a selection method according to an embodiment. Specifically, Fig. 7 is a flowchart illustrating the basic processing steps of the selection method executed by the selection device 100. For example, the selection device 100 includes a circuit and a register, and the circuit performs the following processing using the register.

[0082] First, the selection device 100 holds identification information (first identification information) indicating one of the plurality of processors (S10). Specifically, the selection device 100 includes a first holding circuit, and holds (stores) the first identification information in the first holding circuit.

[0083] The multiple processors are, for example, the above-mentioned targets 210, 220, and 230. The first holding circuit is, for example, the above-mentioned first register 110. Furthermore, the first identification information is, for example, the above-mentioned first target ID.

[0084] Next, the selection device 100 outputs to the debugger only the data output from the one processor indicated by the first identification information, among the one or more data output from one or more processors among the plurality of processors (S20).

[0085] The debugger is, for example, the host 400 described above.

[0086] [Effects, etc.] As described above, the selection device 100 according to the embodiment comprises a plurality of targets 200 and a host 400 that debugs the plurality of targets 200, the selection device 100 being connected to the host 400 in a multi-drop connection with the plurality of targets 200, and comprising: a first register 110 that holds a target ID (first target ID) indicating one of the plurality of targets 200; and a selection circuit 120 that outputs to the host 400 only an ACK output from one target 200 indicated by the target ID, out of one or more ACKs output from one or more targets 200 among the plurality of targets 200.

[0087] For example, when debugging a plurality of targets 200, the host 400 communicates one-to-one with one of the targets 200. At this time, for example, in order to establish communication with one of the targets 200 to be debugged, the host 400 outputs (transmits) a target ID indicating that one target 200 to that one target 200. Here, if the host 400 and the plurality of targets 200 are connected in a multi-drop manner, the target ID output from the host 400 is acquired by each of the plurality of targets 200. Based on the target ID, each of the plurality of targets 200 outputs an acknowledgment to the host 400 if the target indicated by the target ID is its own target, and does not output an acknowledgment to the host 400 if the target indicated by the target ID is not its own target. In this way, one-to-one communication between the host 400 and one target 200 is established. Here, if an unexpected failure due to noise or the like occurs in a system including the selection device 100, multiple targets 200, and the host 400, if the same identifier is mistakenly assigned to two or more of the multiple targets 200, if an output value is incorrectly fixed during power shutdown, if one of the multiple targets 200 operates under a standard that does not support multi-drop connections, or if an unexpected failure occurs in a target 200, there is a possibility that an unintended target 200 will also output an ACK to the host 400. In such cases, there is a possibility that the host 400 will not be able to properly debug. Therefore, based on the target ID, if a conflict occurs in which ACKs are simultaneously output from two or more of the multiple targets 200 in response to a debug request output by the host 400 for debugging, for example, the selection device 100 outputs only the ACK obtained from one target 200 indicated by the target ID to the host 400. This reduces the possibility that the host 400 will be unable to perform debugging due to receiving multiple ACKs.Therefore, the selecting device 100 makes it easier for the host 400 to properly acquire acknowledgments from the target 200 to be debugged, thereby reducing the possibility that the host 400 will not be able to properly debug the target 200.

[0088] Furthermore, for example, the selection circuit 120 and the multiple targets 200 are provided on one chip.

[0089] This allows the LSI 300 on which multiple targets are mounted to be miniaturized, and also reduces the possibility that the host will not be able to properly debug the target 200 .

[0090] In particular, for example, when a multi-drop connection is made outside the LSI 300, it is possible to establish a debug connection and detect a fault using conventional techniques such as a wiring inspection mechanism, but when a multi-drop connection is made inside the LSI, conventional inspection mechanisms cannot be used. Therefore, when a multi-drop connection is made inside the LSI, if an abnormality (failure) occurs, the host 400 may not be able to establish a debug connection with all of the targets 200. It also becomes difficult to identify the cause of the fault.

[0091] On the other hand, the selection device 100 makes it easier for the debugger to properly acquire ACKs from the target to be debugged, even if a multi-drop connection is made inside the LSI 300, that is, even if the selection circuit 120 and multiple targets 200 are provided on one chip. Therefore, the selection device 100 reduces the possibility that the host 400 will not be able to properly debug the target 200, even if the selection circuit 120 and multiple targets 200 are provided on one chip, so the selection device 100 is particularly useful for a configuration in which the selection circuit 120 and multiple targets are provided on one chip.

[0092] Furthermore, for example, the first register 110 holds a target ID included in data output from the host 400 to the multiple targets 200 .

[0093] For example, when the host 400 is about to perform debugging, a debug request and a target ID are output to the multiple targets 200. The first register 110 holds, for example, the target ID output at this time.

[0094] This allows the selection device 100 to easily obtain the target ID.

[0095] Furthermore, for example, the selection device 100 includes a port for receiving the target ID output to the first register 110 .

[0096] This allows the selection device 100 to easily obtain the target ID.

[0097] Also, for example, the selection device 100 includes a second register 140 and a detection circuit 130 that, when a conflict state occurs in which acknowledgments are output from two or more of the multiple targets 200, stores conflict information regarding the conflict state in the second register 140.

[0098] According to this, when a conflict occurs, the cause of the conflict can be easily analyzed by analyzing the conflict information held in the second register 140 .

[0099] Furthermore, for example, the conflict information is an enable signal output by each of two or more targets 200 .

[0100] This makes it easy to identify two or more targets 200 that are the cause of the conflict.

[0101] Furthermore, for example, the contention information is a second target ID indicating two or more processors.

[0102] This makes it easy to identify two or more targets 200 that are the cause of the conflict.

[0103] (Other Embodiments) As described above, the embodiments have been described as examples of the technology according to the present disclosure. However, the technology according to the present disclosure is not limited to these, and can be applied to embodiments in which modifications, substitutions, additions, omissions, etc. are made as appropriate. For example, the following modifications are also included in one embodiment of the present disclosure.

[0104] For example, the selection device 100 may not include the detection circuit 130 .

[0105] Also, for example, the selection device 100 may not include the second register 140 .

[0106] Furthermore, for example, the number of targets (processors) included in the LSI 300 may be two, or may be four or more.

[0107] Furthermore, for example, the LSI 300 and the host 400 may be connected in a multi-drop manner outside the LSI 300. Therefore, the LSI 300 may have ports connected to the host 400 in the same number as the number of targets included in the LSI 300.

[0108] Furthermore, for example, the selection device 100 and the multiple processors are provided on one chip, but the selection device 100 and the multiple processors may be provided on separate chips.

[0109] Furthermore, the first holding circuit and the second holding circuit are each realized by, for example, a register, but as long as they have the function of storing information, they may also be realized by a memory such as a RAM (Random Access Memory).

[0110] Furthermore, for example, some or all of the functions of the selection device 100 according to the above-described embodiment are typically realized by an LSI 300, which is an integrated circuit. These may be individually integrated into single chips, or some or all of them may be integrated into a single chip. Furthermore, the integrated circuit is not limited to an LSI, and may be realized by a dedicated circuit or a general-purpose processor. It is also possible to use an FPGA (Field Programmable Gate Array) that can be programmed after LSI manufacturing, or a reconfigurable processor that can reconfigure the connections and settings of circuit cells within an LSI.

[0111] Furthermore, if an integrated circuit technology that can replace LSI emerges due to advances in semiconductor technology or other derivative technologies, it is natural that each component included in the selection device 100 may be integrated using that technology.

[0112] Furthermore, for example, in the above-described embodiment, the processing performed by a specific processing unit may be performed by another processing unit, the order of multiple processing operations may be changed, or multiple processing operations may be performed in parallel.

[0113] In addition, this disclosure also includes forms obtained by making various modifications to the embodiments that a person skilled in the art would think of, and forms realized by arbitrarily combining the components and functions in each embodiment within the scope of the present disclosure.

[0114] (Additional Note) Below, examples of techniques that can be obtained from the disclosure of this specification will be given, and the effects and the like that can be obtained from the exemplified techniques will be described.

[0115] (Technology 1) A selection device comprising a plurality of processors and a debugger that debugs the plurality of processors, the selection device being connected to the debugger in a multi-drop connection with the plurality of processors, the selection device comprising: a first holding circuit that holds first identification information indicating one of the plurality of processors; and a selection circuit that outputs to the debugger only data output from one processor indicated by the first identification information, out of one or more data output from one or more processors of the plurality of processors.

[0116] The selection device is, for example, the above-mentioned selection device 100. The first holding circuit is, for example, the above-mentioned first register 110. The selection circuit is, for example, the above-mentioned selection circuit 120. The debugger is, for example, the above-mentioned host 400. The multiple processors are, for example, the above-mentioned targets 210, 220, and 220. The first identification information is, for example, the above-mentioned target ID (first target ID) that indicates the processor that the debugger is to debug.

[0117] This reduces the possibility that the debugger will be unable to perform debugging due to receiving multiple acknowledgments. Therefore, this makes it easier for the debugger to properly obtain data from the processor to be debugged, thereby reducing the possibility that the debugger will be unable to properly debug the processor.

[0118] (Technology 2) The selection device according to Technology 1, wherein the selection circuit and the plurality of processors are provided on a single chip.

[0119] This allows the size of an electronic circuit (for example, the above-mentioned LSI 300) equipped with multiple processors to be reduced, and also reduces the possibility that the debugger will not be able to properly debug the processors.

[0120] (Technology 3) The selection device according to Technology 1 or 2, wherein the first holding circuit holds the first identification information included in data output from the debugger to the plurality of processors.

[0121] This allows the selection device to easily obtain the first identification information.

[0122] (Technology 4) A selection device according to any one of technologies 1 to 3, further comprising a port for receiving output of the first identification information to the first holding circuit.

[0123] This allows the selection device to easily obtain the first identification information.

[0124] (Technology 5) A selection device according to any one of technologies 1 to 4, comprising a second holding circuit and a detection circuit that, when a conflict state occurs in which data is output from two or more processors among the plurality of processors, causes the second holding circuit to hold conflict information regarding the conflict state.

[0125] The second holding circuit is, for example, the above-described second register 140. The detection circuit is, for example, the above-described detection circuit .

[0126] According to this, when a conflict occurs, a computer such as the host 400 described above can easily analyze the cause of the conflict by analyzing the conflict information stored in the second holding circuit.

[0127] (Technology 6) The selection device according to Technology 5, wherein the conflict information is an enable signal output by each of the two or more processors.

[0128] This makes it possible to easily identify two or more processors that are the cause of the conflict state from the conflict information.

[0129] (Technology 7) The selection device according to Technology 5 or 6, wherein the conflict information is second identification information indicating the two or more processors.

[0130] The second identification information is the above-mentioned target ID (second target ID) that indicates two or more processors that output the data.

[0131] This makes it possible to easily identify two or more processors that are the cause of the conflict state from the conflict information.

[0132] (Technique 8) The selection device according to any one of claims 5 to 7, wherein the debugger and the second holding circuit are connected so as to be able to communicate with each other.

[0133] This allows the debugger to read out the conflict information held in the second holding circuit.

[0134] (Technology 9) A selection method for a plurality of processors and a debugger that debugs the plurality of processors, the selection method being executed by a selection device connected to the debugger that is multi-drop connected to the plurality of processors, the selection method holding first identification information indicating any one of the plurality of processors, and outputting to the debugger only data output from one processor indicated by the first identification information out of one or more data output from one or more processors among the plurality of processors.

[0135] This provides the same effect as the selection device described in the first technique.

[0136] These comprehensive or specific aspects may be realized as a system, a method, an integrated circuit, a computer program, or a non-transitory recording medium such as a computer-readable CD-ROM, or may be realized as any combination of a system, a method, an integrated circuit, a computer program, and a recording medium.

[0137] The present disclosure can be applied to an LSI that is equipped with multiple processors to be debugged.

[0138] 10 Debug system 100 Selection device 110 First register 120 Selection circuit 130 Detection circuit 140 Second register 200, 210, 220, 230 Target 300 LSI 310 Port unit 400 Host

Claims

1. A selection device comprising a plurality of processors and a debugger that debugs the plurality of processors, the selection device being connected to the debugger in a multi-drop connection with the plurality of processors, the selection device comprising: a first holding circuit that holds first identification information indicating any one of the plurality of processors; and a selection circuit that outputs to the debugger only data output from one processor indicated by the first identification information, out of one or more data output from one or more processors of the plurality of processors.

2. The selection device according to claim 1, wherein the selection circuit and the plurality of processors are provided on a single chip.

3. The selection device according to claim 1, wherein the first holding circuit holds the first identification information included in data output from the debugger to the plurality of processors.

4. The selection device according to claim 1, further comprising a port for receiving output of said first identification information to said first holding circuit.

5. The selection device according to claim 1, further comprising: a second holding circuit; and a detection circuit that, when a conflict state occurs in which data is output from two or more processors among the plurality of processors, causes the second holding circuit to hold conflict information regarding the conflict state.

6. The selection device according to claim 5, wherein the conflict information is an enable signal output by each of the two or more processors.

7. The selection device according to claim 5, wherein the contention information is second identification information indicating the two or more processors.

8. The selection device according to claim 5, wherein the debugger and the second holding circuit are communicatively connected.

9. A selection method for a plurality of processors and a debugger that debugs the plurality of processors, the selection method being executed by a selection device connected to the debugger that is multi-drop connected to the plurality of processors, the selection device holding first identification information indicating any one of the plurality of processors, and outputting to the debugger only data output from one processor indicated by the first identification information out of one or more data output from one or more processors of the plurality of processors.

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