Task processing device and method for controlling task processing device

Abstract

This task processing device is provided with a first core that executes first task processing with a first processing cycle, a second core that executes second task processing with a second processing cycle that is longer than the first processing cycle, and a first storage unit that is provided on the first core side, wherein the first core and the second core set and share, in the first storage unit, a data set relating to the results of the first task processing and the second task processing.

Description

Task processing device and method for controlling task processing device

[0001] The present invention relates to a task processing device and a method for controlling a task processing device.

[0002] In recent years, motors have been used in a variety of devices, one example of which is an electric power steering device that performs assist control related to vehicle steering. The processing load required of electric power steering devices is on the rise, and as a result, higher performance is required of the processing units provided in electric power steering devices. Furthermore, electric power steering devices are designed with redundancy in each component for safety reasons.

[0003] For example, Patent Document 1 discloses a configuration in which a CPU with four cores is used as the processing unit of an electric power steering device, and the four cores are divided into two groups to perform status monitoring using a lockstep method and detect abnormalities.

[0004] Chinese Patent No. 108528523

[0005] In a processing unit provided in an electric power steering device, attention is focused on two cores capable of executing different processes. For example, there is a configuration in which the processing of various functions provided by the electric power steering device is distributed among the cores. With such a configuration, even if a single core does not have sufficient processing performance, it is possible to provide the desired performance by sharing the processing. However, when sharing the processing, it is necessary to consider the synchronization of data between the cores and the processing load related to data access between the cores.

[0006] In view of the above problems, an object of the present invention is to share processing taking into consideration the synchronicity of data between multiple cores and the processing load related to data access between cores.

[0007] In order to solve the above problems, the present invention has the following configuration: A task processing device comprising: a first core that executes a first task process in a first processing cycle, a second core that executes a second task process in a second processing cycle that is longer than the first processing cycle, and a first storage unit provided on the first core side, wherein the first core and the second core set data sets related to the results of the first task process and the second task process in the first storage unit and share the data sets.

[0008] Another aspect of the present invention has the following configuration: A control method for a task processing device including: a first core that executes a first task processing in a first processing cycle; a second core that executes a second task processing in a second processing cycle that is longer than the first processing cycle; and a first storage unit provided on the first core side, wherein a data set relating to results of the first task processing and the second task processing is set in the first storage unit and shared by the first core and the second core.

[0009] The present invention makes it possible to share processing taking into consideration the synchronicity of data between a plurality of cores and the processing load related to data access between cores.

[0010] The present invention relates to a processing unit for executing a program for a computer system, a method for executing a program for a computer, and a computer program product for executing a program for a computer system.

[0011] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the embodiments described below are merely examples for explaining the present invention and are not intended to limit the present invention. Furthermore, not all configurations described in each embodiment are necessarily essential configurations for solving the problems of the present invention. Furthermore, in each drawing, the same components are assigned the same reference numerals to indicate their correspondence. Furthermore, in this specification, terms such as "first" and "second" are used merely to distinguish from other components and are not intended to be interpreted as being limited to specific components. Therefore, such terms may be interpreted appropriately depending on the configuration of the device to which they are applied.

[0012] <First embodiment> A first embodiment of the present invention will be described below. Note that the present invention is widely applicable to devices related to motor control, but in this embodiment, an electric power steering device (EPS: Electric Power Steering) mounted on a vehicle will be described as an example.

[0013] 1 is a block diagram showing an example of the configuration of a processing unit 100 as a task processing device capable of executing processes related to EPS motor control. Only the components according to this embodiment are shown here as an example, and other components may be included when the processing unit is mounted on a controlled object such as an EPS.

[0014] The processing unit 100 according to this embodiment is configured as a so-called quad-core processor having four cores: 111, 112, 121, and 122. In this example, core 111 (also referred to as "core A") and core 112 (also referred to as "core B") form core set 110 (also referred to as "core set A"), which are equipped with a safety function based on the dual lockstep function. Similarly, core 121 (also referred to as "core C") and core 122 (also referred to as "core D") form core set 120 (also referred to as "core set B"), which are equipped with a safety function based on the dual lockstep function. The dual lockstep function synchronizes the clocks of the two cores, executes the same processing in each core, and monitors their status based on whether the processing results are the same. If the processing results of the two cores differ, an abnormality is detected, assuming that an abnormality has occurred in one or both of the cores. The dual lockstep function is well-known, and further detailed description thereof will be omitted.

[0015] The core sets 110 and 120 are each provided with a RAM (Random Access Memory) 113 and 123 as a storage unit. While FIG. 1 illustrates the RAMs 113 and 123 as being located inside each core set, this configuration is not limiting. The storage unit may be any storage unit accessible by each core of the core sets 110 and 120 in accordance with the processing flow described below. The storage unit provided in or available to the processing unit 100 is not limited to RAM, and may further include a register, a cache memory, a ROM (Read Only Memory) used as a main storage device, and the like.

[0016] Although not shown in Fig. 1, the EPS includes, for example, an ECU (Electronic Control Unit), a motor, a steering torque sensor, and a motor angle sensor. The motor is a so-called three-phase permanent magnet synchronous motor. The ECU includes a processing unit 100 shown in Fig. 1, and is, for example, an EPS-ECU. The ECU also includes a power supply management IC, a driver, and the like.

[0017] [Processing Flow] The processing flow according to this embodiment will be described below, focusing on the core 111 and the core 121, which perform different processes, out of the four cores shown in FIG.

[0018] For example, in the case of EPS, current control, which requires a relatively high level of responsiveness, is executed with a task processing cycle of, for example, 100 μs. On the other hand, some EPS control processes do not require as high a responsiveness as current control, and in such processes, task processing is executed with a cycle of, for example, 1 ms.

[0019] In this embodiment, a task process requiring high responsiveness, such as current control (hereinafter also referred to as "first task process"), is executed by the core 111, and a process requiring lower responsiveness than the first task process (hereinafter also referred to as "second task process") is executed by the core 121. The first task process is executed at a 100 μs interval, and the second task process is executed at a 1 ms interval. Note that the periodicity of each task process is merely an example, and other intervals may be set as long as the environment is one in which the relationship between the processes described below is anticipated.

[0020] In this configuration, each core uses the results of task processing by the other core to execute its own task processing. In this case, each core needs to synchronize data based on the results of task processing by the other core. In this example, core 121 performs processing according to instructions from core 111. Furthermore, the cores 111 and 121 will be described as having a configuration in which they synchronize data based on the results of each other's processing at a predetermined timing before using it for processing.

[0021] 2 is a conceptual diagram illustrating the flow of processing by each core according to this embodiment. The core 111 executes processing at 100 μs intervals (ISR processing 202). Therefore, 10 ISR processes 202 (ISR0 to ISR9) occur in 1 ms, which corresponds to a series of task processes 201. The core 111 repeats this task processing 201.

[0022] Meanwhile, the core 121 starts processing based on a processing command (software interrupt) from the core 111 (main processing 203). At this time, the core 111 shares data to be used on the core 121 side prior to the request for the software interrupt to the core 121. Details will be described with reference to FIG. 3.

[0023] When the main processing 203 is completed, the core 121 shares the data resulting from the processing with the core 111. When the data is shared with the core 111, the core 111 uses the data to execute subsequent processing. In this way, processing is repeated while the data is shared between the core 111 and the core 121.

[0024] This will be explained in more detail using Figure 3. Figure 3 is a schematic diagram for explaining data sharing between cores according to this embodiment. In Figure 3, solid arrows indicate function calls, and dashed arrows indicate data flows to the storage unit. Note that for simplification, some arrows and boxes may be omitted. As shown in Figure 2, ISR processing and main processing are repeatedly executed in each core while data sharing is performed.

[0025] In this embodiment, the core 111 and the core 121 have mutually accessible storage units. In this example, the RAM 113 provided on the core 111 side, i.e., on the core set 110 side, has at least four areas, which are used in the processing described below. For convenience, the four areas are referred to as areas A to D here. The RAM 123 provided on the core 121 side, i.e., on the core set 120 side, has at least one area, which is used in the processing described below. The areas provided in each RAM are set to prevent the stored data set from being updated at unintended times by other processing.

[0026] The core 111 executes ISR0. In ISR0, first, a function call is made for data latch processing (1). In the data latch processing, the core 111 acquires a data set set in area A of the RAM 113 based on the results of the previous processing by the core 121 (2). Then, the core 111 sets the acquired data set in area B of the RAM 113 for use in each ISR processing (3). In this example, the data set is held in area B of the RAM 113 for 1 ms.

[0027] Next, the core 111 performs a function call for data set processing (4). In the data set processing, the core 111 sets the data obtained as the processing result in the ISR processing up to this point for use by the core 121 (5). Thereafter, the core 111 executes a soft interrupt to the core 121 (6).

[0028] When the core 111 executes each ISR process, it executes the process by referring to the data set stored in area B of the RAM 113 .

[0029] When a software interrupt occurs from core 111, core 121 performs a function call to execute data latch processing (7). In the data latch processing, core 121 accesses area C of RAM 113 via core 111 and acquires data (8). As described above, area C of RAM 113 stores data obtained as a result of processing by core 111. Then, core 121 sets the acquired data in RAM 123 so that it can be executed by its own main processing (9).

[0030] When executing a main process, the core 121 executes the process by referencing a data set set in the RAM 123. In this embodiment, a priority may be set for each of the multiple main processes, and the main processes may be executed in descending order of priority. Furthermore, the number and types of main processes are not particularly limited.

[0031] Furthermore, the core 121 performs a function call for data set processing at a timing specified in each main process (13). In the data set processing, the core 121 collects data obtained as a processing result in the main process and sets the data in area A of the RAM 113 on the core 111 side (14). At this time, depending on the processing load on the core 111 side, the collected data set may be set in the RAM 123 on the core 121 side, and the core 111 may acquire the data set and set it in area A of the RAM 113 on the core 111 side.

[0032] The function call (13) for data set processing may be executed at different times for each main process. Furthermore, the data set setting (14) may be performed for each processing cycle (1 ms in this example) of the core 121. Alternatively, depending on the processing load, the data set setting (14) may be executed each time a function call (13) is executed, or may be executed collectively, for example, when execution of multiple main processes is completed.

[0033] In this example, depending on the content of the main processing executed by the core 121, the processing results may need to be immediately reflected in the processing on the core 111. In such cases, the core 121 performs a function call for data set processing for immediate reflection during execution of the main processing (10). In the immediate data set processing, the core 121 collects data for immediate reflection obtained in the main processing and sets it in area D of the RAM 113 on the core 111 (11).

[0034] The core 111 executes the ISR process (12) by referring to the dataset set in the area D of the RAM 113. At this time, the core 111 may be configured to preferentially use the dataset set in the area D of the RAM 113 over datasets set in other areas.

[0035] Generally, RAM access between cores takes time. Therefore, it is desirable to configure the system so as not to interfere with the processing of the core 111, which has a heavy processing load, i.e., which requires hard real-time performance. Therefore, in this embodiment, when data access is performed between cores, the core 121, which has a light processing load, i.e., which does not require hard real-time performance, executes data acquisition (8) and data setting (14, 11) in the RAM 113 on the core 111 side.

[0036] In addition, it is desirable that the function call (1), data acquisition (2), and data setting (3) for data set processing by core 111 be performed in ISR0, which is the first ISR processing of task processing 201, but depending on the processing load of core 111, some of these may be moved to ISR1, which is the next ISR processing.

[0037] (Example of Application to EPS) A specific example of processing and data when the configuration shown in FIG. 3 is applied to an EPS will be described.

[0038] Examples of processes executed on the core 111 side that have a relatively high priority and require responsiveness include AD conversion of detected values ​​by various sensors. Examples of processes executed on the core 121 side that have a relatively low priority and do not require responsiveness include current command value calculation, diagnostic processing, communication with an external interface, filtering processing, etc. Note that these are merely examples and are not limiting.

[0039] In data setting (5), examples of the data set set by the core 111 in area C of the RAM 113 on the core 111 side include, for example, the electrical angle of a motor (not shown) provided in the EPS, three-phase current detection values, power supply voltage, motor angular velocity, and motor angular acceleration.

[0040] In data setting (14), examples of the data set set by core 121 in area A of RAM 113 on the core 111 side include information such as the vehicle speed, steering torque, temperature, system status, battery status, and status of each device of a vehicle (not shown) equipped with an EPS.

[0041] The vehicle speed may be obtained, for example, from a vehicle speed sensor (not shown) via a CAN (Controller Area Network) installed in the vehicle. The electrical angle, three-phase current detection value, power supply voltage, steering torque, and temperature may be obtained by performing AD conversion or conversion to physical values ​​on detection values ​​of various sensors installed in the ECU. The motor angular velocity and motor angular acceleration may be calculated from the electrical angle. The system state indicates a transition state of the EPS and may include, for example, an initial diagnosis state, an assist standby state, an assist permitted state, etc. The battery state indicates whether the power supply voltage is within a range. For example, if the battery state is within a range in which driving is not permitted (e.g., low voltage or high voltage), the system state is controlled to enter the assist standby state to protect the circuit. The device state may include, for example, a motor shut-off state, a Gate Drive Unit (GUD) state, etc.

[0042] In the above, for example, detection signals from detectors for the electrical angle, three-phase current detection values, power supply voltage, steering torque, and temperature are AD converted on the core 111 side. The converted values ​​are then converted into physical values ​​shared between core 111 and core 121, and the data is shared in RAM. In such a configuration, for example, the electrical angle, three-phase current detection values, power supply voltage, motor angular velocity, and motor angular acceleration are assigned to be converted into physical values ​​on the core 111 side, since they are desired to be used immediately on the core 111 side. The conversion results are then set in area B or area C of RAM 113, and data sharing, etc. is performed.

[0043] On the other hand, the steering torque and temperature are AD converted by core 111, and the converted values ​​are set (5) in area C of RAM 113 and shared with core 121. Then, core 121 converts the steering torque and temperature values ​​into physical values, and then sets them in area A of RAM 113 on the core 111 side in data setting (14), thereby enabling data sharing.

[0044] The above is just an example, and the division of processing is not limited to this. The division of processing between the core 111 and the core 121 (or the core set 110 and the core set 120) may be defined taking into consideration the responsiveness according to the functions of the EPS, etc.

[0045] For example, in the above example, the AD conversion of the detection values ​​of the various sensors is performed entirely by core 111, i.e., the core that executes the first task processing (in this example, task processing with a 100 μs cycle), but the AD conversion may be shared. Specifically, the AD conversion and physical value conversion of the steering torque and temperature may be performed by core 121, i.e., the core that executes the second task processing (in this example, task processing with a 1 ms cycle).

[0046] Note that data (for example, ADAS (Advanced Driver-Assistance Systems) commands) from a host ECU (not shown) mounted on the vehicle, the vehicle speed, and the like are acquired via communications such as a CAN. Therefore, in consideration of communication loads and the like, it is desirable that processing using such information be handled by a core that has relatively ample time for task processing (in this example, core 121 that executes the second task processing).

[0047] Furthermore, the data setting (11), which requires immediacy, may be used, for example, to satisfy the responsiveness of the EPS. More specifically, the function call (10) and the data setting (11) may be executed in consideration of the responsiveness of a series of processes, such as steering torque detection, current command value calculation, and PWM (Pulse Width Modulation) output. However, as described above, RAM access between cores takes time and imposes a heavy processing load. Therefore, it is desirable to define the processing of the function call (10) and the data setting (11) in consideration of the load of other processes, etc.

[0048] As described above, this embodiment makes it possible to share processing taking into consideration the synchronicity of data between a plurality of cores and the processing load related to data access between cores.

[0049] <Other Embodiments> In the above embodiment, an EPS has been described as an example of a motor control device. However, the present invention can also be applied to other devices, and may be applied to devices including a motor, such as an electric actuator device with a linear motion mechanism. Furthermore, the present invention may be used in an electric actuator device that controls the brakes of a vehicle. Furthermore, the present invention is not limited to motor control, and the processing sharing method according to the present invention may be applied to other types of control.

[0050] In the above example, a quad-core processor configuration that can be used in a motor control device has been described. However, this is not limited to this, and the present invention can be applied to any processor that has multiple cores that can share and execute processing. For example, the processing sharing method of the present invention may be applied to a dual-core processor.

[0051] In addition, in the present invention, a program or application for realizing the functions of the above-mentioned embodiments can be supplied to a system or device using a network or a storage medium, etc., and one or more processors in the computer of the system or device can read and execute the program.

[0052] As such, the present invention is not limited to the above-described embodiments, and the present invention also contemplates the mutual combination of the various components of the embodiments, as well as modifications and applications by those skilled in the art based on the description in the specification and well-known techniques, and these modifications and applications are included in the scope of protection sought.

[0053] As described above, the present specification discloses the following: (1) A task processing device comprising: a first core (e.g., 111) that executes a first task process (e.g., 202) in a first processing cycle (e.g., 100 μs); a second core (e.g., 121) that executes a second task process (e.g., 203) in a second processing cycle (e.g., 1 ms) that is longer than the first processing cycle; and a first storage unit (e.g., 113) provided on the first core side, wherein the first core and the second core set data sets related to the results of the first task process and the second task process in the first storage unit and share them. This configuration enables processing allocation that takes into account data synchronization between multiple cores and the processing load related to data access between the cores.

[0054] (2) The task processing device according to (1), wherein the first core acquires a data set set in the first storage unit by the second core at the start of the first task processing and references the data set in the first task processing. With this configuration, data sharing at the beginning of a predetermined cycle enables each core to execute an appropriate process.

[0055] (3) The task processing device according to (1) or (2), wherein the first core sets a dataset related to the result of the first task processing in the first storage unit, and then transmits an instruction to the second core to execute the second task processing using the dataset. With this configuration, it is possible to update a dataset referenced in processing by the second core and then instruct the second core to use the dataset.

[0056] (4) The task processing device according to (3), further comprising a second storage unit (e.g., 123) provided on the second core side, wherein when the second core receives the instruction from the first core, the second core acquires a data set set in the first storage unit by the first core, sets the data set in the second storage unit, and then executes the second task processing using the data set. With this configuration, the second core can reduce the processing load of the first core, which has a higher processing load, by referring to the storage unit on the first core side.

[0057] (5) The task processing device according to any one of (1) to (4), wherein the second core sets a data set related to the result of the second task processing in the first storage unit in the second processing cycle and shares the data set. With this configuration, the second core sets the data set in the storage unit on the first core side, thereby making it possible to reduce the processing load of the first core, which has a higher processing load.

[0058] (6) The task processing device according to any one of (1) to (5), wherein the second core sets a data set that needs to be shared immediately in the first task processing in the first storage unit and shares the data set regardless of the second processing cycle. With this configuration, the second core can share a data set that requires high immediacy with the first core regardless of the processing cycle.

[0059] (7) The task processing device according to any one of (1) to (6), wherein the first task processing is task processing that requires higher responsiveness than the second task processing. With this configuration, it is possible to have the first core share and execute the task processing that requires higher responsiveness.

[0060] (8) The task processing device according to any one of (1) to (7), characterized in that the task processing device is used in a motor control device, an electric power steering device, or an electric actuator device. With this configuration, it becomes possible to define the allocation of processing loads in consideration of tasks of the motor control device, the electric power steering device, or the electric actuator device.

[0061] (9) A method for controlling a task processing device comprising: a first core that executes a first task process in a first processing cycle; a second core that executes a second task process in a second processing cycle that is longer than the first processing cycle; and a first storage unit provided on the first core side, wherein a data set relating to the results of the first task process and the second task process is set in the first storage unit and shared by the first core and the second core. This configuration enables processing allocation that takes into account data synchronization between multiple cores and the processing load related to data access between cores.

[0062] Although various embodiments have been described above with reference to the drawings, it goes without saying that the present invention is not limited to such examples. It is clear that a person skilled in the art can conceive of various modifications or alterations within the scope of the claims, and it is understood that these also naturally fall within the technical scope of the present invention. Furthermore, the components of the above-described embodiments may be combined in any manner without departing from the spirit of the invention.

[0063] This application is based on a Japanese patent application (Patent Application No. 2024-045566) filed on March 21, 2024, the contents of which are incorporated herein by reference.

[0064] 100... Processing unit 110, 120... Core set 111, 112, 121, 122... Core 113, 123... RAM

Claims

1. A task processing device comprising: a first core that executes a first task processing in a first processing cycle; a second core that executes a second task processing in a second processing cycle that is longer than the first processing cycle; and a first memory unit provided on the first core side, wherein the first core and the second core set data sets related to the results of the first task processing and the second task processing in the first memory unit and share the data sets.

2. The task processing device according to claim 1, characterized in that the first core acquires a dataset set in the first memory unit by the second core at the start of the first task processing and references it in the first task processing.

3. The task processing device according to claim 1, characterized in that the first core sets a dataset related to the results of the first task processing in the first memory unit, and then sends an instruction to the second core to execute the second task processing using the dataset.

4. A task processing device as described in claim 3, further comprising a second memory unit provided on the second core side, wherein when the second core receives the instruction from the first core, the second core acquires the data set set in the first memory unit by the first core and sets it in the second memory unit, and then executes the second task processing using the data set.

5. The task processing device according to claim 1, characterized in that the second core sets a data set relating to the results of the second task processing in the second processing cycle in the first storage unit and shares it.

6. The task processing device according to claim 1, characterized in that the second core sets and shares a data set that needs to be shared immediately in the first task processing in the first memory unit regardless of the second processing cycle.

7. The task processing device according to claim 1, wherein the first task processing is task processing that requires higher responsiveness than the second task processing.

8. The task processing device according to any one of claims 1 to 7, characterized in that the task processing device is used in a motor control device, an electric power steering device, or an electric actuator device.

9. A method for controlling a task processing device comprising: a first core that executes a first task processing in a first processing cycle; a second core that executes a second task processing in a second processing cycle that is longer than the first processing cycle; and a first memory unit provided on the first core side, wherein a data set relating to the results of the first task processing and the second task processing is set in the first memory unit and shared by the first core and the second core.

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