Systems and methods for traversing non-linearity of a mode boundary of a power converter

Abstract

A method for seamlessly traversing a non-linearity on a mode transition boundary of a power converter capable of operating in at least two distinct modes with distinct switching configurations may include maintaining a volt-second balance for the power converter across the mode transition boundary and maintaining an approximate capacitor charge balance for the power converter across the mode transition boundary.

Description

[0001] SYSTEMS AND METHODS FOR TRAVERSING NON-LINEARITY OF A MODE BOUNDARY OF A POWER CONVERTER

[0002] FIELD OF DISCLOSURE

[0003] The present disclosure relates in general to circuits for electronic devices, including without limitation personal audio devices such as wireless telephones and media players, and more specifically, systems and methods for traversing a non-linearity of a mode boundary of a power converter.

[0004] BACKGROUND

[0005] Personal audio devices, including wireless telephones, such as mobile / cellular telephones, cordless telephones, mp3 players, and other consumer audio devices, are in widespread use. Such personal audio devices may include circuitry for driving a pair of headphones, one or more speakers, haptic actuators, camera stabilization motors, and / or other loads. Such circuitry often includes a driver including a power amplifier for driving an output signal to such loads. Oftentimes, a power converter may be used to provide a supply voltage to a power amplifier in order to amplify a signal driven to speakers, headphones, other transducers, or other loads. A switching power converter is a type of electronic circuit that converts a source of power from one direct current (DC) voltage level to another DC voltage level. Examples of such switching DC-DC converters include but are not limited to a boost converter, a buck converter, a buck-boost converter, an inverting buck-boost converter, and other types of switching DC-DC converters. Thus, using a power converter, a DC voltage such as that provided by a battery may be converted to another DC voltage used to power the pow er amplifier. A power converter may be used to provide supply voltage rails to one or more components in a device. A powder converter may also be used in other applications besides driving audio transducers, such as driving haptic actuators or other electrical or electronic loads. Further, a power converter may also be used in charging a battery from a source of electrical energy (e.g., an AC-to-DC adapter), oftentimes as part of a pow er management integrated circuit (PMIC).

[0006] In applications in w hich the output and input voltages of a pow er converter may be expected to be close to one another, a four-switch buck-boost converter is often used. Use of a four-switch buck-boost converter may enable operating in a buck-boost mode when output voltage is close to input voltage and shifting to buck or boost modes when the output voltage is sufficiently separated from the input to improve efficiency.

[0007] The operation in buck-boost mode and transition into and out of buck-boost mode from the buck and boost modes may cause non-linearities in operation that may lead to ripple on the output voltage. In addition, a smooth transition into and out of buck-boost mode may be critical to minimize discontinuity on the output voltage. Further, continuous operation in the buck-boost mode at all times may not be an option to due negative impacts on efficiency.

[0008] In addition to buck-boost converters, other power converters may include similar non-linearities across mode boundaries.

[0009] In applications in which the output and input voltages of a power converter may be expected to be close to one another, a four-switch buck-boost converter is often used. Also in such applications and in applications requiring delivery of high power (e.g., greater than 50 W) at high input voltages (e.g., greater than 20 V), a six-switch three-level buck / two- level boost converter is often used. Use of such power converters may enable operating in a buck-boost mode when output voltage is close to input voltage and shifting to buck or boost modes when the output voltage is sufficiently separated from the input to improve efficiency.

[0010] The operation in buck-boost mode and transition into and out of buck-boost mode from the buck and boost modes may cause non-linearities in operation that may lead to ripple on the output voltage. In addition, a smooth transition into and out of buck-boost mode may be critical to minimize discontinuity on the output voltage.

[0011] In addition to four-switch buck-boost power converters and three-level buck / two- level boost converters, other power converters may include similar non-linearities across mode boundaries.

[0012] SUMMARY

[0013] In accordance with the teachings of the present disclosure, one or more disadvantages and problems associated with operation of power converters may be reduced or eliminated.

[0014] In accordance with embodiments of the present disclosure, a method for seamlessly traversing a non-linearity on a mode transition boundary of a power converter capable of operating in at least two distinct modes with distinct switching configurations may include maintaining a volt-second balance for the power converter across the mode transition boundary and maintaining an approximate capacitor charge balance for the power converter across the mode transition boundary.

[0015] In accordance with these and other embodiments of the present disclosure, a system may include a power converter capable of operating in at least two distinct modes with distinct switching configurations and control circuitry configured to seamlessly traverse a non-linearity on a mode transition boundary of the power converter by maintaining a volt- second balance for the power converter across the mode transition boundary and maintaining an approximate capacitor charge balance for the power converter across the mode transition boundary’.

[0016] In accordance with embodiments of the present disclosure, a system may include a multi-level buck-boost power converter configured to operate in a buck mode and a boost mode and a modulator configured to generate a plurality' of switch control signals for controlling switches of the multi-level buck-boost power converter, the modulator comprising a quantizer configured to maintain one or more of a volt-second balance for a power inductor of the power converter and a capacitor charge balance of a flying capacitor of the power converter across a mode transition boundary' between the buck mode and the boost mode.

[0017] In accordance with these and other embodiments of the present disclosure, a method may include, in a system having a multi-level buck-boost power converter configured to operate in a buck mode and a boost mode, generating, with a modulator, a plurality' of switch control signals for controlling switches of the multi-level buck-boost power converter and maintaining, with a quantizer of the modulator, one or more of a volt-second balance for a power inductor of the power converter and a capacitor charge balance of a flying capacitor of the power converter across a mode transition boundary between the buck mode and the boost mode.

[0018] Technical advantages of the present disclosure may be readily apparent to one skilled in the art from the figures, description and claims included herein. The objects and advantages of the embodiments will be realized and achieved at least by the elements, features, and combinations particularly pointed out in the claims.

[0019] It is to be understood that both the foregoing general description and the following detailed description are examples and explanatory and are not restrictive of the claims set forth in this disclosure.

[0020] BRIEF DESCRIPTION OF THE DRAWINGS

[0021] A more complete understanding of the present embodiments and advantages thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings, in which like reference numbers indicate like features, and wherein:

[0022] FIGURE 1 illustrates a circuit diagram of selected components of an example buckboost power converter, in accordance with embodiments of the present disclosure;

[0023] FIGURE 2 illustrates a block diagram of selected components of an example system for driving a load using a power converter, in accordance with embodiments of the present disclosure;

[0024] FIGURES 3A-3C illustrate operation of the example buck-boost power converter depicted in FIGURE 1 , in accordance with embodiments of the present disclosure;

[0025] FIGURE 4 illustrates example carrier wave signals for use by a modulator to generate switch control signals, in accordance with embodiments of the present disclosure;

[0026] FIGURE 5 illustrates example carrier wave signals and control signals generated therefrom by a modulator for a particular value for a reference signal, in accordance with embodiments of the present disclosure;

[0027] FIGURE 6A illustrates an example cunent waveform for an inductor current through a power inductor of a power converter with two magnetization phases, in accordance with embodiments of the present disclosure;

[0028] FIGURE 6B illustrates an example current waveform for an inductor current through a power inductor of a power converter with two demagnetization phases, in accordance with embodiments of the present disclosure;

[0029] FIGURE 6C illustrates an example current waveform for an inductor current through a power inductor of a power converter over two switching cycles, in accordance with embodiments of the present disclosure;

[0030] FIGURE 7 illustrates example components of an example modulator, in accordance with embodiments of the present disclosure;

[0031] FIGURE 8 illustrates w aveforms of an example mapping of a reference signal into two control variables for conversion into switch control signals, in accordance with embodiments of the present disclosure; FIGURE 9 illustrates example components of an example modulator, in accordance with embodiments of the present disclosure;

[0032] FIGURE 10 illustrates example piecewise carrier wave signals for use by a modulator to generate switch control signals, in accordance with embodiments of the present disclosure;

[0033] FIGURE 11A illustrates example carrier wave signals for use by a modulator to generate intermediate switch control signals, in accordance with embodiments of the present disclosure;

[0034] FIGURE 11B illustrates example additional carrier wave signals for use by a modulator to generate intermediate switch control signals, in accordance with embodiments of the present disclosure;

[0035] FIGURE 12 illustrates a circuit diagram of selected components of an example three-level buck / two-level boost power converter, in accordance with embodiments of the present disclosure;

[0036] FIGURE 13 illustrates a block diagram of selected components of an example system for driving a load using a power converter, in accordance with embodiments of the present disclosure;

[0037] FIGURE 14A illustrates example carrier wave signals for use by a modulator to generate switch control signals, in accordance with embodiments of the present disclosure;

[0038] FIGURE 14B illustrates example carrier wave signals for use by a modulator to generate switch control signals, in accordance with embodiments of the present disclosure;

[0039] FIGURE 15 illustrates an example quantization scheme, in accordance with embodiments of the present disclosure;

[0040] FIGURE 16A illustrates an example waveform of a power inductor current over four switching cycles of a pow er converter within a buck-boost dead zone, in absence of the quantizer biasing, leading to two consecutive boost cycles followed by two consecutive buck cycles, in accordance with embodiments of the present disclosure; and

[0041] FIGURE 16B illustrates an example waveform of a power inductor current over four switching cycles of a power converter within the buck-boost dead zone, with quantizer biasing, leading to alternating buck and boost cycles, in accordance with embodiments of the present disclosure. DETAILED DESCRIPTION

[0042] FIGURE 1 illustrates a circuit diagram of selected components of an example buckboost power converter 100, in accordance with embodiments of the present disclosure. As shown in FIGURE 1. buck-boost power converter 100 may receive an input voltage VIN on an input capacitor 108 and have an output configured to generate an output voltage VOUT on an output capacitor 110 based on switching signals PWM1 and PWM2, which may comprise pulse-width modulation signals. Buck-boost power converter 100 may also include a power inductor 102. In addition, buck-boost power converter 100 may include a plurality of switches 106a. 106b. 106c, and 106d, wherein switch 106a is coupled between the input and a first terminal of power inductor 102, switch 106b is coupled between the first terminal of power inductor 102 and a ground voltage, switch 106c is coupled between the output and a second terminal of power inductor 102, and switch 106d is coupled between the second terminal of power inductor 102 and the ground voltage. In operation, switch 106a may be controlled by control signal PWM1, switch 106b may be controlled by a complement of control signal PWM1 (e.g., PWM1 '), switch 106c may be controlled by control signal PWM2, and switch 106d may be controlled by a complement of control signal PWM2 (e.g., PWM2') in order to drive a power inductor current II through power inductor 102 to regulate output voltage VOUT to a desired target voltage.

[0043] FIGURE 2 illustrates a block diagram of selected components of an example system 200 for driving a load 220 using power converter 100, in accordance with embodiments of the present disclosure. As shown in FIGURE 2, system 200 may include power converter 100, signal combiner 204. loop controller 206, modulator 210, and load 220. In some embodiments, system 200 depicted in FIGURE 2 may use a power converter other than power converter 100 depicted in FIGURE 1.

[0044] Signal combiner 204 may comprise any suitable system, device, or apparatus configured to calculate an error signal ERROR equal to the difference between a target signal TGT and a measured feedback signal MEAS. Target signal TGT may represent a target or desired value for any physical quantity within system 200, including without limitation output voltage VOUT. Likewise, measured feedback signal MEAS may comprise a measured value of such physical quantity (e.g., a measured value for output voltage VOUT). For purposes of clarity and exposition, circuitry for measuring measured feedback signal MEAS is not shown in FIGURE 2; however, system 200 may include such circuitry and those of skill in the art would readily have knowledge of how to implement such circuitry to measure measured feedback signal MEAS.

[0045] Loop controller 206 may comprise any system, device, or apparatus configured to implement a control loop to regulate measured feedback signal MEAS to track target signal TGT. For example, based on error signal ERROR, loop controller 206 may generate a reference signal D. Such reference signal D may represent, for example, a commanded duty cycle for power converter 100 to cause regulation of measured feedback signal MEAS to track target signal TGT. Loop controller 206 may be implemented with a proportional (P) controller, proportional-integral (PI) controller, proportional-differential (PD) controller, proportional-integral-differential (PID) controller, or any other suitable controller.

[0046] Modulator 210 may comprise any suitable system, device, or apparatus configured to receive reference signal D, and generate switching signals PWM1 and PWM2 for controlling switching of switches of power converter 100. In some embodiments, modulator 210 may comprise a pulse-width modulator.

[0047] Load 220 may include any appropriate electrical or electronic load that may be powered from power converter 100, including without limitation a rechargeable battery.

[0048] In operation, switches 106 may be controlled by modulator 210 to regulate output voltage VOUT to a desired target voltage. As shown in FIGURES 3A-3C, operation of power converter 100 may include cyclic, periodic commutation of switches 106 among a low-side buck state LSBk (shown in FIGURE 3 A), a high-side state HS (shown in FIGURE 3B), and a low-side boost-state LSBst (shown in FIGURE 3C).

[0049] For example, as shown in FIGURE 3A, in low-side buck state LSBk, switches 106b and 106c may be activated (and switches 106a and 106d deactivated), such that current flows from ground voltage to the output of power converter 100 through switch 106b, power inductor 102, and switch 106c. As another example, as shown in FIGURE 3B, in high-side buck state HS. switches 106a and 106c may be activated (and switches 106b and 106d deactivated), such that current flows from the input to the output of power converter 100 through switch 106a, power inductor 102, and switch 106c. As a further example, as shown in FIGURE 3C, in low-side boost state LSBst. switches 106a and 106d may be activated (and switches 106b and 106c deactivated), such that current flows from the input of power converter 100 to ground voltage through switch 106a, power inductor 102, and switch 106d.

[0050] FIGURE 4 illustrates example carrier wave signals CAR1 and CAR2 for use by modulator 210 to generate switch control signals PWM1 and PWM2, in accordance with embodiments of the present disclosure. Although FIGURE 4 shows carrier signals CAR1 and CAR2 as sawtooth waves, it is understood that carrier signals CAR1 and CAR2 may comprise any suitable waveform (e.g., triangle wave). As depicted in FIGURE 4, modulator 210 may compare reference signal D to each of CAR1 and CAR2 and based on the comparison, generate appropriate control signals PWM1 and PWM2 to cause switches 106 of power converter 100 to switch into a particular switch state. For example, when reference signal D is less than carrier signal CAR1 and carrier signal CAR2, modulator 210 may generate control signals PWM1 and PWM2 to cause switches 106 of power converter 100 to operate in low-side buck state LSBk. As another example, when reference signal D is greater than carrier signal CAR1 and less than carrier signal CAR2, modulator 210 may generate control signals PWM1 and PWM2 to cause switches 106 of power converter 100 to operate in high-side state HS. As a further example, when reference signal D is greater than carrier signal CAR1 and carrier signal CAR2. modulator 210 may generate control signals PWM1 and PWM2 to cause switches 106 of power converter 100 to operate in low- side boost state LSBst.

[0051] However, the modulation scheme shown in FIGURE 4 may have disadvantages. FIGURE 5 illustrates example carrier wave signals CAR1 and CAR2 (e.g., identical to those in FIGURE 4) and control signals PWM1 and PWM2 generated therefrom by modulator 210 for a particular value of reference signal D near D=l, in accordance with embodiments of the present disclosure. As show n in FIGURE 5, values of reference signal D near D=1 may lead to impractically short switch times which may not be supported by the process technology of switches 106 or other components of power converter 100 and / or system 200. Accordingly, modulation schemes for modulator 210 in which switching times are practically achievable, w hile also maintaining volt-second balance of power converter 100 and capacitor charge balance of capacitors 108 and 110 across the D=1 transition boundary may be desirable.

[0052] FIGURE 6A illustrates an example current waveform for power inductor current II through power inductor 102 of power converter 100 with two magnetization phases in a transition between buck and buck-boost operation, in accordance with embodiments of the present disclosure. As shown in FIGURE 6A, as opposed to the single magnetization phase / single demagnetization phase operation (with slopes m2 and m3 respectively for power inductor current II) of power converter 100 that may occur with the modulation scheme with the carrier waves of FIGURE 4, FIGURE 6A depicts two magnetization phases, one with a slope of mi for pow er inductor current II and another with a slope of m2 for power inductor current II, follow ed by a demagnetization phase with slope m3 for pow er inductor current II. In such operation, there may exist a difference A in power inductor current II at the end of a period of time Ton of the first magnetization phase in two- magnetization phase operation, as compared to at the end of the same period of time in single-magnetization phase operation. Likewise, there may exist a difference B in power inductor current II at its peak current value in two-magnetization phase operation as compared to its peak current in single-magnetization phase operation. In addition, there may be a difference in time AT at which the peak cunent value is reached in two- magnetization phase operation as compared to single-magnetization phase operation.

[0053] Given that A = B, then:

[0054] FIGURE 6B illustrates an example current waveform for pow er inductor current II through power inductor 102 of pow er converter 100 w ith tw o demagnetization phases in a transition between boost and buck-boost operation, in accordance with embodiments of the present disclosure. As shown in FIGURE 6B, as opposed to the single magnetization phase / single demagnetization phase operation (with slopes mi and m2 respectively for powder inductor current II) of powder converter 100 that may occur with the modulation scheme with the carrier waves of FIGURE 4, FIGURE 6B depicts tw o demagnetization phases, one with a slope of m2 for power inductor current II and another with a slope of m3 for power inductor current II, both preceded by a magnetization phase with slope mi for power inductor current II. In such operation, there may exist a difference A between power inductor current II at its peak current value in two-demagnetization phase operation as compared to its peak current in single-demagnetization phase operation. Likewise, there may exist a difference B in power inductor current II at a period of time Toff prior to the end of magnetization, in which time Toff may represent a duration of time of the second demagnetization phase in two-demagnetization phase operation. In addition, the magnetization phase during the single-demagnetization phase operation may occur over a period of time Ton, and there may exist a difference in time AT between duration of the magnetization phase in two-magnetization phase operation as compared to the duration of the magnetization time in single-magnetization phase operation. gly: D)Toff

[0055] The foregoing two-magnetization phase operation and two-magnetization phase operation for power inductor current II may thus achieve volt-second balance and minimize discontinuity between mode transitions of power converter 100.

[0056] While the approach described above with FIGURE 6B may achieve volt-second balance across mode transitions of power converter 100, it may not achieve capacitancecharge balance (i. e. , the amount of energy pushed at the buck / buck-boost boundary and / or the boost / buck-boost boundary may not match). This may occur because such approach may attempt to add the smallest possible durations for low-side buck state LSBk and low- side boost state LSBst. However, there may exist durations for low-side buck state LSBk and low-side boost state LSBst which may not only maintain volt-second balance but also minimize capacitance-charge imbalance. Such durations may be estimated as a function of input voltage VIN and output voltage VOUT. For example, referring to FIGURE 6C, period of time Ton may be calculated to ensure that the shaded area A in the left-side waveform of a switching cycle is equal to the shaded area B in the right-side waveform of a subsequent switching cycle to ensure capacitor-charge balance. Also, period of time Ton may be calculated to ensure volt-second balance acts as a lower limit on the allowed on-time. Accordingly, modulator 210 may be configured to generate control signals PWM1 and PWM2 in order to generate the power inductor current waveforms as described above.

[0057] FIGURE 7 illustrates example components of an example modulator 210A that may generate such power inductor current waveforms, in accordance with embodiments of the present disclosure. Modulator 210A may be used to implement modulator 210. As shown in FIGURE 7, modulator 210A may implement a mapping function 700 that maps reference signal D to control variables Di and D2. Such control variables Di and D2 may respectively be compared by comparators 702 and 704 to carrier signals CAR1 and CAR2 (e.g., which may be equivalent to carrier signals CAR1 and CAR2 shown in FIGURE 4). with control signals PWM1 and PWM2 generated based on the comparisons. For purposes of clarity and exposition, signal generators for generating carrier signals CAR1 and CAR2 are not shown in FIGURE 7. However, it is understood that modulator 210 may include such signal generators.

[0058] FIGURE 8 illustrates w aveforms of an example mapping of reference signal D into control variables Di and D2, in accordance with embodiments of the present disclosure. As shown in FIGURE 8, control variables Di and D2 may each be a function of reference signal D, with piecewise linear sections near transition regions of reference signal D, in order to minimize or eliminate non-linearities between mode transitions of power converter 100. For example, as show n in the example mappings of FIGURE 8, betw een values of reference signal D near zero to a value of Da, control variable Di may increase linearly from a value Dmin to value Da. Between values of reference signal D between value Daand 1, control variable Di may increase linearly from a value Dcto value Da. Between values of reference signal D between 1 and value Db, control variable Di may remain constant at value Da. Betw een values of reference signal D between value Db and 2, control variable Di may remain constant at 1.

[0059] Similarly, control variable D2 may have a similar mapping. In FIGURE 8, the mapping of control variable D2 is shown without its offset of its minimum value (e.g., 1). Thus, betw een values of reference signal D of 0 to a value of Da, control variable D2 may remain constant at 1. Betw een values of reference signal D betw een value Daand 1 , control variable D2 may remain constant at a value 1 + Dmin. Betw een values of reference signal D between 1 and value Db. control variable D2 may linearly increase from value 1+ Dmin to a value 1 + De. Between values of reference signal D between value Db and 2, control variable D2 may increase linearly from value 1 + Db to a value 1 + Dd less than 2. For values of reference signal D above 2, control variable D2 may remain constant at 2.

[0060] Alternatively to generating two control variables Di and D2 based on reference signal D. piecewise linear carrier signals may be used. FIGURE 9 illustrates example piecewise carrier wave signals CAR1 and CAR2 for use by modulator 210 to generate switch control signals PWM1 and PWM2, in accordance with embodiments of the present disclosure. However, as seen in FIGURE 9, such approach includes non-causal values of carrier wave signals CAR1 and CAR2 (i.e., carrier signals CAR1 and CAR2 may not be a mathematical function of time, given that at certain portions of their curves, carrier signals CAR1 and CAR2 may have more than one value at a given time).

[0061] To overcome such disadvantage, carrier wave signals CAR1 and CAR2 may each effectively be split into two carrier signals and fed to different comparators, with outputs of such comparators combined to generate control signals PWM1 and PWM2, as described in greater detail below.

[0062] FIGURE 10 illustrates example components of an example modulator 21 OB, in accordance with embodiments of the present disclosure. Modulator 210B may be used to implement modulator 210. As shown in FIGURE 10, modulator 21 OB may include a comparator 902 to compare reference signal D to a carrier signal CAR! A to generate an intermediate control signal PWM1 A, a comparator 904 to compare reference signal D to a carrier signal CAR1B to generate an intermediate control signal PWM1B, a comparator 906 to compare reference signal D to a carrier signal CAR2A to generate an intermediate control signal PWM2A, and a comparator 908 to compare reference signal D to a carrier signal CAR2B to generate an intermediate control signal PWM2B. Further, modulator 210B may include a signal combiner 910 configured to combine intermediate control signal PWM1A and intermediate control signal PWM1B to generate control signal PWM1, and a signal combiner 912 configured to combine intermediate control signal PWM2A and intermediate control signal PWM2B to generate control signal PWM2. For purposes of clarity and exposition, signal generators for generating carrier signals CAR1A, CAR1B, CAR2A, and CAR2B are not shown in FIGURE 10. However, it is understood that modulator 210B may include such signal generators.

[0063] FIGURE 11A illustrates example carrier wave signals CAR1A and CAR1B for use by modulator 210B to generate intermediate switch control signals PWM1 A and PWM1B, in accordance with embodiments of the present disclosure. As shown in FIGURE 1 1A, carrier signal CAR1A may only be applicable for values of reference signal D less than a threshold value (e.g., 0.9) while carrier signal CAR1B may only be applicable for values of reference signal D greater than or equal to such threshold value. As a result, comparison of reference signal D to carrier signals CAR1 A and CAR1B to generate intermediate switch control signals PWM1A and PWM1B, and the subsequent summation of intermediate switch control signals PWM1A and PWM1B to generate control signal PWM1 may result in the same practical effect as comparing reference signal D to non-causal carrier signal CAR1 shown in FIGURE 9.

[0064] Similarly, FIGURE 1 IB illustrates example carrier wave signals CAR2A and CAR2B for use by modulator 21 OB to generate intermediate switch control signals PWM2A and PWM2B, in accordance with embodiments of the present disclosure. As shown in FIGURE 11B, carrier signal CAR2A may only be applicable for values of reference signal D less than a threshold value (e.g., 1.1) while carrier signal CAR2B may only be applicable for values of reference signal D greater than or equal to such threshold value. As a result, comparison of reference signal D to carrier signals CAR2A and CAR2B to generate intermediate switch control signals PWM2A and PWM2B, and the subsequent summation of intermediate switch control signals PWM2A and PWM2B to generate control signal PWM2 may result in the same practical effect as comparing reference signal D to non-causal carrier signal CAR2 shown in FIGURE 9.

[0065] FIGURE 12 illustrates a circuit diagram of selected components of an example three-level buck / two-level boost power converter 1100, in accordance with embodiments of the present disclosure. As shown in FIGURE 12, power converter 1100 may receive an input voltage VIN on an input capacitor 1108 and have an output configured to generate an output voltage VOUT on an output capacitor 1110 based on switching signals PWM1, PWM2, AND PWM3, which may comprise pulse-width modulation signals. Power converter 1100 may also include a power inductor 1102. In addition, buck-boost power converter 1100 may include a plurality of switches 1106a, 1106b, 1106c, 1106d, 1106e, and 1106f, wherein switch 1106a is coupled between the input and a first terminal of a flying capacitor 1104, switch 1106b is coupled between the first terminal of flying capacitor 1104 and a first switching node SW1 (wherein first switching node SW1 is coupled to a first terminal of power inductor 1 102), switch 1 106c is coupled between first switching node SW1 and a second terminal of flying capacitor 1104, switch 1106d is coupled between the second terminal of flying capacitor 1104 and a ground voltage, switch 1106e is coupled between a second switching node SW2 at a second terminal of power inductor 1102 and the output, and switch 1106f is coupled between second switching node SW2 at the second terminal of power inductor 1102 and the ground voltage. In operation, switch 1106a may be controlled by control signal PWM1, switch 1106d may be controlled by a complement of control signal PWM1 (e.g., PWM1 '), switch 1106b may be controlled by control signal PWM2, switch 1106c may be controlled by a complement of control signal PWM2 (e.g., PWM2'). switch 1106f may be controlled by control signal PWM3. and switch 1106e may be controlled by a complement of control signal PWM3 (e.g., PWM3 ), in order to drive a power inductor current II through power inductor 1102 to regulate output voltage VOUT to a desired target voltage.

[0066] FIGURE 13 illustrates a block diagram of selected components of an example system 1200 for driving a load 1220 using power converter 1 100, in accordance with embodiments of the present disclosure. As shown in FIGURE 2, system 1200 may include power converter 1100, signal combiner 1204, loop controller 1206, modulator 1210, and load 1220. In some embodiments, system 1200 depicted in FIGURE 13 may use a power converter other than power converter 1100 depicted in FIGURE 12.

[0067] Loop controller 1206 may comprise any system, device, or apparatus configured to implement a control loop to regulate measured feedback signal MEAS to track target signal TGT. For example, based on error signal ERROR, loop controller 1206 may generate a reference signal D. Such reference signal D may represent, for example, a commanded duty cycle for power converter 1100 to cause regulation of measured feedback signal MEAS to track target signal TGT. In some embodiments, reference signal D may vary between values of 0 and 2, where the range of values 0 to 1 correspond to duty cycles of 0% and 100%, respectively, of buck operation of power converter 1100 and the range of values 1 to 2 correspond to duty cycles of 0% and 100%. respectively, of boost operation of power converter 1100. Loop controller 1206 may be implemented with a proportional (P) controller, proportional-integral (PI) controller, proportional-differential (PD) controller, proportional-integral-differential (PID) controller, or any other suitable controller. In some embodiments, a gain of loop controller 1206 may be modified based on a mode of operation (e g., buck mode or boost mode) of power converter 1100. In such embodiments, the loop gain may be a dynamic function that adapts to buck or boost operation of power converter 1100. One example of such a function is a function of the maxima of input voltage VIN and output voltage VOUT.

[0068] Modulator 1210 may comprise any suitable system, device, or apparatus configured to receive reference signal D, and generate switching signals PWM1, PWM2, and PWM3 for controlling switching of switches 1106a-1106f of power converter 1100. In some embodiments, modulator 1210 may comprise a pulse-width modulator. As shown in FIGURE 13, modulator 1210 may include a signal combiner 1222, an integrator 1224, a signal combiner 1226, a quantizer 1228. a signal combiner 1242. a signal combiner 1244, a multiplexer 1246, a multiplexer 1248, a comparator 1230, a comparator 1232, and a comparator 1234.

[0069] Signal combiner 1222 may comprise any suitable system, device, or apparatus configured to calculate an error signal equal to a difference between reference signal D and a quantized reference signal DQ output by quantizer 1228.

[0070] Integrator 1224 may comprise any suitable system, device, or apparatus configured to integrate the error signal in order to accumulate the error signal over time.

[0071] Signal combiner 1226 may comprise any suitable system, device, or apparatus configured to sum reference signal D with the accumulated error signal to generate an error adjusted reference signal D'.

[0072] Quantizer 1228 may comprise any system, device, or apparatus configured to generate a quantized reference signal DQ based on adjusted reference signal D'. In some embodiments, such quantization may be performed to avoid generation of control signals PWM1, PWM2, and PWM3 having impractically short switching times, and thus may constrain possible values of quantized reference signal DQ to avoid such impractically short switching times, with the quantization error being compensated for over time by the accumulated integration of error by integrator 1224. For example, for values of adjusted reference signal D' below7a buck limit DbuckMax (e.g.. 0.9) and above a boost limit DboostMin (e.g., 1.1), quantizer 1228 may simply pass the value of adjusted reference signal D' as quantized reference signal DQ. However, for values between buck limit DbuckMax and boost limit DboostMin (e.g., between 0.9 and 1.1). a buck-boost ‘‘dead zone’7may exist to where quantized reference signal DQ is forced to buck limit DbuckMax if adjusted reference signal D' is between buck limit DbuckMax (e.g., 0.9) and a buck- boost boundary Dbound (e.g., 1.0) and forced to boost limit DboostMin if adjusted reference signal D' is between buck-boost boundary Dbound (e.g., 1.0) and boost limit DboostMin (e.g., 1.1).

[0073] Further, as described in greater detail below, in order to minimize ripple on output voltage VOUT, quantizer 1228 may also be configured to, in certain situations, force buck operation of power converter 1100 when adjusted reference signal D' is above buck-boost boundary' Dbound (e.g., 1.0) and force boost operation of power converter 1100 when adjusted reference signal D' is below buck-boost boundary Dbound (e.g.. 1.0).

[0074] Signal combiner 1242 may comprise any suitable system, device, or apparatus configured to subtract an offset signal a from quantized reference signal DQ to provide compensation during the buck mode of operation for power converter 1100 to regulate a flying capacitor voltage VFLY across flying capacitor 1104 during the buck mode. Similarly, combiner 1244 may comprise any suitable system, device, or apparatus configured to sum offset signal a with quantized reference signal DQ to also provide compensation during the buck mode of operation for power converter 1100 to regulate a flying capacitor voltage VFLY across flying capacitor 1104 during the buck mode. Generation of offset signal a is known in the art and is beyond the scope of the present disclosure. For example, in some embodiments, offset signal a may be generated by a closed-loop controller configured to increase offset signal a when flying capacitor voltage VFLY is below' one-half of input voltage VIN and to decrease offset signal a when flying capacitor voltage VFLY is above one-half of input voltage VIN.

[0075] The use of offset signal a in alpha compensation of flying capacitor 1104 may only be relevant to three-level modes of operation of power converter 1100, such as the buck mode of operation of power converter 1100. Thus, the control loop (not shown) for generating offset signal a may be active in three-level modes of operation and may be disabled in two-level modes of operation (e.g.. such that offset signal a is zero in two-level modes). Further, in some embodiments, a gain adjustment may be applied to offset signal a or the control loop for generating offset signal a to fade out offset signal a while approaching the buck-boost boundary from a three-level mode to a tw o-level mode.

[0076] Multiplexer 1246 may comprise any suitable system, device, or apparatus configured to, when quantized reference signal DQ is greater than or equal to buck-boost boundary Dbound (e.g., 1.0), pass the value of the buck-boost boundary Dbound (e g., 1.0) as a reference signal REFI, and when quantized reference signal DQ is lesser than buckboost boundary' Dbound (e.g., 1.0), pass the difference of quantized reference signal DQ and offset signal a (e.g., DQ - a) as reference signal REFI.

[0077] Similarly, multiplexer 1248 may comprise any suitable system, device, or apparatus configured to, when quantized reference signal DQ is greater than or equal to buck-boost boundary' Dbound (e.g., 1.0), pass the value of the buck-boost boundary' Dbound (e.g., 1.0) as a reference signal REF2, and when quantized reference signal DQ is lesser than buckboost boundary Dbound (e.g., 1.0), pass the sum of quantized reference signal DQ and offset signal a (e.g., DQ + a) as reference signal REF2.

[0078] Notably, reference signal REF3 may be equal to quantized reference signal DQ.

[0079] Comparator 1230 may comprise any system, device, or apparatus configured to compare reference signal REFI to a carrier signal CAR1 and generate control signal PWM1 based on such comparison, as described in greater detail below.

[0080] Similarly, comparator 1232 may comprise any system, device, or apparatus configured to compare reference signal REF2 to a carrier signal CAR2 and generate control signal PWM2 based on such comparison, as described in greater detail below.

[0081] Additionally, comparator 1234 may comprise any system, device, or apparatus configured to compare reference signal REF3 to a carrier signal CAR3 and generate control signal PWM3 based on such comparison, as described in greater detail below .

[0082] Load 1220 may include any appropriate electrical or electronic load that may be powered from power converter 1100, including without limitation a rechargeable battery.

[0083] In operation, switches 1106 may be controlled by modulator 1210 to regulate output voltage VOUT to a desired target voltage. Operation of power converter 1100 may include cyclic, periodic commutation of switches 1106 among a plurality of switching configurations, as described in greater detail below'.

[0084] FIGURE 14A illustrates example carrier wave signals CAR1, CAR2, and CAR3 for use by modulator 1210 to generate switch control signals PWM1. PWM2, and PWM3 in accordance with embodiments of the present disclosure. As depicted in FIGURE 14A, modulator 1210 may reference signals REFI, REF2, and REF3 respectively to carrier signals. CARL CAR2, and CAR3 based on the comparisons, generate appropriate control signals PWM1, PWM2, and PWM3 to cause switches 1106a-1106f of power converter 1 100 to switch into a particular switch state. For example, when quantized reference signal DQ is less than buck-boost boundary Dbound (e.g., 1.0), and power converter 1100 is operating in the buck mode, reference signal REF3 may be at all times less than carrier signal CAR3, such that control signal PWM3 remains off during the buck mode. With control signal PWM3 remaining off during the buck mode, switch 1106e may remain enabled (e.g.. on. activated, closed) during the buck mode while switch 1106f may remain disabled (e.g., off, deactivated, closed) during the buck mode. Further, as shown in FIGURE 14A, in the buck mode, power converter 1100 may cycle through a repeating sequence of switch configurations in the order of a VS configuration, a VCS configuration, the VS configuration, and a GCS configuration.

[0085] The VS configuration may occur when reference signal REF 1 is greater than carrier signal CAR1 and reference signal REF2 is greater than carrier signal CAR2. In the VS configuration, switches 1106a, 1106b, and 1106e may be enabled and switches 1106c, 1106d, and 1106f may be disabled.

[0086] The VCS configuration may occur when reference signal REFI is lesser than carrier signal CAR1 and reference signal REF2 is greater than carrier signal CAR2. In the VCS configuration, switches 1106a, 1106c, and 1106e may be enabled and switches 1106b, 1106d, and 1106f may be disabled.

[0087] The GCS configuration may occur when reference signal REFI is greater than carrier signal CAR1 and reference signal REF2 is lesser than carrier signal CAR2. In the VS configuration, switches 1106b, 1106d, and 1106e may be enabled and switches 1106a, 1106c, and 1106f may be disabled.

[0088] The acronyms VS. VCS, and GCS stand for the path of current in each of the respective configurations, wherein “V” stands for the voltage supply, "‘C” stands for flying capacitor 1104, “S” stands for the switching node, and “G” stands for ground voltage.

[0089] As another example, when quantized reference signal DQ is greater than buck-boost boundary Dbound (e.g., 1.0), and power converter 1100 is operating in the boost mode, reference signals REFI and REF2 may at all times be forced on by multiplexers 1246 and 1248, respectively, and thus control signals PWM1 and PWM2 remain on during the buck mode. With control signals PWM1 and PWM2 remaining on during the boost mode, switches 1106a and 1106b may remain enabled during the boost mode while switches 1106c and 1106d may remain disabled during the boost mode. Further, as shown in FIGURE 14A, in the boost mode, power converter 1100 may cycle through a repeating sequence of alternating high-side (HS) and low-side (LS) switch configurations.

[0090] The HS configuration may occur when reference signal REF3 is lesser than carrier signal CAR3. In the HS configuration, switches 1106a, 1106b, and 1106e may be enabled and switches 1106c, 1106d, and 1106f may be disabled. Notably, the switch states of the HS configuration may be the same as the earlier-described VS configuration.

[0091] The LS configuration may occur when reference signal REF3 is greater than carrier signal CAR3. In the LS configuration, switches 1106a, 1106b, and 1106f may be enabled and switches 1106c, 1106d, and 1106e may be disabled.

[0092] FIGURE 14B illustrates example carrier wave signals CARL CAR2, and CAR3 for use by modulator 1210 to generate switch control signals PWM1, PWM2, and PWM3 in accordance with embodiments of the present disclosure. The carrier scheme is FIGURE 14B is similar to that of FIGURE 14A with the exception that carrier signal CAR3 is a sawtooth wave in FIGURE 14B as opposed to a triangle wave in FIGURE 14A. Although FIGURES 14A and 14B show carrier signals CAR1, CAR2, and CAR3 being implemented as certain types of w aves, it is understood that carrier signals CAR1, CAR2 and CAR3 may each comprise any suitable waveform (e.g., triangle wave).

[0093] As mentioned above, quantizer 1228 may be “biased” in certain situations to force buck operation of power converter 1100 when adjusted reference signal D' is above buckboost boundary' Dbound (and would otherw ise operate in boost operation with an unbiased, conventional quantizer) or to force boost operation of power converter 1100 w hen adjusted reference signal D' is below buck-boost boundary Dbound (and would otherwise operate in buck operation with an unbiased, conventional quantizer). To that end, FIGURE 15 illustrates an example quantization scheme that may be implemented by quantizer 1228, in accordance w ith embodiments of the present disclosure.

[0094] As shown in FIGURE 15, for values of adjusted reference signal D' equal to or less than buck limit DbuckMax (e.g., 0.9), quantizer 1228 may generate quantized reference signal DQ equal to adjusted reference signal D', causing a buck switching cycle for power converter 1100. For values of adjusted reference signal D' greater than buck limit DbuckMax (e.g., 0.9), but lesser than a buck-bias threshold DbuckBias (e.g.. 0.95), quantizer 1228 may generate quantized reference signal DQ equal to buck limit DbuckMax (e.g., 0.9), causing a buck switching cycle for power converter 1 100. For values of adjusted reference signal D' greater than or equal to buck-bias threshold DbuckBias (e.g., 0.95), but less than buck-boost boundary Dbound (e.g., 1.0), quantizer 1228 may: (a) if the previous cycle of power converter 1100 was a buck cycle, generate quantized reference signal DQ equal to boost limit DboostMin (e.g., 1.1), causing a boost switching cycle for power converter 1100; and (b) if the previous cycle of power converter 1100 was a boost cycle, generate quantized reference signal DQ equal to buck limit DbuckMax (e.g., 0.9), causing a buck switching cycle for power converter 1100.

[0095] Similarly, for values of adjusted reference signal D' greater than or equal to buckboost boundary Dbound (e.g., 1.0), but less than or equal to a boost-bias threshold DboostBias (e.g., 1.05), quantizer 1228 may: (a) if the previous cycle of power converter 1100 was a boost cycle, generate quantized reference signal DQ equal to buck limit DbuckMax (e.g., 0.9), causing a buck switching cycle for power converter 1100; and (b) if the previous cycle of power converter 1100 was a buck cycle, generate quantized reference signal DQ equal to boost limit DboostMin (e.g., 1.1), causing a boost switching cycle for power converter 1100.

[0096] Stated another way, for values of adjusted reference signal D' greater than or equal to buck-bias threshold DbuckBias (e.g., 0.95) but lesser than boost-bias threshold DboostBias (e.g.. 1.05), quantizer 1228 may toggle quantized reference signal DQ between buck limit DbuckMax (e.g., 0.9) and boost limit DboostMin (e.g., 1. 1), to create alternating buck and boost switching cycles for power converter 1100.

[0097] Further, for values of adjusted reference signal D' greater than boost-bias threshold DboostBias (e.g., 1.05). but lesser or equal to than boost limit DboostMin (e.g.. 1.1), quantizer 1228 may generate quantized reference signal DQ equal to buck limit DboostMin (e.g., 1.1), causing a boost switching cycle for power converter 1100. Also, for values of adjusted reference signal D' greater than or equal to boost limit DboostMin (e.g., 1.1), quantizer 1228 may generate quantized reference signal DQ equal to adjusted reference signal D , causing a boost switching cycle for power converter 1100.

[0098] The foregoing quantization scheme applies a fixed / deterministic value to generate quantized reference signal DQ. However, in some embodiments, quantizer 1228 may apply a quantization scheme in which the value of quantized reference signal DQ is random when adjusted reference signal D' is greater than buck-bias threshold DbuckBias (e.g., 0.95) but lesser than boost-bias threshold DboostBias (e.g., 1.05) To illustrate the motivation for such biasing of quantizer 1228, reference is made to FIGURES 16A and 16B.

[0099] FIGURE 16A illustrates an example waveform of power inductor current II over four switching cycles of power converter 1100 within the buck-boost dead zone (and in particular the region in which adjusted reference signal D' is between buck-bias threshold DbuckBias and boost-bias threshold DboostBias), in absence of the biasing described above, leading to two consecutive boost cycles followed by two consecutive buck cycles, in accordance with embodiments of the present disclosure. Under such operation, a “conventional” quantizer may correct for cycle-to-cycle charge error and regulate the average of output voltage VOUT to its target voltage level. However, as seen from FIGURE 16 A, such operation may add high-frequency noise and successive buck or boost cycles may lead to substantial variation in power inductor current II.

[0100] FIGURE 16B illustrates an example waveform of power inductor current II over four switching cycles of power converter 1100 within the buck-boost dead zone (and in particular the region in which adjusted reference signal D' is between buck-bias threshold DbuckBias and boost-bias threshold DboostBias), with the biasing described above, leading to alternating buck and boost cycles, in accordance with embodiments of the present disclosure. As compared to FIGURE 16 A, FIGURE 16B demonstrates that the biased quantizer 1228 may lead to an improved volt-second balance for power inductor 1102 and a lower ripple in power inductor current II. Such improved volt-second balance and minimized ripple in power inductor current II may lead to lower ripple in output voltage VOUT.

[0101] Although the foregoing contemplates operation in the buck mode as a three-level power converter and operation in the boost mode as a two-level power converter, in some embodiments, switches 1106 and power inductor 1102 of power converter 1100 may be arranged for operation in the buck mode as a two-level power converter and operation in the boost mode as a three-level power converter. In other embodiments, switches 106 and power inductor 1102 of power converter 1100 may be arranged for operation in the buck mode as a three-level power converter and operation in the boost mode as a three-level power converter. In yet other embodiments, switches 1106 and power inductor 1102 of power converter 1100 may be arranged for operation in the buck mode as a two-level power converter and operation in the boost mode as a two-level power converter. As used herein, when two or more elements are referred to as "coupled" to one another, such term indicates that such two or more elements are in electronic communication or mechanical communication, as applicable, whether connected indirectly or directly, with or without intervening elements.

[0102] This disclosure encompasses all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Similarly, where appropriate, the appended claims encompass all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Moreover, reference in the appended claims to an apparatus or system or a component of an apparatus or system being adapted to, arranged to, capable of, configured to, enabled to, operable to, or operative to perform a particular function encompasses that apparatus, system, or component, whether or not it or that particular function is activated, turned on, or unlocked, as long as that apparatus, system, or component is so adapted, arranged, capable, configured, enabled, operable, or operative. Accordingly, modifications, additions, or omissions may be made to the systems, apparatuses, and methods described herein without departing from the scope of the disclosure. For example, the components of the systems and apparatuses may be integrated or separated. Moreover, the operations of the systems and apparatuses disclosed herein may be performed by more, fewer, or other components and the methods described may include more, fewer, or other steps. Additionally, steps may be performed in any suitable order. As used in this document, "each" refers to each member of a set or each member of a subset of a set.

[0103] Although exemplary embodiments are illustrated in the figures and described below, the principles of the present disclosure may be implemented using any number of techniques, whether currently known or not. The present disclosure should in no way be limited to the exemplary implementations and techniques illustrated in the drawings and described above.

[0104] Unless otherwise specifically noted, articles depicted in the drawings are not necessarily drawn to scale.

[0105] All examples and conditional language recited herein are intended for pedagogical objects to aid the reader in understanding the disclosure and the concepts contributed by the inventor to furthering the art, and are construed as being without limitation to such specifically recited examples and conditions. Although embodiments of the present disclosure have been described in detail, it should be understood that various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the disclosure. Although specific advantages have been enumerated above, vanous embodiments may include some, none, or all of the enumerated advantages. Additionally, other technical advantages may become readily apparent to one of ordinary' skill in the art after review of the foregoing figures and description.

[0106] To aid the Patent Office and any readers of any patent issued on this application in interpreting the claims appended hereto, applicants wish to note that they do not intend any of the appended claims or claim elements to invoke 35 U.S.C. § 112(f) unless the words “means for” or “step for” are explicitly used in the particular claim.

Claims

WHAT IS CLAIMED IS:

1. A method for seamlessly traversing a non-linearity on a mode transition boundary of a power converter capable of operating in at least two distinct modes with distinct switching configurations, comprising: maintaining a volt-second balance for the power converter across the mode transition boundary'; and maintaining an approximate capacitor charge balance for the power converter across the mode transition boundary.

2. The method of Claim 1, wherein maintaining the volt-second balance and maintaining the approximate capacitor charge balance further comprises using a digital pulse-width modulation scheme that generates one or more switch control signals for switching switches of the power converter among the switching configurations.

3. The method of Claim 2, wherein using the digital pulse-width modulation scheme comprises: mapping a primary control value for controlling the power converter into a first control variable and a second control variable; comparing the first control variable to a first pulse-width modulation carrier to generate a first switch control signal of the one or more switch control signals; and comparing the second control variable to a second pulse-width modulation carrier to generate a second switch control signal of the one or more switch control signals.

4. The method of Claim 3, wherein the primary' control variable is representative of a duh’ cycle of the power converter.

5. The method of Claim 4, wherein: the first switch control signal is a first duty cycle for one or more first switches of the power converter; and the second switch control signal is a second duty cycle for one or more second switches of the power converter.

6. The method of Claim 5, wherein: the one or more first switches comprise a first set of complementary switches; and the one or more second switches comprise a second set of complementary switches.

7. The method of Claim 6, further comprising dynamically modifying the first duty cycle and the second duty cycle around the mode transition boundary to ensure one or more of: a volt-second balance for the power converter across the mode transition boundary; a capacitor charge balance for the power converter across the mode transition boundary; and practically realizable switching times for switches of the power converter.

8. The method of Claim 7, wherein dynamically modifying the first duty cycle and the second duty cycle comprises making non-linear modifications to the first duty cycle and the second duty cycle.

9. The method of Claim 8, wherein dynamically modifying the first duty cycle and the second duty cycle comprises making step adjustments to the first duty cycle and the second duty cycle.

10. The method of Claim 8, wherein dy namically modifying the first duty cycle and the second duty cycle results in introduction of an additional switching phase during a switching cycle of the pow er converter.

11. The method of any of Claims 3-10, w herein: the first pulse-width modulation carrier is piecewise linear; and the second pulse-width modulation carrier is piecewise linear.

12. The method of Claim 11, wherein: the first pulse-width modulation carrier has step discontinuities; and the second pulse-width modulation carrier has step discontinuities.T113. The method of Claim 12, wherein: the first pulse-width modulation carrier is a combination of a first set of multiple individual linear sections; and the second pulse-width modulation carrier is a combination of a second set of multiple individual linear sections.

14. The method of any of Claims 1-13, wherein the non-linearity is traversed while maintaining on and off times of switches of the power converter above a predetermined threshold.

15. The method of any of Claims 1-14, wherein the power converter is a buckboost converter.

16. The method of Claim 15, wherein the seamless transition occurs across the buck-boost mode boundary by introducing an additional switching phase to a switching cycle of the power converter.

17. A system comprising: a power converter capable of operating in at least two distinct modes with distinct switching configurations; and control circuitry configured to seamlessly traverse a non-linearity on a mode transition boundary’ of the power converter by: maintaining a volt-second balance for the power converter across the mode transition boundary'; and maintaining an approximate capacitor charge balance for the power converter across the mode transition boundary.

18. The system of Claim 17, wherein maintaining the volt-second balance and maintaining the approximate capacitor charge balance further comprises using a digital pulse-width modulation scheme that generates one or more switch control signals for switching switches of the power converter among the switching configurations.

19. The system of Claim 18, wherein using the digital pulse-width modulation scheme comprises: mapping a primary control value for controlling the power converter into a first control variable and a second control variable; comparing the first control variable to a first pulse-width modulation carrier to generate a first switch control signal of the one or more switch control signals; and comparing the second control variable to a second pulse-width modulation carrier to generate a second switch control signal of the one or more switch control signals.

20. The system of Claim 19, wherein the primary control variable is representative of a duty cycle of the powder converter.

21. The system of Claim 20, wherein: the first switch control signal is a first duty cycle for one or more first switches of the pow er converter; and the second switch control signal is a second duty cycle for one or more second switches of the power converter.

22. The system of Claim 21, wherein: the one or more first switches comprise a first set of complementary switches; and the one or more second switches comprise a second set of complementary switches.

23. The system of Claim 22, the control circuitry further configured to dynamically modify the first duty cycle and the second duty cycle around the mode transition boundary’ to ensure one or more of: a volt-second balance for the power converter across the mode transition boundary; a capacitor charge balance for the power converter across the mode transition boundary ; and practically realizable switching times for switches of the power converter.

24. The system of Claim 23, wherein dynamically modifying the first duty cycle and the second duty cycle comprises making non-linear modifications to the first duty cycle and the second duty cycle.

25. The system of Claim 24, wherein dynamically modifying the first duty cycle and the second duty cycle comprises making step adjustments to the first duty cycle and the second duty cycle.

26. The system of Claim 24, wherein dynamically modifying the first duty cycle and the second duty cycle results in introduction of an additional switching phase during a switching cycle of the power converter.

27. The system of any of Claims 19-26, wherein: the first pulse-width modulation carrier is piecewise linear; and the second pulse-width modulation carrier is piecewise linear.

28. The system of Claim 27, wherein: the first pulse-width modulation carrier has step discontinuities; and the second pulse-width modulation carrier has step discontinuities.

29. The system of Claim 28, wherein: the first pulse-width modulation carrier is a combination of a first set of multiple individual linear sections; and the second pulse-width modulation carrier is a combination of a second set of multiple individual linear sections.

30. The system of aby of Claims 17-29, wherein the non-linearity is traversed while maintaining on and off times of switches of the power converter above a predetermined threshold.

31. The system of any of Claims 17-30, wherein the power converter is a buckboost converter.

32. The system of Claim 31, wherein the seamless transition occurs across the buck-boost mode boundary7by introducing an additional switching phase to a switching cycle of the power converter.

33. A system comprising: a multi-level buck-boost power converter configured to operate in a buck mode and a boost mode; and a modulator configured to generate a plurality of switch control signals for controlling switches of the multi-level buck-boost power converter, the modulator comprising a quantizer configured to maintain one or more of a volt-second balance for a power inductor of the power converter and a capacitor charge balance of a flying capacitor of the power converter across a mode transition boundary between the buck mode and the boost mode.

34. The system of Claim 33, wherein the multi-level buck-boost power converter operates as a three-level power converter in the buck mode and as a two-level power converter in the boost mode.

35. The system of Claim 33, wherein the multi-level buck-boost power converter operates as a two-level power converter in the buck mode and as a three-level power converter in the boost mode.

36. The system of Claim 33, wherein the multi-level buck-boost power converter operates as a two-level power converter in the buck mode and as a two-level power converter in the boost mode.

37. The system of Claim 33, wherein the multi-level buck-boost power converter operates as a three-level power converter in the buck mode and as a three-level power converter in the boost mode.

38. The system of any of Claims 33-37, wherein maintaining one or more of a volt-second balance for a power inductor of the power converter and a capacitor charge balance of a flying capacitor of the power converter comprises using a digital pulse-width modulation scheme that generates one or more switch control signals for switching switches of the power converter among switching configurations.

39. The system of Claim 38, wherein using the digital pulse-width modulation scheme comprises: comparing a first primary control value generated by the quantizer to a first pulsewidth modulation carrier to generate a first swatch control signal of the plurality of switch control signals, the first switch control signal for operation in the buck mode; and comparing a second primary control value generated by the quantizer to a second pulse-width modulation carrier to generate a second switch control signal of the plurality of switch control signals, the second switch control signal for operation in the boost mode.

40. The system of Claim 39, wherein using the digital pulse-width modulation scheme further comprises comparing the first primary control value generated by the quantizer to a second pulse-width modulation carrier to generate a third switch control signal of the plurality7of switch control signals, the third switch control signal for operation in the buck mode.

41. The system of Claim 39, wherein using the digital pulse-width modulation scheme further comprises comparing the second primary7control value generated by the quantizer to a second pulse-width modulation carrier to generate a third switch control signal of the plurality of switch control signals, the third switch control signal for operation in the boost mode.

42. The system of any of Claims 39-41, wherein the first primary control variable and the second primary7control variable are representative of a duty7cycle of the multi-level buck-boost power converter.

43. The system of any of Claims 33-42, further comprising a control loop for controlling an offset signal for regulating a voltage on a flying capacitor of the multi-level buck-boost power converter.

44. The system of Claim 43, wherein the control loop is active during three- level modes of the multi-level buck-boost power converter and inactive during two-level modes of the multi-level buck-boost power converter.

45. The system of Claim 44. further comprising a gain adjustment configured to apply a gain to the offset signal to fade the offset signal when approaching the buckboost boundary' from a three-level mode.

46. The system of any of Claims 33-45, wherein the modulator comprises a quantized delta-sigma modulator.

47. The system of Claim 46, wherein a gain of a loop controller of the quantized delta-sigma modulator is modified based on a mode of operation of the multi-level buckboost power converter.

48. The system of Claim 47, wherein the gain is a dynamic function that adapts to buck operation or boost operation of the multi-level buck-boost power converter.

49. The system of Claim 48, wherein the dynamic function is a function of maxima of an input voltage and an output voltage of the multi-level buck-boost power converter.

50. The system of any of Claims 33-49, wherein the quantizer is further configured to, for a range of values of the control variable within a predetermined difference from a boundary of the control variable between the boost mode and the buck mode, bias the control variable by a bias amount to:increase a probability of operating the switching circuit in the boost mode for a switching cycle if a previous switching cycle of the switching circuit was in the buck mode; and increase a probability of operating the switching circuit in the buck mode for the switching cycle if the previous switching cycle of the switching circuit was in the boost mode.

51. The system of Claim 50, wherein the bias amount is a fixed value.

52. The system of Claim 50, wherein the bias amount is a random value.

53. A method comprising, in a system having a multi-level buck-boost power converter configured to operate in a buck mode and a boost mode: generating, with a modulator, a plurality of switch control signals for controlling switches of the multi-level buck-boost power converter; and maintaining, with a quantizer of the modulator, one or more of a volt-second balance for a power inductor of the power converter and a capacitor charge balance of a flying capacitor of the power converter across a mode transition boundary between the buck mode and the boost mode.

54. The method of Claim 53, wherein the multi-level buck-boost power converter operates as a three-level power converter in the buck mode and as a two-level power converter in the boost mode.

55. The method of Claim 53, wherein the multi-level buck-boost power converter operates as a two-level power converter in the buck mode and as a three-level power converter in the boost mode.

56. The method of Claim 53, wherein the multi-level buck-boost power converter operates as a two-level power converter in the buck mode and as a two-level power converter in the boost mode.

57. The method of Claim 53, wherein the multi-level buck-boost power converter operates as a three-level power converter in the buck mode and as a three-level power converter in the boost mode.

58. The method of any of Claims 53-57, wherein maintaining one or more of a volt-second balance for a power inductor of the power converter and a capacitor charge balance of a flying capacitor of the power converter comprises using a digital pulse-width modulation scheme that generates one or more switch control signals for switching switches of the power converter among switching configurations.

59. The method of Claim 58, wherein using the digital pulse-width modulation scheme comprises: comparing a first primary control value generated by the quantizer to a first pulsewidth modulation carrier to generate a first switch control signal of the plurality of switch control signals, the first switch control signal for operation in the buck mode; and comparing a second primary control value generated by the quantizer to a second pulse-width modulation carrier to generate a second switch control signal of the plurality of switch control signals, the second switch control signal for operation in the boost mode.

60. The method of Claim 59, wherein using the digital pulse-width modulation scheme further comprises comparing the first primary control value generated by the quantizer to a second pulse-width modulation earner to generate a third switch control signal of the plurality of switch control signals, the third switch control signal for operation in the buck mode.

61. The method of Claim 59, wherein using the digital pulse-width modulation scheme further comprises comparing the second primary control value generated by the quantizer to a second pulse-width modulation carrier to generate a third switch control signal of the plurality of switch control signals, the third switch control signal for operation in the boost mode.

62. The method of any of Claims 59-61, wherein the first primary control variable and the second primary control variable are representative of a duty cycle of the multi-level buck-boost power converter.

63. The method of any of Claims 53-62. further comprising controlling, with a control loop, an offset signal for regulating a voltage on a flying capacitor of the multi-level buck-boost power converter.

64. The method of Claim 63, wherein the control loop is active during three- level modes of the multi-level buck-boost power converter and inactive during two-level modes of the multi-level buck-boost power converter.

65. The method of Claim 64, further comprising applying a gain to the offset signal to fade the offset signal when approaching the buck-boost boundary from a three- level mode.

66. The method of any of Claims 53-65, wherein the modulator comprises a quantized delta-sigma modulator.

67. The method of Claim 66, further comprising modifying a gain of a loop controller of the quantized delta-sigma modulator based on a mode of operation of the multi-level buck-boost power converter.

68. The method of Claim 67, wherein the gain is a dynamic function that adapts to buck operation or boost operation of the multi-level buck-boost power converter.

69. The method of Claim 68, wherein the dynamic function is a function of maxima of an input voltage and an output voltage of the multi-level buck-boost power converter.

70. The method of any of Claims 63-69, further comprising, for a range of values of the control variable within a predetermined difference from a boundary' of thecontrol variable between the boost mode and the buck mode, biasing the control variable, with the quantizer, by a bias amount to: increase a probability of operating the switching circuit in the boost mode for a switching cycle if a previous switching cycle of the switching circuit was in the buck mode; and increase a probability of operating the switching circuit in the buck mode for the switching cycle if the previous switching cycle of the switching circuit was in the boost mode.

71. The method of Claim 70, wherein the bias amount is a fixed value.

72. The method of Claim 70, wherein the bias amount is a random value.

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