Driver circuit, driver module, and display apparatus

Abstract

Provided are a driver circuit, a driver module, and a display apparatus. The driver circuit comprises a first noise reduction circuit, a second noise reduction circuit (12), and an output noise reduction circuit (13); the first noise reduction circuit comprises a first noise reduction control circuit (11) and a first transistor (M1); a gate of the first transistor (M1) and a second electrode of the first transistor (M1), both being electrically connected to a first noise reduction node (PD1), and a first electrode of the first transistor (M1), which is electrically connected to a first noise reduction clock signal line (CK1); the first noise reduction control circuit (11), under the control of a first noise reduction clock signal and a potential of a first node (PU), controls a potential of the first noise reduction node (PD1); the second noise reduction circuit (12), under the control of a noise reduction control signal and the potential of the first node (PU), controls a potential of a second noise reduction node (PD2); and the output noise reduction circuit (13), under the control of the potential of the first noise reduction node (PD1) and the potential of the second noise reduction node (PD2), performs noise reduction on a drive signal. A display apparatus using a driver circuit allows for a narrow bezel.

Description

Driving circuit, driving module and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a driving circuit, a driving module, and a display device. Background Art

[0002] In recent years, with the development of display technology and people's demand for advancements in display technology, narrow-border LCDs have become a trend.

[0003] In relevant display panels, a GOA (Gate On Array, a gate drive circuit arranged on an array substrate) module is used. The GOA module integrates the gate drive circuit on the array substrate of the display panel to achieve the purpose of high integration and low cost. At the same time, due to the requirements of product reliability, the GOA module uses more signal lines and the gate drive circuit structure design is complex, which causes it to occupy a larger space on the display panel, which is not conducive to the narrow frame design of the display panel.

[0004] Summary of the Invention

[0005] In a first aspect, an embodiment of the present disclosure provides a driving circuit including a first noise reduction circuit, a second noise reduction circuit, and an output noise reduction circuit;

[0006] The first noise reduction circuit includes a first noise reduction control circuit and a first transistor;

[0007] The gate of the first transistor and the second electrode of the first transistor are both electrically connected to the first noise reduction node, and the first electrode of the first transistor is electrically connected to the first noise reduction clock signal line;

[0008] The first noise reduction control circuit is electrically connected to the first noise reduction clock signal line, the first noise reduction node, and the first node, respectively, and is configured to control the potential of the first noise reduction node under the control of the first noise reduction clock signal provided by the first noise reduction clock signal line and the potential of the first node;

[0009] The second noise reduction circuit is electrically connected to the noise reduction control line, the first node and the second noise reduction node, and is configured to control the potential of the second noise reduction node under the control of the noise reduction control signal provided by the noise reduction control line and the potential of the first node;

[0010] The output noise reduction circuit is electrically connected to the first noise reduction node, the second noise reduction node and the drive signal output end respectively, and is used to reduce the noise of the drive signal provided by the drive signal output end under the control of the potential of the first noise reduction node and the potential of the second noise reduction node.

[0011] Optionally, the noise reduction control line is a second noise reduction clock signal line.

[0012] Optionally, the noise reduction control line is a first voltage line.

[0013] Optionally, the first noise reduction control circuit is also electrically connected to the second voltage line, and is used to control the connection between the first noise reduction node and the first noise reduction clock signal line under the control of the first noise reduction clock signal, and to control the connection between the first noise reduction node and the second voltage line under the control of the potential of the first node.

[0014] Optionally, the second noise reduction circuit is also electrically connected to the second noise reduction control node and the second voltage line, respectively, and is used to control the connection between the second noise reduction control node and the second noise reduction clock signal line under the control of the first noise reduction clock signal, control the connection between the second noise reduction control node and the second voltage line under the control of the potential of the first node, control the connection between the second noise reduction node and the second noise reduction clock signal line under the control of the potential of the second noise reduction control node, and control the connection between the second noise reduction node and the second voltage line under the control of the potential of the first node.

[0015] Optionally, the second noise reduction circuit is also electrically connected to the second voltage line, and is used to control the connection between the noise reduction control line and the second noise reduction node under the control of the noise reduction control signal provided by the noise reduction control line, and to control the connection between the second noise reduction node and the second voltage line under the control of the potential of the first node.

[0016] Optionally, the second noise reduction circuit is also electrically connected to the second voltage line, and is used to control the connection between the second noise reduction node and the second noise reduction clock signal line under the control of the second noise reduction clock signal provided by the second noise reduction clock signal line, and to control the connection between the second noise reduction node and the second voltage line under the control of the potential of the first node, and to control the connection between the second noise reduction clock signal line and the second noise reduction node under the control of the potential of the second noise reduction node.

[0017] Optionally, the first noise reduction control circuit includes a second transistor and a third transistor;

[0018] The gate of the second transistor and the first electrode of the second transistor are electrically connected to the first noise reduction clock signal line, and the second electrode of the second transistor is electrically connected to the first noise reduction node;

[0019] A gate of the third transistor is electrically connected to the first node, a first electrode of the third transistor is electrically connected to the first noise reduction node, and a second electrode of the third transistor is electrically connected to the second voltage line.

[0020] Optionally, the second noise reduction circuit includes a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor;

[0021] The gate of the fourth transistor and the first electrode of the fourth transistor are electrically connected to the second noise reduction clock signal line, and the second electrode of the fourth transistor is electrically connected to the second noise reduction control node;

[0022] The gate of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the second noise reduction control node, and the second electrode of the fifth transistor is electrically connected to the second voltage line;

[0023] The gate of the sixth transistor is electrically connected to the second noise reduction control node, the first electrode of the sixth transistor is electrically connected to the second noise reduction clock signal line, and the second electrode of the sixth transistor is electrically connected to the second noise reduction node;

[0024] A gate of the seventh transistor is electrically connected to the first node, a first electrode of the seventh transistor is electrically connected to the second noise reduction node, and a second electrode of the seventh transistor is electrically connected to the second voltage line.

[0025] Optionally, the second noise reduction circuit includes a fourth transistor and a fifth transistor;

[0026] The gate of the fourth transistor and the first electrode of the fourth transistor are both electrically connected to the noise reduction control line, and the second electrode of the fourth transistor is electrically connected to the second noise reduction node;

[0027] A gate of the fifth transistor is electrically connected to the first node, a first electrode of the fifth transistor is electrically connected to the second noise reduction node, and a second electrode of the fifth transistor is electrically connected to the second voltage line.

[0028] Optionally, the second noise reduction circuit includes a fourth transistor, a fifth transistor and a sixth transistor;

[0029] The gate of the fourth transistor and the first electrode of the fourth transistor are electrically connected to the second noise reduction clock signal line, and the second electrode of the fourth transistor is electrically connected to the second noise reduction node;

[0030] The gate of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the second noise reduction node, and the second electrode of the fifth transistor is electrically connected to the second voltage line;

[0031] A gate electrode of the sixth transistor and a second electrode of the sixth transistor are both electrically connected to a second noise reduction node, and a first electrode of the sixth transistor is electrically connected to the second noise reduction node.

[0032] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a carry output circuit, a carry reset circuit and a driving output circuit;

[0033] The carry output circuit is electrically connected to the first node, the output clock signal line and the carry signal output terminal respectively, and is used to control the communication between the carry signal output terminal and the output clock signal line under the control of the potential of the first node;

[0034] The carry reset circuit is electrically connected to the first noise reduction node, the second noise reduction node, the carry signal output terminal, and a third voltage line, respectively, and is configured to control the communication between the carry signal output terminal and the third voltage line under the control of the potential of the first noise reduction node, and to control the communication between the carry signal output terminal and the third voltage line under the control of the potential of the second noise reduction node;

[0035] The drive output circuit is electrically connected to the first node, the drive signal output end and the output clock signal line respectively, and is used to control the connection between the drive signal output end and the output clock signal line under the control of the potential of the first node.

[0036] Optionally, the driving circuit described in at least one embodiment of the present disclosure further includes an energy storage circuit, a first node control circuit, and a noise reduction node control circuit;

[0037] The energy storage circuit is electrically connected to the first node and the drive signal output terminal respectively, and is used to store electrical energy;

[0038] The first node control circuit is electrically connected to the first input terminal, the second input terminal, the first node, the reset terminal, the first noise reduction node, the second noise reduction node, and the second voltage line, respectively, and is configured to control the connection between the first node and the second input terminal under the control of a first input signal provided by the first input terminal, control the connection between the first node and the second voltage line under the control of a reset signal provided by the reset terminal, control the connection between the first node and the second voltage line under the control of a potential of the first noise reduction node, and control the connection between the first node and the second voltage line under the control of a potential of the second noise reduction node;

[0039] The noise reduction node control circuit is electrically connected to the first noise reduction node, the second noise reduction node, the first input end and the second voltage line, respectively, and is used to control the connection between the first noise reduction node and the second voltage line, and control the connection between the second noise reduction node and the second voltage line under the control of the first input signal provided by the first input end.

[0040] Optionally, the first node control circuit is further electrically connected to a frame reset terminal, and is configured to control the connection between the first node and the second voltage line under the control of a frame reset signal provided by the frame reset terminal.

[0041] Optionally, the carry output circuit includes a carry output transistor, the carry reset circuit includes a first carry reset transistor and a second carry reset transistor, the drive output circuit includes a drive output transistor, and the output noise reduction circuit includes a first output noise reduction transistor and a second output noise reduction transistor;

[0042] The gate of the carry output transistor is electrically connected to the first node, the first electrode of the carry output transistor is electrically connected to the output clock signal line, and the second electrode of the carry output transistor is electrically connected to the carry signal output terminal;

[0043] The gate of the first carry reset transistor is electrically connected to the first noise reduction node, the first electrode of the first carry reset transistor is electrically connected to the carry signal output terminal, and the second electrode of the first carry reset transistor is electrically connected to the third voltage line;

[0044] a gate of the second carry reset transistor electrically connected to the second noise reduction node, a first electrode of the second carry reset transistor electrically connected to the carry signal output terminal, and a second electrode of the second carry reset transistor electrically connected to the third voltage line;

[0045] The gate of the driving output transistor is electrically connected to the first node, the first electrode of the driving output transistor is electrically connected to the output clock signal line, and the second electrode of the driving output transistor is electrically connected to the driving signal output terminal;

[0046] The gate of the first output noise reduction transistor is electrically connected to the first noise reduction node, the first electrode of the first output noise reduction transistor is electrically connected to the drive signal output terminal, and the second electrode of the first output noise reduction transistor is electrically connected to the third voltage line;

[0047] A gate of the second output noise reduction transistor is electrically connected to the second noise reduction node, a first electrode of the second output noise reduction transistor is electrically connected to the drive signal output terminal, and a second electrode of the second output noise reduction transistor is electrically connected to the third voltage line.

[0048] Optionally, the first node control circuit includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor; the noise reduction node control circuit includes a thirteenth transistor and a fourteenth transistor;

[0049] The gate of the eighth transistor is electrically connected to the first input terminal, the first electrode of the eighth transistor is electrically connected to the second input terminal, and the second electrode of the eighth transistor is electrically connected to the first node;

[0050] The gate of the ninth transistor is electrically connected to the reset terminal, the first electrode of the ninth transistor is electrically connected to the first node, and the second electrode of the ninth transistor is electrically connected to the second voltage line;

[0051] The gate of the tenth transistor is electrically connected to the first noise reduction node, the first electrode of the tenth transistor is electrically connected to the first node, and the second electrode of the tenth transistor is electrically connected to the second voltage line;

[0052] The gate of the eleventh transistor is electrically connected to the second noise reduction node, the first electrode of the eleventh transistor is electrically connected to the first node, and the second electrode of the eleventh transistor is electrically connected to the second voltage line;

[0053] The gate of the twelfth transistor is electrically connected to the frame reset terminal, the first electrode of the twelfth transistor is electrically connected to the first node, and the second electrode of the twelfth transistor is electrically connected to the second voltage line;

[0054] The gate of the thirteenth transistor is electrically connected to the first input terminal, the first electrode of the thirteenth transistor is electrically connected to the first noise reduction node, and the second electrode of the thirteenth transistor is electrically connected to the second voltage line;

[0055] A gate of the fourteenth transistor is electrically connected to the first input terminal, a first electrode of the fourteenth transistor is electrically connected to the second noise reduction node, and a second electrode of the fourteenth transistor is electrically connected to the second voltage line.

[0056] In a second aspect, an embodiment of the present disclosure provides a driving module comprising multiple stages of the above-mentioned driving circuits.

[0057] Optionally, the driving module includes 2N clock signal lines; N is a positive integer;

[0058] The driving circuit is the a-th level driving circuit included in the driving module; a is a positive integer;

[0059] The first noise reduction clock signal line is the N+ath clock signal line, and the second noise reduction clock signal line and the output clock signal line are the ath clock signal line.

[0060] Optionally, the driving circuit includes a carry signal output terminal, a first input terminal and a reset terminal;

[0061] The first input terminal of the a-th level driving circuit is electrically connected to the carry signal output terminal of the aN-th level driving circuit, and the reset terminal of the a-th level driving circuit is electrically connected to the carry signal output terminal of the a+N-th level driving circuit.

[0062] Optionally, the driving circuit further includes a second input terminal and a driving signal output terminal;

[0063] The second input terminal of the a-th stage driving circuit is electrically connected to the driving signal output terminal of the aN-th stage driving circuit or the carry signal output terminal of the aN-th stage driving circuit.

[0064] In a third aspect, an embodiment of the present disclosure provides a display device comprising the aforementioned driving module. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] FIG1 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0066] FIG2 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0067] FIG3 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0068] FIG4 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0069] FIG5 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0070] FIG6 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0071] FIG7 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0072] FIG8 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0073] FIG9 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0074] FIG10 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0075] FIG11 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0076] FIG12 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0077] FIG13 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0078] FIG14 is a timing diagram of clock signals used by a driving module according to at least one embodiment of the present disclosure;

[0079] FIG15 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0080] FIG16 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0081] FIG17 is a structural diagram of a driving module according to at least one embodiment of the present disclosure;

[0082] FIG18 is an operation timing diagram of the driving module according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0083] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0084] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0085] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0086] The driving circuit according to the embodiment of the present disclosure includes a first noise reduction circuit, a second noise reduction circuit and an output noise reduction circuit;

[0087] The first noise reduction circuit includes a first noise reduction control circuit and a first transistor;

[0088] The gate of the first transistor and the second electrode of the first transistor are both electrically connected to the first noise reduction node, and the first electrode of the first transistor is electrically connected to the first noise reduction clock signal line;

[0089] The first noise reduction control circuit is electrically connected to the first noise reduction clock signal line, the first noise reduction node, and the first node, respectively, and is configured to control the potential of the first noise reduction node under the control of the first noise reduction clock signal provided by the first noise reduction clock signal line and the potential of the first node;

[0090] The second noise reduction circuit is electrically connected to the noise reduction control line, the first node and the second noise reduction node, and is configured to control the potential of the second noise reduction node under the control of the noise reduction control signal provided by the noise reduction control line and the potential of the first node;

[0091] The output noise reduction circuit is electrically connected to the first noise reduction node, the second noise reduction node and the drive signal output end respectively, and is used to reduce the noise of the drive signal provided by the drive signal output end under the control of the potential of the first noise reduction node and the potential of the second noise reduction node.

[0092] In the driving circuit of at least one embodiment of the present disclosure, the first noise reduction circuit operates under the control of the first noise reduction clock signal provided by the first noise reduction clock signal line, and the second noise reduction circuit operates under the control of the noise reduction control signal provided by the noise reduction control line. The noise reduction control line can be a second noise reduction clock signal line or a first voltage line. The driving circuit described in at least one embodiment of the present disclosure does not use the first control voltage line VDDO and the second control voltage line VDDE, reducing the number of signal lines used, which is beneficial to reducing the space occupied by the driving module including the driving circuit, and is beneficial to achieving a narrow frame.

[0093] As shown in FIG1 , the driving circuit according to at least one embodiment of the present disclosure includes a first noise reduction circuit and a second noise reduction circuit 12 and an output noise reduction circuit 13 ;

[0094] The first noise reduction circuit includes a first noise reduction control circuit 11 and a first transistor M1;

[0095] The gate of the first transistor M1 and the source of the first transistor M1 are both electrically connected to the first noise reduction node PD1, and the drain of the first transistor M1 is electrically connected to the first noise reduction clock signal line CK1;

[0096] The first noise reduction control circuit 11 is electrically connected to the first noise reduction clock signal line CK1, the first noise reduction node PD1, and the first node PU, respectively, and is configured to control the potential of the first noise reduction node PD1 under the control of the first noise reduction clock signal provided by the first noise reduction clock signal line CK1 and the potential of the first node PU;

[0097] The second noise reduction circuit 12 is electrically connected to the noise reduction control line SC, the first node PU and the second noise reduction node PD2, and is configured to control the potential of the second noise reduction node PD2 under the control of the noise reduction control signal provided by the noise reduction control line SC and the potential of the first node PU;

[0098] The output noise reduction circuit 13 is electrically connected to the first noise reduction node PD1, the second noise reduction node PD2 and the drive signal output terminal GT, respectively, and is used to reduce the noise of the drive signal provided by the drive signal output terminal GT under the control of the potential of the first noise reduction node PD1 and the potential of the second noise reduction node PD2.

[0099] When at least one embodiment of the driving circuit shown in Figure 1 of the present disclosure is in operation, the first noise reduction control circuit 11 controls the potential of the first noise reduction node PD1 under the control of the first noise reduction clock signal and the potential of the first node PU, and the first transistor M1 controls the connection or disconnection between the first noise reduction node PD1 and the first noise reduction clock signal line CK1 under the control of the potential of the first noise reduction node PD1; the second noise reduction circuit 12 controls the potential of the second noise reduction node PD2 under the control of the noise reduction control signal and the potential of the first node PU; the output noise reduction circuit 13 performs noise reduction on the driving signal provided by the driving signal output terminal GT under the control of the potential of the first noise reduction node PD1 and the potential of the second noise reduction node PD2.

[0100] Optionally, the noise reduction control line is a second noise reduction clock signal line.

[0101] Optionally, the noise reduction control line is a first voltage line.

[0102] In a specific implementation, the noise reduction control line may be a second noise reduction clock signal line or a first voltage line. For example, the first voltage line may be a power supply voltage line; but the present invention is not limited thereto.

[0103] In at least one embodiment of the present disclosure, the first noise reduction control circuit is also electrically connected to the second voltage line, and is used to control the connection between the first noise reduction node and the first noise reduction clock signal line under the control of the first noise reduction clock signal, and to control the connection between the first noise reduction node and the second voltage line under the control of the potential of the first node.

[0104] In a specific implementation, the first noise reduction control circuit can also control the connection between the first noise reduction node and the first noise reduction clock signal line under the control of the first noise reduction clock signal, and control the connection between the first noise reduction node and the second voltage line under the control of the potential of the first node.

[0105] Optionally, the second voltage line may be a first low voltage line, but is not limited thereto.

[0106] As shown in Figure 2, based on at least one embodiment of the driving circuit shown in Figure 1, the first noise reduction control circuit 11 is also electrically connected to the second voltage line V2, and is used to control the connection between the first noise reduction node PD1 and the first noise reduction clock signal line CK1 under the control of the first noise reduction clock signal, and to control the connection between the first noise reduction node PD1 and the second voltage line V2 under the control of the potential of the first node PU.

[0107] In at least one embodiment of the present disclosure, the second noise reduction circuit is further electrically connected to the second noise reduction control node and the second voltage line, respectively, and is configured to control the second noise reduction control node to be connected to the second noise reduction clock signal line under the control of the first noise reduction clock signal, control the second noise reduction control node to be connected to the second voltage line under the control of the potential of the first node, control the second noise reduction node to be connected to the second noise reduction clock signal line under the control of the potential of the second noise reduction control node, and control the second noise reduction node to be connected to the second voltage line under the control of the potential of the first node.

[0108] In a specific implementation, the second noise reduction circuit can control the connection between the second noise reduction control node and the second noise reduction clock signal line under the control of the first noise reduction clock signal, control the connection between the second noise reduction control node and the second voltage line under the control of the potential of the first node, control the connection between the second noise reduction node and the second noise reduction clock signal line under the control of the potential of the second noise reduction control node, and control the connection between the second noise reduction node and the second voltage line under the control of the potential of the first node, so as to control the potential of the second noise reduction node.

[0109] As shown in FIG3 , based on at least one embodiment of the driving circuit shown in FIG2 , the noise reduction control line is a second noise reduction clock signal line CK2 ;

[0110] The second noise reduction circuit 12 is also electrically connected to the second noise reduction control node PDCN2 and the second voltage line V2, respectively, and is used to control the connection between the second noise reduction control node PDCN2 and the second noise reduction clock signal line CK2 under the control of the first noise reduction clock signal, and control the connection between the second noise reduction control node PDCN2 and the second voltage line V2 under the control of the potential of the first node PU, and control the connection between the second noise reduction node PD2 and the second noise reduction clock signal line CK2 under the control of the potential of the second noise reduction control node PDCN2, and control the connection between the second noise reduction node PD2 and the second voltage line V2 under the control of the potential of the first node PU.

[0111] In at least one embodiment of the present disclosure, the second noise reduction circuit is also electrically connected to the second voltage line, and is used to control the connection between the noise reduction control line and the second noise reduction node under the control of the noise reduction control signal provided by the noise reduction control line, and to control the connection between the second noise reduction node and the second voltage line under the control of the potential of the first node.

[0112] In a specific implementation, the second noise reduction circuit can control the connection between the noise reduction control line and the second noise reduction node under the control of the noise reduction control signal, and control the connection between the second noise reduction node and the second voltage line under the control of the potential of the first node to control the potential of the second noise reduction node.

[0113] As shown in Figure 4, based on at least one embodiment of the driving circuit shown in Figure 2, the second noise reduction circuit 12 is also electrically connected to the second voltage line V2, and is used to control the connection between the noise reduction control line SC and the second noise reduction node PD2 under the control of the noise reduction control signal provided by the noise reduction control line SC, and to control the connection between the second noise reduction node PD2 and the second voltage line V2 under the control of the potential of the first node PU.

[0114] In at least one embodiment of the present disclosure, the second noise reduction circuit is also electrically connected to the second voltage line, and is used to control the connection between the second noise reduction node and the second noise reduction clock signal line under the control of the second noise reduction clock signal provided by the second noise reduction clock signal line, control the connection between the second noise reduction node and the second voltage line under the control of the potential of the first node, and control the connection between the second noise reduction clock signal line and the second noise reduction node under the control of the potential of the second noise reduction node.

[0115] In a specific implementation, the second noise reduction circuit can control the connection between the second noise reduction node and the second noise reduction clock signal line under the control of the second noise reduction clock signal, control the connection between the second noise reduction node and the second voltage line under the control of the potential of the first node, and control the connection between the second noise reduction clock signal line and the second noise reduction node under the control of the potential of the second noise reduction node.

[0116] As shown in FIG5 , based on at least one embodiment of the driving circuit shown in FIG2 , the noise reduction control line may be a second noise reduction clock signal line CK2 ;

[0117] The second noise reduction circuit 12 is also electrically connected to the second voltage line V2, and is used to control the connection between the second noise reduction node PD2 and the second noise reduction clock signal line CK2 under the control of the second noise reduction clock signal provided by the second noise reduction clock signal line CK2, and to control the connection between the second noise reduction node PD2 and the second voltage line V2 under the control of the potential of the first node PU, and to control the connection between the second noise reduction clock signal line CK2 and the second noise reduction node PD2 under the control of the potential of the second noise reduction node PD2.

[0118] In at least one embodiment of the present disclosure, when a driving module including the above-mentioned driving circuit adopts 12 clock signal lines, and the duty cycle of the clock signal provided by the clock signal line is 1 / 2, the high level duration of the clock signal is 6H, and the low level duration of the clock signal is 6H, the first noise reduction clock signal line can be the a+6th clock signal line, and the second noise reduction signal line can be the ath clock signal line, where a is a positive integer and 1H is a row scanning time.

[0119] Optionally, the first noise reduction control circuit includes a second transistor and a third transistor;

[0120] The gate of the second transistor and the first electrode of the second transistor are electrically connected to the first noise reduction clock signal line, and the second electrode of the second transistor is electrically connected to the first noise reduction node;

[0121] A gate of the third transistor is electrically connected to the first node, a first electrode of the third transistor is electrically connected to the first noise reduction node, and a second electrode of the third transistor is electrically connected to the second voltage line.

[0122] Optionally, the second noise reduction circuit includes a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor;

[0123] The gate of the fourth transistor and the first electrode of the fourth transistor are electrically connected to the second noise reduction clock signal line, and the second electrode of the fourth transistor is electrically connected to the second noise reduction control node;

[0124] The gate of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the second noise reduction control node, and the second electrode of the fifth transistor is electrically connected to the second voltage line;

[0125] The gate of the sixth transistor is electrically connected to the second noise reduction control node, the first electrode of the sixth transistor is electrically connected to the second noise reduction clock signal line, and the second electrode of the sixth transistor is electrically connected to the second noise reduction node;

[0126] A gate of the seventh transistor is electrically connected to the first node, a first electrode of the seventh transistor is electrically connected to the second noise reduction node, and a second electrode of the seventh transistor is electrically connected to the second voltage line.

[0127] Optionally, the second noise reduction circuit includes a fourth transistor and a fifth transistor;

[0128] The gate of the fourth transistor and the first electrode of the fourth transistor are both electrically connected to the noise reduction control line, and the second electrode of the fourth transistor is electrically connected to the second noise reduction node;

[0129] A gate of the fifth transistor is electrically connected to the first node, a first electrode of the fifth transistor is electrically connected to the second noise reduction node, and a second electrode of the fifth transistor is electrically connected to the second voltage line.

[0130] Optionally, the second noise reduction circuit includes a fourth transistor, a fifth transistor and a sixth transistor;

[0131] The gate of the fourth transistor and the first electrode of the fourth transistor are electrically connected to the second noise reduction clock signal line, and the second electrode of the fourth transistor is electrically connected to the second noise reduction node;

[0132] The gate of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the second noise reduction node, and the second electrode of the fifth transistor is electrically connected to the second voltage line;

[0133] A gate electrode of the sixth transistor and a second electrode of the sixth transistor are both electrically connected to a second noise reduction node, and a first electrode of the sixth transistor is electrically connected to the second noise reduction node.

[0134] The driving circuit according to at least one embodiment of the present disclosure further includes a carry output circuit, a carry reset circuit and a driving output circuit;

[0135] The carry output circuit is electrically connected to the first node, the output clock signal line and the carry signal output terminal respectively, and is used to control the communication between the carry signal output terminal and the output clock signal line under the control of the potential of the first node;

[0136] The carry reset circuit is electrically connected to the first noise reduction node, the second noise reduction node, the carry signal output terminal, and a third voltage line, respectively, and is configured to control the communication between the carry signal output terminal and the third voltage line under the control of the potential of the first noise reduction node, and to control the communication between the carry signal output terminal and the third voltage line under the control of the potential of the second noise reduction node;

[0137] The drive output circuit is electrically connected to the first node, the drive signal output end and the output clock signal line respectively, and is used to control the connection between the drive signal output end and the output clock signal line under the control of the potential of the first node.

[0138] In a specific implementation, the drive circuit may further include a carry output circuit, a carry reset circuit and a drive output circuit; the carry output circuit controls the connection between the carry signal output terminal and the output clock signal line under the control of the potential of the first node; the carry reset circuit controls the connection between the carry signal output terminal and the third voltage line under the control of the potential of the first noise reduction node, and controls the connection between the carry signal output terminal and the third voltage line under the control of the potential of the second noise reduction node; the drive output circuit controls the connection between the drive signal output terminal and the output clock signal line under the control of the potential of the first node.

[0139] Optionally, the third voltage line may be a second low voltage line;

[0140] The output clock signal line and the second noise reduction clock signal line may be the same clock signal line to reduce the number of clock signal lines used, thereby facilitating the realization of a narrow frame; but the present invention is not limited thereto.

[0141] As shown in FIG6 , based on at least one embodiment of the driving circuit shown in FIG3 , the driving circuit according to at least one embodiment of the present disclosure further includes a carry output circuit 61 , a carry reset circuit 62 and a driving output circuit 63 ;

[0142] The carry output circuit 61 is electrically connected to the first node PU, the output clock signal line CLK and the carry signal output terminal OC, respectively, and is used to control the communication between the carry signal output terminal PU and the output clock signal line CLK under the control of the potential of the first node PU;

[0143] The carry reset circuit 62 is electrically connected to the first noise reduction node PD1, the second noise reduction node PD2, the carry signal output terminal OC, and the third voltage line V3, respectively, and is configured to control the communication between the carry signal output terminal OC and the third voltage line V3 under the control of the potential of the first noise reduction node PD1, and to control the communication between the carry signal output terminal OC and the third voltage line V3 under the control of the potential of the second noise reduction node PD2;

[0144] The drive output circuit 63 is electrically connected to the first node PU, the drive signal output terminal GT and the output clock signal line CLK respectively, and is used to control the connection between the drive signal output terminal GT and the output clock signal line CLK under the control of the potential of the first node PU.

[0145] As shown in FIG7 , based on at least one embodiment of the driving circuit shown in FIG4 , the driving circuit according to at least one embodiment of the present disclosure further includes a carry output circuit 61 , a carry reset circuit 62 and a driving output circuit 63 ;

[0146] The carry output circuit 61 is electrically connected to the first node PU, the output clock signal line CLK and the carry signal output terminal OC, respectively, and is used to control the communication between the carry signal output terminal PU and the output clock signal line CLK under the control of the potential of the first node PU;

[0147] The carry reset circuit 62 is electrically connected to the first noise reduction node PD1, the second noise reduction node PD2, the carry signal output terminal OC, and the third voltage line V3, respectively, and is configured to control the communication between the carry signal output terminal OC and the third voltage line V3 under the control of the potential of the first noise reduction node PD1, and to control the communication between the carry signal output terminal OC and the third voltage line V3 under the control of the potential of the second noise reduction node PD2;

[0148] The drive output circuit 63 is electrically connected to the first node PU, the drive signal output terminal GT and the output clock signal line CLK respectively, and is used to control the connection between the drive signal output terminal GT and the output clock signal line CLK under the control of the potential of the first node PU.

[0149] As shown in FIG8 , based on at least one embodiment of the driving circuit shown in FIG5 , the driving circuit according to at least one embodiment of the present disclosure further includes a carry output circuit 61 , a carry reset circuit 62 and a driving output circuit 63 ;

[0150] The carry output circuit 61 is electrically connected to the first node PU, the output clock signal line CLK and the carry signal output terminal OC, respectively, and is used to control the communication between the carry signal output terminal PU and the output clock signal line CLK under the control of the potential of the first node PU;

[0151] The carry reset circuit 62 is electrically connected to the first noise reduction node PD1, the second noise reduction node PD2, the carry signal output terminal OC, and the third voltage line V3, respectively, and is configured to control the communication between the carry signal output terminal OC and the third voltage line V3 under the control of the potential of the first noise reduction node PD1, and to control the communication between the carry signal output terminal OC and the third voltage line V3 under the control of the potential of the second noise reduction node PD2;

[0152] The drive output circuit 63 is electrically connected to the first node PU, the drive signal output terminal GT and the output clock signal line CLK respectively, and is used to control the connection between the drive signal output terminal GT and the output clock signal line CLK under the control of the potential of the first node PU.

[0153] The driving circuit according to at least one embodiment of the present disclosure further includes an energy storage circuit, a first node control circuit, and a noise reduction node control circuit;

[0154] The energy storage circuit is electrically connected to the first node and the drive signal output terminal respectively, and is used to store electrical energy;

[0155] The first node control circuit is electrically connected to the first input terminal, the second input terminal, the first node, the reset terminal, the first noise reduction node, the second noise reduction node, and the second voltage line, respectively, and is configured to control the connection between the first node and the second input terminal under the control of a first input signal provided by the first input terminal, control the connection between the first node and the second voltage line under the control of a reset signal provided by the reset terminal, control the connection between the first node and the second voltage line under the control of a potential of the first noise reduction node, and control the connection between the first node and the second voltage line under the control of a potential of the second noise reduction node;

[0156] The noise reduction node control circuit is electrically connected to the first noise reduction node, the second noise reduction node, the first input end and the second voltage line, respectively, and is used to control the connection between the first noise reduction node and the second voltage line, and control the connection between the second noise reduction node and the second voltage line under the control of the first input signal provided by the first input end.

[0157] In a specific implementation, the driving circuit may further include a storage circuit, a first node control circuit and a noise reduction node control circuit; the first node control circuit controls the connection between the first node and the second input terminal under the control of a first input signal, controls the connection between the first node and the second voltage line under the control of a reset signal, controls the connection between the first node and the second voltage line under the control of the potential of the first noise reduction node, and controls the connection between the first node and the second voltage line under the control of the potential of the second noise reduction node; the noise reduction node control circuit controls the connection between the first noise reduction node and the second voltage line, and controls the connection between the second noise reduction node and the second voltage line under the control of the first input signal.

[0158] In at least one embodiment of the present disclosure, the first node control circuit is further electrically connected to a frame reset terminal, and is configured to control the connection between the first node and the second voltage line under the control of a frame reset signal provided by the frame reset terminal.

[0159] In a specific implementation, the first node controllable circuit may further control the connection between the first node and the second voltage line under the control of a frame reset signal.

[0160] As shown in FIG9 , based on at least one embodiment of the driving circuit shown in FIG6 , the driving circuit according to at least one embodiment of the present disclosure further includes a tank circuit 91 , a first node control circuit 92 , and a noise reduction node control circuit 93 ;

[0161] The energy storage circuit 91 is electrically connected to the first node PU and the drive signal output terminal GT respectively, and is used to store electrical energy;

[0162] The first node control circuit 92 is electrically connected to the first input terminal I1, the second input terminal I2, the first node PU, the reset terminal RST, the first noise reduction node PD1, the second noise reduction node PD2, and the second voltage line V2, respectively, and is configured to control the connection between the first node PU and the second input terminal I2 under the control of a first input signal provided by the first input terminal I1, control the connection between the first node PU and the second voltage line V2 under the control of a reset signal provided by the reset terminal RST, control the connection between the first node PU and the second voltage line V2 under the control of the potential of the first noise reduction node PD1, and control the connection between the first node PU and the second voltage line V2 under the control of the potential of the second noise reduction node PD2;

[0163] The noise reduction node control circuit 93 is electrically connected to the first noise reduction node PD1, the second noise reduction node PD2, the first input terminal I1, and the second voltage line V2, respectively, and is configured to control the first noise reduction node PD1 to be connected to the second voltage line V2, and to control the second noise reduction node PD2 to be connected to the second voltage line V2, under the control of the first input signal provided by the first input terminal I1;

[0164] The first node control circuit 92 is also electrically connected to the frame reset terminal TRST, and is configured to control the connection between the first node PU and the second voltage line V2 under the control of a frame reset signal provided by the frame reset terminal TRST.

[0165] As shown in FIG10 , based on at least one embodiment of the driving circuit shown in FIG7 , the driving circuit according to at least one embodiment of the present disclosure further includes a tank circuit 91 , a first node control circuit 92 , and a noise reduction node control circuit 93 ;

[0166] The energy storage circuit 91 is electrically connected to the first node PU and the drive signal output terminal GT respectively, and is used to store electrical energy;

[0167] The first node control circuit 92 is electrically connected to the first input terminal I1, the second input terminal I2, the first node PU, the reset terminal RST, the first noise reduction node PD1, the second noise reduction node PD2, and the second voltage line V2, respectively, and is configured to control the connection between the first node PU and the second input terminal I2 under the control of a first input signal provided by the first input terminal I1, control the connection between the first node PU and the second voltage line V2 under the control of a reset signal provided by the reset terminal RST, control the connection between the first node PU and the second voltage line V2 under the control of the potential of the first noise reduction node PD1, and control the connection between the first node PU and the second voltage line V2 under the control of the potential of the second noise reduction node PD2;

[0168] The noise reduction node control circuit 93 is electrically connected to the first noise reduction node PD1, the second noise reduction node PD2, the first input terminal I1, and the second voltage line V2, respectively, and is configured to control the first noise reduction node PD1 to be connected to the second voltage line V2, and to control the second noise reduction node PD2 to be connected to the second voltage line V2, under the control of the first input signal provided by the first input terminal I1;

[0169] The first node control circuit 92 is also electrically connected to the frame reset terminal TRST, and is configured to control the connection between the first node PU and the second voltage line V2 under the control of a frame reset signal provided by the frame reset terminal TRST.

[0170] As shown in FIG11 , based on at least one embodiment of the driving circuit shown in FIG8 , the driving circuit according to at least one embodiment of the present disclosure further includes a tank circuit 91 , a first node control circuit 92 , and a noise reduction node control circuit 93 ;

[0171] The energy storage circuit 91 is electrically connected to the first node PU and the drive signal output terminal GT respectively, and is used to store electrical energy;

[0172] The first node control circuit 92 is electrically connected to the first input terminal I1, the second input terminal I2, the first node PU, the reset terminal RST, the first noise reduction node PD1, the second noise reduction node PD2, and the second voltage line V2, respectively, and is configured to control the connection between the first node PU and the second input terminal I2 under the control of a first input signal provided by the first input terminal I1, control the connection between the first node PU and the second voltage line V2 under the control of a reset signal provided by the reset terminal RST, control the connection between the first node PU and the second voltage line V2 under the control of the potential of the first noise reduction node PD1, and control the connection between the first node PU and the second voltage line V2 under the control of the potential of the second noise reduction node PD2;

[0173] The noise reduction node control circuit 93 is electrically connected to the first noise reduction node PD1, the second noise reduction node PD2, the first input terminal I1, and the second voltage line V2, respectively, and is configured to control the first noise reduction node PD1 to be connected to the second voltage line V2, and to control the second noise reduction node PD2 to be connected to the second voltage line V2, under the control of the first input signal provided by the first input terminal I1;

[0174] The first node control circuit 92 is also electrically connected to the frame reset terminal TRST, and is configured to control the connection between the first node PU and the second voltage line V2 under the control of a frame reset signal provided by the frame reset terminal TRST.

[0175] Optionally, the carry output circuit includes a carry output transistor, the carry reset circuit includes a first carry reset transistor and a second carry reset transistor, the drive output circuit includes a drive output transistor, and the output noise reduction circuit includes a first output noise reduction transistor and a second output noise reduction transistor;

[0176] The gate of the carry output transistor is electrically connected to the first node, the first electrode of the carry output transistor is electrically connected to the output clock signal line, and the second electrode of the carry output transistor is electrically connected to the carry signal output terminal;

[0177] The gate of the first carry reset transistor is electrically connected to the first noise reduction node, the first electrode of the first carry reset transistor is electrically connected to the carry signal output terminal, and the second electrode of the first carry reset transistor is electrically connected to the third voltage line;

[0178] a gate of the second carry reset transistor electrically connected to the second noise reduction node, a first electrode of the second carry reset transistor electrically connected to the carry signal output terminal, and a second electrode of the second carry reset transistor electrically connected to the third voltage line;

[0179] The gate of the driving output transistor is electrically connected to the first node, the first electrode of the driving output transistor is electrically connected to the output clock signal line, and the second electrode of the driving output transistor is electrically connected to the driving signal output terminal;

[0180] The gate of the first output noise reduction transistor is electrically connected to the first noise reduction node, the first electrode of the first output noise reduction transistor is electrically connected to the drive signal output terminal, and the second electrode of the first output noise reduction transistor is electrically connected to the third voltage line;

[0181] A gate of the second output noise reduction transistor is electrically connected to the second noise reduction node, a first electrode of the second output noise reduction transistor is electrically connected to the drive signal output terminal, and a second electrode of the second output noise reduction transistor is electrically connected to the third voltage line.

[0182] Optionally, the first node control circuit includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor; the noise reduction node control circuit includes a thirteenth transistor and a fourteenth transistor;

[0183] The gate of the eighth transistor is electrically connected to the first input terminal, the first electrode of the eighth transistor is electrically connected to the second input terminal, and the second electrode of the eighth transistor is electrically connected to the first node;

[0184] The gate of the ninth transistor is electrically connected to the reset terminal, the first electrode of the ninth transistor is electrically connected to the first node, and the second electrode of the ninth transistor is electrically connected to the second voltage line;

[0185] The gate of the tenth transistor is electrically connected to the first noise reduction node, the first electrode of the tenth transistor is electrically connected to the first node, and the second electrode of the tenth transistor is electrically connected to the second voltage line;

[0186] The gate of the eleventh transistor is electrically connected to the second noise reduction node, the first electrode of the eleventh transistor is electrically connected to the first node, and the second electrode of the eleventh transistor is electrically connected to the second voltage line;

[0187] The gate of the twelfth transistor is electrically connected to the frame reset terminal, the first electrode of the twelfth transistor is electrically connected to the first node, and the second electrode of the twelfth transistor is electrically connected to the second voltage line;

[0188] The gate of the thirteenth transistor is electrically connected to the first input terminal, the first electrode of the thirteenth transistor is electrically connected to the first noise reduction node, and the second electrode of the thirteenth transistor is electrically connected to the second voltage line;

[0189] A gate of the fourteenth transistor is electrically connected to the first input terminal, a first electrode of the fourteenth transistor is electrically connected to the second noise reduction node, and a second electrode of the fourteenth transistor is electrically connected to the second voltage line.

[0190] As shown in FIG12, based on at least one embodiment of the driving circuit shown in FIG9,

[0191] The first noise reduction control circuit includes a second transistor M2 and a third transistor M3;

[0192] The gate of the second transistor M2 and the drain of the second transistor M2 are electrically connected to the first noise reduction clock signal line CK1, and the source of the second transistor M2 is electrically connected to the first noise reduction node PD1;

[0193] The gate of the third transistor M3 is electrically connected to the first node PU, the drain of the third transistor M3 is electrically connected to the first noise reduction node PD1, and the source of the third transistor M3 is electrically connected to the first low voltage line LVSS;

[0194] The second noise reduction circuit includes a fourth transistor M4, a fifth transistor M5, a sixth transistor M6 and a seventh transistor M7;

[0195] The gate of the fourth transistor M4 and the drain of the fourth transistor M4 are electrically connected to the second noise reduction clock signal line CK2, and the source of the fourth transistor M4 is electrically connected to the second noise reduction control node PDCN2;

[0196] The gate of the fifth transistor M5 is electrically connected to the first node PU, the drain of the fifth transistor M5 is electrically connected to the second noise reduction control node PDCN2, and the source of the fifth transistor M5 is electrically connected to the first low voltage line LVSS;

[0197] The gate of the sixth transistor M6 is electrically connected to the second noise reduction control node PDCN2, the drain of the sixth transistor M6 is electrically connected to the second noise reduction clock signal line CK2, and the source of the sixth transistor M6 is electrically connected to the second noise reduction node PD2;

[0198] The gate of the seventh transistor M7 is electrically connected to the first node PU, the drain of the seventh transistor M7 is electrically connected to the second noise reduction node PD2, and the source of the seventh transistor M7 is electrically connected to the first low voltage line LVSS;

[0199] The carry output circuit includes a carry output transistor MC, the carry reset circuit includes a first carry reset transistor MR1 and a second carry reset transistor MR2, the drive output circuit includes a drive output transistor MO, and the output noise reduction circuit includes a first output noise reduction transistor MJ1 and a second output noise reduction transistor MJ2;

[0200] The gate of the carry output transistor MC is electrically connected to the first node PU, the drain of the carry output transistor MC is electrically connected to the second noise reduction clock signal line CK2, and the source of the carry output transistor MC is electrically connected to the carry signal output terminal OC;

[0201] The gate of the first carry reset transistor MR1 is electrically connected to the first noise reduction node PD1, the drain of the first carry reset transistor MR1 is electrically connected to the carry signal output terminal OC, and the source of the first carry reset transistor MR1 is electrically connected to the second low voltage line VSS;

[0202] The gate of the second carry reset transistor MR2 is electrically connected to the second noise reduction node PD2, the drain of the second carry reset transistor MR2 is electrically connected to the carry signal output terminal OC, and the source of the second carry reset transistor MR2 is electrically connected to the second low voltage line VSS;

[0203] The gate of the driving output transistor MO is electrically connected to the first node PU, the drain of the driving output transistor MO is electrically connected to the second noise reduction clock signal line CK2, and the source of the driving output transistor MO is electrically connected to the driving signal output terminal GT;

[0204] The gate of the first output noise reduction transistor MJ1 is electrically connected to the first noise reduction node PD1, the drain of the first output noise reduction transistor MJ1 is electrically connected to the driving signal output terminal GT, and the source of the first output noise reduction transistor MJ1 is electrically connected to the second low voltage line VSS;

[0205] The gate of the second output noise reduction transistor MJ2 is electrically connected to the second noise reduction node PD2, the drain of the second output noise reduction transistor MJ2 is electrically connected to the drive signal output terminal GT, and the source of the second output noise reduction transistor MJ2 is electrically connected to the second low voltage line VSS;

[0206] The first node control circuit includes an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12; the noise reduction node control circuit includes a thirteenth transistor M13 and a fourteenth transistor M14;

[0207] The gate of the eighth transistor M8 is electrically connected to the first input terminal I1, the drain of the eighth transistor M8 is electrically connected to the second input terminal I2, and the source of the eighth transistor M8 is electrically connected to the first node PU;

[0208] The gate of the ninth transistor M9 is electrically connected to the reset terminal RST, the drain of the ninth transistor M9 is electrically connected to the first node PU, and the source of the ninth transistor M9 is electrically connected to the first low voltage line LVSS;

[0209] The gate of the tenth transistor M10 is electrically connected to the first noise reduction node PD1, the drain of the tenth transistor M10 is electrically connected to the first node PU, and the source of the tenth transistor M10 is electrically connected to the first low voltage line LVSS;

[0210] The gate of the eleventh transistor M11 is electrically connected to the second noise reduction node PD2, the drain of the eleventh transistor M11 is electrically connected to the first node PU, and the source of the eleventh transistor M11 is electrically connected to the first low voltage line LVSS;

[0211] The gate of the twelfth transistor M12 is electrically connected to the frame reset terminal TRST, the drain of the twelfth transistor M12 is electrically connected to the first node PU, and the source of the twelfth transistor M12 is electrically connected to the first low voltage line LVSS;

[0212] The gate of the thirteenth transistor M13 is electrically connected to the first input terminal I1, the drain of the thirteenth transistor M13 is electrically connected to the first noise reduction node PD1, and the source of the thirteenth transistor M13 is electrically connected to the first low voltage line LVSS;

[0213] The gate of the fourteenth transistor M14 is electrically connected to the first input terminal I1, the drain of the fourteenth transistor M14 is electrically connected to the second noise reduction node PD2, and the source of the fourteenth transistor M14 is electrically connected to the first low voltage line LVSS;

[0214] The energy storage circuit includes a storage capacitor Cst;

[0215] A first end of Cst is electrically connected to the first node PU, and a second end of Cst is electrically connected to the driving signal output terminal GT.

[0216] In at least one embodiment of the present disclosure, the voltage value of the first low voltage signal provided by LVSS may be lower than the voltage value of the second low voltage signal provided by VSS, but is not limited thereto. In actual operation, the voltage value of the first low voltage signal provided by LVSS may also be equal to the voltage value of the second low voltage signal provided by VSS.

[0217] In at least one embodiment of the driving circuit shown in FIG. 12 , all transistors are n-type transistors, but the present invention is not limited thereto.

[0218] In at least one embodiment of the driving circuit shown in FIG. 12 , the output clock signal line is the second noise reduction clock signal line CK2 , but the present invention is not limited thereto.

[0219] In at least one embodiment of the driver circuit shown in FIG12 of the present disclosure, the first control voltage line and the second control voltage line in the related art are replaced by a first noise reduction clock signal line CK1 and a second noise reduction clock signal line CK2. CK1 and CK2 can be the same clock signal lines as the output clock signal lines used in the related art. This reduces the number of signal lines used in the driver module including at least one embodiment of the driver circuit shown in FIG12 of the present disclosure, thereby facilitating a narrow frame and reducing the area occupied by the driver module. For example, the frame size occupied by the driver module can be reduced from 5325μm to 255μm.

[0220] In at least one embodiment of the driving circuit shown in FIG. 12 of the present disclosure, when in operation, CK2 may be the first clock signal line CLK1 , and CK1 may be the seventh clock signal line CLK7 ;

[0221] As shown in FIG13 , the driving module may use twelve clock signal lines: a first clock signal line CLK1, a second clock signal line CLK2, a third clock signal line CLK3, a fourth clock signal line CLK4, a fifth clock signal line CLK5, a sixth clock signal line CLK6, a seventh clock signal line CLK7, an eighth clock signal line CLK8, a ninth clock signal line CLK9, a tenth clock signal line CLK10, an eleventh clock signal line CLK11, and a twelfth clock signal line CLK12.

[0222] The duty cycle of the first clock signal provided by CLK1, the duty cycle of the second clock signal provided by CLK2, the duty cycle of the third clock signal provided by CLK3, the duty cycle of the fourth clock signal provided by CLK4, the duty cycle of the fifth clock signal provided by CLK5, the duty cycle of the sixth clock signal provided by CLK6, the duty cycle of the seventh clock signal provided by CLK7, the duty cycle of the eighth clock signal provided by CLK8, the duty cycle of the ninth clock signal provided by CLK9, the duty cycle of the tenth clock signal provided by CLK10, the duty cycle of the eleventh clock signal provided by CLK11, and the duty cycle of the twelfth clock signal provided by CLK12 may all be 1 / 2;

[0223] The period of the first clock signal, the period of the second clock signal, the period of the third clock signal, the period of the fourth clock signal, the period of the fifth clock signal, the period of the sixth clock signal, the period of the seventh clock signal, the period of the eighth clock signal, the period of the ninth clock signal, the period of the tenth clock signal, the period of the eleventh clock signal and the period of the twelfth clock signal may all be 12H;

[0224] Among them, 1H is the scanning time of one line;

[0225] In one cycle, the potential of each clock signal may be continuously high for 6 hours, and the potential of each clock signal may be continuously low for 6 hours.

[0226] The second clock signal may be delayed by 1H compared to the first clock signal, the third clock signal may be delayed by 1H compared to the second clock signal, the fourth clock signal may be delayed by 1H compared to the third clock signal, the fifth clock signal may be delayed by 1H compared to the fourth clock signal, the sixth clock signal may be delayed by 1H compared to the fifth clock signal, the seventh clock signal may be delayed by 1H compared to the sixth clock signal, the eighth clock signal may be delayed by 1H compared to the seventh clock signal, the ninth clock signal may be delayed by 1H compared to the eighth clock signal, the tenth clock signal may be delayed by 1H compared to the ninth clock signal, the eleventh clock signal may be delayed by 1H compared to the tenth clock signal, and the twelfth clock signal may be delayed by 1H compared to the eleventh clock signal.

[0227] In at least one embodiment of the driving circuit shown in FIG. 12 of the present disclosure, during operation, during a portion of the time period at the beginning of a frame time and a portion of the time period at the end of a frame time, TRST provides a high voltage signal, M12 is turned on, PU is connected to LVSS, and the potential of PU is reset;

[0228] One frame time may include an input phase, an output phase, a reset phase, and an output cutoff phase that are set in sequence;

[0229] In the input phase, I1 and I2 both provide high-voltage signals, M8 is turned on, PU is connected to I2, the potential of PU is high, M3 and M5 are turned on, the potentials of PD1 and PD2 are low, MC and MO are turned on, OC is connected to CK2, and GT is connected to CK2. At this time, CK2 provides a low-voltage signal, and OC and GT output low-voltage signals.

[0230] In the output phase, CK2 provides a high voltage signal, the potential of PU is bootstrapped by Cst, the potential of PU is high, M3 and M5 are turned on, the potential of PD1 and PD2 are low, MC and MO are turned on, OC is connected to CK2, and GT is connected to CK2; at this time, CK2 provides a low voltage signal, and OC and GT output low voltage signals;

[0231] In the reset phase, RST provides a high voltage signal, M9 is turned on, PU is connected to LVSS, and the potential of PU is low voltage;

[0232] In the reset phase, the potential of PU is low; CK1 or CK2 provides a high voltage signal, the potential of PD1 or PD2 is high voltage, MR1 or MR2 is open, MJ1 or MJ2 is open, and OC and GT both output low voltage signals;

[0233] During at least part of the output cutoff phase, the potential of PU remains at a low voltage; CK1 or CK2 provides a high voltage signal, the potential of PD1 or PD2 is high voltage, MR1 or MR2 is open, MJ1 or MJ2 is open, and OC and GT both output low voltage signals.

[0234] In the output cutoff stage, since M1 is in a diode connection state, when CK1 provides a low voltage signal, the potential of PD1 is a low voltage;

[0235] In the output cut-off state, when CK2 provides a low voltage signal, since M4 is in a diode connection state, the potential of PDCN2 is low voltage, M6 is turned off, and the potential of PD2 can be maintained at a high voltage, which can reduce the noise of OC and GT through MR2 and MJ2.

[0236] At least one embodiment of the driving circuit shown in FIG. 12 of the present disclosure can also achieve noise reduction when the duty cycle of the clock signal provided by CK1 and the duty cycle of the clock signal provided by CK2 are less than 50% during operation.

[0237] In at least one embodiment of the present disclosure, when the driving module uses 2N clock signal lines, N and m are both positive integers;

[0238] The carry signal output terminal of the m-th stage driving circuit is electrically connected to the first input terminal of the m+N-th stage driving circuit, and the drive signal output terminal of the m-th stage driving circuit is electrically connected to the second input terminal of the m+N-th stage driving circuit; or,

[0239] The carry signal output terminal of the mth stage driving circuit is electrically connected to the first input terminal of the m+Nth stage driving circuit, and the carry signal output terminal of the mth stage driving circuit is electrically connected to the second input terminal of the m+Nth stage driving circuit.

[0240] As shown in FIG14, based on at least one embodiment of the driving circuit shown in FIG10,

[0241] The first noise reduction control circuit includes a second transistor M2 and a third transistor M3;

[0242] The gate of the second transistor M2 and the drain of the second transistor M2 are electrically connected to the first noise reduction clock signal line CK1, and the source of the second transistor M2 is electrically connected to the first noise reduction node PD1;

[0243] The gate of the third transistor M3 is electrically connected to the first node PU, the drain of the third transistor M3 is electrically connected to the first noise reduction node PD1, and the source of the third transistor M3 is electrically connected to the first low voltage line LVSS;

[0244] The second noise reduction circuit includes a fourth transistor M4 and a fifth transistor M5;

[0245] The gate of the fourth transistor M4 and the drain of the fourth transistor M4 are electrically connected to the power supply voltage line VDD, and the source of the fourth transistor M4 is electrically connected to the second noise reduction node PD2;

[0246] The gate of the fifth transistor M5 is electrically connected to the first node PU, the drain of the fifth transistor M5 is electrically connected to the second noise reduction node PD2, and the source of the fifth transistor M5 is electrically connected to the first low voltage line LVSS;

[0247] The carry output circuit includes a carry output transistor MC, the carry reset circuit includes a first carry reset transistor MR1 and a second carry reset transistor MR2, the drive output circuit includes a drive output transistor MO, and the output noise reduction circuit includes a first output noise reduction transistor MJ1 and a second output noise reduction transistor MJ2;

[0248] The gate of the carry output transistor MC is electrically connected to the first node PU, the drain of the carry output transistor MC is electrically connected to the second noise reduction clock signal line CK2, and the source of the carry output transistor MC is electrically connected to the carry signal output terminal OC;

[0249] The gate of the first carry reset transistor MR1 is electrically connected to the first noise reduction node PD1, the drain of the first carry reset transistor MR1 is electrically connected to the carry signal output terminal OC, and the source of the first carry reset transistor MR1 is electrically connected to the second low voltage line VSS;

[0250] The gate of the second carry reset transistor MR2 is electrically connected to the second noise reduction node PD2, the drain of the second carry reset transistor MR2 is electrically connected to the carry signal output terminal OC, and the source of the second carry reset transistor MR2 is electrically connected to the second low voltage line VSS;

[0251] The gate of the driving output transistor MO is electrically connected to the first node PU, the drain of the driving output transistor MO is electrically connected to the second noise reduction clock signal line CK2, and the source of the driving output transistor MO is electrically connected to the driving signal output terminal GT;

[0252] The gate of the first output noise reduction transistor MJ1 is electrically connected to the first noise reduction node PD1, the drain of the first output noise reduction transistor MJ1 is electrically connected to the driving signal output terminal GT, and the source of the first output noise reduction transistor MJ1 is electrically connected to the second low voltage line VSS;

[0253] The gate of the second output noise reduction transistor MJ2 is electrically connected to the second noise reduction node PD2, the drain of the second output noise reduction transistor MJ2 is electrically connected to the drive signal output terminal GT, and the source of the second output noise reduction transistor MJ2 is electrically connected to the second low voltage line VSS;

[0254] The first node control circuit includes an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12; the noise reduction node control circuit includes a thirteenth transistor M13 and a fourteenth transistor M14;

[0255] The gate of the eighth transistor M8 is electrically connected to the first input terminal I1, the drain of the eighth transistor M8 is electrically connected to the second input terminal I2, and the source of the eighth transistor M8 is electrically connected to the first node PU;

[0256] The gate of the ninth transistor M9 is electrically connected to the reset terminal RST, the drain of the ninth transistor M9 is electrically connected to the first node PU, and the source of the ninth transistor M9 is electrically connected to the first low voltage line LVSS;

[0257] The gate of the tenth transistor M10 is electrically connected to the first noise reduction node PD1, the drain of the tenth transistor M10 is electrically connected to the first node PU, and the source of the tenth transistor M10 is electrically connected to the first low voltage line LVSS;

[0258] The gate of the eleventh transistor M11 is electrically connected to the second noise reduction node PD2, the drain of the eleventh transistor M11 is electrically connected to the first node PU, and the source of the eleventh transistor M11 is electrically connected to the first low voltage line LVSS;

[0259] The gate of the twelfth transistor M12 is electrically connected to the frame reset terminal TRST, the drain of the twelfth transistor M12 is electrically connected to the first node PU, and the source of the twelfth transistor M12 is electrically connected to the first low voltage line LVSS;

[0260] The gate of the thirteenth transistor M13 is electrically connected to the first input terminal I1, the drain of the thirteenth transistor M13 is electrically connected to the first noise reduction node PD1, and the source of the thirteenth transistor M13 is electrically connected to the first low voltage line LVSS;

[0261] The gate of the fourteenth transistor M14 is electrically connected to the first input terminal I1, the drain of the fourteenth transistor M14 is electrically connected to the second noise reduction node PD2, and the source of the fourteenth transistor M14 is electrically connected to the first low voltage line LVSS;

[0262] The energy storage circuit includes a storage capacitor Cst;

[0263] A first end of Cst is electrically connected to the first node PU, and a second end of Cst is electrically connected to the driving signal output terminal GT.

[0264] In at least one embodiment of the driving circuit shown in FIG. 14 , all transistors are n-type transistors, but the present invention is not limited thereto.

[0265] In at least one embodiment of the driving circuit shown in FIG. 14 , the output clock signal line is the power voltage line VDD, but the present invention is not limited thereto.

[0266] At least one embodiment of the driving circuit shown in FIG. 14 of the present disclosure is in operation.

[0267] When the first noise reduction circuit is operating, as the potential of the clock signal provided by CK1 changes between high and low levels, PD1 is charged and discharged through M2 and M1. When the potential of PD1 is low, MR1, MJ1, and M10 are all inoperative, and the operating time of MR1, MJ1, and M10 decreases by at least 50%, reducing characteristic drift and improving reliability. The first noise reduction circuit does not operate when CK1 provides a low-voltage signal. The second noise reduction circuit is controlled by VDD and can control the potential of PD2 to a high voltage when PU is low.

[0268] In at least one embodiment of the driving circuit shown in FIG14 , the second noise reduction circuit includes only two transistors. Reducing the number of transistors used can further reduce the space occupied by the driving module, thereby facilitating the realization of a narrow frame.

[0269] When at least one embodiment of the driving circuit shown in FIG14 of the present disclosure is in operation, VDD provides a power supply voltage signal, which is a high voltage signal, and M4 is turned on. When the potential of PU is a low voltage, the potential of PD2 continues to be a high voltage, controlling MR2 and MJ2 to be turned on, thereby reducing the noise of OC and GT.

[0270] As shown in FIG15 , based on at least one embodiment of the driving circuit shown in FIG10 ,

[0271] The first noise reduction control circuit includes a second transistor M2 and a third transistor M3;

[0272] The gate of the second transistor M2 and the drain of the second transistor M2 are electrically connected to the first noise reduction clock signal line CK1, and the source of the second transistor M2 is electrically connected to the first noise reduction node PD1;

[0273] The gate of the third transistor M3 is electrically connected to the first node PU, the drain of the third transistor M3 is electrically connected to the first noise reduction node PD1, and the source of the third transistor M3 is electrically connected to the first low voltage line LVSS;

[0274] The second noise reduction circuit includes a fourth transistor M4 and a fifth transistor M5;

[0275] The gate of the fourth transistor M4 and the drain of the fourth transistor M4 are electrically connected to the second noise reduction clock signal line CK2, and the source of the fourth transistor M4 is electrically connected to the second noise reduction node PD2;

[0276] The gate of the fifth transistor M5 is electrically connected to the first node PU, the drain of the fifth transistor M5 is electrically connected to the second noise reduction node PD2, and the source of the fifth transistor M5 is electrically connected to the first low voltage line LVSS;

[0277] The carry output circuit includes a carry output transistor MC, the carry reset circuit includes a first carry reset transistor MR1 and a second carry reset transistor MR2, the drive output circuit includes a drive output transistor MO, and the output noise reduction circuit includes a first output noise reduction transistor MJ1 and a second output noise reduction transistor MJ2;

[0278] The gate of the carry output transistor MC is electrically connected to the first node PU, the drain of the carry output transistor MC is electrically connected to the second noise reduction clock signal line CK2, and the source of the carry output transistor MC is electrically connected to the carry signal output terminal OC;

[0279] The gate of the first carry reset transistor MR1 is electrically connected to the first noise reduction node PD1, the drain of the first carry reset transistor MR1 is electrically connected to the carry signal output terminal OC, and the source of the first carry reset transistor MR1 is electrically connected to the second low voltage line VSS;

[0280] The gate of the second carry reset transistor MR2 is electrically connected to the second noise reduction node PD2, the drain of the second carry reset transistor MR2 is electrically connected to the carry signal output terminal OC, and the source of the second carry reset transistor MR2 is electrically connected to the second low voltage line VSS;

[0281] The gate of the driving output transistor MO is electrically connected to the first node PU, the drain of the driving output transistor MO is electrically connected to the second noise reduction clock signal line CK2, and the source of the driving output transistor MO is electrically connected to the driving signal output terminal GT;

[0282] The gate of the first output noise reduction transistor MJ1 is electrically connected to the first noise reduction node PD1, the drain of the first output noise reduction transistor MJ1 is electrically connected to the driving signal output terminal GT, and the source of the first output noise reduction transistor MJ1 is electrically connected to the second low voltage line VSS;

[0283] The gate of the second output noise reduction transistor MJ2 is electrically connected to the second noise reduction node PD2, the drain of the second output noise reduction transistor MJ2 is electrically connected to the drive signal output terminal GT, and the source of the second output noise reduction transistor MJ2 is electrically connected to the second low voltage line VSS;

[0284] The first node control circuit includes an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12; the noise reduction node control circuit includes a thirteenth transistor M13 and a fourteenth transistor M14;

[0285] The gate of the eighth transistor M8 is electrically connected to the first input terminal I1, the drain of the eighth transistor M8 is electrically connected to the second input terminal I2, and the source of the eighth transistor M8 is electrically connected to the first node PU;

[0286] The gate of the ninth transistor M9 is electrically connected to the reset terminal RST, the drain of the ninth transistor M9 is electrically connected to the first node PU, and the source of the ninth transistor M9 is electrically connected to the first low voltage line LVSS;

[0287] The gate of the tenth transistor M10 is electrically connected to the first noise reduction node PD1, the drain of the tenth transistor M10 is electrically connected to the first node PU, and the source of the tenth transistor M10 is electrically connected to the first low voltage line LVSS;

[0288] The gate of the eleventh transistor M11 is electrically connected to the second noise reduction node PD2, the drain of the eleventh transistor M11 is electrically connected to the first node PU, and the source of the eleventh transistor M11 is electrically connected to the first low voltage line LVSS;

[0289] The gate of the twelfth transistor M12 is electrically connected to the frame reset terminal TRST, the drain of the twelfth transistor M12 is electrically connected to the first node PU, and the source of the twelfth transistor M12 is electrically connected to the first low voltage line LVSS;

[0290] The gate of the thirteenth transistor M13 is electrically connected to the first input terminal I1, the drain of the thirteenth transistor M13 is electrically connected to the first noise reduction node PD1, and the source of the thirteenth transistor M13 is electrically connected to the first low voltage line LVSS;

[0291] The gate of the fourteenth transistor M14 is electrically connected to the first input terminal I1, the drain of the fourteenth transistor M14 is electrically connected to the second noise reduction node PD2, and the source of the fourteenth transistor M14 is electrically connected to the first low voltage line LVSS;

[0292] The energy storage circuit includes a storage capacitor Cst;

[0293] A first end of Cst is electrically connected to the first node PU, and a second end of Cst is electrically connected to the driving signal output terminal GT.

[0294] In at least one embodiment of the driving circuit shown in FIG. 15 , all transistors are n-type transistors, but the present invention is not limited thereto.

[0295] In at least one embodiment of the driving circuit shown in FIG. 15 , the output clock signal line is the second noise reduction clock signal line CK2 .

[0296] The difference between at least one embodiment of the driving circuit shown in FIG. 15 of the present disclosure and at least one embodiment of the driving circuit shown in FIG. 14 of the present disclosure is that:

[0297] The gate of M4 and the drain of M4 are both electrically connected to the second noise reduction clock signal line CK2.

[0298] Compared with at least one embodiment of the driving circuit shown in FIG14 of the present disclosure, at least one embodiment of the driving circuit shown in FIG15 of the present disclosure reduces the use of the power supply voltage line VDD, which can further reduce the space occupied by the driving module, thereby facilitating the realization of a narrow frame; for example, the frame size can be further reduced by 126 μm.

[0299] In at least one embodiment of the driving circuit shown in FIG15 of the present disclosure, when the potential of PU is low and CK2 provides a high voltage signal, the potential of PD2 is high.

[0300] When the potential of PU is low and CK2 provides a low voltage signal, the potential of PD2 can be maintained at a high voltage, so that MR2 and MJ2 are turned on, thereby reducing noise for OC and GT.

[0301] As shown in FIG16 , based on at least one embodiment of the driving circuit shown in FIG11 ,

[0302] The first noise reduction control circuit includes a second transistor M2 and a third transistor M3;

[0303] The gate of the second transistor M2 and the drain of the second transistor M2 are electrically connected to the first noise reduction clock signal line CK1, and the source of the second transistor M2 is electrically connected to the first noise reduction node PD1;

[0304] The gate of the third transistor M3 is electrically connected to the first node PU, the drain of the third transistor M3 is electrically connected to the first noise reduction node PD1, and the source of the third transistor M3 is electrically connected to the first low voltage line LVSS;

[0305] The second noise reduction circuit includes a fourth transistor M4, a fifth transistor M5 and a sixth transistor M6;

[0306] The gate and drain of the fourth transistor M4 are electrically connected to the second noise reduction clock signal line CK2, and the source of the fourth transistor M4 is electrically connected to the second noise reduction node PD2;

[0307] The gate of the fifth transistor M5 is electrically connected to the first node PU, the drain of the fifth transistor M5 is electrically connected to the second noise reduction node PD2, and the source of the fifth transistor M5 is electrically connected to the first low voltage line LVSS;

[0308] The gate of the sixth transistor M6 is electrically connected to the second noise reduction node PD2, the drain of the sixth transistor M6 is electrically connected to the second noise reduction clock signal line CK2, and the source of the sixth transistor M6 is electrically connected to the second noise reduction node PD2;

[0309] The carry output circuit includes a carry output transistor MC, the carry reset circuit includes a first carry reset transistor MR1 and a second carry reset transistor MR2, the drive output circuit includes a drive output transistor MO, and the output noise reduction circuit includes a first output noise reduction transistor MJ1 and a second output noise reduction transistor MJ2;

[0310] The gate of the carry output transistor MC is electrically connected to the first node PU, the drain of the carry output transistor MC is electrically connected to the second noise reduction clock signal line CK2, and the source of the carry output transistor MC is electrically connected to the carry signal output terminal OC;

[0311] The gate of the first carry reset transistor MR1 is electrically connected to the first noise reduction node PD1, the drain of the first carry reset transistor MR1 is electrically connected to the carry signal output terminal OC, and the source of the first carry reset transistor MR1 is electrically connected to the second low voltage line VSS;

[0312] The gate of the second carry reset transistor MR2 is electrically connected to the second noise reduction node PD2, the drain of the second carry reset transistor MR2 is electrically connected to the carry signal output terminal OC, and the source of the second carry reset transistor MR2 is electrically connected to the second low voltage line VSS;

[0313] The gate of the driving output transistor MO is electrically connected to the first node PU, the drain of the driving output transistor MO is electrically connected to the second noise reduction clock signal line CK2, and the source of the driving output transistor MO is electrically connected to the driving signal output terminal GT;

[0314] The gate of the first output noise reduction transistor MJ1 is electrically connected to the first noise reduction node PD1, the drain of the first output noise reduction transistor MJ1 is electrically connected to the driving signal output terminal GT, and the source of the first output noise reduction transistor MJ1 is electrically connected to the second low voltage line VSS;

[0315] The gate of the second output noise reduction transistor MJ2 is electrically connected to the second noise reduction node PD2, the drain of the second output noise reduction transistor MJ2 is electrically connected to the drive signal output terminal GT, and the source of the second output noise reduction transistor MJ2 is electrically connected to the second low voltage line VSS;

[0316] The first node control circuit includes an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12; the noise reduction node control circuit includes a thirteenth transistor M13 and a fourteenth transistor M14;

[0317] The gate of the eighth transistor M8 is electrically connected to the first input terminal I1, the drain of the eighth transistor M8 is electrically connected to the second input terminal I2, and the source of the eighth transistor M8 is electrically connected to the first node PU;

[0318] The gate of the ninth transistor M9 is electrically connected to the reset terminal RST, the drain of the ninth transistor M9 is electrically connected to the first node PU, and the source of the ninth transistor M9 is electrically connected to the first low voltage line LVSS;

[0319] The gate of the tenth transistor M10 is electrically connected to the first noise reduction node PD1, the drain of the tenth transistor M10 is electrically connected to the first node PU, and the source of the tenth transistor M10 is electrically connected to the first low voltage line LVSS;

[0320] The gate of the eleventh transistor M11 is electrically connected to the second noise reduction node PD2, the drain of the eleventh transistor M11 is electrically connected to the first node PU, and the source of the eleventh transistor M11 is electrically connected to the first low voltage line LVSS;

[0321] The gate of the twelfth transistor M12 is electrically connected to the frame reset terminal TRST, the drain of the twelfth transistor M12 is electrically connected to the first node PU, and the source of the twelfth transistor M12 is electrically connected to the first low voltage line LVSS;

[0322] The gate of the thirteenth transistor M13 is electrically connected to the first input terminal I1, the drain of the thirteenth transistor M13 is electrically connected to the first noise reduction node PD1, and the source of the thirteenth transistor M13 is electrically connected to the first low voltage line LVSS;

[0323] The gate of the fourteenth transistor M14 is electrically connected to the first input terminal I1, the drain of the fourteenth transistor M14 is electrically connected to the second noise reduction node PD2, and the source of the fourteenth transistor M14 is electrically connected to the first low voltage line LVSS;

[0324] The energy storage circuit includes a storage capacitor Cst;

[0325] A first end of Cst is electrically connected to the first node PU, and a second end of Cst is electrically connected to the driving signal output terminal GT.

[0326] In at least one embodiment of the driving circuit shown in FIG. 16 , all transistors are n-type transistors, but the present invention is not limited thereto.

[0327] In at least one embodiment of the driving circuit shown in FIG. 16 , the output clock signal line is the second noise reduction clock signal line CK2 , but the present invention is not limited thereto.

[0328] In at least one embodiment of the driving circuit shown in FIG. 16 of the present disclosure, when CK1 provides a high voltage signal and the potential of PU is low, the potential of PD1 is high, and noise reduction is performed by PD1;

[0329] When CK2 provides a high voltage signal and the potential of PU is low, the potential of PD2 is high, and noise reduction is controlled by PD2;

[0330] When CK1 provides a low voltage signal, the potential of PD1 leaks to M1 and M2 and becomes a low voltage;

[0331] When CK2 provides a low voltage signal, the potential of PD2 leaks to M4 and M6 and becomes a low voltage.

[0332] When at least one embodiment of the driving circuit shown in Figure 16 of the present disclosure is working, when the duty cycle of the clock signal provided by CK1 and the duty cycle of the clock signal provided by CK2 are 1 / 2, when the potential of PU is a low voltage, the potential of PD1 or the potential of PD2 is a high voltage, and OC and GT are controlled to output low voltage signals. When the duty cycle of the clock signal provided by CK1 and the duty cycle of the clock signal provided by CK2 are less than 50%, there will be some time when the first noise reduction circuit and the second noise reduction circuit do not work. Therefore, in actual operation, the duty cycle of the clock signal provided by CK1 and the duty cycle of the clock signal provided by CK2 can be set to be larger.

[0333] The driving module described in the embodiment of the present disclosure includes multiple stages of the above-mentioned driving circuits.

[0334] Optionally, the driving module includes 2N clock signal lines; N is a positive integer;

[0335] The driving circuit is the a-th level driving circuit included in the driving module; a is a positive integer;

[0336] The first noise reduction clock signal line is the N+ath clock signal line, and the second noise reduction clock signal line and the output clock signal line are the ath clock signal line.

[0337] In at least one embodiment of the present disclosure, the driving circuit includes a carry signal output terminal, a first input terminal, and a reset terminal;

[0338] The first input terminal of the a-th level driving circuit is electrically connected to the carry signal output terminal of the aN-th level driving circuit, and the reset terminal of the a-th level driving circuit is electrically connected to the carry signal output terminal of the a+N-th level driving circuit.

[0339] In at least one embodiment of the present disclosure, the driving circuit further includes a second input terminal and a driving signal output terminal;

[0340] The second input terminal of the a-th stage driving circuit is electrically connected to the driving signal output terminal of the aN-th stage driving circuit or the carry signal output terminal of the aN-th stage driving circuit.

[0341] As shown in FIG17 , the driving module according to at least one embodiment of the present disclosure uses 12 clock signal lines: a first clock signal line CLK1, a second clock signal line CLK2, a third clock signal line CLK3, a fourth clock signal line CLK4, a fifth clock signal line CLK5, a sixth clock signal line CLK6, a seventh clock signal line CLK7, an eighth clock signal line CLK8, a ninth clock signal line CLK9, a tenth clock signal line CLK10, an eleventh clock signal line CLK11, and a twelfth clock signal line CLK12.

[0342] In FIG17 , S1 is a first-stage driving circuit included in the driving module, S2 is a second-stage driving circuit included in the driving module, S3 is a third-stage driving circuit included in the driving module, S4 is a fourth-stage driving circuit included in the driving module, S5 is a fifth-stage driving circuit included in the driving module, S6 is a sixth-stage driving circuit included in the driving module, S7 is a seventh-stage driving circuit included in the driving module, S8 is an eighth-stage driving circuit included in the driving module, S9 is a ninth-stage driving circuit included in the driving module, S10 is a tenth-stage driving circuit included in the driving module, S11 is an eleventh-stage driving circuit included in the driving module, and S12 is a twelfth-stage driving circuit included in the driving module.

[0343] S1 is electrically connected to the first clock signal line CLK1 and the seventh clock signal line CLK7, respectively; S2 is electrically connected to the second clock signal line CLK2 and the eighth clock signal line CLK8, respectively; S3 is electrically connected to the third clock signal line CLK3 and the ninth clock signal line CLK9, respectively; S4 is electrically connected to the fourth clock signal line CLK4 and the tenth clock signal line CLK10, respectively; S5 is electrically connected to the fifth clock signal line CLK5 and the eleventh clock signal line CLK11, respectively; S6 is electrically connected to the sixth clock signal line CLK6 and the twelfth clock signal line CLK12, respectively;

[0344] S7 is electrically connected to the first clock signal line CLK1 and the seventh clock signal line CLK7, respectively; S8 is electrically connected to the second clock signal line CLK2 and the eighth clock signal line CLK8, respectively; S9 is electrically connected to the third clock signal line CLK3 and the ninth clock signal line CLK9, respectively; S10 is electrically connected to the fourth clock signal line CLK4 and the tenth clock signal line CLK10, respectively; S11 is electrically connected to the fifth clock signal line CLK5 and the eleventh clock signal line CLK11, respectively; S12 is electrically connected to the sixth clock signal line CLK6 and the twelfth clock signal line CLK12, respectively;

[0345] The carry signal output terminal of S1 is electrically connected to the first input terminal of S7, and the carry signal output terminal of S7 is electrically connected to the reset terminal of S1;

[0346] The driving signal output terminal of S1 is electrically connected to the second input terminal of S7;

[0347] The carry signal output terminal of S2 is electrically connected to the first input terminal of S8, and the carry signal output terminal of S8 is electrically connected to the reset terminal of S2;

[0348] The driving signal output terminal of S2 is electrically connected to the second input terminal of S8;

[0349] The carry signal output terminal of S3 is electrically connected to the first input terminal of S9, and the carry signal output terminal of S9 is electrically connected to the reset terminal of S2;

[0350] The driving signal output terminal of S3 is electrically connected to the second input terminal of S9;

[0351] The carry signal output terminal of S4 is electrically connected to the first input terminal of S10, and the carry signal output terminal of S10 is electrically connected to the reset terminal of S4;

[0352] The driving signal output terminal of S4 is electrically connected to the second input terminal of S10;

[0353] The carry signal output terminal of S5 is electrically connected to the first input terminal of S11, and the carry signal output terminal of S11 is electrically connected to the reset terminal of S5;

[0354] The driving signal output terminal of S5 is electrically connected to the second input terminal of S11;

[0355] The carry signal output terminal of S6 is electrically connected to the first input terminal of S12, and the carry signal output terminal of S12 is electrically connected to the reset terminal of S6;

[0356] The driving signal output terminal of S6 is electrically connected to the second input terminal of S12;

[0357] The first input terminal of S1, the first input terminal of S3, the first input terminal of S5, the second input terminal of S1, the second input terminal of S3 and the second input terminal of S5 are connected to the first starting voltage STV1;

[0358] The first input terminal of S2 , the first input terminal of S4 , the first input terminal of S6 , the second input terminal of S2 , the second input terminal of S4 , and the second input terminal of S6 are connected to the second starting voltage STV2 .

[0359] In at least one embodiment of the present disclosure, the reset terminals of the last six driving circuits included in the driving module can be connected to a reset voltage signal.

[0360] FIG18 is an operation timing diagram of the driving module according to at least one embodiment of the present disclosure.

[0361] In FIG18 , the terminal labeled GT2160 is the 2160th level drive signal output terminal, the terminal labeled TZ is a frame time, and the terminal labeled TB is a blank area;

[0362] In one cycle, the potential of each clock signal is continuously at a high level for 6 hours, and the potential of each clock signal is continuously at a low level for 6 hours;

[0363] The frame reset signal provided by TRST remains at a high level for 6 hours.

[0364] The time during which the potential of the first starting voltage STV1 is continuously at a high level is 11 hours, and the time during which the potential of the second starting voltage STV2 is continuously at a high level is 11 hours;

[0365] Among them, 1H is the scanning time of one line.

[0366] The display device described in the embodiment of the present disclosure includes the above-mentioned driving module.

[0367] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A driving circuit comprising a first noise reduction circuit, a second noise reduction circuit and an output noise reduction circuit; The first noise reduction circuit includes a first noise reduction control circuit and a first transistor; The gate of the first transistor and the second electrode of the first transistor are both electrically connected to the first noise reduction node, and the first electrode of the first transistor is electrically connected to the first noise reduction clock signal line; The first noise reduction control circuit is electrically connected to the first noise reduction clock signal line, the first noise reduction node, and the first node, respectively, and is configured to control the potential of the first noise reduction node under the control of the first noise reduction clock signal provided by the first noise reduction clock signal line and the potential of the first node; The second noise reduction circuit is electrically connected to the noise reduction control line, the first node and the second noise reduction node, and is configured to control the potential of the second noise reduction node under the control of the noise reduction control signal provided by the noise reduction control line and the potential of the first node; The output noise reduction circuit is electrically connected to the first noise reduction node, the second noise reduction node and the drive signal output end respectively, and is used to reduce the noise of the drive signal provided by the drive signal output end under the control of the potential of the first noise reduction node and the potential of the second noise reduction node.

2. The driving circuit according to claim 1, wherein: The noise reduction control line is a second noise reduction clock signal line.

3. The driving circuit according to claim 1, wherein: The noise reduction control line is a first voltage line.

4. The driving circuit according to claim 2, wherein: The first noise reduction control circuit is also electrically connected to the second voltage line, and is used to control the connection between the first noise reduction node and the first noise reduction clock signal line under the control of the first noise reduction clock signal, and to control the connection between the first noise reduction node and the second voltage line under the control of the potential of the first node.

5. The driving circuit according to claim 2, wherein: The second noise reduction circuit is also electrically connected to the second noise reduction control node and the second voltage line, respectively, and is used to control the connection between the second noise reduction control node and the second noise reduction clock signal line under the control of the first noise reduction clock signal, control the connection between the second noise reduction control node and the second voltage line under the control of the potential of the first node, control the connection between the second noise reduction node and the second noise reduction clock signal line under the control of the potential of the second noise reduction control node, and control the connection between the second noise reduction node and the second voltage line under the control of the potential of the first node.

6. The driving circuit according to claim 2 or 3, wherein: The second noise reduction circuit is also electrically connected to the second voltage line, and is used to control the connection between the noise reduction control line and the second noise reduction node under the control of the noise reduction control signal provided by the noise reduction control line, and to control the connection between the second noise reduction node and the second voltage line under the control of the potential of the first node.

7. The driving circuit according to claim 2, wherein: The second noise reduction circuit is also electrically connected to the second voltage line, and is used to control the connection between the second noise reduction node and the second noise reduction clock signal line under the control of the second noise reduction clock signal provided by the second noise reduction clock signal line, control the connection between the second noise reduction node and the second voltage line under the control of the potential of the first node, and control the connection between the second noise reduction clock signal line and the second noise reduction node under the control of the potential of the second noise reduction node.

8. The driving circuit according to claim 4, wherein: The first noise reduction control circuit includes a second transistor and a third transistor; The gate of the second transistor and the first electrode of the second transistor are electrically connected to the first noise reduction clock signal line, and the second electrode of the second transistor is electrically connected to the first noise reduction node; A gate of the third transistor is electrically connected to the first node, a first electrode of the third transistor is electrically connected to the first noise reduction node, and a second electrode of the third transistor is electrically connected to the second voltage line.

9. The driving circuit according to claim 5, wherein: The second noise reduction circuit includes a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor; The gate of the fourth transistor and the first electrode of the fourth transistor are electrically connected to the second noise reduction clock signal line, and the second electrode of the fourth transistor is electrically connected to the second noise reduction control node; The gate of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the second noise reduction control node, and the second electrode of the fifth transistor is electrically connected to the second voltage line; The gate of the sixth transistor is electrically connected to the second noise reduction control node, the first electrode of the sixth transistor is electrically connected to the second noise reduction clock signal line, and the second electrode of the sixth transistor is electrically connected to the second noise reduction node; A gate of the seventh transistor is electrically connected to the first node, a first electrode of the seventh transistor is electrically connected to the second noise reduction node, and a second electrode of the seventh transistor is electrically connected to the second voltage line.

10. The driving circuit according to claim 6, wherein: The second noise reduction circuit includes a fourth transistor and a fifth transistor; The gate of the fourth transistor and the first electrode of the fourth transistor are both electrically connected to the noise reduction control line, and the second electrode of the fourth transistor is electrically connected to the second noise reduction node; A gate of the fifth transistor is electrically connected to the first node, a first electrode of the fifth transistor is electrically connected to the second noise reduction node, and a second electrode of the fifth transistor is electrically connected to the second voltage line.

11. The driving circuit according to claim 7, wherein: The second noise reduction circuit includes a fourth transistor, a fifth transistor and a sixth transistor; The gate of the fourth transistor and the first electrode of the fourth transistor are electrically connected to the second noise reduction clock signal line, and the second electrode of the fourth transistor is electrically connected to the second noise reduction node; The gate of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the second noise reduction node, and the second electrode of the fifth transistor is electrically connected to the second voltage line; A gate electrode of the sixth transistor and a second electrode of the sixth transistor are both electrically connected to a second noise reduction node, and a first electrode of the sixth transistor is electrically connected to the second noise reduction node.

12. The driving circuit according to any one of claims 1 to 11, wherein: It also includes a carry output circuit, a carry reset circuit and a drive output circuit; The carry output circuit is electrically connected to the first node, the output clock signal line and the carry signal output terminal respectively, and is used to control the connection between the carry signal output terminal and the output clock signal line under the control of the potential of the first node. Pass; The carry reset circuit is electrically connected to the first noise reduction node, the second noise reduction node, the carry signal output terminal, and a third voltage line, respectively, and is configured to control the communication between the carry signal output terminal and the third voltage line under the control of the potential of the first noise reduction node, and to control the communication between the carry signal output terminal and the third voltage line under the control of the potential of the second noise reduction node; The drive output circuit is electrically connected to the first node, the drive signal output end and the output clock signal line respectively, and is used to control the connection between the drive signal output end and the output clock signal line under the control of the potential of the first node.

13. The driving circuit according to any one of claims 1 to 11, wherein: Also included is an energy storage circuit, a first node control circuit, and a noise reduction node control circuit; The energy storage circuit is electrically connected to the first node and the drive signal output terminal respectively, and is used to store electrical energy; The first node control circuit is electrically connected to the first input terminal, the second input terminal, the first node, the reset terminal, the first noise reduction node, the second noise reduction node, and the second voltage line, respectively, and is configured to control the connection between the first node and the second input terminal under the control of a first input signal provided by the first input terminal, control the connection between the first node and the second voltage line under the control of a reset signal provided by the reset terminal, control the connection between the first node and the second voltage line under the control of a potential of the first noise reduction node, and control the connection between the first node and the second voltage line under the control of a potential of the second noise reduction node; The noise reduction node control circuit is electrically connected to the first noise reduction node, the second noise reduction node, the first input end and the second voltage line, respectively, and is used to control the connection between the first noise reduction node and the second voltage line, and control the connection between the second noise reduction node and the second voltage line under the control of the first input signal provided by the first input end.

14. The driving circuit according to claim 13, wherein: The first node control circuit is also electrically connected to the frame reset terminal, and is used to control the connection between the first node and the second voltage line under the control of a frame reset signal provided by the frame reset terminal.

15. The driving circuit according to claim 12, wherein: The carry output circuit includes a carry output transistor, the carry reset circuit includes a first carry reset transistor and a second carry reset transistor, the drive output circuit includes a drive output transistor, and the output noise reduction circuit includes a first output noise reduction transistor and a second output noise reduction transistor; The gate of the carry output transistor is electrically connected to the first node, the first electrode of the carry output transistor is electrically connected to the output clock signal line, and the second electrode of the carry output transistor is electrically connected to the carry signal output terminal; The gate of the first carry reset transistor is electrically connected to the first noise reduction node, the first electrode of the first carry reset transistor is electrically connected to the carry signal output terminal, and the second electrode of the first carry reset transistor is electrically connected to the third voltage line; a gate of the second carry reset transistor electrically connected to the second noise reduction node, a first electrode of the second carry reset transistor electrically connected to the carry signal output terminal, and a second electrode of the second carry reset transistor electrically connected to the third voltage line; The gate of the driving output transistor is electrically connected to the first node, the first electrode of the driving output transistor is electrically connected to the output clock signal line, and the second electrode of the driving output transistor is electrically connected to the driving signal output terminal; The gate of the first output noise reduction transistor is electrically connected to the first noise reduction node, the first electrode of the first output noise reduction transistor is electrically connected to the drive signal output terminal, and the second electrode of the first output noise reduction transistor is electrically connected to the third voltage line; A gate of the second output noise reduction transistor is electrically connected to the second noise reduction node, a first electrode of the second output noise reduction transistor is electrically connected to the drive signal output terminal, and a second electrode of the second output noise reduction transistor is electrically connected to the third voltage line.

16. The driving circuit according to claim 14, wherein: The first node control circuit includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor; the noise reduction node control circuit includes a thirteenth transistor and a fourteenth transistor; The gate of the eighth transistor is electrically connected to the first input terminal, the first electrode of the eighth transistor is electrically connected to the second input terminal, and the second electrode of the eighth transistor is electrically connected to the first node; The gate of the ninth transistor is electrically connected to the reset terminal, the first electrode of the ninth transistor is electrically connected to the first node, and the second electrode of the ninth transistor is electrically connected to the second voltage line; The gate of the tenth transistor is electrically connected to the first noise reduction node, the first electrode of the tenth transistor is electrically connected to the first node, and the second electrode of the tenth transistor is electrically connected to the second voltage line; The gate of the eleventh transistor is electrically connected to the second noise reduction node, the first electrode of the eleventh transistor is electrically connected to the first node, and the second electrode of the eleventh transistor is electrically connected to the second voltage line; The gate of the twelfth transistor is electrically connected to the frame reset terminal, the first electrode of the twelfth transistor is electrically connected to the first node, and the second electrode of the twelfth transistor is electrically connected to the second voltage line; The gate of the thirteenth transistor is electrically connected to the first input terminal, the first electrode of the thirteenth transistor is electrically connected to the first noise reduction node, and the second electrode of the thirteenth transistor is electrically connected to the second voltage line; A gate of the fourteenth transistor is electrically connected to the first input terminal, a first electrode of the fourteenth transistor is electrically connected to the second noise reduction node, and a second electrode of the fourteenth transistor is electrically connected to the second voltage line.

17. A driving module comprising a plurality of driving circuits according to any one of claims 1 to 16.

18. The driving module according to claim 17, wherein: The driving module includes 2N clock signal lines; N is a positive integer; The driving circuit is the a-th level driving circuit included in the driving module; a is a positive integer; The first noise reduction clock signal line is the N+ath clock signal line, and the second noise reduction clock signal line and the output clock signal line are the ath clock signal line.

19. The driving module according to claim 18, wherein: The driving circuit includes a carry signal output terminal, a first input terminal and a reset terminal; The first input terminal of the a-th level driving circuit is electrically connected to the carry signal output terminal of the aN-th level driving circuit, and the reset terminal of the a-th level driving circuit is electrically connected to the carry signal output terminal of the a+N-th level driving circuit.

20. The driving module according to claim 19, wherein: The driving circuit further includes a second input terminal and a driving signal output terminal; The second input terminal of the a-th stage driving circuit is electrically connected to the driving signal output terminal of the aN-th stage driving circuit or the carry signal output terminal of the aN-th stage driving circuit.

21. A display device comprising the driving module according to any one of claims 17 to 20.

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