Access method and apparatus for multi-level cache system, electronic device, and storage medium

Abstract

Disclosed are an access method and apparatus for a multi-level cache system, an electronic device, a storage medium, a computer program product, and a computer program. The access method for a multi-level cache system comprises: before an access request sent by a request processor core reaches a home node to which a target data block belongs, determining whether a first child node, storing the target data block, of the request processor core has been recognized; in response to the first child node having not been recognized, acquiring a first distance from the request processor core to a second child node, acquiring a second distance from the request processor core to the home node, and on the basis of the first distance and the second distance, determining a target processing object from among the second child node and the home node; and processing the access request by means of the target processing object.

Description

Access method, device, electronic device and storage medium of multi-level cache system

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese Patent Application No. 2024103654044 filed in China on March 28, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of chip technology, and in particular to a method, device, electronic device, storage medium, computer program product, and computer program for accessing a multi-level cache system. Background Art

[0004] With the rapid development of applications such as artificial intelligence, high-performance computing, and networking, the demand for computing power from high-performance processors is increasing. Rapid advances in semiconductor technology have enabled microprocessors to achieve ever-increasing speed and integration. The number and variety of transistor resources available to processor designers are increasing. Multi-core processors are the future of high-performance processors, and the trend is toward integrating an increasing number of processor cores on a chip. This is accompanied by a rapid increase in the scale and complexity of processor designs. How to efficiently utilize on-chip resources to achieve multi-core cache coherence, improve storage resource utilization, reduce access latency to each level of the cache storage hierarchy, and reduce the latency required to maintain cache coherence are currently key research issues of widespread concern and interest in both academia and industry.

[0005] In multi-core processors, the Snoop coherence protocol and the Directory coherence protocol are two common implementations of cache coherence protocols. The Directory coherence protocol uses a directory to record the distribution of data copies across processor cores. Compared to the Snoop coherence protocol, it offers better scalability and can be expanded to more processor cores, such as 128 or 256 cores. Therefore, it is currently the most widely used coherence protocol in multi-core processors.

[0006] In the directory consistency protocol, all access requests must first enter the directory protocol controller of the master node for processing, resulting in unbalanced node access and excessive access pressure on local nodes.

[0007] Summary of the Invention

[0008] The present disclosure aims to solve one of the technical problems in the related art at least to a certain extent.

[0009] To this end, one objective of the present disclosure is to provide an access method for a multi-level cache system.

[0010] A second objective of the present disclosure is to provide an access device for a multi-level cache system.

[0011] A third objective of the present disclosure is to provide an electronic device.

[0012] A fourth object of the present disclosure is to provide a non-transitory computer-readable storage medium.

[0013] A fifth object of the present disclosure is to provide a computer program product.

[0014] A sixth object of the present disclosure is to provide a computer program.

[0015] To achieve the above-mentioned purpose, an embodiment of the first aspect of the present disclosure proposes an access method for a multi-level cache system, including: before the access request sent by the requesting processor core reaches the main node to which the target data block belongs, determining whether the first child node of the requesting processor core storing the target data block is identified; in response to not identifying the first child node, obtaining a first distance from the requesting processor core to the second child node of the main node of the requesting processor core storing the target data block, and obtaining a second distance from the requesting processor core to the main node, and based on the first distance and the second distance, determining a target processing object from the second child node and the main node; and processing the access request through the target processing object.

[0016] According to one embodiment of the present disclosure, determining the target processing object from the second child node and the main node based on the first distance and the second distance includes: comparing the first distance and the second distance; in response to the existence of a first distance smaller than the second distance, determining the target child node corresponding to the minimum value in the first distance as the target processing object; in response to the first distances being greater than or equal to the second distance, determining the main node as the target processing object.

[0017] According to one embodiment of the present disclosure, the processing of the access request through the target processing object includes: in response to the target processing object being the main node, returning the data in the target data block to the requesting processor core through the main node; in response to the target processing object being the target child node, obtaining the request type of the access request, and based on the request type, processing the access request through the target child node.

[0018] According to one embodiment of the present disclosure, the access request is processed by the target child node based on the request type, including: in response to the request type being a read failure request, the access request is forwarded to the target child node by the master node; an access link is established with the requesting processor core based on the access request by the target child node, and the data in the target data block is returned to the requesting processor core through the access link.

[0019] According to an embodiment of the present disclosure, the method further includes: entering a node identifier of the requesting processor core in the target subnode to make the requesting processor core a subnode of the target subnode.

[0020] According to an embodiment of the present disclosure, the method further includes: obtaining a node identifier of the requesting processor core; and entering the node identifier into a directory protocol controller of the master node to make the requesting processor core a child node of the master node.

[0021] According to one embodiment of the present disclosure, the access request is processed by the target child node based on the request type, including: in response to the request type being a write failure request, the access request is forwarded to the target child node by the master node, and the data block status of the target data block is obtained; based on the data block status, the access request is processed by the target child node.

[0022] According to one embodiment of the present disclosure, the access request is processed through the target child node based on the data block status, including: in response to the data block status being a shared state, the data in the target data block is returned to the requesting processor core through the target child node, and at the same time, the data of the target data block in all second child nodes is invalidated through the main node.

[0023] According to an embodiment of the present disclosure, the method further includes: modifying the data block state of the target data block to an exclusive state through a directory protocol controller, and recording that the owner of the target data block is the requesting processor core.

[0024] According to one embodiment of the present disclosure, the access request is processed through the target child node based on the data block status, including: in response to the data block status being an exclusive state, returning the data in the target data block to the requesting processor core through the target child node, and invalidating the data of the target data block in the target child node.

[0025] According to an embodiment of the present disclosure, the method further includes: recording, through a directory protocol controller, that the owner of the target data block is the requesting processor core.

[0026] According to one embodiment of the present disclosure, obtaining the first distance from the request processor core to the second child node of the main node of the request processor core storing the target data block, and obtaining the second distance from the request processor core to the main node, include: mapping the request processor core, all the second child nodes of the request processor core and the main node into a routing distribution map according to their actual distribution positions in the on-chip network; calculating the first distance from the request processor core to at least one second child node of the request processor core, and the second distance from the request processor core to the main node based on the routing distribution map.

[0027] According to one embodiment of the present disclosure, calculating a first distance from the request processor core to at least one second child node of the request processor core and a second distance from the request processor core to the master node based on the routing distribution map includes: calculating a first X-direction hop count and a first Y-direction hop count from the request processor core to the at least one second child node of the request processor core based on the routing distribution map, and calculating a second X-direction hop count and a second Y-direction hop count from the request processor core to the master node based on the routing distribution map; adding the first X-direction hop count and the first Y-direction hop count to obtain the first distance, and adding the second X-direction hop count and the second Y-direction hop count to obtain the second distance.

[0028] According to one embodiment of the present disclosure, the first distance from the request processor core to at least one second sub-node of the request processor core is calculated based on the routing distribution map, including: for any second sub-node of the request processor core, determining the candidate distances of all paths from the request processor core to the second sub-node in the routing distribution map; and taking the minimum value among the candidate distances as the first distance between the request processor core and the second sub-node.

[0029] According to one embodiment of the present disclosure, the method further includes: in response to identifying the first child node, obtaining the data block status of the target data block and the request type of the access request; based on the data block status and the request type, determining the target processing object from the first child node and the main node.

[0030] According to one embodiment of the present disclosure, determining the target processing object from the first child node and the master node based on the data block status and the request type includes: in response to the data block status being a shared state and the request type being a write failure request, determining the master node as the target processing object; in response to the data block status being a non-shared state, determining the first child node as the target processing object.

[0031] According to an embodiment of the present disclosure, the method further includes: in response to the target processing object being the first child node, eliminating the operation of the access request entering the main node.

[0032] According to one embodiment of the present disclosure, the judgment of whether the first child node of the requesting processor core storing the target data block is identified includes: obtaining the processor core identifier of any candidate processor core that the access request sent by the requesting processor core passes through before reaching the main node to which the target data block belongs; comparing the processor core identifier with the node identifiers of all first child nodes of the requesting processor core; and determining that the candidate processor core is the first child node storing the target data block in response to the presence of a target node identifier that is identical to the processor core identifier.

[0033] According to one embodiment of the present disclosure, the determining whether the first child node of the requesting processor core storing the target data block is identified includes: determining whether the first child node of the requesting processor core storing the target data block is identified through a Bloom filter, wherein the Bloom filter is respectively set in the routers corresponding to all processor cores.

[0034] According to one embodiment of the present disclosure, the Bloom filter is used to determine whether the first child node storing the target data block of the requesting processor core is identified, including: for any candidate processor core that the access request sent by the requesting processor core passes through before reaching the main node to which the target data block belongs, the Bloom filter is used to perform a fully associative search based on the access request to determine whether the candidate processor core is the first child node storing the target data block; in response to the Bloom filter determining that the candidate processor core is not the first child node storing the target data block, the access request is sent to the next processor core through the router of the candidate processor core; in response to the Bloom filter determining that the candidate processor core is the first child node storing the target data block, the access request is sent to the candidate processor core through the router corresponding to the candidate processor core.

[0035] To achieve the above-mentioned purpose, the second aspect embodiment of the present disclosure proposes an access device for a multi-level cache system, including: a judgment module, used to judge whether the first child node of the requesting processor core storing the target data block is identified before the access request sent by the requesting processor core reaches the main node to which the target data block belongs; a determination module, used to obtain a first distance from the requesting processor core to the second child node of the main node of the requesting processor core storing the target data block in response to not identifying the first child node, and obtain a second distance from the requesting processor core to the main node, and determine the target processing object from the second child node and the main node based on the first distance and the second distance; a processing module, used to process the access request through the target processing object.

[0036] To achieve the above-mentioned purpose, a third embodiment of the present disclosure provides an electronic device, including a memory and a processor;

[0037] The processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to implement the access method of the multi-level cache system as in any embodiment of the first aspect of the present disclosure.

[0038] To achieve the above-mentioned purpose, an embodiment of the fourth aspect of the present disclosure proposes a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to implement an access method of a multi-level cache system such as any embodiment of the first aspect of the present disclosure when executed by a processor.

[0039] To achieve the above-mentioned purpose, the fifth embodiment of the present disclosure proposes a computer program product, including a computer program, which, when executed by a processor, is used to implement an access method of a multi-level cache system as in any embodiment of the first aspect of the present disclosure.

[0040] To achieve the above-mentioned purpose, the sixth embodiment of the present disclosure proposes a computer program, including computer program code. When the computer program code is run on a computer, the computer executes the access method of the multi-level cache system as in any embodiment of the first aspect of the present disclosure.

[0041] Before the access request sent by the requesting processor core reaches the main node to which the target data block belongs, and if the first child node storing the target data block is not identified, by determining the first distance from the requesting processor core to the second child node, and determining the second distance from the requesting processor core to the main node, a target processing object with better transmission effect is selected from the second child node and the main node to process the access request, which can shorten the communication time and reduce the transmission power consumption. At the same time, the processing load of the main node can be shared by the second child node, thereby improving the performance of the multi-core processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] FIG1 is a schematic diagram of an access method of a multi-level cache system according to an embodiment of the present disclosure;

[0043] FIG2 is an example of a multi-level cache system architecture diagram according to an embodiment of the present disclosure;

[0044] FIG3 is a schematic diagram of another method for accessing a multi-level cache system according to an embodiment of the present disclosure;

[0045] FIG4 is a schematic diagram of another method for accessing a multi-level cache system according to an embodiment of the present disclosure;

[0046] FIG5 is a schematic diagram of another method for accessing a multi-level cache system according to an embodiment of the present disclosure;

[0047] FIG6 is a schematic diagram of a routing distribution diagram when the access request is a read invalidation request in an embodiment of the present disclosure;

[0048] FIG7 is a schematic diagram of a routing distribution diagram when the access request is a write invalidation request in an embodiment of the present disclosure;

[0049] FIG8 is a schematic diagram of another method for accessing a multi-level cache system according to an embodiment of the present disclosure;

[0050] FIG9 is a schematic diagram of another method for accessing a multi-level cache system according to an embodiment of the present disclosure;

[0051] FIG10 is a schematic diagram of maintaining a virtual tree structure and determining the sharer in a processor core according to an embodiment of the present disclosure;

[0052] FIG11 is a schematic structural diagram of a router component according to an embodiment of the present disclosure;

[0053] FIG12 is a schematic diagram of an access device of a multi-level cache system according to an embodiment of the present disclosure;

[0054] FIG13 is a schematic diagram of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0055] The following describes in detail embodiments of the present disclosure, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present disclosure, and should not be construed as limiting the present disclosure.

[0056] The acquisition, storage, use, and processing of data in this disclosed technical solution comply with the relevant provisions of relevant laws and regulations.

[0057] FIG1 is a schematic diagram of a method for accessing a multi-level cache system according to an embodiment of the present disclosure. As shown in FIG1 , the method for accessing the multi-level cache system includes the following steps S101 to S103 .

[0058] S101 , before an access request sent by a requesting processor core reaches a master node to which a target data block belongs, it is determined whether a first child node storing a target data block of the requesting processor core is identified.

[0059] The access method of the multi-level cache system of the embodiment of the present disclosure can be applied to the scenario of multi-core processor data processing. The executor of the access of the multi-level cache system of the embodiment of the present disclosure can be the access device of the multi-level cache system of the embodiment of the present disclosure, and the access device of the multi-level cache system can be set on an electronic device.

[0060] In implementation, the data stored in the multi-level cache system can be obtained by initiating a corresponding request to the multi-level cache system.

[0061] In some embodiments, a request corresponding to reading data stored in the multi-level cache system may be determined as an access request to the multi-level cache system.

[0062] In the embodiment of the present disclosure, the multi-level cache system is configured with a corresponding functional unit for receiving and reading the access requests it receives. The access requests sent to the multi-level cache system can be obtained by reading the information received in the functional unit.

[0063] In an embodiment of the present disclosure, a multi-core processor architecture is proposed, as shown in FIG2 , which is an example of a multi-level cache system architecture diagram proposed in an embodiment of the present disclosure. It should be noted that the interconnection structure of the multi-core processor in the embodiment of the present disclosure includes a multi-level cross network structure, a two-dimensional mesh network Mesh structure, a three-dimensional ring network Torus structure, etc., which are not limited here. Taking the two-dimensional Mesh structure as an example, a cache consistency protocol is maintained between multiple processor cores within a multi-core processor. In an embodiment of the present disclosure, the first-level cache memory (L1 Cache) is in the processor core, and the second-level cache memory (L2 Cache) is interconnected through an on-chip network, wherein the first-level cache memory is private to the processor core and the second-level cache memory is shared by multiple processor cores. The processor core may also include a private first-level cache memory and a private second-level cache memory, and the third-level cache memory is shared by multiple processor cores, and the third-level cache memory is interconnected through an on-chip network, which is not limited here. In the organizational architecture of the second-level cache memory shared and interconnected through the on-chip network (NoC) in the embodiment of the present disclosure, the second-level cache memory is uniformly addressed and each second-level cache memory block has a fixed master node (Home node), and cache consistency maintenance is performed through the master node directory protocol controller.

[0064] It should be noted that there are multiple master nodes in the multi-level cache system. The master node in the embodiment of the present disclosure is the master node specified by the access request, and the master node contains the target data block.

[0065] S102, in response to not identifying the first child node, obtain a first distance from the requesting processor core to the second child node of the main node of the requesting processor core, which stores the target data block, and obtain a second distance from the requesting processor core to the main node, and based on the first distance and the second distance, determine the target processing object from the second child node and the main node.

[0066] In the embodiment of the present disclosure, if the first child node is identified, the access request can be directly processed by the first child node, and the data in the target data block can be returned to the requesting processor core without subsequently entering the main node, thereby reducing the processing load of the main node.

[0067] If the first child node is not identified, in an embodiment of the present disclosure, a first distance from the requesting processor core to the second child node of the main node of the requesting processor core storing the target data block can be obtained, and a second distance from the requesting processor core to the main node can be obtained. Based on the first distance and the second distance, a target processing object that is closer to the requesting processor core can be selected from the main node and the second child node. This can shorten the communication time and reduce the transmission power consumption. At the same time, the processing load of the main node can be shared by the second child node.

[0068] In the embodiment of the present disclosure, there may be multiple methods for obtaining the first distance from the requesting processor core to the second sub-node storing the target data block of the main node of the requesting processor core, and obtaining the second distance from the requesting processor core to the main node. No limitation is made here, and the specific settings can be made according to actual design needs.

[0069] In some embodiments, this can be achieved through the distance perception technology of the master node. Based on the serial number of the child node recorded by the master node directory protocol controller, the routing algorithm adopted by the multi-core processor on-chip network can be used to calculate the distance from the child node to the requesting processor core, as well as the distance from the master node to the requesting processor core.

[0070] In some embodiments, a distance calculation model or algorithm may be used to calculate a first distance between the requesting processor core and a second child node of the requesting processor core's master node storing the target data block, and a second distance between the requesting processor core and the master node. This example calculation model or algorithm is pre-defined and can be modified based on actual design requirements, and is not limited herein.

[0071] S103: Process the access request through the target processing object.

[0072] In the embodiment of the present disclosure, the access request includes the storage information corresponding to the target access data block stored in the multi-level cache system. Therefore, the response to the requesting processor core can be achieved according to the access request.

[0073] In some embodiments, the data stored in the target access data block corresponding to the access request may be provided to the initiator of the access request according to the storage path of the target access data block indicated in the access request.

[0074] In some embodiments, it can be determined whether the access request can normally access the target access data block that needs to be read according to the storage status of the target access data block.

[0075] When it is determined that the target access data block can be read normally, return information corresponding to normal reading can be generated according to the access request, and the received access request can be responded to based on the return information.

[0076] Accordingly, when it is determined that the access request cannot normally read the target access data block, the reason why the access request cannot normally access the data block can be determined according to the access request, and corresponding response information can be generated to respond to the received access request.

[0077] In an embodiment of the present disclosure, before the access request sent by the requesting processor core reaches the main node to which the target data block belongs, it is determined whether the first child node storing the target data block of the requesting processor core is identified. In response to the first child node not being identified, a first distance from the requesting processor core to the second child node storing the target data block of the main node of the requesting processor core is obtained, and a second distance from the requesting processor core to the main node is obtained. Based on the first distance and the second distance, a target processing object is determined from the second child node and the main node, and finally the access request is processed by the target processing object. Thus, before the access request sent by the requesting processor core reaches the main node to which the target data block belongs, if the first child node storing the target data block is not identified, the first distance from the requesting processor core to the second child node and the second distance from the requesting processor core to the main node are determined, and a target processing object with better transmission effect is selected from the second child node and the main node to process the access request. This can shorten the communication time and reduce the transmission power consumption. At the same time, the processing load of the main node can be shared by the second child node, thereby improving the performance of the multi-core processor.

[0078] In an embodiment of the present disclosure, based on the first distance and the second distance, the target processing object is determined from the second child node and the main node. The first distance and the second distance can be compared first. In response to the existence of a first distance less than the second distance, the target child node corresponding to the minimum value in the first distance is determined as the target processing object. In response to the first distance being greater than or equal to the second distance, the main node is determined to be the target processing object. It should be noted that the target child node is the child node with the smallest first distance among the second child nodes.

[0079] In an embodiment of the present disclosure, an access request is processed by a target processing object. In response to the target processing object being a master node, data in a target data block is returned to the requesting processor core through the master node. In response to the target processing object being a target child node, a request type of the access request is obtained. Based on the request type, the access request is processed by the target child node.

[0080] In the above embodiment, the access request is processed by the target child node based on the request type, which can be further explained by Figure 3. Figure 3 is a schematic diagram of another access method of a multi-level cache system according to an embodiment of the present disclosure, and the method includes the following steps S301 to S302.

[0081] S301 , in response to a request type being a read invalidation request, forwarding the access request to a target child node via the master node.

[0082] In implementation, the first private cache of a multi-level cache system may send an access request to a second private cache, wherein, in response to the access status of the access request sent by the first private cache to the second private cache in the multi-level cache system being access invalid, the first private cache sends an invalidation processing request to the shared cache in the multi-level cache system.

[0083] In this scenario, the first private cache can continue to send the corresponding invalidation processing request to the shared cache at the next level. Through the response of the shared cache to the invalidation processing request initiated by it, the first private cache can receive the access request initiated by the second private cache.

[0084] It should be noted that a read miss request occurs when a processor core executes a fetch instruction whose address is not in the data cache. Therefore, the required cache line data must be obtained from the master node's L2 cache or another processor core.

[0085] After determining that the target child node corresponding to the minimum value in the first distance is the target processing object, it is necessary to send a read instruction to the target child node through the master node.

[0086] S302 : establishing an access link with the requesting processor core through the target child node based on the access request, and returning the data in the target data block to the requesting processor core through the access link.

[0087] In an embodiment of the present disclosure, in response to a read-failure request, the master node forwards the access request to the target child node. The target child node then establishes an access link with the requesting processor core based on the access request, and returns the data in the target data block to the requesting processor core via the access link. Thus, by forwarding the access request to a second child node closer to the requesting processor core via the master node, assuming the request type is a read-failure request, communication time can be shortened, transmission power consumption can be reduced, and the processing load of the master node can be shared by the second child node, thereby improving the performance of the multi-core processor.

[0088] In one embodiment of the present disclosure, a node identifier of a requesting processor core is obtained, and the node identifier is entered into a directory protocol controller of a master node, so that the requesting processor core is used as a child node of the master node.

[0089] In the embodiment of the present disclosure, the master node directory protocol controller can be set up according to the following table, without restriction. It only needs to record the cache block tag (TAG), cache block status and child nodes of the master node, that is, the owner bit vector of the processor core with backup that the master node needs to record.

[0090] It's important to note that different processor cores have corresponding node identifiers, which serve as a distinguishing and recording feature for different processor cores. After a requesting processor core obtains data from a target data block, it becomes eligible to become a second child of the master node. By recording the node identifier and becoming a second child of the master node, this provides more options for other processor cores to subsequently obtain data from the target data block.

[0091] The node identifier of the requesting processor core is entered in the target child node, so that the requesting processor core is used as a child node of the target child node.

[0092] In another embodiment of the present disclosure, the node identifier of the requesting processor core is entered into the target child node, thereby making the requesting processor core a child node of the target child node. Since the current requesting child node has obtained the data in the target data block, when the target child node needs to obtain data, the requesting processor core can serve as the first child node to provide data to the target child node before the access request reaches the master node to which the target data block belongs.

[0093] In the above embodiment, the access request is processed by the target child node based on the request type, which can be further explained by Figure 4. Figure 4 is a schematic diagram of another access method of a multi-level cache system according to an embodiment of the present disclosure, and the method includes the following steps S401 to S402.

[0094] S401 , in response to a request type being a write invalidation request, forwarding the access request to a target child node via a master node, and obtaining a data block status of a target data block.

[0095] In the embodiment of the present disclosure, the data block state of the target data block can be multiple, which is not limited herein. In some embodiments, the target data block can be divided into an exclusive state (Exclusive) and a shared state (Shared).

[0096] In the exclusive state, data can only be stored in the cache of one central processing unit (CPU) core, while the caches of other CPU cores do not have the data.

[0097] When in shared state, it means that the same data may be in the cache of multiple CPU cores.

[0098] It's important to note that a write-invalidate request occurs when a processor core executes a store instruction and the address of the store instruction doesn't match the data cache. This means the cache line required for the store isn't in the data cache. This is called a write-invalidate. A write-invalidate requires exclusive access and invalidates any cache copies of the same block owned by other processor cores before the store operation can proceed.

[0099] S402: Based on the data block status, the access request is processed through the target child node.

[0100] In the disclosed embodiment, in response to a data block being in a shared state, the target child node returns the data in the target data block to the requesting processor core, while the master node simultaneously invalidates the data in the target data block in all second child nodes. The directory protocol controller then changes the data block state of the target data block to an exclusive state, and records the owner of the target data block as the requesting processor core.

[0101] In response to the data block being in exclusive state, the target child node returns the data in the target data block to the requesting processor core, and invalidates the data in the target data block in the target child node. The directory protocol controller then records the owner of the target data block as the requesting processor core.

[0102] In an embodiment of the present disclosure, in response to a write-invalidation request, the master node forwards the access request to the target child node, obtains the data block status of the target data block, and then processes the access request based on the data block status. Thus, in the case of a write-invalidation request, by determining the data block status, different methods can be used to process the processor cores in the multi-level cache system, thereby improving the practicality of the present disclosure.

[0103] In the above embodiment, obtaining the first distance from the requesting processor core to the second child node storing the target data block of the main node of the requesting processor core, and obtaining the second distance from the requesting processor core to the main node can be further explained by Figure 5. Figure 5 is a schematic diagram of another access method of a multi-level cache system of an embodiment of the present disclosure, and the method includes the following steps S501 to S502.

[0104] S501 : Map the requesting processor core, all second child nodes of the requesting processor core, and the main node into a routing distribution map according to actual distribution positions in the on-chip network.

[0105] In the embodiment of the present disclosure, the routing distribution map is a distribution map according to the actual distribution position of each processor core in the on-chip network proposed in the embodiment of the present disclosure. Each node of the routing distribution map is a processor core, and the routing distribution map also includes a master node.

[0106] S502 : Calculate a first distance from the requesting processor core to at least one second sub-node of the requesting processor core, and a second distance from the requesting processor core to the main node based on the routing distribution graph.

[0107] In an embodiment of the present disclosure, a first X-direction hop count and a first Y-direction hop count from a requesting processor core to at least one second child node of the requesting processor core may be calculated based on a routing distribution graph, and a second X-direction hop count and a second Y-direction hop count from the requesting processor core to a master node may be calculated based on the routing distribution graph. Then, the first X-direction hop count and the first Y-direction hop count are added together to form a first distance, and the second X-direction hop count and the second Y-direction hop count are added together to form a second distance.

[0108] For example, as shown in Figure 6, Figure 6 is a schematic diagram of the routing distribution diagram of the access request of the embodiment of the present disclosure which is a read invalidation request. Request R1: Processor core A issues a first-level cache block read invalidation request (read_shared) and sends the request to the master node. At this time, only the master node has a backup of the block. The master node returns the shared status data to the requesting processor core A, and records in the master node directory protocol controller that processor core A has a backup of the block.

[0109] Request R2: Processor core B issues a read invalidation request (read_shared) for the same L1 cache block and sends the request to the master node. The master node then records that processor core A has a backup of the block. The master node calculates the distance from processor core A to the requesting processor core B, which is 2 hops in the horizontal X direction and 2 hops in the vertical Y direction, for a total of 4 hops. The master node calculates the distance from the requesting processor core B, which is 1 hop in the horizontal X direction and 2 hops in the vertical Y direction, for a total of 3 hops. The master node returns a response to the requesting processor core B, which is shorter. Therefore, the master node returns the shared state and data to the requesting processor core B and records in the master node directory protocol controller that processor core B also has a backup of the cache block. That is, both processor cores A and B have backups of the cache block.

[0110] Request R3: Processor C issues a read invalidation request (read_shared) for the same L1 cache block and sends it to the master node. Using the XY routing algorithm, the request does not pass through processor cores A and B on its way to the master node. Upon reaching the master node, the request queries the master node's directory protocol controller, recording that processor cores A and B have copies of the cache block. The master node calculates the distance from processor core A to the requesting processor C as 2 hops in the horizontal X direction and 3 hops in the vertical Y direction, for a total of 5 hops. The distance from processor core B to the requesting processor C is 0 hop in the horizontal X direction and 1 hop in the vertical Y direction, for a total of 1 hop. The distance from the master node to the requesting processor C is 1 hop in the horizontal X direction and 3 hops in the vertical Y direction, for a total of 4 hops. Since the distance for processor core B to return the status and data response to processor core C is shorter, the master node notifies processor core B to return the shared status and data to the requesting processor C. Simultaneously, the master node records in processor core B that processor core C also has a copy of the block, making processor core C a child of processor core B.

[0111] Request R4: Processor core D issues a read-failure request (read_shared) for the same primary cache block and sends the request to the master node. Using the XY routing algorithm, the read_shared request passes through the node processor core C in the virtual tree of the target cache block during transmission to the master node. Processor core C has the required cache block data backup. The router then directly sends the request to processor core C, which then returns the cache block status and data response to the requester, processor core D, without having to resend the request to the master node for the master node directory protocol controller to operate. Furthermore, the request to processor core D is recorded in processor core C, which acts as its child node.

[0112] For example, as shown in Figure 7, processor core D issues a read_exclusive write invalidation request R for a first-level cache block. The target cache block is in a shared state, so D directly sends the request to the master node directory controller for unified processing. The directory searches for processor core A, which holds a data backup and is close to the requester, and forwards the request to processor core A, asking it to provide the data. The master node directory protocol controller records the processor cores that own the backup, namely processor cores A and B. The stored shared backups must be invalidated, meaning the master node sends an invalidate request (Invalidate) to processor cores A and B. Processor core A, an intermediate node in the virtual tree, is responsible for invalidating the data backup of processor core C, the sharer that obtained the data from this node. After completing the invalidation, processor core C sends a response to processor core A. After completing the invalidation, processor cores A and B return a response to the invalidation request to the master node. After the invalidation request responses are returned to the master node, the cache block status recorded by the master node directory protocol controller changes from shared to exclusive by the requester, and records the processor core with exclusive status as processor core D.

[0113] It should be noted that, since there may be multiple paths from one node to another in the routing distribution graph, in the embodiment of the present disclosure, only the optimal path is selected as the distance that needs to be finally calculated.

[0114] The first distance from the requesting processor core to at least one second sub-node of the requesting processor core is calculated based on the routing distribution graph. For any second sub-node of the requesting processor core, the candidate distances of all paths from the requesting processor core to the second sub-node are determined in the routing distribution graph, and then the minimum value among the candidate distances is used as the first distance between the requesting processor core and the second sub-node.

[0115] In an embodiment of the present disclosure, the requesting processor core, all of the requesting processor core's second child nodes, and the master node are first mapped into a routing map according to their actual distribution locations in the on-chip network. Then, based on the routing map, a first distance from the requesting processor core to at least one of the requesting processor core's second child nodes, as well as a second distance from the requesting processor core to the master node, are calculated. Thus, using the routing map proposed in the present disclosure, the distances from the requesting processor core to the master node and the second node can be quickly calculated, which is more efficient and intuitive.

[0116] In the above embodiment, before the access request sent by the requesting processor core reaches the main node to which the target data block belongs, if the first child node of the requesting processor core storing the target data block is identified, it can also be processed by the method shown in Figure 8. Figure 8 is a schematic diagram of another access method of a multi-level cache system according to an embodiment of the present disclosure, and the method includes the following steps S801 to S802.

[0117] S801 : In response to identifying a first child node, obtaining a data block status of a target data block and a request type of an access request.

[0118] In an embodiment of the present disclosure, to determine whether the first child node is identified, the processor core identifier of the candidate processor core can be first obtained for any candidate processor core that the access request sent by the requesting processor core passes through before reaching the main node to which the target data block belongs. The processor core identifier is then compared with the node identifiers of all first child nodes of the requesting processor core. Finally, in response to the existence of a target node identifier that is identical to the processor core identifier, the candidate processor core is determined to be the first child node that stores the target data block.

[0119] S802: Determine a target processing object from the first child node and the master node based on the data block status and the request type.

[0120] In an embodiment of the present disclosure, in response to the data block status being a shared state and the request type being a write failure request, the master node is determined as the target processing object, and in response to the data block status being a non-shared state, the first child node is determined as the target processing object.

[0121] It should be noted that, if the data block state is shared state and the request type is a write failure request, for simplifying the process, no matter whether run into the node of this piece place virtual tree, all request is sent to the master node directory protocol controller unified processing.Master node will seek for holding data backup and the second processor core nearer to the requester, and request is forwarded to it, allows it to provide data.The shared backup that preserves in all processor cores of directory record will all be invalidated, and the intermediate node of virtual tree is responsible for invalidating the sharer processor core that obtains data from this node, and the cache block state of directory record is become exclusive by the requester from sharing.If directory does not find closer sharer, then return data by the secondary Cache of master node.

[0122] If the data block state is a non-shared state, the first child node is determined to be a target processing object.

[0123] It should be noted that if the target processing object is the first child node, the operation of accessing the main node is eliminated.

[0124] In the disclosed embodiment, first, in response to identifying the first child node, the data block status of the target data block and the request type of the access request are obtained. Then, based on the data block status and the request type, a target processing object is determined from the first child node and the master node. Thus, by obtaining the data block status of the target data block and the request type of the access request, and selecting a target processing object with a better data processing performance from the first child node and the master node, the first child node can share the processing load with the master node, thereby improving the performance of the multi-core processor.

[0125] In the above embodiment, to determine whether the first child node storing the target data block of the requesting processor core is identified, the processor core identifier of the candidate processor core can be obtained for any candidate processor core that the access request sent by the requesting processor core passes through before reaching the main node to which the target data block belongs, and the processor core identifier is compared with the node identifiers of all the first child nodes of the requesting processor core. In response to the existence of a target node identifier that is identical to the processor core identifier, the candidate processor core is determined to be the first child node storing the target data block.

[0126] It should be noted that the node identifiers of all first child nodes may be stored in the directory protocol controller. When a comparison is required, the node identifiers of the first child nodes and the processor core identifiers may be compared via the directory protocol controller.

[0127] In another embodiment of the present disclosure, whether the first child node storing the target data block of the requesting processor core is identified can be determined by using a Bloom filter, wherein the Bloom filter is respectively set in the routers corresponding to all processor cores and can also be set in the processor core.

[0128] In an embodiment of the present disclosure, whether the first child node storing the target data block of the requesting processor core is identified is determined by a Bloom filter, which can be further explained by Figure 9. Figure 9 is a schematic diagram of another access method of a multi-level cache system according to an embodiment of the present disclosure, and the method includes the following steps S901 to S903.

[0129] S901, for any candidate processor core that the access request sent by the requesting processor core passes through before reaching the main node to which the target data block belongs, a full associative search is performed based on the access request through a Bloom filter to determine whether the candidate processor core is the first child node storing the target data block.

[0130] In the disclosed embodiment, as shown in Figure 10, Figure 10 is a schematic diagram of maintaining a virtual tree structure and carrying out the determination of having a sharer in the processor core, which requires increased hardware. First, it is necessary to increase the hardware for maintaining the virtual tree structure. In each processor core, a structure VT Node field is added to preserve the sharer information, which is used to preserve the child node information of the virtual tree with the processor core as the parent node. A Bloom Filter structure is added in the router to determine whether the target cache block is in the primary cache of the corresponding processor core. Specifically, before the access request sent by the requesting processor core reaches the master node to which the target data block belongs, the requesting processor core can be determined by the Bloom Filter to determine whether it is identified. In order to avoid the mutual contamination of the instruction cache block and the data cache block to the Bloom Filter, an instruction Bloom Filter filter and a data Bloom Filter filter are implemented respectively. The Bloom Filter determines that requests in the four directions of up, down, left and right are carried out simultaneously, and the request address is sent to the Bloom Filter to perform a fully associative search. If the Bloom Filter determines that it hits, the request is sent to the processor core, and the request query is performed on the primary cache. The primary cache checks whether the request is actually in the processor core, and if so, returns the data. If the Bloom Filter determines that the request is not in the processor core, or if the Bloom Filter determines that the request is in the processor core but the query shows that the request is not in the processor core, the router will continue to transmit the request to the next hop node. The Bloom Filter decision can be performed in parallel with the route calculation, without increasing the pipeline level of the router.

[0131] It should be noted that, as shown in Figure 10, requests between the router component and the Bloom filter in the router are requests in the four directions of up, down, left, and right, and responses between the router component and the Bloom filter are also responses in the four directions of up, down, left, and right, which are not shown in Figure 10. Figure 11 is a schematic diagram of the structure of a router component in an embodiment of the present disclosure, including a crossbar switch and an arbiter, for exchanging requests and responses with the Bloom filter in the four directions of up, down, left, and right.

[0132] It should be noted that the first-level cache consistency control component in the processor core takes each cache line data as 256 bits and the first-level cache tag TAG as 36 bits as an example. The dirty bit indicates whether the data is dirty data. If it is dirty data, it needs to be written back to the second-level cache when it is replaced. 0 means it is not dirty data, and 1 means it is dirty data. The status bit indicates the status of the first-level cache block, including shared state, exclusive state, and invalid state. The virtual tree node domain stores the sharer information. For example, A, B, and C in Figure 3 are all identifiers of the first child node. If it is not the first child node, it can be represented by -1.

[0133] It should be noted that the Bloom filter signature has the following characteristics: if the judgment result is yes, the element is not necessarily in the set; but if the judgment result is no, the element is definitely not in the set. Therefore, if the Bloom filter determines that the element is not in the processor core, it is definitely not in the corresponding processor core's L1 cache.

[0134] The primary data structure of a Bloom filter is a bit array consisting of m binary bits, all initially set to 0. The Bloom filter also requires k hash functions, which map input elements to k positions in the bit array, each marked with a 1. The specific hash function can be any hash algorithm, without limitation, such as MD5 and SHA1.

[0135] When inserting an element into a Bloom filter, it is necessary to map the element to k positions in the bit array through k hash functions and set the values ​​of these positions to 1. When checking whether an element is in the Bloom filter, it is only necessary to map the element to k positions in the bit array through k hash functions and check whether the values ​​of these positions are all 1. If they are all 1, the element may exist in the set, otherwise the element definitely does not exist in the set.

[0136] Counting Bloom Filter (CBF) is an improved algorithm based on Bloom Filter that can count the number of repetitions of each element and allow elements to be deleted.

[0137] The main feature of CBF is that instead of storing only 0s or 1s in the bit array, an L-bit counter is used to store the number of times each element appears. Specifically, CBF uses a bit array C of m elements and k hash functions, each of which maps an element to a position in the bit array. For an element e, the corresponding CBF calculation method includes:

[0138] Add 1 to the counters of all locations in C that are mapped by the hash function;

[0139] If the counter value exceeds a threshold (usually 3), the element is marked as present in the CBF;

[0140] When querying whether an element is in the CBF, it is necessary to query whether the values ​​of the counters at all locations mapped by the hash function are greater than 0. If they are all greater than 0, it is considered that the element may exist in the CBF; and

[0141] When deleting an element, the counters of all the locations in the CBF to which the hash function is mapped need to be reduced by 1. If the counter at a certain location is reduced to 0, it is considered that the element no longer exists in the CBF.

[0142] In the embodiment of the present disclosure, in order to reduce the possibility that a coherence request address that does not exist in the processor core is mistakenly determined to exist in the processor core and further reduce additional access to the processor core, a Bloom Filter with a counter may be used for determination.

[0143] S902 : In response to the Bloom filter determining that the candidate processor core is not the first child node storing the target data block, send the access request to the next processor core through the router of the candidate processor core.

[0144] S903 : In response to the Bloom filter determining that the candidate processor core is the first child node storing the target data block, an access request is sent to the candidate processor core through a router corresponding to the candidate processor core.

[0145] In the embodiment disclosed herein, first, for any candidate processor core that the access request sent by the requesting processor core passes through before reaching the main node to which the target data block belongs, a full associative search is performed based on the access request through a Bloom filter to determine whether the candidate processor core is the first child node storing the target data block. In response to the Bloom filter determining that the candidate processor core is not the first child node storing the target data block, the access request is sent to the next processor core through the router of the candidate processor core. In response to the Bloom filter determining that the candidate processor core is the first child node storing the target data block, the access request is sent to the candidate processor core through the router corresponding to the candidate processor core. Therefore, by introducing the Bloom filter, the determination and routing calculation can be performed in parallel without increasing the pipeline level of the router, and the determination result of the Bloom filter is more accurate.

[0146] Corresponding to the access methods of the multi-level cache system provided in the above-mentioned embodiments, an embodiment of the present disclosure also provides an access device for a multi-level cache system. Since the access device for the multi-level cache system provided in the embodiment of the present disclosure corresponds to the access methods for the multi-level cache system provided in the above-mentioned embodiments, the implementation methods of the above-mentioned multi-level cache system are also applicable to the access device for the multi-level cache system provided in the embodiment of the present disclosure, and will not be described in detail in the following embodiments.

[0147] FIG12 is a schematic diagram of an access device of a multi-level cache system according to an embodiment of the present disclosure. As shown in FIG12 , the access device 1200 of the multi-level cache system includes: a judgment module 1210 , a determination module 1220 , and a processing module 1230 .

[0148] The judgment module 1210 is configured to judge whether the first child node storing the target data block of the requesting processor core is identified before the access request sent by the requesting processor core reaches the master node to which the target data block belongs.

[0149] Determination module 1220 is used to obtain a first distance from the requesting processor core to the second sub-node storing the target data block of the main node of the requesting processor core in response to the first sub-node not being identified, and obtain a second distance from the requesting processor core to the main node, and determine the target processing object from the second sub-node and the main node based on the first distance and the second distance.

[0150] The processing module 1230 is configured to process the access request through the target processing object.

[0151] In one embodiment of the present disclosure, the determination module 1220 is further used to: compare the first distance and the second distance; in response to the existence of a first distance smaller than the second distance, determine the target sub-node corresponding to the minimum value in the first distance as the target processing object; in response to the first distances being greater than or equal to the second distance, determine the main node as the target processing object.

[0152] In one embodiment of the present disclosure, the determination module 1220 is further used to: in response to the target processing object being a master node, return the data in the target data block to the requesting processor core through the master node; in response to the target processing object being a target child node, obtain the request type of the access request, and based on the request type, process the access request through the target child node.

[0153] In one embodiment of the present disclosure, the determination module 1220 is further used to: in response to a request type being a read invalidation request, forward the access request to the target child node through the master node; establish an access link with the requesting processor core based on the access request through the target child node, and return the data in the target data block to the requesting processor core through the access link.

[0154] In one embodiment of the present disclosure, the determination module 1220 is further configured to: enter the node identifier of the requesting processor core in the target subnode, so as to make the requesting processor core a subnode of the target subnode.

[0155] In one embodiment of the present disclosure, the determination module 1220 is further configured to: obtain a node identifier of the requesting processor core; and enter the node identifier into the directory protocol controller of the master node to treat the requesting processor core as a child node of the master node.

[0156] In one embodiment of the present disclosure, the determination module 1220 is further used to: in response to the request type being a write failure request, forward the access request to the target child node through the master node, and obtain the data block status of the target data block; based on the data block status, process the access request through the target child node.

[0157] In one embodiment of the present disclosure, the determination module 1220 is further used to: in response to the data block status being a shared state, return the data in the target data block to the requesting processor core through the target child node, and at the same time invalidate the data of the target data blocks in all second child nodes through the main node.

[0158] In one embodiment of the present disclosure, the determination module 1220 is further configured to: modify the data block state of the target data block to an exclusive state through the directory protocol controller, and record the owner of the target data block as the requesting processor core.

[0159] In one embodiment of the present disclosure, the determination module 1220 is further used to: in response to the data block status being an exclusive state, return the data in the target data block to the requesting processor core through the target child node, and invalidate the data of the target data block in the target child node.

[0160] In one embodiment of the present disclosure, the owner of the target data block is recorded as the requesting processor core through the directory protocol controller.

[0161] In one embodiment of the present disclosure, the determination module 1220 is further used to: map the requesting processor core, all second sub-nodes of the requesting processor core, and the main node into a routing distribution map according to their actual distribution positions in the on-chip network; and calculate a first distance from the requesting processor core to at least one second sub-node of the requesting processor core, and a second distance from the requesting processor core to the main node based on the routing distribution map.

[0162] In one embodiment of the present disclosure, the determination module 1220 is further configured to calculate, based on the routing distribution graph, a first distance between the requesting processor core and at least one second child node of the requesting processor core, and a second distance between the requesting processor core and the master node, including: calculating, based on the routing distribution graph, a first X-direction hop count and a first Y-direction hop count from the requesting processor core to the at least one second child node of the requesting processor core, and calculating, based on the routing distribution graph, a second X-direction hop count and a second Y-direction hop count from the requesting processor core to the master node; adding the first X-direction hop count and the first Y-direction hop count to obtain the first distance, and adding the second X-direction hop count and the second Y-direction hop count to obtain the second distance.

[0163] In one embodiment of the present disclosure, the determination module 1220 is further used to: for any second sub-node of the requesting processor core, determine the candidate distances of all paths from the requesting processor core to the second sub-node in the routing distribution map; and use the minimum value of the candidate distances as the first distance between the requesting processor core and the second sub-node.

[0164] In one embodiment of the present disclosure, the determination module 1220 is further used to: in response to identifying the first child node, obtain the data block status of the target data block and the request type of the access request; based on the data block status and the request type, determine the target processing object from the first child node and the main node.

[0165] In one embodiment of the present disclosure, the determination module 1220 is further used to: in response to the data block status being a shared state and the request type being a write failure request, determine the master node as the target processing object; in response to the data block status being a non-shared state, determine the first child node as the target processing object.

[0166] In one embodiment of the present disclosure, the determination module 1220 is further configured to: in response to the target processing object being the first child node, eliminate the operation of the access request entering the main node.

[0167] In one embodiment of the present disclosure, the judgment module 1210 is further used to: obtain the processor core identifier of a candidate processor core for any candidate processor core that the access request sent by the requesting processor core passes through before reaching the main node to which the target data block belongs; compare the processor core identifier with the node identifiers of all first child nodes of the requesting processor core; and in response to the presence of a target node identifier that is identical to the processor core identifier, determine that the candidate processor core is the first child node storing the target data block.

[0168] In one embodiment of the present disclosure, the judgment module 1210 is further configured to: determine whether the first child node storing the target data block of the requesting processor core is identified through a Bloom filter, wherein the Bloom filter is respectively set in the routers corresponding to all the processor cores.

[0169] In one embodiment of the present disclosure, the judgment module 1210 is further configured to: for any candidate processor core that the access request sent by the requesting processor core passes through before reaching the master node to which the target data block belongs, perform a fully associative search based on the access request using a Bloom filter to determine whether the candidate processor core is the first child node storing the target data block; in response to the Bloom filter determining that the candidate processor core is not the first child node storing the target data block, send the access request to the next processor core via the router of the candidate processor core. In response to the Bloom filter determining that the candidate processor core is the first child node storing the target data block, send the access request to the candidate processor core via the router corresponding to the candidate processor core.

[0170] In order to implement the above embodiments, the embodiments of the present disclosure also propose an electronic device 1300. Figure 13 is a schematic diagram of an electronic device of an embodiment of the present disclosure. As shown in Figure 13, the electronic device 1300 includes: a processor 1301 and a memory 1302 communicatively connected to the processor, the memory 1302 stores instructions that can be executed by at least one processor, and the instructions are executed by at least one processor 1301, so as to implement the access method of the multi-level cache system of the embodiments of Figures 1 to 11 of the present disclosure.

[0171] In order to implement the above embodiments, the embodiments of the present disclosure also propose a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable a computer to implement an access method of a multi-level cache system as in the embodiments of Figures 1 to 10 of the present disclosure.

[0172] In order to implement the above embodiments, the embodiments of the present disclosure further provide a computer program product, including a computer program. When the computer program is executed by a processor, the computer program implements the access method of the multi-level cache system of the embodiments of Figures 1 to 10 of the present disclosure.

[0173] In order to implement the above embodiments, the embodiments of the present disclosure also propose a computer program, including computer program code. When the computer program code runs on a computer, the computer executes the access method of the multi-level cache system of the embodiments of Figures 1 to 10 of the present disclosure.

[0174] It should be noted that the explanation of the access method of the multi-level cache system in the above embodiment is also applicable to the device, computer-readable storage medium, computer program product and computer program of the embodiment of the present disclosure, and will not be repeated here.

[0175] All embodiments of the present disclosure may be implemented individually or in combination with other embodiments, and are all considered to be within the scope of protection claimed by the present disclosure.

[0176] It is important to note that personal information collected from users should be used for legitimate and reasonable purposes and should not be shared or sold beyond these legitimate uses. Furthermore, such collection / sharing should be conducted only after receiving the user's informed consent, including but not limited to notifying the user to read the user agreement / user notice and sign an agreement / authorization that includes the relevant user information before using the feature. Furthermore, any necessary steps must be taken to safeguard and secure access to such personal information and ensure that others with access to personal information comply with its privacy policy and procedures.

[0177] This disclosure contemplates providing implementations that allow users to selectively block the use or access of personal information data. Specifically, this disclosure contemplates providing hardware and / or software to prevent or block access to such personal information data. Risks can be minimized by limiting data collection and deleting data once it is no longer needed. Furthermore, where applicable, such personal information can be de-identified to protect user privacy.

[0178] In the descriptions of the aforementioned embodiments, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are mutually inconsistent.

[0179] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. Throughout the present disclosure, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0180] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present disclosure includes additional implementations in which functions may be performed out of the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present disclosure belong.

[0181] The logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (e.g., a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). For purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include the following: an electrical connection with one or more wires (electronic devices), a portable computer disk cartridge (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and a portable compact disc read-only memory (CDROM). Furthermore, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or otherwise processing it in a suitable manner if necessary, and then storing it in a computer memory.

[0182] It should be understood that various parts of the present disclosure can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used to implement: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0183] Those skilled in the art will understand that all or part of the steps in the method for implementing the above-mentioned embodiment can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiment.

[0184] In addition, the functional units in the various embodiments of the present disclosure may be integrated into a single processing module, each unit may exist physically separately, or two or more units may be integrated into a single module. The aforementioned integrated modules may be implemented in the form of hardware or in the form of software functional modules. If the integrated modules are implemented in the form of software functional modules and sold or used as independent products, they may also be stored in a computer-readable storage medium.

[0185] The storage medium mentioned above may be a read-only memory, a magnetic disk, or an optical disk, etc. Although the embodiments of the present disclosure have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. A person of ordinary skill in the art may make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A method for accessing a multi-level cache system, comprising: Before the access request sent by the requesting processor core reaches the master node to which the target data block belongs, determining whether the first child node of the requesting processor core storing the target data block is identified; In response to not identifying the first child node, obtaining a first distance from the requesting processor core to a second child node of the master node of the requesting processor core, where the target data block is stored, and obtaining a second distance from the requesting processor core to the master node, and determining a target processing object from the second child node and the master node based on the first distance and the second distance; The access request is processed by the target processing object.

2. The method according to claim 1, wherein determining a target processing object from the second child node and the main node based on the first distance and the second distance comprises: comparing the first distance and the second distance; In response to a first distance smaller than the second distance, determining a target child node corresponding to a minimum value of the first distance as the target processing object; In response to the first distances being greater than or equal to the second distances, the master node is determined to be the target processing object.

3. The method according to claim 2, wherein processing the access request by the target processing object comprises: In response to the target processing object being the master node, returning the data in the target data block to the requesting processor core via the master node; In response to the target processing object being the target child node, a request type of the access request is obtained, and based on the request type, the access request is processed by the target child node.

4. The method according to claim 3, wherein processing the access request by the target subnode based on the request type comprises: In response to the request type being a read invalidation request, forwarding the access request to the target child node through the master node; An access link is established with the requesting processor core based on the access request through the target child node, and the data in the target data block is returned to the requesting processor core through the access link.

5. The method according to claim 4, wherein the method further comprises: The node identifier of the requesting processor core is entered into the target child node, so as to make the requesting processor core a child node of the target child node.

6. The method according to claim 5, wherein the method further comprises: Obtaining a node identifier of the requesting processor core; The node identifier is entered into the directory protocol controller of the master node to make the request processor core a child node of the master node.

7. The method according to claim 3, wherein processing the access request by the target child node based on the request type comprises: In response to the request type being a write invalidation request, forwarding the access request to the target child node through the master node, and obtaining a data block status of the target data block; The access request is processed by the target child node based on the data block status.

8. The method according to claim 7, wherein processing the access request by the target child node based on the data block status comprises: In response to the data block being in a shared state, the data in the target data block is returned to the requesting processor core via the target child node, and at the same time, the data in the target data block in all second child nodes is invalidated via the master node.

9. The method according to claim 8, wherein the method further comprises: The data block state of the target data block is modified to an exclusive state through a directory protocol controller, and the owner of the target data block is recorded as the requesting processor core.

10. The method according to claim 7, wherein processing the access request by the target child node based on the data block status comprises: In response to the data block state being an exclusive state, the data in the target data block is returned to the requesting processor core through the target child node, and the data in the target data block in the target child node is invalidated.

11. The method according to claim 10, wherein the method further comprises: The directory protocol controller records the owner of the target data block as the requesting processor core.

12. The method according to any one of claims 1 to 11, wherein obtaining a first distance from the requesting processor core to a second child node of the master node of the requesting processor core, where the target data block is stored, and obtaining a second distance from the requesting processor core to the master node, comprises: Mapping the request processor core, all second child nodes of the request processor core, and the master node into a routing distribution map according to actual distribution positions in the on-chip network; A first distance from the request processor core to at least one second child node of the request processor core and a second distance from the request processor core to the main node are calculated based on the routing distribution map.

13. The method according to claim 12, wherein calculating, based on the routing distribution graph, a first distance from the requesting processor core to at least one second child node of the requesting processor core and a second distance from the requesting processor core to the master node comprises: calculating a first X-direction hop count and a first Y-direction hop count from the requesting processor core to at least one second child node of the requesting processor core based on the routing distribution map, and calculating a second X-direction hop count and a second Y-direction hop count from the requesting processor core to the master node based on the routing distribution map; The first X-direction hop count and the first Y-direction hop count are added together to obtain the first distance, and the second X-direction hop count and the second Y-direction hop count are added together to obtain the second distance.

14. The method according to claim 12 or 13, wherein calculating the first distance from the requesting processor core to at least one second child node of the requesting processor core based on the routing distribution map comprises: For any second child node of the requesting processor core, determining, in the routing distribution map, candidate distances of all paths from the requesting processor core to the second child node; The minimum value among the candidate distances is used as the first distance between the requesting processor core and the second child node.

15. The method according to any one of claims 1 to 14, wherein the method further comprises: In response to identifying the first child node, obtaining a data block status of the target data block and a request type of the access request; Based on the data block status and the request type, a target processing object is determined from the first child node and the master node.

16. The method according to claim 15, wherein determining a target processing object from the first child node and the master node based on the data block status and the request type comprises: In response to the data block state being a shared state and the request type being a write invalidation request, determining the master node as the target processing object; In response to the data block being in a non-shared state, the first child node is determined to be the target processing object.

17. The method according to claim 16, wherein the method further comprises: In response to the target processing object being the first child node, the operation of the access request entering the main node is eliminated.

18. The method according to any one of claims 1 to 17, wherein the determining whether the first child node storing the target data block of the requesting processor core is identified comprises: For any candidate processor core that the access request sent by the requesting processor core passes through before reaching the master node to which the target data block belongs, obtaining a processor core identifier of the candidate processor core; Comparing the processor core identifier with node identifiers of all first child nodes of the requesting processor core; In response to the presence of a target node identifier identical to the processor core identifier, the candidate processor core is determined to be the first child node storing the target data block.

19. The method according to any one of claims 1 to 17, wherein the determining whether the first child node storing the target data block of the requesting processor core is identified comprises: A Bloom filter is used to determine whether the first child node of the requesting processor core storing the target data block is identified, wherein the Bloom filter is respectively set in the routers corresponding to all the processor cores.

20. The method according to claim 19, wherein determining whether the first child node storing the target data block of the requesting processor core is identified through a Bloom filter comprises: For any candidate processor core that the access request sent by the requesting processor core passes through before reaching the master node to which the target data block belongs, performing a full associative search based on the access request through the Bloom filter to determine whether the candidate processor core is the first child node storing the target data block; In response to the Bloom filter determining that the candidate processor core is not the one storing the target data block, The first child node sends the access request to the next processor core through the router of the candidate processor core; In response to the Bloom filter determining that the candidate processor core is the first child node storing the target data block, the access request is sent to the candidate processor core through a router corresponding to the candidate processor core.

21. An access device for a multi-level cache system, comprising: a judgment module, configured to judge whether a first child node storing the target data block of the requesting processor core is identified before the access request sent by the requesting processor core reaches the master node to which the target data block belongs; a determination module configured to, in response to failure to identify the first child node, obtain a first distance from the requesting processor core to a second child node of the master node of the requesting processor core, where the target data block is stored, and obtain a second distance from the requesting processor core to the master node, and determine a target processing object from the second child node and the master node based on the first distance and the second distance; A processing module is used to process the access request through the target processing object.

22. An electronic device comprising a memory and a processor; in, The processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to implement the access method of the multi-level cache system according to any one of claims 1 to 20.

23. A computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are used to implement the access method of the multi-level cache system according to any one of claims 1 to 20 when executed by a processor. 24 . A computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements the method for accessing the multi-level cache system according to claim 1 . 25 . A computer program comprising computer program codes, which, when executed on a computer, causes the computer to execute the method for accessing a multi-level cache system according to claim 1 .

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