Cache replacement method and apparatus for multi-core processor

Abstract

Disclosed are a cache replacement method and apparatus for a multi-core processor, an electronic device, a storage medium, a computer program product, and a computer program.

Description

A cache replacement method and device for a multi-core processor

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese Patent Application No. 2024103653944 filed in China on March 28, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of processor technology, and in particular to a cache replacement method, device, electronic device, storage medium, computer program product, and computer program for a multi-core processor. Background Art

[0004] The rapid development of semiconductor technology has led to ever-increasing microprocessor speeds and integration. The number and variety of transistor resources available to processor designers are increasing. Multi-core processors are the trend in high-performance processor design, and the trend is toward an increasing number of on-chip processor cores. This is accompanied by a rapid increase in the scale and complexity of processor designs. Efficiently implementing multi-core cache coherence—maintaining cache coherence while effectively utilizing valuable on-chip cache resources and improving storage resource utilization—is a key research topic of widespread concern in academia and industry.

[0005] Summary of the Invention

[0006] The present disclosure aims to solve one of the technical problems in the related art at least to a certain extent.

[0007] Therefore, one objective of the present disclosure is to provide a cache replacement method for a multi-core processor.

[0008] A second objective of the present disclosure is to provide a cache replacement device for a multi-core processor.

[0009] A third objective of the present disclosure is to provide an electronic device.

[0010] A fourth object of the present disclosure is to provide a non-transitory computer-readable storage medium.

[0011] A fifth object of the present disclosure is to provide a computer program product.

[0012] A sixth object of the present disclosure is to provide a computer program.

[0013] To achieve the above-mentioned purpose, an embodiment of the first aspect of the present disclosure proposes a cache replacement method for a multi-core processor, comprising: sending a first access request to a first-level private cache included in a multi-level cache system, and determining a first hit status of the first access request in the first-level private cache; in response to a first target data block to be accessed by the first access request not existing in the first-level private cache, or the first target data block being in an invalid state, determining that the first hit status of the first access request in the first-level private cache is an access miss, then generating first replacement information corresponding to the first-level private cache based on a preset replacement strategy, the first replacement information including first way information and first address information corresponding to the first data block to be replaced in the first-level private cache; generating a second access request sent to a second-level shared cache based on the first replacement information, wherein the second-level shared cache is an adjacent lower-level cache of the first-level private cache;

[0014] Sending the second access request to the secondary shared cache, and determining a second hit status of the second access request in the secondary shared cache;

[0015] In response to the second hit status indicating that the second access request has hit the second level shared cache, obtaining return data from the second level shared cache, and completing cache replacement of the first level private cache based on the return data;

[0016] In response to the second hit status indicating that the second access request misses the second shared cache, obtaining a plurality of candidate second replacement information corresponding to the second shared cache based on a preset replacement strategy;

[0017] Sending a third access request to the lower-layer storage system and obtaining return data returned from the lower-layer storage system;

[0018] Acquire the first address information included in the first replacement information, and acquire the candidate second address information included in each candidate second replacement information among the plurality of candidate second replacement information;

[0019] Comparing the first address information with each of the candidate second address information to determine whether there is candidate second address information that is the same as the first address information;

[0020] If there is candidate second address information identical to the first address information, performing cache replacement on the second data block corresponding to the identical candidate second address information based on the returned data returned by the lower-layer storage system;

[0021] If there is no candidate second address information identical to the first address information, a second data block corresponding to one of the plurality of candidate second address information is cache-replaced based on the return data returned by the lower-layer storage system.

[0022] According to one embodiment of the present disclosure, cache replacement of the first-level private cache is completed based on the returned data, including: recording first replacement information in the cache directory corresponding to the second-level shared cache; and cache replacing the first data block corresponding to the first replacement information based on the returned data.

[0023] According to one embodiment of the present disclosure, first replacement information is recorded in a cache directory corresponding to a secondary shared cache, including: determining whether there is an empty path of a directory entry in the cache directory; if there is an empty path of a directory entry in the cache directory, recording the first replacement information in the empty path of the directory entry; if there is no empty path of a directory entry in the cache directory, determining a directory entry to be replaced from the cache directory, and recording the first replacement information in the directory entry to be replaced.

[0024] According to one embodiment of the present disclosure, determining a directory item to be replaced from a cache directory includes: obtaining multiple candidate directory item information corresponding to the cache directory based on a preset replacement strategy; obtaining first address information contained in first replacement information, and obtaining candidate directory item address information contained in each candidate directory item information in the multiple candidate directory item information; comparing the first address information with each candidate directory item address information to determine whether there is candidate directory item address information that is identical to the first address information; if there is candidate directory item address information that is identical to the first address information, determining that the directory item corresponding to the identical candidate directory item address information is the directory item to be replaced; if there is no candidate directory item address information that is identical to the first address information, determining that the directory item corresponding to one of the candidate directory item address information in the multiple candidate directory item information is the directory item to be replaced.

[0025] According to one embodiment of the present disclosure, determining a second hit status of a second access request in the secondary shared cache includes: in response to the second target data block to be accessed by the second access request existing in the secondary shared cache and the second target data block being in a valid state, determining that the second hit status of the second access request in the secondary shared cache is an access hit; in response to the second target data block to be accessed by the second access request not existing in the secondary shared cache, or the second target data block being in an invalid state, determining that the second hit status of the second access request in the secondary shared cache is an access miss.

[0026] According to an embodiment of the present disclosure, the preset replacement strategies include a random replacement strategy, a least recently used replacement strategy, a least frequently used replacement strategy, and a first-in-first-out replacement strategy.

[0027] To achieve the above-mentioned purpose, an embodiment of the second aspect of the present disclosure proposes a cache replacement device for a multi-core processor, comprising: a sending module for sending a first access request to a first-level private cache included in a multi-level cache system, and determining a first hit status of the first access request in the first-level private cache; a first generating module for, in response to the first target data block to be accessed by the first access request not existing in the first-level private cache, or the first target data block being in an invalid state, determining that the first hit status of the first access request in the first-level private cache is an access miss, then, based on a preset replacement strategy, generating first replacement information corresponding to the first-level private cache, the first replacement information including first-way information and first address information corresponding to the first data block to be replaced in the first-level private cache; a second generating module for generating a second access request sent to a second-level shared cache based on the first replacement information, wherein the second-level shared cache is an adjacent lower-level cache of the first-level private cache; a replacement module for sending the second access request to the second-level shared cache, and determining a second hit status of the second access request in the second-level shared cache; and in response to the second hit status indicating that the second access request has accessed a hit in the second-level shared cache. , then obtain the return data of the secondary shared cache, and complete the cache replacement of the first-level private cache based on the return data; in response to the second hit status indicating that the second access request does not hit the access in the secondary shared cache, obtain multiple candidate second replacement information corresponding to the secondary shared cache based on the preset replacement strategy; send a third access request to the lower-level storage system, and obtain the return data returned from the lower-level storage system; obtain the first address information contained in the first replacement information, and obtain the candidate second address information contained in each candidate second replacement information in the multiple candidate second replacement information; compare the first address information with each candidate second address information to determine whether there is candidate second address information that is identical to the first address information; if there is candidate second address information that is identical to the first address information, cache replacement is performed on the second data block corresponding to the identical candidate second address information based on the return data returned by the lower-level storage system; if there is no candidate second address information that is identical to the first address information, cache replacement is performed on the second data block corresponding to one of the multiple candidate second address information based on the return data returned by the lower-level storage system.

[0028] According to an embodiment of the present disclosure, the replacement module is further configured to: record first replacement information in a cache directory corresponding to the secondary shared cache; and perform cache replacement on a first data block corresponding to the first replacement information based on the returned data.

[0029] According to one embodiment of the present disclosure, the replacement module is also used to: determine whether there is an empty path in the directory entry in the cache directory; if there is an empty path in the directory entry in the cache directory, record the first replacement information in the empty path in the directory entry; if there is no empty path in the directory entry in the cache directory, determine the directory entry to be replaced from the cache directory, and record the first replacement information in the directory entry to be replaced.

[0030] According to one embodiment of the present disclosure, the replacement module is further used to: obtain multiple candidate directory item information corresponding to the cache directory based on a preset replacement strategy; obtain the first address information contained in the first replacement information, and obtain the candidate directory item address information contained in each candidate directory item information in the multiple candidate directory item information; compare the first address information with each candidate directory item address information to determine whether there is candidate directory item address information that is identical to the first address information; if there is candidate directory item address information that is identical to the first address information, determine that the directory item corresponding to the identical candidate directory item address information is the directory item to be replaced; if there is no candidate directory item address information that is identical to the first address information, determine that the directory item corresponding to one of the candidate directory item address information in the multiple candidate directory item information is the directory item to be replaced.

[0031] According to one embodiment of the present disclosure, the replacement module is further used to: in response to the second target data block to be accessed by the second access request existing in the secondary shared cache and the second target data block being in a valid state, determine that the second hit state of the second access request in the secondary shared cache is an access hit; in response to the second target data block to be accessed by the second access request not existing in the secondary shared cache, or the second target data block being in an invalid state, determine that the second hit state of the second access request in the secondary shared cache is an access miss.

[0032] According to one embodiment of the present disclosure, the preset replacement strategy includes but is not limited to a random replacement strategy, a least recently used replacement strategy, a least frequently used replacement strategy, and a first-in-first-out replacement strategy.

[0033] To achieve the above-mentioned purpose, an embodiment of the third aspect of the present disclosure proposes an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to implement the cache replacement method of the multi-core processor as described in any embodiment of the first aspect of the present disclosure.

[0034] To achieve the above-mentioned purpose, an embodiment of the fourth aspect of the present disclosure proposes a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to implement the cache replacement method of a multi-core processor as described in any embodiment of the first aspect of the present disclosure.

[0035] To achieve the above-mentioned purpose, the fifth embodiment of the present disclosure proposes a computer program product, including a computer program, which, when executed by a processor, implements the cache replacement method for a multi-core processor as described in any embodiment of the first aspect of the present disclosure.

[0036] To achieve the above-mentioned purpose, the sixth embodiment of the present disclosure proposes a computer program, including computer program code. When the computer program code is run on a computer, the computer executes the cache replacement method of the multi-core processor as described in any embodiment of the first aspect of the present disclosure.

[0037] The present disclosure achieves at least the following beneficial effects: the present disclosure aims to reduce the replacement caused by upper-level access failure, and the replacement of the first-level private cache in different ways to maintain the inclusion relationship of the directory or the second-level shared cache to the first-level private cache, resulting in additional replacement of the same cache line in different ways, thereby increasing the retention time of the first-level private cache block on the processor chip and improving the on-chip storage capacity utilization of the processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The above and / or additional aspects and advantages of the present disclosure will become apparent and readily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0039] FIG1 is a schematic diagram showing an exemplary implementation of a cache replacement method for a multi-core processor according to an embodiment of the present disclosure.

[0040] FIG2 is a schematic diagram of a multi-level cache system according to an embodiment of the present disclosure.

[0041] FIG3 is a schematic diagram of a TAG of a first-level private cache according to an embodiment of the present disclosure.

[0042] FIG4 is a schematic diagram of a TAG of a secondary shared cache according to an embodiment of the present disclosure.

[0043] FIG5 is a schematic diagram of a multi-way group-connected directory according to an embodiment of the present disclosure.

[0044] FIG6 is a schematic diagram showing an exemplary implementation of a cache replacement method for a multi-core processor according to an embodiment of the present disclosure.

[0045] FIG7 is a schematic diagram showing an exemplary implementation of a cache replacement method for a multi-core processor according to an embodiment of the present disclosure.

[0046] FIG8 is a schematic diagram of a cache replacement device for a multi-core processor according to an embodiment of the present disclosure.

[0047] FIG9 is a schematic diagram of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0048] The following describes in detail embodiments of the present disclosure, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present disclosure, and should not be construed as limiting the present disclosure.

[0049] It should be noted that all actions of obtaining information, permissions, and providing services in this disclosure are carried out in compliance with the relevant data protection laws and policies of the location and with the authorization given by the owner of the corresponding device. They are in compliance with relevant laws and regulations and do not violate public order and good morals.

[0050] In multi-core processor architectures, snoop and directory protocols are two common implementations of cache coherence protocols. The directory coherence protocol is highly scalable and can be expanded to larger numbers of processor cores, such as 64, 128, and 256 cores. Therefore, it is currently the most widely used coherence protocol in multi-core processors. The directory controller is the core component of the directory coherence protocol, maintaining multi-core cache coherence by recording the distribution of cache block replicas across processor cores through the directory.

[0051] The tag directory is replicated to maintain consistency by copying the tag (TAG) field of the previous level cache. However, consistency maintenance information needs to be broadcast, which consumes bandwidth and has poor scalability. The sparse directory uses an independent directory structure to record the distribution of data copies in the processor cores. For scalability, multi-core processors generally use a sparse directory. The sparse directory uses a group-associative directory structure, and each directory entry stores information about the upper cache. Sparse directories may have inter-group conflicts and will replace the directory information of some upper cache blocks that were originally in use. Accordingly, the upper cache blocks corresponding to the replaced directory entries need to be invalidated.

[0052] Inclusive, Non-Inclusive, and Exclusive cache architectures are three organizational methods for cache storage hierarchies. In an Inclusive cache hierarchy, because cache hierarchies maintain an inclusion relationship, cache block data from the previous storage hierarchy exists in all subsequent storage hierarchies. The subsequent storage hierarchies can maintain a directory to record which caches in the previous storage hierarchy contain cache blocks and their status. When a replacement occurs in the next storage hierarchy, cache blocks in the previous storage hierarchy must also be replaced to maintain the inclusion relationship. In cache hierarchies that do not maintain an inclusion relationship (Non-Inclusive and Exclusive), maintaining consistency in the upper cache hierarchy also requires maintaining a directory in the lower cache. The directory records which cache blocks exist in the upper cache hierarchy and their status. When a replacement occurs due to insufficient directory entries, the cache blocks recorded in the replacement directory entry in the upper storage system must also be replaced to maintain the directory.

[0053] The replacement of cache blocks due to cache miss in the upper cache, the replacement of upper cache blocks caused by directory replacement in the lower cache to maintain directory record entries, or the replacement of upper cache blocks caused by cache miss in the lower cache of Inclusive Cache to maintain inclusion relationship are all distributed and independent processing processes, which lead to the replacement of upper cache miss and the replacement of upper cache to maintain directory or inclusion relationship of lower cache to upper cache, which occur in different ways of the same cache line in the upper layer, resulting in multiple replacements of one upper cache block, reducing the retention time of the upper cache block, so that the cache capacity is not used more effectively.

[0054] Figure 1 is a schematic diagram of an exemplary implementation of a cache replacement method for a multi-core processor according to the first aspect of the present disclosure. As shown in Figure 1 , the cache replacement method for a multi-core processor includes the following steps S101 to S104 .

[0055] S101 : Send a first access request to a first-level private cache included in a multi-level cache system, and determine a first hit status of the first access request in the first-level private cache.

[0056] Figure 2 is a schematic diagram of a multi-level cache system according to an embodiment of the present disclosure. As shown in Figure 2, a multi-core processor includes 128 processor cores, a total of 64MB of L2 cache, 256MB of L3 cache, each cache line is 512 bits, and the physical address is 40 bits.

[0057] The multi-level cache system architecture is shown in Figure 2. As shown in Figure 2, L2 Cache is the upper-level cache and L3 Cache is the lower-level cache. That is, L2 Cache can be used as a first-level private cache and L3 Cache can be used as a second-level shared cache.

[0058] It should be noted that in the disclosed embodiments, the first-level private cache is not limited to the L2 cache, and the second-level shared cache is not limited to the L3 cache. In some embodiments, the first-level private cache can be any level of the processor's first-level cache (L1 cache), second-level cache, or even the level above the last-level cache (LLC); the second-level shared cache can be any level of the processor's second-level cache, third-level cache, or even the last-level cache (LLC). The second-level shared cache is the adjacent lower-level cache of the first-level private cache.

[0059] Each level of cache includes cache tags and cache data.

[0060] In an embodiment of the present disclosure, when data needs to be obtained from a first-level private cache, it is necessary to send a first access request to the first-level private cache included in the multi-level cache system. In an embodiment of the present disclosure, the hit status of the first access request in the first-level private cache is referred to as a first hit status, that is, after sending the first access request to the first-level private cache included in the multi-level cache system, it is necessary to determine the first hit status of the first access request in the first-level private cache.

[0061] If the first target data block to be accessed by the first access request does not exist in the first-level private cache, or the first target data block is in an invalid state, the first hit state of the first access request in the first-level private cache is determined to be an access miss.

[0062] S102, in response to the first hit status indicating that the first access request does not hit the first-level private cache, first replacement information corresponding to the first-level private cache is generated, and the first replacement information includes first-way information and first address information corresponding to the first data block to be replaced in the first-level private cache.

[0063] The following first introduces the first-level private cache.

[0064] As an example, the first-level private cache is an 8-way set-associative structure, and the first-level private cache includes a first-level private cache TAG (tag) and a first-level private cache Data (data).

[0065] The TAG of the L1 private cache is shown in Figure 3. It includes: the address tag of the L1 private cache, a valid bit (used to indicate whether the tag item is valid), a flag bit (used to record whether the L1 private cache block has been written to, that is, whether it is dirty), and a status bit (indicating the status of the corresponding cache block in the L1 private cache). A status bit of SHD indicates that the corresponding cache block is in the shared (SHD) state in the L1 private cache, and a status bit of EXC indicates that the corresponding block is in the exclusive (EXC) state in the L1 private cache.

[0066] In an embodiment of the present disclosure, if the first hit status indicates that the first access request misses the first-level private cache, first replacement information corresponding to the first-level private cache is generated. The first replacement information includes first way information and first address information corresponding to the first data block to be replaced in the first-level private cache.

[0067] Among them, when generating the first replacement information, the first replacement information corresponding to the first-level private cache can be generated based on a preset replacement strategy (the preset replacement strategy includes but is not limited to a random replacement strategy (Random), a least recently used replacement strategy (Least Recently Used, LRU), a least frequently used replacement strategy (Least Frequently Used, LFU) and a first-in first-out replacement strategy (First In First Out, FIFO, and any one of them can be selected when generating the first replacement information.).

[0068] S103 : Generate a second access request to be sent to a level 2 shared cache based on the first replacement information, where the level 2 shared cache is a lower-level cache adjacent to the level 1 private cache.

[0069] The following first introduces the secondary shared cache.

[0070] For example, the L2 shared cache has an 8-way set-associative structure and includes a L2 shared cache tag and L2 shared cache data. The L2 shared cache tag, as shown in Figure 4, includes the L2 shared cache address tag, valid bit, and flag bit. When the flag bit is 1, it indicates that dirty data has been written to the cache block and must be written to the underlying storage system when replacement occurs.

[0071] In the disclosed embodiment, a second access request is generated and sent to the L2 shared cache based on first replacement information, wherein the first replacement information includes first way information and first address information corresponding to a first data block to be replaced in the L1 private cache.

[0072] S104: Send the second access request to the second-level shared cache, obtain return data from the second-level shared cache, and complete cache replacement of the first-level private cache based on the return data.

[0073] The following describes the cache directories corresponding to the L2 shared cache. A multi-way set-associative directory (e.g., an 8-way set-associative directory) is used as an example. Cache coherence for inclusive, non-inclusive, and exclusive relationships can all be maintained using the directory.

[0074] The directory information contained in each row of the directory is shown in Table 1, and the schematic diagram of the multi-way group connected directory is shown in Figure 5.

[0075] The valid bit is used to indicate whether the directory entry is valid.

[0076] Upper cache block address, indicating the block address of the first-level private cache recorded in the directory entry.

[0077] The upper cache block status bit indicates the status of the corresponding cache block in the first-level private cache. This field is valid only when the valid bit is Valid.

[0078] Directory bit vector, indicating in which first-level private caches the corresponding cache block exists. This field is valid only when the valid bit is Valid.

[0079] Table 1 Directory information contained in each row

[0080] The valid bit is 1 for valid (Valid) and 0 for invalid (INV, Invalid).

[0081] The L1 private cache status bits include:

[0082] CLEAN: Indicates that the corresponding block is in the shared (SHD) state in the first-level private cache.

[0083] DIRTY: Indicates that the corresponding block is in the exclusive (EXC) state in the first-level private cache, or in a consistency protocol that supports the MOESI (Modified, Owned, Exclusive, Shared or Invalid) state, there is an Owner in the first-level private cache who has the latest data of the cache block.

[0084] Directory bit vector: This records which first-level private caches contain the cache block. The directory bit vector for the corresponding entry is valid only when the directory entry is in the Valid state. The directory bit vector records which first-level private caches have a backup of the block. Generally, a 1 in the corresponding directory bit vector indicates that the corresponding first-level private cache has a backup of the block, while a 0 indicates that the corresponding first-level private cache does not have a backup of the block.

[0085] The directory bit vector can be recorded using a coarse vector directory, a compressed directory, or a full bit vector directory. For example, using a full bit vector directory, 0000...1111 indicates that the cache block is backed up in the first-level private cache of processor cores 0, 1, 2, and 3.

[0086] It also includes information used by the replacement algorithm when all directory lines are full, such as age information and usage frequency information used in the least recently used algorithm. The MOESI consistency protocol also includes the owner node number, which is used to record which processor core's L1 private cache is the owner of the data block.

[0087] In the embodiments of the present disclosure, the case where the first-level private cache and the second-level shared cache maintain a containment relationship is mainly introduced. If the first-level private cache and the second-level shared cache maintain a containment relationship, the second access request is sent to the second-level shared cache to obtain the return data of the second-level shared cache, and the cache replacement of the first-level private cache and the cache directory is completed based on the return data, so that if the replacement of the first-level private cache and the replacement of the lower-level cache directory item or the replacement of the first-level private cache block caused by the replacement of the second-level shared cache are the same cache line, the same replacement path as the replacement path passed down by the first-level private cache can be selected for replacement.

[0088] In some embodiments, the first-level private cache and the second-level shared cache may not maintain a containment relationship. If the first-level private cache and the second-level shared cache do not maintain a containment relationship, the second access request is sent to the second-level shared cache to obtain the return data of the second-level shared cache, and the cache directory is updated based on the returned data.

[0089] The present disclosure provides a cache replacement method for a multi-core processor, comprising: sending a first access request to a first-level private cache included in a multi-level cache system, and determining a first hit status of the first access request in the first-level private cache; in response to the first hit status indicating that the first access request did not hit the first-level private cache, generating first replacement information corresponding to the first-level private cache, the first replacement information including first way information and first address information corresponding to a first data block to be replaced in the first-level private cache; generating a second access request based on the first replacement information and sending it to a second-level shared cache, wherein the second-level shared cache is an adjacent lower-level cache of the first-level private cache; sending the second access request to the second-level shared cache, obtaining return data from the second-level shared cache, and completing cache replacement of the first-level private cache based on the return data. The present disclosure aims to reduce the occurrence of replacements due to upper-level access failures, as well as the occurrence of additional replacements of different ways of the same cache line due to replacements of the first-level private cache in different ways to maintain the inclusion relationship of a directory or a second-level shared cache to the first-level private cache, thereby increasing the retention time of the first-level private cache block on the processor chip and improving the on-chip storage capacity utilization of the processor.

[0090] In the disclosed embodiment, before the multi-level cache system is put into use, it is necessary to initialize the multi-level cache system. Specifically, the valid bits of each row in the cache directory corresponding to the second-level shared cache must be invalidated; the valid bits of each row in the tag of each row in the first-level private cache must be invalidated; and the valid bits of each row in the tag of each row in the second-level shared cache must be invalidated. This ensures that all cached data is invalid when the system starts, thereby avoiding the existence of dirty or erroneous data. This allows a clean state to be established before the system is operational, ensuring data consistency.

[0091] Figure 6 is a schematic diagram illustrating an exemplary implementation of a cache replacement method for a multi-core processor according to an embodiment of the present disclosure. As shown in Figure 6 , the cache replacement method for a multi-core processor includes the following steps S601 to S606 .

[0092] S601: Send a first access request to a first-level private cache included in a multi-level cache system, and determine a first hit status of the first access request in the first-level private cache.

[0093] S602, in response to the first hit status indicating that the first access request does not hit the first-level private cache, first replacement information corresponding to the first-level private cache is generated, and the first replacement information includes first-way information and first address information corresponding to the first data block to be replaced in the first-level private cache.

[0094] S603: Generate a second access request to the second-level shared cache based on the first replacement information, wherein the first-level private cache and the second-level shared cache are in a maintenance inclusion relationship, and the second-level shared cache is an adjacent lower-level cache of the first-level private cache.

[0095] For a detailed description of steps S601 to S603 , please refer to the detailed description of the relevant parts in the above embodiment, which will not be repeated here.

[0096] S604: Send the second access request to the L2 shared cache, and determine a second hit status of the second access request in the L2 shared cache.

[0097] Specifically, if the second target data block to be accessed by the second access request exists in the L2 shared cache and is in a valid state, the second hit state of the second access request in the L2 shared cache is determined to be an access hit.

[0098] S605 : In response to the second hit status indicating that the second access request is hit in the L2 shared cache, obtain return data from the L2 shared cache.

[0099] S606: Complete cache replacement of the first-level private cache based on the returned data.

[0100] The first replacement information is recorded in a cache directory corresponding to the secondary shared cache, and cache replacement is performed on the first data block corresponding to the first replacement information based on the returned data.

[0101] Specifically, when recording the first replacement information in the cache directory corresponding to the secondary shared cache, it is first necessary to determine whether there is an empty directory entry in the cache directory.

[0102] In some embodiments, if there is an empty way in the directory entry in the cache directory, the first replacement information is directly recorded in the empty way in the directory entry.

[0103] In some embodiments, if there is no empty directory entry in the cache directory, a directory entry to be replaced is determined from the cache directory, and the first replacement information is recorded in the directory entry to be replaced. Determining the directory entry to be replaced from the cache directory includes: obtaining multiple candidate directory entry information corresponding to the cache directory based on a preset replacement strategy; obtaining the first address information contained in the first replacement information, and obtaining the candidate directory entry address information contained in each candidate directory entry information in the multiple candidate directory entry information; comparing the first address information with each candidate directory entry address information to determine whether there is candidate directory entry address information that is identical to the first address information; if there is candidate directory entry address information that is identical to the first address information, determining that the directory entry corresponding to the identical candidate directory entry address information is the directory entry to be replaced; if there is no candidate directory entry address information that is identical to the first address information, determining that the directory entry corresponding to one of the candidate directory entry address information in the multiple candidate directory entry information is the directory entry to be replaced.

[0104] Among them, the preset replacement strategy includes but is not limited to a random replacement strategy (Random), a least recently used replacement strategy (Least Recently Used, LRU), a least frequently used replacement strategy (Least Frequently Used, LFU) and a first in first out replacement strategy (First In First Out, FIFO), and here, at least two of them can be selected.

[0105] It should be noted that the preset replacement strategy here is only for illustration and does not limit the scope of protection of the present disclosure.

[0106] The disclosed embodiment mainly introduces the situation where the second access request hits the second-level shared cache to achieve invalid access to the first-level private cache. The multi-level cache system can configure different levels of cache as needed and expand according to system requirements. When the second-level shared cache directly hits, the return data of the second-level shared cache is obtained and directly compared with the first replacement information to perform directory records and cache replacement of the first-level private cache, effectively utilizing cache resources, improving cache hit rates, increasing the time that the first-level private cache block remains on the processor chip, improving the utilization rate of the processor's on-chip storage capacity, and providing a better user experience.

[0107] Figure 7 is a schematic diagram illustrating an exemplary implementation of a cache replacement method for a multi-core processor according to an embodiment of the present disclosure. As shown in Figure 7 , the cache replacement method for a multi-core processor includes the following steps S701 to S708 .

[0108] S701: Send a first access request to a first-level private cache included in a multi-level cache system, and determine a first hit status of the first access request in the first-level private cache.

[0109] S702, in response to the first hit status indicating that the first access request does not hit the first-level private cache, first replacement information corresponding to the first-level private cache is generated, and the first replacement information includes first-way information and first address information corresponding to the first data block to be replaced in the first-level private cache.

[0110] S703 : Generate a second access request to the second-level shared cache based on the first replacement information, wherein the first-level private cache and the second-level shared cache are in a maintenance inclusion relationship, and the second-level shared cache is an adjacent lower-level cache of the first-level private cache.

[0111] For the detailed description of steps S701 to S703 , please refer to the detailed description of the relevant parts in the above embodiment, which will not be repeated here.

[0112] S704: Send the second access request to the L2 shared cache, and determine a second hit status of the second access request in the L2 shared cache.

[0113] Specifically, if the second target data block to be accessed by the second access request does not exist in the L2 shared cache, or the second target data block is in an invalid state, the second hit state of the second access request in the L2 shared cache is determined to be an access miss.

[0114] S705 : In response to the second hit status indicating that the second access request misses the second shared cache, obtaining a plurality of candidate second replacement information corresponding to the second shared cache based on a preset replacement strategy.

[0115] Among them, the preset replacement strategy includes but is not limited to a random replacement strategy (Random), a least recently used replacement strategy (Least Recently Used, LRU), a least frequently used replacement strategy (Least Frequently Used, LFU) and a first in first out replacement strategy (First In First Out, FIFO), and here, at least two of them can be selected.

[0116] S706: Send a third access request to the lower-layer storage system, and obtain return data returned from the lower-layer storage system.

[0117] S707 , performing cache replacement on the secondary shared cache by combining the first replacement information and a plurality of candidate second replacement information.

[0118] The first address information included in the first replacement information is obtained, and the candidate second address information included in each candidate second replacement information among a plurality of candidate second replacement information is obtained.

[0119] The first address information is compared with each candidate second address information to determine whether there is candidate second address information that is the same as the first address information.

[0120] If there is candidate second address information identical to the first address information, cache replacement is performed on the second data block corresponding to the identical candidate second address information based on the returned data.

[0121] If there is no candidate second address information identical to the first address information, a second data block corresponding to one of the plurality of candidate second address information is cache-replaced based on the returned data.

[0122] S708: Complete cache replacement of the first-level private cache based on the returned data.

[0123] The returned data after the cache replacement is performed in the secondary shared cache is obtained, first replacement information is recorded in a cache directory corresponding to the secondary shared cache, and a first data block corresponding to the first replacement information is cache replaced based on the returned data.

[0124] Specifically, when recording the first replacement information in the cache directory corresponding to the secondary shared cache, it is first necessary to determine whether there is an empty directory entry in the cache directory.

[0125] In some embodiments, if there is an empty way in the directory entry in the cache directory, the first replacement information is directly recorded in the empty way in the directory entry.

[0126] In some embodiments, if there is no empty directory entry in the cache directory, a directory entry to be replaced is determined from the cache directory, and the first replacement information is recorded in the directory entry to be replaced. Determining the directory entry to be replaced from the cache directory includes: obtaining multiple candidate directory entry information corresponding to the cache directory based on a preset replacement strategy; obtaining the first address information contained in the first replacement information, and obtaining the candidate directory entry address information contained in each candidate directory entry information in the multiple candidate directory entry information; comparing the first address information with each candidate directory entry address information to determine whether there is candidate directory entry address information that is identical to the first address information; if there is candidate directory entry address information that is identical to the first address information, determining that the directory entry corresponding to the identical candidate directory entry address information is the directory entry to be replaced; if there is no candidate directory entry address information that is identical to the first address information, determining that the directory entry corresponding to one of the candidate directory entry address information in the multiple candidate directory entry information is the directory entry to be replaced. The preset replacement strategy includes but is not limited to at least two of a random replacement strategy (Random), a least recently used replacement strategy (Least Recently Used, LRU), a least frequently used replacement strategy (Least Frequently Used, LFU), and a first in first out replacement strategy (First In First Out, FIFO).

[0127] This disclosed embodiment primarily addresses the situation where a second access request misses the L2 shared cache, thereby invalidating the L1 private cache. A multi-level cache system can be configured with different levels of cache as needed and expanded based on system requirements. When a L2 shared cache replacement is required, the first address information can be directly compared and the L2 shared cache replaced, reducing the number of main memory accesses and improving system performance.

[0128] FIG8 is a schematic diagram of a cache replacement device for a multi-core processor according to an embodiment of the second aspect of the present disclosure. As shown in FIG8 , the cache replacement device 800 for a multi-core processor includes a sending module 801, a first generating module 802, a second generating module 803, and a replacement module 804, wherein:

[0129] The sending module 801 is configured to send a first access request to a first-level private cache included in the multi-level cache system, and determine a first hit status of the first access request in the first-level private cache.

[0130] The first generation module 802 is used to generate first replacement information corresponding to the first-level private cache in response to the first hit status indicating that the first access request does not hit the first-level private cache. The first replacement information includes first-way information and first address information corresponding to the first data block to be replaced in the first-level private cache.

[0131] The second generating module 803 is configured to generate a second access request to be sent to a level 2 shared cache based on the first replacement information, wherein the level 2 shared cache is a lower-layer cache adjacent to the level 1 private cache.

[0132] The replacement module 804 is configured to send the second access request to the L2 shared cache, obtain return data from the L2 shared cache, and complete cache replacement of the L1 private cache based on the return data.

[0133] The device of the embodiment of the present disclosure is intended to reduce the replacement caused by upper-level access failure, and the replacement of the first-level private cache occurs on different ways to maintain the inclusion relationship of the directory or the second-level shared cache to the first-level private cache, resulting in additional replacement of the same cache line on different ways, thereby increasing the time that the first-level private cache block remains on the processor chip and improving the on-chip storage capacity utilization of the processor.

[0134] In some embodiments, the first generating module 802 is further configured to generate first replacement information corresponding to the first-level private cache based on a preset replacement strategy.

[0135] In some embodiments, the sending module 801 is also used to: in response to the first target data block to be accessed by the first access request not existing in the first-level private cache, or the first target data block is in an invalid state, determine that the first hit status of the first access request in the first-level private cache is an access miss.

[0136] In some embodiments, the replacement module 804 is further used to: send the second access request to the secondary shared cache, and determine a second hit status of the second access request in the secondary shared cache; in response to the second hit status indicating that the second access request is accessed and hit in the secondary shared cache, obtain the return data of the secondary shared cache.

[0137] In some embodiments, the replacement module 804 is further used to: in response to the second hit status indicating that the second access request does not hit the access in the secondary shared cache, obtain multiple candidate second replacement information corresponding to the secondary shared cache based on a preset replacement strategy; send a third access request to the lower-level storage system and obtain return data returned from the lower-level storage system; and perform cache replacement on the secondary shared cache in combination with the first replacement information and the multiple candidate second replacement information.

[0138] In some embodiments, the replacement module 804 is also used to: obtain the first address information contained in the first replacement information, and obtain the candidate second address information contained in each candidate second replacement information in multiple candidate second replacement information; compare the first address information with each candidate second address information to determine whether there is candidate second address information that is identical to the first address information; if there is candidate second address information that is identical to the first address information, cache replace the second data block corresponding to the identical candidate second address information based on the returned data; if there is no candidate second address information that is identical to the first address information, cache replace the second data block corresponding to one of the multiple candidate second address information based on the returned data.

[0139] In some embodiments, the replacement module 804 is further configured to: record first replacement information in a cache directory corresponding to the secondary shared cache; and perform cache replacement on the first data block corresponding to the first replacement information based on the returned data.

[0140] In some embodiments, the replacement module 804 is also used to: determine whether there is an empty path in the directory entry in the cache directory; if there is an empty path in the directory entry in the cache directory, record the first replacement information in the empty path in the directory entry; if there is no empty path in the directory entry in the cache directory, determine the directory entry to be replaced from the cache directory, and record the first replacement information in the directory entry to be replaced.

[0141] In some embodiments, the replacement module 804 is further used to: obtain multiple candidate directory item information corresponding to the cache directory based on a preset replacement strategy; obtain the first address information contained in the first replacement information, and obtain the candidate directory item address information contained in each candidate directory item information in the multiple candidate directory item information; compare the first address information with each candidate directory item address information to determine whether there is candidate directory item address information that is identical to the first address information; if there is candidate directory item address information that is identical to the first address information, determine that the directory item corresponding to the identical candidate directory item address information is the directory item to be replaced; if there is no candidate directory item address information that is identical to the first address information, determine that the directory item corresponding to one of the candidate directory item address information in the multiple candidate directory item information is the directory item to be replaced.

[0142] In some embodiments, the replacement module 804 is further used to: in response to the second target data block to be accessed by the second access request existing in the secondary shared cache and the second target data block being in a valid state, determine that the second hit state of the second access request in the secondary shared cache is an access hit; in response to the second target data block to be accessed by the second access request not existing in the secondary shared cache, or the second target data block being in an invalid state, determine that the second hit state of the second access request in the secondary shared cache is an access miss.

[0143] In some embodiments, the preset replacement strategies appearing in the above modules include but are not limited to a random replacement strategy, a least recently used replacement strategy, a least frequently used replacement strategy, and a first-in-first-out replacement strategy.

[0144] To implement the above embodiments, the third aspect of the present disclosure provides an electronic device 900. As shown in FIG9 , the electronic device 900 includes a processor 901 and a memory 902 communicatively connected to the processor. The memory 902 stores instructions executable by at least one processor. The instructions are executed by the at least one processor 901 to implement the cache replacement method for a multi-core processor as described in any of the embodiments of the first aspect.

[0145] In order to implement the above embodiments, the fourth aspect of the present disclosure proposes a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable the computer to implement the cache replacement method of the multi-core processor as shown in any embodiment of the first aspect above.

[0146] In order to implement the above embodiments, the fifth aspect of the present disclosure proposes a computer program product, including a computer program, which, when executed by a processor, implements the cache replacement method for a multi-core processor as shown in any embodiment of the first aspect above.

[0147] In order to implement the above embodiments, the sixth aspect of the present disclosure proposes a computer program, including computer program code. When the computer program code runs on a computer, the computer executes the cache replacement method for a multi-core processor as shown in any embodiment of the first aspect above.

[0148] It should be noted that the explanation of the cache replacement method for a multi-core processor in the aforementioned embodiment is also applicable to the device, computer-readable storage medium, computer program product and computer program in the embodiments of the present disclosure, and will not be repeated here.

[0149] All embodiments of the present disclosure may be implemented individually or in combination with other embodiments, and are all considered to be within the scope of protection claimed by the present disclosure.

[0150] In the description of the present disclosure, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation to the present disclosure.

[0151] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the present disclosure, "plurality" means two or more, unless otherwise specifically defined.

[0152] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and features of different embodiments or examples, unless they are mutually inconsistent.

[0153] Although the embodiments of the present disclosure have been shown and described above, it is understood that the above embodiments are illustrative and are not to be construed as limitations on the present disclosure. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present disclosure.

Claims

1. A cache replacement method for a multi-core processor, comprising: Sending a first access request to a first-level private cache included in a multi-level cache system, and determining a first hit status of the first access request in the first-level private cache; In response to a first target data block to be accessed by the first access request not existing in the first-level private cache, or the first target data block being in an invalid state, determining that the first hit state of the first access request in the first-level private cache is an access miss, generating first replacement information corresponding to the first-level private cache based on a preset replacement strategy, the first replacement information including first way information and first address information corresponding to the first data block to be replaced in the first-level private cache; generating a second access request to a secondary shared cache based on the first replacement information, wherein the secondary shared cache is a lower-level cache adjacent to the primary private cache; Sending the second access request to the secondary shared cache, and determining a second hit status of the second access request in the secondary shared cache; In response to the second hit status indicating that the second access request has hit the second level shared cache, obtaining return data from the second level shared cache, and completing cache replacement of the first level private cache based on the return data; In response to the second hit status indicating that the second access request misses the second shared cache, obtaining a plurality of candidate second replacement information corresponding to the second shared cache based on a preset replacement strategy; Sending a third access request to the lower-layer storage system and obtaining return data returned from the lower-layer storage system; Acquire the first address information included in the first replacement information, and acquire the candidate second address information included in each candidate second replacement information among the plurality of candidate second replacement information; Comparing the first address information with each of the candidate second address information to determine whether there is candidate second address information that is the same as the first address information; If there is candidate second address information identical to the first address information, performing cache replacement on the second data block corresponding to the identical candidate second address information based on the returned data returned by the lower-layer storage system; If there is no candidate second address information identical to the first address information, a second data block corresponding to one of the plurality of candidate second address information is cache-replaced based on the return data returned by the lower-layer storage system.

2. The method according to claim 1, wherein completing cache replacement of the first-level private cache based on the returned data comprises: Recording the first replacement information in a cache directory corresponding to the secondary shared cache; A cache replacement is performed on the first data block corresponding to the first replacement information based on the returned data.

3. The method according to claim 2, wherein recording the first replacement information in the cache directory corresponding to the secondary shared cache comprises: Determine whether there is an empty directory path in the cache directory; If there is an empty path in the directory entry in the cache directory, recording the first replacement information in the empty path in the directory entry; If there is no empty directory entry in the cache directory, a directory entry to be replaced is determined from the cache directory, and the first replacement information is recorded in the directory entry to be replaced.

4. The method according to claim 3, wherein determining the directory entry to be replaced from the cache directory comprises: Based on a preset replacement strategy, obtaining information of multiple candidate directory entries corresponding to the cache directory; Acquire the first address information included in the first replacement information, and acquire the candidate directory entry address information included in each candidate directory entry information among the plurality of candidate directory entry information; Comparing the first address information with each candidate directory entry address information to determine whether there is candidate directory entry address information that is the same as the first address information; If there is candidate directory entry address information identical to the first address information, determining the directory entry corresponding to the identical candidate directory entry address information as the directory entry to be replaced; If there is no candidate directory entry address information identical to the first address information, a directory entry corresponding to one of the candidate directory entry address information among the plurality of candidate directory entry information is determined to be the directory entry to be replaced.

5. The method according to any one of claims 1 to 4, wherein determining a second hit status of the second access request in the L2 shared cache comprises: In response to a second target data block to be accessed by the second access request existing in the secondary shared cache and the second target data block being in a valid state, determining that the second hit status of the second access request in the secondary shared cache is an access hit; In response to the second target data block to be accessed by the second access request not existing in the secondary shared cache, or the second target data block being in an invalid state, the second hit state of the second access request in the secondary shared cache is determined to be an access miss. 6 . The method according to claim 1 , wherein the preset replacement strategy comprises a random replacement strategy, a least recently used replacement strategy, a least frequently used replacement strategy, and a first-in-first-out replacement strategy.

7. A cache replacement device for a multi-core processor, comprising: a sending module, configured to send a first access request to a first-level private cache included in the multi-level cache system, and determine a first hit status of the first access request in the first-level private cache; a first generating module, configured to, in response to a first target data block to be accessed by the first access request not existing in the first-level private cache or the first target data block being in an invalid state, determine that the first hit status of the first access request in the first-level private cache is an access miss, and then generate first replacement information corresponding to the first-level private cache based on a preset replacement strategy, the first replacement information including first way information and first address information corresponding to the first data block to be replaced in the first-level private cache; a second generating module, configured to generate a second access request to be sent to a second-level shared cache based on the first replacement information, wherein the second-level shared cache is a lower-level cache adjacent to the first-level private cache; A replacement module is used to send the second access request to the secondary shared cache and determine the second hit status of the second access request in the secondary shared cache; in response to the second hit status indicating that the second access request has a hit in the secondary shared cache, obtain the return data of the secondary shared cache and complete the cache replacement of the first-level private cache based on the return data; in response to the second hit status indicating that the second access request has a miss in the secondary shared cache, obtain multiple candidate second replacement information corresponding to the secondary shared cache based on a preset replacement strategy; send a third access request to the lower-level storage system and obtain the return data returned from the lower-level storage system; obtain the first replacement information contained in the first replacement information address information, and obtaining the candidate second address information contained in each candidate second replacement information among the multiple candidate second replacement information; comparing the first address information with each of the candidate second address information to determine whether there is candidate second address information that is identical to the first address information; if there is candidate second address information that is identical to the first address information, performing cache replacement on the second data block corresponding to the identical candidate second address information based on the return data returned by the lower-layer storage system; if there is no candidate second address information that is identical to the first address information, performing cache replacement on the second data block corresponding to one of the multiple candidate second address information based on the return data returned by the lower-layer storage system.

8. An electronic device comprising: at least one processor; as well as, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the cache replacement method for the multi-core processor according to any one of claims 1 to 6.

9. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to enable the computer to execute the cache replacement method for a multi-core processor according to any one of claims 1 to 6. 10 . A computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements the cache replacement method for a multi-core processor according to claim 1 . 11 . A computer program comprising computer program codes, which, when executed on a computer, enable the computer to execute the cache replacement method for a multi-core processor according to claim 1 .

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