Integrated circuit and electronic device

Abstract

Embodiments of the present application relate to the field of computers, and disclosed are an integrated circuit and an electronic device, which solve the problems of how to increase the storage capacity of a wafer-scale integration system and how to improve the flexibility of computing power of the wafer-scale integration system. The specific solution comprises: providing an integrated circuit, wherein the integrated circuit comprises a memory wafer, an interconnect wafer, and at least one processor die, and the interconnect wafer comprises a network-on-chip. The memory wafer and the interconnect wafer are stacked, and the at least one processor die and the memory wafer are respectively connected to the network-on-chip in the interconnect wafer. The at least one processor die is used for writing data into the memory wafer or reading data from the memory wafer by means of the network-on-chip.

Description

Integrated circuit and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on March 25, 2024, with application number 202410361425.9 and application name “An Integrated Circuit and Electronic Device,” the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present application relates to the field of computers, and in particular to an integrated circuit and an electronic device. Background Art

[0003] Wafer-scale integration (WSI) systems are a new type of computing system that uses entire wafers to construct very large integrated circuit networks to generate a single "superchip" to meet the extreme computing power requirements of specific applications. By combining large size with streamlined packaging, WSI systems can significantly reduce the cost of supercomputing systems used for artificial intelligence (AI) training and high-performance computing (HPC), such as massively parallel supercomputers.

[0004] How to increase the storage capacity of wafer-level integrated systems and improve the flexibility of their computing power has become an urgent problem that needs to be solved. Summary of the Invention

[0005] The embodiments of the present application provide an integrated circuit and an electronic device that solve the problem of how to increase the storage capacity of a wafer-level integrated system and improve the flexibility of the computing power of the wafer-level integrated system.

[0006] To achieve the above objectives, the present invention adopts the following technical solutions:

[0007] In a first aspect of an embodiment of the present application, an integrated circuit is provided, comprising a memory wafer, an interconnect wafer, and at least one processor die, wherein the interconnect wafer includes an on-chip network. The memory wafer and the interconnect wafer are stacked, and the at least one processor die and the memory wafer are respectively connected to the on-chip network in the interconnect wafer. The at least one processor die is configured to write data to the memory wafer or read data from the memory wafer via the on-chip network.

[0008] Based on this solution, the storage wafer and the interconnect wafer are stacked, and at least one processor die and the storage wafer are respectively connected to the on-chip network in the interconnect wafer. At least one processor die is used to write data to the storage wafer or read data from the storage wafer through the on-chip network. Compared with the wafer-level system in the prior art that only includes one wafer, the integrated circuit includes an independent storage wafer, so the storage capacity of the integrated circuit is larger. Compared with the wafer-level system in the prior art, at least one processor die and the on-chip network are not set in the same wafer, so that processor dies with different computing power can be flexibly selected according to computing power requirements, and the computing power flexibility of the integrated circuit is better.

[0009] In combination with the first aspect, in a possible implementation, the integrated circuit further includes a silicon interposer or substrate disposed on a side of the interconnect wafer away from the storage wafer, and at least one processor die is connected to the on-chip network through the silicon interposer or substrate.

[0010] Based on this solution, at least one processor die is connected to the on-chip network through a silicon interposer or substrate. Compared with the prior art in which processors are connected through copper wires on a printed circuit board, this can increase the bandwidth of the processor die accessing the storage wafer and also increase the bandwidth of communication between processor dies.

[0011] In combination with the first aspect, in a possible implementation, the storage wafer and the interconnect wafer are packaged using wafer-to-wafer bonding.

[0012] In combination with the first aspect, in a possible implementation, the on-chip network includes multiple routing nodes, the interconnected wafer also includes multiple storage controllers, the storage wafer includes multiple media banks, the multiple routing nodes are respectively connected to the multiple storage controllers, and the multiple storage controllers are respectively connected to the multiple media banks through through holes.

[0013] Based on this solution, the on-chip network includes multiple routing nodes, and the interconnected wafer also includes multiple storage controllers. The multiple routing nodes are respectively connected to the multiple storage controllers, and the multiple storage controllers are respectively connected to the multiple media banks in the storage wafer through through holes. Each storage controller is used to drive the media bank connected to the storage controller, so that any processor die can send read and write instructions to at least one storage controller through the on-chip network. The at least one storage controller can read data from the corresponding at least one media bank or write data to the corresponding at least one media bank according to the read and write instructions, thereby realizing flexible adjustment of the bandwidth and storage capacity corresponding to the processor die, and meeting the requirements of different scenarios such as AI large model scenarios and HPC for flexible ratio of computing power, bandwidth and storage capacity.

[0014] With reference to the first aspect, in a possible implementation, the network on chip is a two-dimensional grid network on chip.

[0015] In combination with the first aspect, in a possible implementation, the interconnect wafer further includes at least one deserializer connected to the on-chip network, and the at least one processor die is connected to the at least one deserializer.

[0016] In a possible embodiment, at least one deserializer is a high-density deserializer, thereby improving the data transmission efficiency between the processor die and the media bank, or improving the data transmission efficiency between the processor die and the processor die.

[0017] Based on this solution, at least one processor die is connected to at least one deserializer, so that at least one processor die can communicate with the on-chip network through at least one deserializer. By using the deserializer, the data transmission efficiency of the integrated circuit can be improved, and the cost and power consumption can be reduced.

[0018] In combination with the first aspect, in one possible implementation, one processor die in at least one processor die is connected to one deserializer in at least one deserializer, and / or multiple processor dies in at least one processor die are connected to one deserializer in at least one deserializer.

[0019] In combination with the first aspect, in a possible implementation, the types of the multiple media banks include static random access memory, dynamic random access memory, or flash memory.

[0020] Based on this solution, when the type of the media bank included in the storage wafer changes, the storage capacity of each media bank will change, and the bandwidth between each media bank and the corresponding storage controller will also change differently. It can be understood that by changing the type of the media bank in the storage wafer, the bandwidth and storage capacity corresponding to the processor die can be adjusted more flexibly, thereby meeting the flexible ratio requirements of computing power, bandwidth and storage capacity in different scenarios such as AI large model scenarios and HPC.

[0021] In combination with the first aspect, in one possible implementation, the type of at least one processor die includes at least one of a central processing unit, a graphics processing unit, or a neural network processor.

[0022] In a second aspect of an embodiment of the present application, an electronic device is provided, which includes a housing and an integrated circuit arranged in the housing, wherein the integrated circuit is an integrated circuit as described in the first aspect and any possible implementation of the first aspect.

[0023] In a possible embodiment, the electronic device is a computer.

[0024] The description of the second aspect in this application can refer to the detailed description of the first aspect; and the beneficial effects of the second aspect can refer to the analysis of the beneficial effects of the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] FIG1 is a schematic structural diagram of a wafer-level integrated system;

[0026] FIG2 is a schematic diagram of the structure of another wafer-level integrated system;

[0027] FIG3 is a schematic diagram of the structure of an integrated circuit provided in an embodiment of the present application;

[0028] FIG4 is a schematic diagram of the structure of another integrated circuit provided in an embodiment of the present application;

[0029] FIG5 is a schematic diagram of the structure of another integrated circuit provided in an embodiment of the present application;

[0030] FIG6 is a schematic structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] The following sections discuss the making and use of various embodiments in detail. However, it should be understood that many applicable inventive concepts provided herein can be implemented in a variety of specific contexts. The specific embodiments discussed are intended merely to illustrate specific ways to implement and use the present description and technology and are not intended to limit the scope of this application.

[0032] Unless defined otherwise, all technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art.

[0033] Various circuits or other components may be described or referred to as being "configured to" perform one or more tasks. In this case, "configured to" is used to imply structure by indicating that the circuit / component includes structure (e.g., circuitry) that performs the one or more tasks during operation. Thus, even when a specified circuit / component is not currently operational (e.g., not turned on), the circuit / component may be referred to as being configured to perform the task. Circuits / components used with the phrase "configured to" include hardware, such as circuitry that performs an operation, etc.

[0034] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. In the present application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, b, c, a and b, a and c, b and c or a, b and c, where a, b and c can be single or multiple. In addition, in the embodiments of the present application, words such as "first" and "second" do not limit the quantity and order.

[0035] In this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0036] Before introducing the embodiments of the present application, the technical terms and background technologies involved in the present application are first introduced.

[0037] Wafer: refers to the silicon chip used to make semiconductor circuits.

[0038] Die: refers to the chip produced after the wafer is cut.

[0039] Wafer-to-wafer bonding (W2W): is a technology that tightly bonds two wafers together.

[0040] Network-on-chip (NOC): It is a new on-chip communication architecture designed for system on chip (SoC).

[0041] Deserializer (serdes): Short for serializer / deserializer, it is a device that converts parallel data into serial data for transmission and converts received serial data into parallel data. Deserializers include high-density deserializers, which enable high-speed, high-density, and long-distance serial data transmission and are commonly used in high-speed data transmission and communications.

[0042] As shown in Figure 1, a schematic diagram of the structure of a wafer-level integrated system 100 is shown. The wafer-level integrated system 100 includes a wafer 110, which includes an on-chip network 111, as well as multiple computing units 112 and multiple on-chip high-bandwidth memories 113 connected to the on-chip network 111. The wafer-level integrated system 100 is used to support AI training that requires ultra-high computing power. The deep learning computing resources provided by the wafer-level integrated system 100 are equivalent to an old-style computer cluster in a single device. It is easy to program as a single node, which can reduce programming complexity and computing time.

[0043] However, due to the size limitation of the wafer 110, the total storage capacity of multiple on-chip high-bandwidth memories 113 in the wafer-level integrated system 100 is limited to only tens of gigabytes (GB), which cannot meet the demand for storing a large number of training parameters during AI training, nor can it meet the needs of HPC applications that require larger memory capacity.

[0044] As shown in (a) of Figure 2, a schematic diagram of the structure of another wafer-level integrated system 200 is shown. The wafer-level integrated system 200 includes a storage wafer 210 and a computing wafer 220 disposed on the storage wafer 210. The storage wafer 210 and the computing wafer 220 are packaged into a three-dimensional integrated circuit (3DIC) using wafer-to-wafer bonding. The storage wafer 210 can also be called a wafer-scale memory (WSM) wafer, and the computing wafer 220 can also be called a wafer-scale computing (WSC) wafer.

[0045] Specifically, as shown in (b) in Figure 2, it is a schematic structural diagram of the wafer-level integrated system 200 after decomposition. Among them, the storage wafer 210 includes multiple on-chip memories 211, and the computing wafer 220 includes an on-chip network 221, and multiple computing units 222 connected to the on-chip network 221. Between the on-chip network 221 in the storage wafer 210 and the computing wafer 220, high-bandwidth interconnection is achieved through silicon vias (through silicon via, TSV) (not shown in the figure). Compared with the wafer-level integrated system 100 shown in Figure 1 above, which only includes one wafer 110, the wafer-level integrated system 200 includes independent storage wafers 210 and computing wafers 220, so that the storage capacity of the storage wafer 210 is compared with the sum of the storage capacity of the above-mentioned multiple on-chip high-bandwidth memories 113. The storage capacity of the storage wafer 210 is larger, which can reach terabyte (terabyte, TB) level, which can meet the needs of storing a large amount of training parameters during AI training, and can also meet the needs of HPC applications that require larger access capacity.

[0046] However, since the on-chip network 221 and the multiple computing units 222 in the computing wafer 220 are not decoupled, the computing power of each computing unit 222 is fixed, resulting in the sum of the computing power of the multiple computing units 222 being fixed. The computing power of the computing unit 222 is fixed, and the computing power flexibility of the wafer-level integrated system 200 is poor, which cannot meet the requirements of different scenarios such as AI large model scenarios and HPC for flexible allocation of computing power, bandwidth and storage capacity.

[0047] In summary, current wafer-level integrated systems have the problems of small storage capacity and poor computing flexibility. To address this problem, an embodiment of the present application provides an integrated circuit, which can also be called a wafer-level integrated system, which has a larger storage capacity and better computing flexibility.

[0048] FIG3 is a schematic diagram of the exploded structure of an integrated circuit 300 provided in an embodiment of the present application. The integrated circuit 300 includes a memory wafer 310, an interconnect wafer 320, and at least one processor die 330. The interconnect wafer 320 includes an on-chip network 321. The embodiment of the present application does not limit the specific number of processor dies 330.

[0049] The memory wafer 310 and the interconnect wafer 320 are stacked, and at least one processor die 330 and the memory wafer 310 are respectively connected to an on-chip network 321 in the interconnect wafer 320. The at least one processor die 330 is used to write data to the memory wafer 310 or read data from the memory wafer 310 via the on-chip network 321.

[0050] It is understandable that, compared to the wafer-level integrated system 100 shown in FIG1 , which includes only one wafer 110, the integrated circuit 300 includes an independent storage wafer 310. Thus, the storage capacity of the storage wafer 310 is greater than the sum of the storage capacities of the multiple on-chip high-bandwidth memories 113, and can reach the TB level, capable of storing all parameters of a trillion-parameter large model. The integrated circuit 300 has a greater storage capacity. Compared to the wafer-level integrated system 200 shown in FIG2 , at least one processor die 330 and the on-chip network 321 are not provided on the same wafer. Thus, processor dies 330 of different computing power can be flexibly selected based on computing power requirements, thereby improving the computing power flexibility of the integrated circuit 300.

[0051] In a possible embodiment, the memory wafer 310 and the interconnect wafer 320 are packaged using wafer-to-wafer bonding to form a three-dimensional integrated circuit.

[0052] In one possible embodiment, the type of the at least one processor die 330 includes at least one of a central processing unit (CPU), a graphics processing unit (GPU), or a neural network processing unit (NPU).

[0053] In one possible embodiment, since the storage wafer 310, the interconnect wafer 320 and the at least one processor die 330 are independent of each other, they can be produced based on different processes, so that appropriate processes can be selected to optimize performance as much as possible, or to reduce production costs.

[0054] The integrated circuit 300 provided in the embodiment of the present application has a stacked storage wafer 310 and an interconnect wafer 320, and at least one processor die 330 and the storage wafer 310 are respectively connected to the on-chip network 321 in the interconnect wafer 320. At least one processor die 330 is used to write data to the storage wafer 310 or read data from the storage wafer 310 through the on-chip network 321. Compared with the wafer-level integrated system 100 shown in Figure 1 above, which only includes one wafer 110, the integrated circuit 300 includes an independent storage wafer 310, so the storage capacity of the integrated circuit 300 is larger. Compared with the wafer-level integrated system 200 shown in Figure 2 above, at least one processor die 330 and the on-chip network 321 are not arranged in the same wafer, so that processor dies 330 of different computing power can be flexibly selected according to computing power requirements, and the computing power flexibility of the integrated circuit 300 is better.

[0055] In one possible embodiment, as shown in FIG4 , a schematic diagram of the exploded structure of the integrated circuit 300 is shown. The integrated circuit 300 further includes a silicon interposer (also referred to as a passive interposer) or substrate 340 disposed on a side of the interconnect wafer 320 away from the memory wafer 310. At least one processor die 330 is connected to an on-chip network 321 via the silicon interposer or substrate 340. This embodiment of the present application uses the example of at least one processor die 330 being connected to the on-chip network 321 via the substrate 340 as an example for illustrative description.

[0056] Compared with the prior art in which processors are connected via copper wires on a printed circuit board (PCB), at least one processor die 330 is connected to the on-chip network 321 via a silicon interposer or substrate 340, which can increase the bandwidth of the processor die 330 accessing the storage wafer 310 and also increase the bandwidth of communication between the processor die 330.

[0057] In the integrated circuit 300 provided in the embodiment of the present application, at least one processor die 330 is connected to the on-chip network 321 through a silicon interposer or substrate 340, thereby increasing the bandwidth of the processor die 330 accessing the storage wafer 310 and also increasing the bandwidth of communication between the processor die 330.

[0058] In one possible embodiment, as shown in FIG4 , the on-chip network 321 includes multiple routing nodes 3211, the interconnect wafer 320 further includes multiple storage controllers 322, the storage wafer 310 includes multiple dielectric banks 311, the multiple routing nodes 3211 are respectively connected to the multiple storage controllers 322, and the multiple storage controllers 322 are respectively connected to the multiple dielectric banks 311 via through-holes (also called through-silicon vias, not shown in the figure). Specifically, the multiple storage controllers 322 are respectively connected to the multiple dielectric banks 311 via parallel buses (not shown in the figure) in the through-holes.

[0059] Each routing node 3211 is used for data forwarding, flow control, and routing decision-making, and each storage controller 322 is used to drive the medium Bank 311 connected to the storage controller 322 .

[0060] In one possible embodiment, each processor die 330 can be connected to a media bank 311 via an on-chip network 321. Each processor die 330 can exclusively use the storage capacity of the media bank 311 connected to the processor die 330. Specifically, the processor die 330 can send read and write instructions to the storage controller 322 corresponding to the media bank 311. The storage controller 322 can read data from the media bank 311 or write data to the media bank 311 based on the read and write instructions. In this case, the number of processor dies 330 included in the integrated circuit 300 can be the same as the number of media banks 311 included in the memory wafer 310.

[0061] Exemplarily, when the integrated circuit 300 is used for distributed computing, each processor die 330 can perform matrix calculations and vector calculations based on the model parameters in the medium Bank 311 connected to the processor die 330. After each round of calculation, multiple processor die 330 can be synchronized through the on-chip network 321 using an all-reduce collective communication mechanism. Compared with traditional AI inference servers and clusters that interconnect multiple independent processors with high-cost high-bandwidth memory (HBM) to perform distributed computing, in order to meet the requirements of large model inference scenarios for memory access bandwidth and network communication latency, high-cost HBM and large-bandwidth inter-chip interconnection buses are used. In the integrated circuit 300 provided in the embodiment of the present application, the processor die 330 writes data to the media Bank 311 through the on-chip network 321 and the storage controller 322, or reads data from the media Bank 311. The on-chip network 321 has the advantages of high bandwidth and low latency, so that the integrated circuit 300 can meet the requirements of large model inference scenarios for memory access bandwidth and network communication latency, and does not require the use of high-cost HBM and large-bandwidth inter-chip interconnection buses, which can reduce costs.

[0062] In one possible embodiment, multiple media banks 311 in the storage wafer 310 support global addressing. Any processor die 330 can send read and write instructions to multiple storage controllers 322 via the on-chip network 321. The multiple storage controllers 322 read data from or write data to the corresponding multiple media banks 311 based on the read and write instructions. This allows for flexible adjustment of the bandwidth and storage capacity corresponding to the processor die 330, supporting high-bandwidth memory access for high-computing-power processor dies 330. Compared to using an HBM package solution to achieve high-bandwidth memory access for high-computing-power processors, this integrated circuit 300 has a lower cost.

[0063] In one possible embodiment, the on-chip network 321 can be designed with topology, routing, bandwidth and latency as needed to match the communication requirements between the processor die 330 and the media Bank 311. The embodiment of the present application does not limit the specific topology, routing, bandwidth and latency of the on-chip network 321.

[0064] In a possible embodiment, referring to FIG. 4 , multiple storage controllers 322 may be arranged in a two-dimensional array, the on-chip network 321 may be a two-dimensional mesh (2D mesh) on-chip network, and multiple routing nodes 3211 may also be arranged in a two-dimensional array.

[0065] In one possible embodiment, the types of the plurality of media banks 311 include static random-access memory (SRAM), dynamic random access memory (DRAM), or flash memory. When the type of the media bank 311 included in the storage wafer 310 changes, the storage capacity of each media bank 311 will change, and the bandwidth between each media bank 311 and the corresponding storage controller 322 will also change differently. It is understandable that by changing the type of the media bank 311 in the storage wafer 310, the bandwidth and storage capacity corresponding to the processor die 330 can be more flexibly adjusted, thereby meeting the flexible ratio requirements of computing power, bandwidth, and storage capacity in different scenarios such as AI large model scenarios and HPC.

[0066] In one possible embodiment, each media Bank 311 may include multiple storage arrays (also referred to as media tiles), and each storage array includes multiple storage cells. The embodiment of the present application does not limit the specific number of storage arrays included in each media Bank 311, nor the specific number of storage cells included in each storage array.

[0067] Exemplarily, each memory array may be a 512×512 memory cell array, or each memory array may be a 1024×1024 memory cell array.

[0068] The integrated circuit 300 provided in the embodiment of the present application has an on-chip network 321 including multiple routing nodes 3211, and the interconnected wafer 320 also includes multiple storage controllers 322. The multiple routing nodes 3211 are respectively connected to the multiple storage controllers 322, and the multiple storage controllers 322 are respectively connected to the multiple media banks 311 in the storage wafer 310 through through holes. Each storage controller 322 is used to drive the media bank 311 connected to the storage controller 322, so that any processor die 330 can send read and write instructions to at least one storage controller 322 through the on-chip network 321. The at least one storage controller 322 can read data from the corresponding at least one media bank 311 according to the read and write instructions, or write data to the corresponding at least one media bank 311, thereby realizing flexible adjustment of the bandwidth and storage capacity corresponding to the processor die 330, and meeting the requirements of different scenarios such as AI large model scenarios and HPC for flexible ratio of computing power, bandwidth and storage capacity.

[0069] In one possible embodiment, as shown in FIG4 , the interconnect wafer 320 further includes at least one deserializer 323 connected to the on-chip network 321, and at least one processor die 330 is connected to the at least one deserializer 323. The embodiment of the present application does not limit the specific number of deserializers 323 included in the at least one deserializer 323. Thus, the at least one processor die 330 can communicate with the on-chip network 321 via the at least one deserializer 323. The use of the deserializer 323 can improve the data transmission efficiency of the integrated circuit 300 and reduce costs and power consumption.

[0070] In one possible embodiment, as shown in FIG5 , which is a top view of the integrated circuit 300, one of the at least one processor die 330 is connected to one of the at least one deserializer 323, and / or multiple processor dies 330 in the at least one processor die 330 are connected to one of the at least one deserializer 323, although this embodiment of the present application is not limited thereto.

[0071] For example, referring to FIG. 5 , the at least one processor die 330 includes a first processor die 331 , the at least one deserializer 323 includes a first deserializer 3231 , and the first processor die 331 is connected to the first deserializer 3231 .

[0072] For another example, referring to FIG. 5 , at least one processor die 330 includes a second processor die 332 and a third processor die 333 , at least one deserializer 323 includes a second deserializer 3232 , and the second processor die 332 and the third processor die 333 are connected to the second deserializer 3232 .

[0073] In one possible embodiment, at least one deserializer 323 is a high-density deserializer, thereby improving the data transmission efficiency between each processor die 330 and the media bank 311, or improving the data transmission efficiency between the processor die 330 and the processor die 330.

[0074] In the integrated circuit 300 provided in an embodiment of the present application, at least one processor die 330 is connected to at least one deserializer 323, so that the at least one processor die 330 can communicate with the on-chip network 321 through the at least one deserializer 323. By adopting the deserializer 323, the data transmission efficiency of the integrated circuit 300 can be improved, and the cost and power consumption can be reduced.

[0075] Based on this, as shown in Figure 6, an embodiment of the present application also provides an electronic device 600, which includes a shell 610 and an integrated circuit 300 arranged in the shell 610. The structure of the integrated circuit 300 is the structure of the integrated circuit 300 shown in any of the above Figures 3 to 5.

[0076] In a possible embodiment, the electronic device 600 is a computer.

[0077] The above detailed description of the integrated circuit 300 and the analysis of its beneficial effects can be correspondingly referred to the electronic device 600 , and will not be further elaborated herein in the embodiment of the present application.

[0078] The above is only a specific embodiment of the present application, but the scope of protection of this application is not limited to this. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. An integrated circuit, characterized in that: The integrated circuit includes a memory wafer, an interconnect wafer, and at least one processor die, wherein the interconnect wafer includes an on-chip network; The storage wafer and the interconnect wafer are stacked; The at least one processor die and the memory wafer are respectively connected to the on-chip network in the interconnect wafer; The at least one processor die is configured to write data to the storage wafer or read data from the storage wafer via the on-chip network.

2. The integrated circuit according to claim 1, wherein: The integrated circuit further includes a silicon interposer or substrate disposed on a side of the interconnect wafer away from the memory wafer, and the at least one processor die is connected to the on-chip network via the silicon interposer or substrate.

3. The integrated circuit according to claim 1 or 2, characterized in that The storage wafer and the interconnect wafer are packaged by wafer-to-wafer bonding.

4. The integrated circuit according to any one of claims 1 to 3, characterized in that The on-chip network includes multiple routing nodes, the interconnected wafer also includes multiple storage controllers, the storage wafer includes multiple media banks, the multiple routing nodes are respectively connected to the multiple storage controllers, and the multiple storage controllers are respectively connected to the multiple media banks through through holes.

5. The integrated circuit according to claim 4, wherein: The on-chip network is a two-dimensional grid on-chip network.

6. The integrated circuit according to claim 4 or 5, characterized in that The interconnect wafer further includes at least one deserializer connected to the on-chip network, and the at least one processor die is connected to the at least one deserializer.

7. The integrated circuit according to claim 6, wherein: One of the at least one processor die is connected to one of the at least one deserializer, and / or a plurality of the at least one processor die is connected to one of the at least one deserializer.

8. The integrated circuit according to any one of claims 4 to 7, characterized in that: The types of the multiple media banks include static random access memory, dynamic random access memory or flash memory.

9. The integrated circuit according to any one of claims 1 to 8, characterized in that The type of the at least one processor die includes at least one of a central processing unit, a graphics processing unit, or a neural network processor.

10. An electronic device, characterized in that: The electronic device includes a housing and an integrated circuit disposed in the housing, wherein the integrated circuit is the integrated circuit according to any one of claims 1 to 9.

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