Foldable screen system and signal transmission method

Abstract

The embodiments of the present application relate to the technical field of chips. Provided are a foldable screen system and a signal transmission method, by means of which the power consumption of a foldable screen system is reduced, and the performance of the foldable screen system is improved. The specific solution involves: the foldable screen system comprising a main board, an auxiliary board, and an axial flexible printed circuit (FPC) coupled between the main board and the auxiliary board, wherein the main board comprises a system on chip; the system on chip comprises a first bus interface; the first bus interface is disposed in an always-on domain of the system on chip; the auxiliary board comprises an aggregated chip; the aggregated chip comprises a second bus interface; the first bus interface and the second bus interface are coupled by means of the axial FPC; the system on chip is used for transmitting a first signal to the auxiliary board by means of the first bus interface; and the aggregated chip is used for converting the first signal received by means of the second bus interface into a plurality of second signals, the rate of the first signal being greater than or equal to the rate of the second signal. The embodiments of the present application are used for a signal transmission process between a main board and an auxiliary board.

Description

Folding screen system and signal transmission method

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on March 29, 2024, with application number 202410385138.1 and application name “Folding Screen System and Signal Transmission Method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of chip technology, and in particular to a folding screen system and a signal transmission method. Background Art

[0003] With the continuous development of science and technology, more and more electronic devices with display functions are widely used in people's daily lives, bringing great convenience to people's daily lives and work, and becoming an indispensable and important tool for people.

[0004] An increasing number of electronic devices are using foldable display panels. These devices typically consist of a main board and a secondary board, with signals transmitted between the two boards via a through-shaft flexible printed circuit (FPC). To improve the stability of the through-shaft FPC connection and reduce the number of board-to-board (BTB) interfaces between the main and secondary boards, thereby reducing the area of ​​the main and secondary boards, a polymer chip has been added between the main and secondary boards.

[0005] Aggregate chips can transmit a greater number of signals through a smaller number of hinges and effectively improve the stability of hinge hinge signals. However, with the increasing demand for thinner and lighter foldable screens, the area resources of the main and sub-boards are becoming increasingly limited. How to improve the performance of foldable screens within limited area resources is of great significance to the development of foldable screens. Summary of the Invention

[0006] The embodiments of the present application provide a folding screen system and a signal transmission method, which reduce the power consumption of the folding screen system and improve the performance of the folding screen system.

[0007] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions.

[0008] In a first aspect, an embodiment of the present application provides a folding screen system, comprising: a main board, a sub-board, and a through-axis flexible printed circuit board (FPC) coupled between the main board and the sub-board. The main board includes a system-on-chip (SoC), which includes a first bus interface, which is located in a normal power area of ​​the SoC. The sub-board includes a polymer chip, which includes a second bus interface, and the first bus interface and the second bus interface are coupled via the through-axis FPC. The SoC is configured to transmit a first signal to the sub-board via the first bus interface, and the polymer chip is configured to convert the first signal received via the second bus interface into multiple second signals, wherein the rate of the first signal is greater than or equal to the rate of the second signal.

[0009] Therefore, in the folding screen system provided by the embodiment of the present application, the first signal can be a fusion signal, that is, a signal obtained by fusion of multiple low-speed signals or multiple high-speed signals. The first signal on the main board can be transmitted to the sub-board through the first bus interface, and the aggregation chip on the sub-board can convert the first signal into multiple second signals with lower rates, which is equivalent to using the first bus interface and the second bus interface to transmit high-speed signals between the main board and the sub-board, and then converting the high-speed signal into multiple low-speed signals through the aggregation chip on the sub-board side, thereby reducing the number of signals passing through the axis between the main board and the sub-board and improving the integration of the folding screen system. In addition, since the first bus interface needs to re-establish the link when the system-level chip is powered on again after being powered off, setting the first bus interface in the normal power area of ​​the system-level chip can avoid the link establishment process when powering on again after being powered off, and can reduce the delay of the first bus interface in transmitting the first signal to the sub-board, thereby reducing the power consumption of the folding screen system and improving the performance of the folding screen system.

[0010] In one possible design, the aggregate chip also includes a first interrupt interface, and the system-on-chip also includes a second interrupt interface, with the first and second interrupt interfaces coupled via a through-shaft FPC. The aggregate chip is further configured to transmit interrupt signals from the slave board via the first interrupt interface to the second interrupt interface of the system-on-chip. This allows the aggregate chip to transmit multiple interrupt signals via the first and second interrupt interfaces, eliminating the need to transmit multiple interrupt signals via the first and second bus interfaces. This reduces the delay required for interrupt signals and lowers the power consumption associated with transmitting interrupt signals.

[0011] In one possible design, the SoC also includes a third bus interface, and the aggregation chip also includes a fourth bus interface, and the third and fourth bus interfaces are coupled via a through-shaft FPC. The aggregation chip is further configured to transmit indication information to the third bus interface of the SoC via the fourth bus interface, where the indication information is used to indicate the type of interrupt signal. Thus, the SoC can determine the type of interrupt signal based on the indication information transmitted via the third bus interface, thereby enabling coupling between the interrupt interface and the SoC via a single signal line, saving a significant amount of through-shaft resources.

[0012] In one possible design, the aggregation chip also includes a frequency division module, which is used to generate a clock signal based on the system clock. Therefore, setting up a frequency division module on the aggregation chip side can generate a clock signal for use by the peripherals on the sub-board side. This can avoid the problem of the aggregation chip being unable to power off if a clock signal is output after the clock signal is aggregated, further reducing the power consumption of the folding screen system.

[0013] In a possible design, the first bus interface or the second bus interface is a Peripheral Component Interconnect Express (PCIE) bus interface.

[0014] In one possible design, the third bus interface or the fourth bus interface is an improved inter-integrated circuit I3C bus interface.

[0015] In the second aspect, an embodiment of the present application provides a mainboard, the mainboard includes a system-level chip, the system-level chip includes a first bus interface, the first bus interface is arranged in the normal power area of ​​the system-level chip, the first bus interface is coupled to the sub-board through the through-axis flexible printed circuit board FPC, and the system-level chip is used to transmit a first signal to the sub-board through the first bus interface.

[0016] Therefore, in the mainboard provided in the embodiment of the present application, the first bus interface is set in the normal power area of ​​the system-level chip, which can avoid the need for the first bus interface to re-establish the link when the system-level chip is powered on again after being powered off, thereby reducing the delay of the first bus interface in transmitting the first signal to the sub-board, reducing the power consumption of the mainboard, and improving the performance of the mainboard.

[0017] In a third aspect, embodiments of the present application further provide a slave board, comprising an aggregation chip, the aggregation chip including a second bus interface, the second bus interface coupled to the master board via a through-axis flexible printed circuit board (FPC). The aggregation chip is configured to convert a first signal received via the second bus interface into multiple second signals, wherein the rate of the first signal is greater than or equal to the rate of the second signal.

[0018] Therefore, in the sub-board provided in the embodiment of the present application, the first signal can be a fused signal, that is, a signal obtained by fusion of multiple low-speed signals or multiple high-speed signals, which is equivalent to the signal transmitted between the main board and the sub-board being a high-speed signal. The aggregation chip then converts the high-speed signal into multiple low-speed signals, reducing the number of signals passing through the axis between the main board and the sub-board, and improving the integration of the folding screen system.

[0019] In a fourth aspect, an embodiment of the present application provides a signal transmission method, which is applied to a foldable screen system. The foldable screen system includes: a main board, a sub-board, and a through-axis flexible printed circuit board (FPC) coupled between the main board and the sub-board. The main board includes a system-level chip, the system-level chip includes a first bus interface, and the first bus interface is arranged in the normal power area of ​​the system-level chip. The sub-board includes a polymerization chip, the polymerization chip includes a second bus interface, and the first bus interface and the second bus interface are coupled via the through-axis FPC. The method includes: the system-level chip transmits a first signal to the sub-board via the first bus interface, the polymerization chip converts the first signal received via the second bus interface into multiple second signals, and the rate of the first signal is greater than or equal to the rate of the second signal.

[0020] In one possible design, the aggregate chip also includes a first interrupt interface, the system-level chip includes a second interrupt interface, and the first interrupt interface and the second interrupt interface are coupled through a through-axis FPC; the method also includes: the aggregate chip sends the interrupt signal of the sub-board to the second interrupt interface of the system-level chip through the first interrupt interface.

[0021] In one possible design, the system-level chip also includes a third bus interface, the aggregation chip also includes a fourth bus interface, and the third bus interface and the fourth bus interface are coupled through a through-axis FPC; the method also includes: the aggregation chip transmits indication information to the third bus interface of the system-level chip through the fourth bus interface, and the indication information is used to indicate the type of the interrupt signal.

[0022] In one possible design, the aggregate chip further includes a frequency division module; the method further includes: the frequency division module generating a clock signal based on the system clock.

[0023] In a possible design, the first bus interface or the second bus interface is a Peripheral Component Interconnect Express (PCIE) bus interface.

[0024] In one possible design, the third bus interface or the fourth bus interface is an improved inter-integrated circuit I3C bus interface.

[0025] In a fifth aspect, an embodiment of the present application provides an electronic device, which includes a touch screen and the folding screen system of the first aspect, and the touch screen and the folding screen system are electrically connected.

[0026] In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium, comprising computer instructions. When the computer instructions are executed on an electronic device, the electronic device executes the signal transmission method in any of the above aspects and any possible implementation methods.

[0027] In a seventh aspect, an embodiment of the present application provides a computer program product, which, when running on a computer or a processor, enables the computer or the processor to execute the signal transmission method in any of the above aspects and any possible implementation methods.

[0028] It can be understood that any of the folding screen systems, electronic devices, computer-readable storage media or computer program products provided above can be applied to the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods and will not be repeated here.

[0029] These and other aspects of the present application will become more readily apparent from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] FIG1 is a schematic structural diagram of a folding screen system provided in an embodiment of the present application;

[0031] FIG2 is a schematic structural diagram of another folding screen system provided in an embodiment of the present application;

[0032] FIG3 is a flow chart of a PCIE bus interface link establishment process provided in an embodiment of the present application;

[0033] FIG4 is a schematic structural diagram of another folding screen system provided in an embodiment of the present application;

[0034] FIG5 is a flowchart of another PCIE bus interface link establishment process provided in an embodiment of the present application;

[0035] FIG6 is a schematic structural diagram of another folding screen system provided in an embodiment of the present application;

[0036] FIG7 is a schematic structural diagram of another folding screen system provided in an embodiment of the present application;

[0037] FIG8 is a flowchart of a signal transmission method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] For ease of understanding, some examples of concepts related to the embodiments of this application are provided for reference as follows:

[0039] 1. Serial peripheral interface (SPI), a high-speed, full-duplex, and synchronous communication bus. SPI communication is master-slave, involving a master device and one or more slave devices, requiring at least four wires. All SPI-based devices share these four wires: master input slave output (MISO), master output slave input (MOSI), serial clock (SCLK), and chip select (CS). MISO is the master data input and slave data output. MOSI is the master data output and slave data input. The CS signal is the slave enable signal, a control signal that determines whether the slave device has been selected by the master. The SCLK signal is the clock pulse provided by the master, and MISO and MOSI complete data transmission based on this clock pulse.

[0040] 2. The inter-IC sound (I2S) bus is a bus standard developed for transmitting audio data between digital audio devices, such as CD players, digital sound processors, and digital TV sound systems. An I2S bus cable consists of three serial conductors: a time-division multiplexed data line, a word select line, and a clock line. The I2S bus uses separate wires to transmit clock and data signals. By separating the data and clock signals, distortion caused by time differences is avoided.

[0041] 3. The inter-integrated circuit (I2C) bus is a bus used to connect microcontrollers and their peripheral devices. The I2C bus consists of two wires: serial data (SDA) and serial clock (SCL). SDA and SCL carry messages between devices connected to the bus. Each device connected to the bus is software-addressed using a unique address and a simple, consistent master / slave relationship. The master can act as either a master transmitter or a master receiver.

[0042] 4. General-purpose input / output (GPIO). Some of the chip's pins are available for users to freely use through programs. Pins can be used as general-purpose input (GPI), general-purpose output (GPO), or GPIO depending on practical considerations.

[0043] 5. Subscriber Identity Module (SIM) is used in GSM (Global System for Mobile Communication) digital mobile phones. The SIM card chip stores the customer's information, encryption keys, and the user's phone book, which can be used to authenticate the GSM network customer and encrypt the voice information during the customer's call.

[0044] 6. Peripheral Component Interconnect Express (PCIE), a high-speed serial computer expansion bus standard. PCIE is a high-speed serial point-to-point dual-channel, high-bandwidth transmission standard. Connected devices are allocated exclusive channel bandwidth and do not share bus bandwidth. It primarily supports active power management, error reporting, end-to-end reliable transmission, hot plugging, and quality of service.

[0045] 7. Small Computer System Interface (SCSI): An interface that connects a host computer to peripheral devices. It supports a variety of devices, including hard drives, optical drives, and scanners. The SCSI bus is a parallel bus with the advantage of wide adaptability.

[0046] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application. In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships can exist, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, "multiple" means two or more than two.

[0047] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this embodiment, unless otherwise specified, "plurality" means two or more.

[0048] In order to reduce the number of through-axis signals of the folding screen, an aggregation chip can be provided on both the main board and the sub-board side, as shown in Figure 1, which is a structural schematic diagram of a folding screen system provided by an embodiment of the present application. The folding screen system may include a main board and a sub-board. The main board may be provided with a system-on-a-chip (SoC) and a first aggregation chip, and the sub-board may be provided with a second aggregation chip and multiple peripherals. The first aggregation chip includes a first digital interface, and the second aggregation chip includes a second digital interface. The first digital interface and the second digital interface may be a serial bus (serdes to serdes, STS) interface. The multiple signals of the system-level chip are converted into fused signals through the first digital interface in the first aggregation chip and transmitted to the second digital interface on the sub-board. The second aggregation chip expands the fused signals received by the second digital interface into multiple low-speed signals, and then transmits the low-speed signals to the relevant peripherals. In addition, there are some independent signals between the main board and the sub-board, namely through-axis signals. The independent signals cannot be transmitted through the first digital interface and the second digital interface, and need to be transmitted using a through-axis signal strategy. The second aggregation chip may integrate a low-speed interface intellectual property core (IP), such as GPIO, SPI, I2C or SIM.

[0049] In the motherboard, the SoC can control the operating state of the first aggregation chip through instructions, switching between high-speed, low-speed, and standby modes as needed. After the first aggregation chip completes the state of the corresponding service, the first aggregation chip switches state. At this time, after the SoC completes the service configuration, the area connected to the SoC and the first aggregation chip can enter a dormant state, completely decoupling the service states of the SoC and the first aggregation chip, thereby reducing the power consumption of the motherboard.

[0050] However, as foldable screens become increasingly thin and lightweight, the motherboard's real estate resources are becoming increasingly limited. The first aggregation chip is large, occupying a large amount of motherboard real estate resources. In addition, some independent signals from the motherboard need to be transmitted to the sub-board using a through-axis strategy.

[0051] In one possible implementation, in order to reduce the circuit area on the mainboard, as shown in FIG2 , the aggregation chip on the mainboard can be eliminated based on the folding screen shown in FIG1 , and only one aggregation chip can be provided on the sub-board side. In other words, the aggregation chip on the sub-board side can communicate directly with the system-level chip on the mainboard side. The mainboard may include a first bus interface, which is coupled to the second bus interface on the sub-board side through a through-axis FPC. The first bus interface may be provided in the system-level chip. Specifically, the first bus word interface may be provided in the peripheral circuit (PERI) area of ​​the system-level chip. The first bus interface and the second bus interface may be PCIE bus interfaces.

[0052] In some scenarios, the PCIE bus interface needs to be re-established, for example: (1) When the PERI area is powered off, if the application processor (A) core issues a task, the PERI area needs to be powered on and the PCIE bus interface needs to start establishing a link. (2) When the PERI area is powered off, another core (such as the image sensor processor (ISP) core) issues a task. At this time, the A core can still be in sleep mode, but the PERI area needs to be powered on and the PCIE bus interface needs to start establishing a link.

[0053] Among them, as shown in Figure 3, the link establishment process of the PCIE bus interface may include: S301, the application processor subsystem (AP) / modem and the sensor hub (sensorhub) perform inter-process communication (IPC) to initiate communication mechanism interaction. S302, PERI area power on. S303, configure the registers of the aggregation chip through the bus to realize the initialization configuration of the aggregation chip business. S304, PCIE bus interface link establishment. Among them, the latency of the folding screen system using the PCIE bus interface is greater than the latency of the folding screen using the STS interface.

[0054] In other words, as long as the aggregation chip is in operation, the PERI area of ​​the system-level chip must be powered on at all times, and the system-level chip cannot enter a sleep state, which increases the additional power consumption of the system-level chip. In addition, the link establishment process of the PCIE bus interface requires a large delay, which has a significant impact on the delay of high-speed signals and a large power loss of the foldable screen.

[0055] Therefore, the embodiment of the present application provides a folding screen system, in which the first signal on the main board can be transmitted to the sub-board through the first bus interface, and the aggregation chip on the sub-board can convert the first signal into multiple second signals with lower rates, which is equivalent to using the first bus interface and the second bus interface to transmit high-speed signals between the main board and the sub-board, and then converting the high-speed signal into multiple low-speed signals through the aggregation chip on the sub-board side, thereby reducing the number of signals passing through the axis between the main board and the sub-board and improving the integration of the folding screen system. In addition, since the first bus interface needs to re-establish the link when the system-level chip is powered on again after being powered off, setting the first bus interface in the normal power area of ​​the system-level chip can avoid the link establishment process when powering on again after being powered off, and can reduce the delay of the first bus interface in transmitting the first signal to the sub-board, thereby reducing the power consumption of the folding screen system and improving the performance of the folding screen system.

[0056] In the above scenario, the folding screen system provided in the embodiment of the present application can be applied to electronic devices, and the electronic devices can be mobile phones, tablet computers, desktop computers, laptops, handheld computers, notebook computers, ultra-mobile personal computers (UMPCs), netbooks, as well as cellular phones, personal digital assistants (PDAs), augmented reality (AR) and virtual reality (VR) devices, etc., which include folding screens. The embodiment of the present application does not impose any special restrictions on the specific form of the device.

[0057] The foldable screen system can be coupled to the foldable screen, and the foldable screen can display image data and text data transmitted by the foldable screen system. The foldable screen in the embodiments of the present application can be a flexible screen. In some embodiments, the foldable screen can be folded along a first direction and can also be folded along a second direction, with the first direction and the second direction being perpendicular.

[0058] The folding screen system provided in the embodiment of the present application is further described below.

[0059] An embodiment of the present application provides a folding screen system, as shown in Figure 4, which is a structural diagram of another folding screen system provided by an embodiment of the present application. The folding screen system includes a main board, a sub-board, and a through-axis FPC coupled between the main board and the sub-board. The main board includes a system-on-chip (SoC), the system-on-chip includes a first bus interface, the first bus interface is arranged in the always on domain (AON) of the system-on-chip, the sub-board includes an aggregation chip, the aggregation chip includes a second bus interface, and the first bus interface and the second bus interface are coupled through the through-axis FPC.

[0060] Among them, the normal power area is the area that always remains powered on during the operation of the chip. The normal power area may include some key circuits and modules, such as clock circuits, reset circuits, and power management circuits. The normal power area can ensure that the chip can work normally at any time. For example, the clock circuit can always provide timing control for the chip to ensure that each module operates according to the correct timing. The reset circuit can restore the chip to its initial state when the chip is powered on or an abnormal situation occurs. The power management circuit can manage the power supply of the chip to ensure the stable operation of the chip. In the embodiment of the present application, the first bus interface is set in the normal power area of ​​the system-level chip, which can ensure that the first bus interface is always in a working state after the system-level chip is powered on for the first time, ensuring that the system-level chip and the aggregation chip of the sub-board can maintain a long-term link, and avoiding the re-link process of the first bus interface.

[0061] The system-level chip is used to transmit a first signal to the secondary board through the first bus interface. The aggregation chip is used to convert the first signal received through the second bus interface into multiple second signals, where the rate of the first signal is greater than or equal to the rate of the second signal.

[0062] Exemplarily, the first bus interface and the second bus interface may be high-speed bus interfaces, such as a PCIE bus interface, serial attached SCSI (SAS), serial advanced technology attachment (SATA), non-volatile memory express (NVME), and mini serial attached SCSI (mini SAS). The embodiments of the present application do not impose specific restrictions on the types of the first bus interface and the second bus interface.

[0063] For example, the first signal can be understood as a fusion signal. The system-level chip can convert multiple low-speed signals or multiple high-speed signals that the main board needs to transmit to the sub-board into a fusion signal, and transmit it to the second bus interface on the sub-board side through the first bus interface. Since the first bus interface transmits the fusion signal to the second bus interface, the number of signals that need to pass through the axis between the main board and the sub-board can be reduced, thereby improving the integration of the folding screen system.

[0064] For example, the first signal may be a high-speed signal, and the second signal may be a low-speed signal. In one possible example, the first signal may be a service signal of a system-level chip. After receiving the first signal, the aggregation chip may decompose the first signal into service signals corresponding to the peripherals of the sub-board through an unpacking process.

[0065] Furthermore, the aggregate chip can be integrated with multiple low-speed interfaces, which are coupled to multiple peripherals on the secondary board. Specifically, the peripherals on the secondary board can include a SIM card, a gravity sensor, an acceleration sensor, a Hall sensor, a smart power amplifier (smartPA), a fingerprint (FP) sensor, a dual / stereo digital microphone interface (digital monolithic integrated circuit, DMIC), and a touch panel (touch panel, TP).

[0066] Optionally, the first bus interface or the second bus interface is a PCIE bus interface.

[0067] As shown in Figure 5, Figure 5 is a flowchart of another PCIE bus interface link establishment process provided by an embodiment of the present application. The PCIE bus interface link establishment process may include: S501, the application processor subsystem / modem and the sensor hub perform inter-core inter-process communication to initiate communication mechanism interaction. S502, configure the registers of the aggregation chip through the bus to implement the initialization configuration of the aggregation chip service. Compared with the flowchart of the PCIE bus interface link establishment in Figure 3, since the first bus interface is set in the normal power area, the step of "powering on the PERI area" in Figure 3 can be omitted. In addition, since the link of the PCIE bus interface is always maintained, the step of "PCIE bus interface link establishment" in Figure 3 can also be omitted. In addition, since the link of the PCIE bus interface is always maintained, some of the service functions of the aggregation chip do not need to be reconfigured due to the state maintenance, thereby reducing the configuration time of the bus. Specifically, the latency of the PCIE bus interface can be further reduced.

[0068] Therefore, when core A has non-aggregated services, the constant power area can control the aggregation chip on the slave board to enter standby mode. Because the system-level chip itself includes a constant power area, this operation does not increase power consumption significantly compared to the folding screen system shown in Figure 2, and can also improve the latency impact of the folding screen system. Due to the improved latency impact of the folding screen system, low-latency signals such as TP and SIM can be aggregated through the first bus interface and the second bus interface.

[0069] Optionally, as shown in Figure 6, Figure 6 is a structural diagram of another folding screen system provided in an embodiment of the present application. The aggregation chip further includes a first interrupt interface, the system-level chip includes a second interrupt interface, and the first interrupt interface and the second interrupt interface are coupled. The aggregation chip is also used to send an interrupt signal from the sub-board to the second interrupt interface of the system-level chip through the first interrupt interface. The interrupt signal can be used to wake up the system-level chip.

[0070] For example, as can be seen from the foregoing, even if the PCIE bus interface is set in the normal power area of ​​the system-level chip, the latency of the PCIE bus interface is reduced. If there are frequent interrupt signals that need to be aggregated, although the interrupt service time is very short, such as tens of microseconds, each interrupt service is superimposed with a PCIE bus interface link establishment delay, it will still increase the power consumption of the folding screen system. Therefore, the embodiment of the present application transmits the interrupt signal to the system-level chip through the first interrupt interface and the second interrupt interface. That is to say, the interrupt signal can be directly transmitted to the system-level chip without going through the high-speed voting of the aggregation chip.

[0071] For example, after receiving multiple interrupt signals from peripherals, the aggregation chip aggregates the multiple interrupt signals and transmits the aggregated interrupt signals to the system-level chip through the first interrupt interface. In this way, by transmitting frequent interrupt signals through a dedicated interrupt interface, the power consumption of the foldable screen system can be further reduced.

[0072] Continuing with Figure 6 , the SoC also includes a third bus interface, and the aggregation chip also includes a fourth bus interface. The third and fourth bus interfaces are coupled via a through-axis FPC. The aggregation chip is further configured to transmit indication information to the SoC's third bus interface via the fourth bus interface, indicating the type of interrupt signal.

[0073] Exemplarily, the third bus interface or the fourth bus interface may be a low-speed bus interface, such as an SPI bus, an I2C bus, or a GPIO.

[0074] For example, after receiving multiple interrupt signals sent by the interrupt interface of the aggregation chip, the system-level chip can also receive indication information sent by the aggregation chip through the fourth bus interface through the third bus interface to determine the peripheral device that sent the interrupt and then perform subsequent corresponding services. In addition, the third bus interface and the fourth bus interface can also transmit configuration signals, which can be used to initialize the configuration of the aggregation chip or other state configurations.

[0075] Optionally, the third bus interface or the fourth bus interface is an improved inter integrated circuit (I3C) bus interface.

[0076] For example, the I3C bus is an improved I2C bus. Compared to the I2C bus, the I3C bus can connect to more peripheral devices without adding additional logic signals to support interrupts or sleep modes. The I3C bus and the I2C bus use similar interfaces. The I3C bus supports multiple types of devices, including the current master device, auxiliary master devices, I3C slave devices, and I2C slave devices. The I3C master device can dynamically assign 7-bit addresses to I3C slave devices and also supports static address assignment for I2C slave devices. As a result, the I3C bus is compatible with the I2C bus. In addition, the power consumption of the I3C bus is reduced compared to the power consumption of the I2C bus, but the transmission rate is increased.

[0077] Therefore, if the third bus interface or the fourth bus interface is an I3C bus interface, it can cooperate with the interrupt interface to transmit multiple interrupt signals, so that the first interrupt interface and the second interrupt interface can be coupled through only one signal line, which can save a lot of axis resources.

[0078] Optionally, as shown in Figure 7, Figure 7 is a structural diagram of another folding screen system provided in an embodiment of the present application. Among them, the aggregation chip also includes a frequency division module, which is used to generate a clock signal based on the system clock.

[0079] For example, if the mainboard's clock signal is transmitted to the secondary board via the aggregation chip, the aggregation chip will be unable to power off when a clock signal is output, which will cause the folding screen system to generate unnecessary power consumption. Therefore, the embodiment of the present application sets a frequency division module on the secondary board side. The frequency division module can generate a clock signal based on the system clock for use by the peripherals on the secondary board side.

[0080] Specifically, the motherboard can provide the system clock (19.2 MHz) to the frequency divider module via the through-axis FPC. The aggregation chip can provide a gating signal to the frequency divider module. When the gating signal is enabled, the frequency divider module can generate signals of different frequencies based on the system clock. For example, the frequency divider module can generate a clock signal for the touch screen, such as clk. In addition, the touch screen can also send an interrupt signal, such as clk_req, to ​​the aggregation chip, which can actively initiate clock calibration.

[0081] Therefore, by setting a frequency division module in the aggregation chip, a clock signal can be generated for use by the peripherals on the sub-board side. This can avoid the problem that after the clock signal is aggregated, if there is a clock signal output, the aggregation chip will not be able to power off, further reducing the power consumption of the folding screen system.

[0082] An embodiment of the present application further provides a motherboard, comprising a system-on-chip (SoC), the SoC comprising a first bus interface, the first bus interface being disposed in a normal power region of the SoC and coupled to a sub-board via a through-shaft FPC. The SoC is configured to transmit a first signal to the sub-board via the first bus interface.

[0083] For example, in the motherboard provided in the embodiment of the present application, the first bus interface is set in the normal power area of ​​the system-level chip, which can avoid the need for the first bus interface to re-establish the link when the system-level chip is powered on again after being powered off, thereby reducing the delay of the first bus interface in transmitting the first signal to the sub-board, reducing the power consumption of the mainboard, and improving the performance of the mainboard.

[0084] An embodiment of the present application further provides a secondary board, comprising an aggregation chip, the aggregation chip including a second bus interface, the second bus interface being coupled to the primary board via a through-shaft FPC. The aggregation chip is configured to convert a first signal received via the second bus interface into multiple second signals, wherein the rate of the first signal is greater than or equal to the rate of the second signal.

[0085] For example, in the sub-board provided in the embodiment of the present application, the first signal can be a fused signal, that is, a signal obtained by fusion of multiple low-speed signals or multiple high-speed signals, which is equivalent to the signal transmitted between the main board and the sub-board being a high-speed signal. The aggregation chip then converts the high-speed signal into multiple low-speed signals, reducing the number of signals passing through the axis between the main board and the sub-board, and improving the integration of the folding screen system.

[0086] Applied to the above-mentioned folding screen system, the signal transmission method provided in the embodiment of the present application is introduced below.

[0087] An embodiment of the present application provides a signal transmission method, as shown in Figure 8, which is a flow chart of a signal transmission method provided by an embodiment of the present application. The folding screen system includes a main board, a sub-board, and a through-axis FPC coupled between the main board and the sub-board. The main board includes a system-level chip, the system-level chip includes a first bus interface, and the first bus interface is set in the normal power area of ​​the system-level chip. The sub-board includes an aggregation chip, the aggregation chip includes a second bus interface, and the first bus interface and the second bus interface are coupled through the through-axis FPC. The method may include the following S801 and S802.

[0088] S801. The system-on-chip transmits a first signal to the secondary board through a first bus interface.

[0089] S802: The aggregation chip converts a first signal received through the second bus interface into multiple second signals.

[0090] The rate of the first signal is greater than or equal to the rate of the second signal.

[0091] Exemplarily, the first signal can be a fusion signal, that is, a high-speed signal obtained by fusing multiple low-speed signals or multiple high-speed signals. The first signal on the main board can be transmitted to the sub-board through the first bus interface. The aggregation chip on the sub-board can convert the first signal into multiple second signals with lower rates. This is equivalent to using the first bus interface and the second bus interface to transmit high-speed signals between the main board and the sub-board, and then converting the high-speed signal into multiple low-speed signals through the aggregation chip on the sub-board side, thereby reducing the number of signals passing through the axis between the main board and the sub-board and improving the integration of the folding screen system. In addition, since the first bus interface needs to re-establish the link when the system-level chip is powered on again after being powered off, setting the first bus interface in the normal power area of ​​the system-level chip can reduce the delay of the first bus interface in transmitting the first signal to the sub-board, reduce the power consumption of the folding screen system, and improve the performance of the folding screen system.

[0092] Optionally, the aggregate chip further includes a first interrupt interface, and the system-level chip further includes a second interrupt interface, wherein the first interrupt interface and the second interrupt interface are coupled via a through-shaft FPC. The method further includes: the aggregate chip sending an interrupt signal from the slave board to the second interrupt interface of the system-level chip via the first interrupt interface.

[0093] For example, the aggregation chip can transmit the interrupt signal through the first interrupt interface and the second interrupt interface without transmitting the interrupt signal through the first bus interface and the second bus interface, which can reduce the delay required for the interrupt signal and reduce the power consumption of transmitting the interrupt signal.

[0094] Optionally, the system-on-chip further includes a third bus interface, and the aggregation chip further includes a fourth bus interface, wherein the third bus interface and the fourth bus interface are coupled via a through-shaft FPC. The method further includes: the aggregation chip transmitting indication information to the third bus interface of the system-on-chip via the fourth bus interface, wherein the indication information is used to indicate the type of the interrupt signal.

[0095] Exemplarily, the system-level chip can determine the type of the interrupt signal through the indication information transmitted by the third bus interface, so that the first interrupt interface and the second interrupt interface can be coupled through only one signal line, which can save a lot of axis-threading resources.

[0096] Optionally, the aggregation chip further includes a frequency division module, and the method further includes: the frequency division module generates a clock signal based on the system clock.

[0097] For example, a frequency division module is set on the aggregation chip side to generate a clock signal for use by the peripherals on the sub-board side. This can avoid the problem that after the clock signal is aggregated, if there is a clock signal output, the aggregation chip will not be able to power off, thereby further reducing the power consumption of the folding screen system.

[0098] An embodiment of the present application also provides an electronic device, which includes a touch screen and a folding screen system, and the touch screen and the folding screen system are electrically connected.

[0099] For example, the sub-board in the folding screen system can provide a clock signal to the touch screen, and the touch screen can also send an interrupt signal to the sub-board to calibrate the clock signal.

[0100] An embodiment of the present application further provides a computer storage medium storing computer instructions. When the computer instructions are executed on an electronic device, the electronic device executes the above-mentioned related method steps to implement the signal transmission method in the above-mentioned embodiment.

[0101] An embodiment of the present application further provides a computer program product. When the computer program product is run on a computer, the computer is caused to execute the above-mentioned related steps to implement the signal transmission method executed by the electronic device in the above-mentioned embodiment.

[0102] In addition, an embodiment of the present application also provides a device, which can specifically be a chip, component or module, and the device may include a connected processor and memory; wherein the memory is used to store computer-executable instructions, and when the device is running, the processor can execute the computer-executable instructions stored in the memory to enable the chip to execute the signal transmission method performed by the electronic device in the above-mentioned method embodiments.

[0103] Among them, the folding screen system, electronic device, computer storage medium, computer program product or chip provided in this embodiment are all used to execute the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods provided above, and will not be repeated here.

[0104] Through the description of the above implementation methods, technical personnel in the relevant field can understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0105] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the modules or units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0106] The units described as separate components may or may not be physically separate, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple places. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0107] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0108] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a device (which can be a single-chip microcomputer, chip, etc.) or a processor (processor) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0109] The above content is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A folding screen system, characterized in that: The folding screen system includes: a main board, a sub-board, and a through-axis flexible printed circuit board (FPC) coupled between the main board and the sub-board, the main board includes a system-level chip, the system-level chip includes a first bus interface, the first bus interface is set in the normal power area of ​​the system-level chip, the sub-board includes a polymerization chip, the polymerization chip includes a second bus interface, the first bus interface and the second bus interface are coupled through the through-axis FPC; The system-on-chip is configured to transmit a first signal to the secondary board via the first bus interface; The aggregation chip is configured to convert the first signal received through the second bus interface into a plurality of second signals, wherein a rate of the first signal is greater than or equal to a rate of the second signal.

2. The system according to claim 1, wherein: The aggregation chip further includes a first interrupt interface, and the system-level chip further includes a second interrupt interface, and the first interrupt interface and the second interrupt interface are coupled via the through-axis FPC; The aggregation chip is further configured to send the interrupt signal of the secondary board to the second interrupt interface of the system-level chip through the first interrupt interface.

3. The system according to claim 2, characterized in that The system-level chip further includes a third bus interface, and the aggregation chip further includes a fourth bus interface, and the third bus interface and the fourth bus interface are coupled via the through-axis FPC; The aggregation chip is further used to transmit indication information to the third bus interface of the system-level chip through the fourth bus interface, where the indication information is used to indicate the type of the interrupt signal.

4. The system according to claim 1, wherein: The aggregation chip further includes a frequency division module; The frequency division module is used to generate a clock signal based on the system clock.

5. The system according to any one of claims 1 to 4, characterized in that: The first bus interface or the second bus interface is a Peripheral Component Interconnect Express (PCIE) bus interface.

6. The system according to any one of claims 1 to 5, characterized in that: The third bus interface or the fourth bus interface is an improved inter-integrated circuit I3C bus interface.

7. A motherboard, characterized in that: The mainboard includes a system-level chip, the system-level chip includes a first bus interface, the first bus interface is arranged in a normal power area of ​​the system-level chip, and the first bus interface is coupled to the sub-board through a through-axis flexible printed circuit board FPC; The system-on-chip is configured to transmit a first signal to the secondary board through the first bus interface.

8. A sub-plate, characterized in that: The secondary board includes a polymer chip, the polymer chip includes a second bus interface, and the second bus interface is coupled to the main board via a through-axis flexible printed circuit board FPC; The aggregation chip is configured to convert a first signal received through the second bus interface into a plurality of second signals, wherein a rate of the first signal is greater than or equal to a rate of the second signal.

9. A signal transmission method, characterized in that: The method is applied to a foldable screen system, which includes: a main board, a sub-board, and a through-axis flexible printed circuit board (FPC) coupled between the main board and the sub-board, wherein the main board includes a system-level chip, the system-level chip includes a first bus interface, and the first bus interface is set in a normal power area of ​​the system-level chip; the sub-board includes a polymerization chip, the polymerization chip includes a second bus interface, and the first bus interface and the second bus interface are coupled via the through-axis FPC; the method includes: The system-on-chip transmits a first signal to the secondary board via a first bus interface; The aggregation chip converts the first signal received through the second bus interface into a plurality of second signals, where a rate of the first signal is greater than or equal to a rate of the second signal.

10. The method according to claim 9, characterized in that The aggregation chip further includes a first interrupt interface, the system-level chip further includes a second interrupt interface, and the first interrupt interface and the second interrupt interface are coupled via the through-axis FPC; the method further includes: The aggregation chip sends the interrupt signal of the sub-board to the second interrupt interface of the system-level chip through the first interrupt interface.

11. The method according to claim 10, characterized in that The system-level chip further includes a third bus interface, the aggregation chip further includes a fourth bus interface, and the third bus interface and the fourth bus interface are coupled via the through-axis FPC; the method further includes: The aggregation chip transmits indication information to the third bus interface of the system-on-chip through the fourth bus interface, where the indication information is used to indicate the type of the interrupt signal.

12. The method according to claim 9, characterized in that The aggregation chip further includes a frequency division module; and the method further includes: The frequency division module generates a clock signal based on the system clock.

13. The method according to any one of claims 9 to 12, characterized in that: The first bus interface or the second bus interface is a Peripheral Component Interconnect Express (PCIE) bus interface.

14. The method according to any one of claims 9 to 13, characterized in that: The third bus interface or the fourth bus interface is an improved inter-integrated circuit I3C bus interface.

15. An electronic device, characterized in that: A touch screen and a folding screen system as described in any one of claims 1 to 6, wherein the touch screen and the folding screen system are electrically connected.

16. A computer-readable storage medium, characterized in that The method comprises computer instructions, which, when the computer instructions are executed on an electronic device, cause the electronic device to execute the method according to any one of claims 9 to 14.

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