Hardware logic-based process control circuits, chips, and process control methods

Abstract

This application relates to the field of communication technology and discloses a hardware logic-based flow control circuit, chip, and flow control method. The flow control circuit is integrated inside the chip and is used to control multiple controlled modules. The flow control circuit includes: a bus interface for controlling multiple controlled modules or acquiring the status of multiple controlled modules; an instruction sequence execution controller for storing multiple sets of instruction sequences, each set of instruction sequences corresponding to a status index; the instruction sequence execution controller for executing the corresponding instruction sequence according to the input current status index, performing read / write operations or logical operations through the bus interface, and outputting an execution completion signal and a calculation result flag after all instructions in the corresponding instruction sequence have been executed; and a flow control state machine for outputting the current status index to the instruction sequence execution controller and receiving the execution completion signal and the calculation result flag, thereby controlling the flow while ensuring the robustness of the system.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a hardware logic-based process control circuit, chip, and process control method. Background Technology

[0002] In modern integrated circuit design, especially for mixed-signal chips with complex training processes, the flexibility of process control is crucial. To achieve this flexibility, the current mainstream design approach typically integrates a microcontroller (MCU) within the chip as the process management controller. The advantage of using an integrated MCU is that the MCU's software (firmware) can be updated online via the chip's serial interface. This allows for flexible adjustments to control strategies or fixes to logic defects without altering the hardware layout, greatly facilitating chip debugging and iteration.

[0003] However, while introducing MCUs brings flexibility, it also comes at a significant cost. First, integrating an MCU requires additional IP cores, increasing chip area and licensing costs. Second, in certain specific fields with extremely high reliability requirements, such as automotive chips, there are extremely stringent requirements for the quality of MCU hardware and software design (such as the ISO 26262 functional safety standard). Integrating a quality-compliant MCU system in these fields is not only highly complex but also involves long verification cycles and significant risks.

[0004] On the other hand, if a pure hard logic (such as a traditional finite state machine) is used instead of an MCU to implement process control, although it is easier to meet high standards in terms of design quality and system robustness, and does not require complex software certification, its biggest drawback is the loss of debugging flexibility. Once the chip is fabricated, the hard-wired control logic is fixed, and pure hard logic solutions are often helpless in the face of timing adjustment requirements that may arise in complex mixed-signal training processes. Summary of the Invention

[0005] One objective of this application is to provide a hardware logic-based process control circuit, chip, and process control method, which at least addresses the technical problems of high resource consumption and high design verification threshold when using microcontroller (MCU) solutions to implement complex process control, while pure hardware logic solutions face the problems of fixed control flow and lack of debugging flexibility.

[0006] To achieve the above objectives, some embodiments of this application provide the following aspects:

[0007] In a first aspect, some embodiments of this application provide a hardware logic-based flow control circuit, which is integrated inside a chip and used to control multiple controlled modules. The control inputs and status outputs of the multiple controlled modules are mapped to registers with independent access addresses. The flow control circuit includes:

[0008] The bus interface connects the multiple controlled modules via signal lines and reads and writes the registers based on independent access addresses to control the multiple controlled modules or obtain the status of the multiple controlled modules.

[0009] An instruction sequence execution controller, connected to the bus interface, is used to store multiple sets of instruction sequences, each set of instruction sequences corresponding to a status index; the instruction sequence execution controller is used to execute the corresponding instruction sequence according to the input current status index, perform the read / write operation or logical operation through the bus interface, and output an execution completion signal and an operation result flag after all instructions in the corresponding instruction sequence have been executed;

[0010] A process control state machine, connected to the instruction sequence execution controller, is used to output the current state index to the instruction sequence execution controller and receive the execution completion signal and the calculation result flag;

[0011] The process control state machine is implemented using hardware logic circuits. These hardware logic circuits are used to determine the next state based on the calculation result flag after receiving the execution completion signal.

[0012] Secondly, some embodiments of this application also provide a chip, the chip comprising:

[0013] Multiple controlled modules, including analog circuit modules or digital circuit modules, wherein the control inputs and status outputs of the multiple controlled modules are mapped to registers with independent access addresses;

[0014] The process control circuit based on hardware logic as described in any of the above embodiments is connected to the plurality of controlled modules via an internal bus to control the initialization process or working state of the plurality of controlled modules.

[0015] Thirdly, some embodiments of this application also provide a process control method applied to the hardware logic-based process control circuit described in any of the above claims, the method comprising:

[0016] Execute the corresponding instruction sequence according to the received current state index, read and write the register based on the independent access address, and output the execution completion signal and operation result flag after the corresponding instruction sequence is executed;

[0017] The current state index is output, and after receiving the execution completion signal, the next state is determined by hardware logic circuitry based on the calculation result flag.

[0018] Compared with related technologies, the solution provided in this application, firstly, by employing a pure hardware architecture with an instruction sequence execution controller and bus address mapping, eliminates the need to integrate expensive MCU IP cores or write and maintain complex embedded software stacks. This significantly reduces the design threshold and verification risks of the chip while meeting system robustness and functional safety standards.

[0019] Secondly, by abstracting the control logic into a configurable sequence of instructions and storing it in a read-write memory unit, it still supports online updates of the control flow via a bus interface (such as a serial interface). This means that in the complex training process of mixed-signal chips, developers can flexibly adjust timing and parameters as if operating an MCU, achieving both robustness and flexibility.

[0020] Furthermore, compared to the interrupt delays and uncertainties that may exist in MCU software execution, the hardware logic of this application can execute instruction sequences in a defined clock cycle. Combined with the hardware status polling mechanism, it can accurately control and synchronize the status of analog components, making it particularly suitable for timing-sensitive mixed-signal control scenarios. Attached Figure Description

[0021] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0022] Figure 1 This is a diagram of the architecture of a traditional process control circuit.

[0023] Figure 2 An architecture diagram of a hardware logic-based flow control circuit is provided for an exemplary embodiment of this disclosure;

[0024] Figure 3 This embodiment of the present disclosure provides a schematic diagram of the interaction interface signals between a process control state machine and an instruction sequence execution controller;

[0025] Figure 4 A diagram illustrating a bus control architecture with an integrated external debugging path provided in an exemplary embodiment of this disclosure is shown.

[0026] Figure 5 A flowchart illustrating a hardware logic-based flow control method provided as an exemplary embodiment of this disclosure. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0028] The main data path of existing mixed-signal chips typically consists of a series of cascaded analog and digital functional components. During the initial power-on phase, a step-by-step training process is required to enter the correct operating state. Each step in the process involves activating, calibrating, or adapting certain functional components. The process control module needs to manage numerous switching operations, parameter configurations, and status reporting operations for these functional components. If a default pure hardware logic implementation is used, the system configuration would look like this... Figure 1 As shown.

[0029] Figure 2 This disclosure provides an exemplary embodiment of a hardware logic-based flow control circuit architecture diagram. The flow control circuit is integrated within a chip and is used to control multiple controlled modules. The control inputs and status outputs of the multiple controlled modules are mapped to registers with independent access addresses. The flow control circuit includes:

[0030] The bus interface connects the multiple controlled modules via signal lines and reads and writes the registers based on independent access addresses to control the multiple controlled modules or obtain the status of the multiple controlled modules.

[0031] An instruction sequence execution controller, connected to the bus interface, is used to store multiple sets of instruction sequences, each set of instruction sequences corresponding to a status index; the instruction sequence execution controller is used to execute the corresponding instruction sequence according to the input current status index, perform read / write operations or logical operations through the bus interface, and output an execution completion signal and an operation result flag after all instructions in the corresponding instruction sequence have been executed;

[0032] A process control state machine, connected to the instruction sequence execution controller, is used to output the current state index to the instruction sequence execution controller and receive the execution completion signal and the calculation result flag;

[0033] The process control state machine is implemented using hardware logic circuits. These hardware logic circuits are used to determine the next state based on the calculation result flag after receiving the execution completion signal. Furthermore, the process control state machine itself does not directly access the bus interface or the registers.

[0034] Specifically, such as Figure 2 As shown, the flow control module includes an instruction sequence execution controller and a flow control state machine, used for unified management of multiple controlled modules within the chip. These multiple controlled modules are specifically shown as "Digital Components 1 to n" and "Analog Components 1 to n" in the figure, representing the functional units responsible for digital signal processing and the circuit units responsible for analog signal transmission and reception, respectively. For the independent address access and register mapping, this embodiment employs a read-write separated bus architecture. Specifically, the bus interface is represented in hardware connection as the address lines and selector combination shown in the figure: In the write direction, the flow control module connects to the control terminal of the demultiplexer (DEMUX) by outputting a write address signal (write_addr), accurately distributing the control quantity to specific analog or digital components, corresponding to a write operation on the register; in the read direction, the flow control module connects to the control terminal of the multiplexer (MUX) by outputting a read address signal (read_addr), selecting and reading back the state quantity from various components, corresponding to a read operation on the register. In this way, the component interfaces distributed throughout the chip are logically mapped to a continuous or non-contiguous address space, and the flow control module can access any component simply by manipulating the address.

[0035] The instruction sequence execution controller is connected to the bus interface and integrates a storage unit (not shown in the figure) to store multiple sets of predefined instruction sequences. Each sequence corresponds to a specific hardware operation process (e.g., "power-on initialization process" or "data transmission configuration process") and is identified by a unique "status index". When the controller receives the input current status index, it retrieves the corresponding instruction sequence from the storage unit and executes it one by one. During execution, the controller parses the microinstructions into hardware actions, directly driving the write_addr bus and control data lines in the figure to configure component parameters, or driving the read_addr bus and reading the component's status variables (such as PLL lock flag or FIFO empty / full flag) through the MUX. When all instructions in an instruction sequence (including read / write operations and necessary logical operations) have been executed, the controller sends an execution completion signal and simultaneously outputs a calculation result flag (e.g., "initialization successful" or "calibration failed").

[0036] The flow control state machine resides above the instruction sequence execution controller, responsible for logical decisions and state transitions. Connected to the instruction sequence execution controller, its primary function is to output the current state index to the controller based on the current chip operating stage, thereby initiating specific hardware operation tasks. During task execution, the state machine is in a waiting state. Once it receives an execution completion signal from the controller, it immediately uses its internal hardware combinational logic circuitry (pure hardware logic) to quickly determine the next state based on the synchronously received calculation result flag, and generates a new state index to send back to the controller. This mechanism forms a closed-loop automated control flow: the state machine handles decision-making, the controller handles execution, and the bus interface handles transmission. These three work together to achieve efficient control of all digital and analog components without CPU software intervention. Furthermore, the instruction sequence execution controller is configured to execute only linear instruction sequences; its instruction set does not contain complex control flow instructions such as program counter (PC) jumps, subfunction calls, or stack operations. All state transition logic is completely decoupled and implemented by the flow control state machine through hardware combinational logic. This design makes the controller's hardware logic extremely simple, avoiding the complex pipelined risks and stack overflow risks found in general-purpose CPUs.

[0037] In this embodiment, by mapping multiple controlled modules to registers with independent access addresses and accessing them through a bus interface (MUX / DEMUX), the wiring complexity at the top level of the chip is greatly simplified, avoiding the wiring congestion problem caused by traditional point-to-point control and significantly improving the scalability of the circuit. Secondly, by adopting an architecture of instruction sequence execution controller combined with process control state machine, the control flow is configurable. Developers can flexibly adjust the chip's control timing (such as modifying the power-on sequence or waiting time) simply by updating the instruction sequence in the storage unit. This provides the flexibility of MCU software control while avoiding the high cost and design verification risks associated with introducing MCU IP cores. Finally, the entire control loop is implemented based on pure hardware logic, with instruction execution and state transitions having nanosecond-level responses and no uncertainty caused by software interrupt delays, thus ensuring extremely high real-time performance and robustness for controlling mixed-signal circuits.

[0038] Furthermore, in one embodiment, each instruction in the instruction sequence adopts a fixed-length encoding format, which includes a high-order control field and a low-order payload field;

[0039] The high-order control field includes: an operation type flag bit, used to distinguish between bus transmission and logical operations; a read / write flag bit, used to distinguish between read and write operations; a register selection bit, used to select an internal temporary register; and a data type flag bit.

[0040] The low-order payload field is reused to store the independent access address, immediate value, or operation type code, the specific meaning of which is determined by the operation type identifier bit and the data type identifier bit.

[0041] Specifically, to optimize hardware decoding efficiency and reduce storage resource consumption, the single instruction in this embodiment adopts a fixed-length encoding format (e.g., 20 bits), whose structure is logically divided into a high-order control field and a low-order payload field. The high-order control field contains several key identifier bits: the "operation type identifier bit" fundamentally indicates whether the current instruction is a data transfer instruction (Load / Store) or a calculation instruction (Calculation); the "read / write identifier bit" further distinguishes the operation direction, and this identifier bit only has indicative meaning when the operation type identifier bit indicates data transfer; the "register selection bit" (A or B) indicates which internal temporary register the data transfer or calculation result is destined for; and the "data type identifier bit" assists in indicating the attributes of the payload data.

[0042] The physical meaning and data flow of the low-order load field are jointly determined by the aforementioned control fields. When the operation type is indicated as Move, if the read / write flag is Load and the data type is address, the instruction reads data from a register address specified by the load field and writes the data to the result register selected by the register select bit. If the data type is numeric, the load field is directly written as an immediate value to the result register. Conversely, if the read / write flag is Store, the instruction writes the value in the selected result register to a register address specified by the load field. Typically, the value in the result register comes from the immediate value loaded by the previous instruction (Move Immediate) or the calculation result generated by the logic unit, thereby enabling the issuance of control quantities.

[0043] When the operation type indicator is a computational instruction, the read / write flag is no longer effective, and the low-order load field is directly parsed into the computation type code (cal_type). At this time, the instruction sequence execution controller drives the internal arithmetic logic unit (ALU) to perform the operation specified by the type code on the data in the temporary register. To ensure the completeness of the algorithm, this embodiment selects eight operations as the minimum subset of the ALU design, specifically including: addition, subtraction, bitwise AND, bitwise OR, bitwise XOR, logical left shift, logical right shift, and arithmetic right shift. Any complex control algorithm operation can be decomposed into a sequence combination of these eight basic operations.

[0044] Based on the above instruction definitions, the instruction sequence executed by the flow control module in each state typically follows a specific execution flow: the first part of the sequence usually consists of Store instructions, used to write configuration values ​​into the registers of functional modules; the second part of the sequence usually consists of Load instructions combined with calculation instructions, that is, first reading the state value of a controlled module into a temporary register, then using the ALU for comparison or calculation, and finally feeding back the resulting zero-judgment or overflow flag to the flow control state machine as the basis for determining the next state transition. The instruction decoder is responsible for hardware decoding of the above logic: if it is a Load instruction, it initiates read enable and read address, and writes the result to the temporary register after it is returned; if it is a Store instruction, it initiates write enable, write address, and write data; if it is a calculation instruction, it sets the write enable of the temporary register and writes the ALU calculation result, thereby ensuring the accurate execution of the entire control flow at the hardware level.

[0045] In this embodiment, by adopting the fixed-length encoding and field multiplexing format, the area overhead of the on-chip storage unit is significantly reduced and the storage density is increased. On the other hand, the fixed bit definition eliminates the dependence on complex instruction decoders, so that the instruction sequence execution controller can realize instruction parsing and control signal generation in a single clock cycle only through hardware combinational logic, thereby ensuring the high-speed response characteristics and timing determinism of the flow control circuit.

[0046] In one embodiment, the instruction sequence execution controller is used to execute the instructions in the instruction sequence according to the instruction fetch stage, the execution stage, and the input / output waiting stage; wherein, in the input / output waiting stage, the instruction sequence execution controller waits for the bus ready signal fed back by the bus interface, and completes the execution of the current instruction after receiving the bus ready signal; the flow control state machine is used to determine the next state as the current state if, after reading the value of the register through the instruction sequence execution controller, it is determined according to the calculation result flag that the state of the plurality of controlled modules does not meet the preset conditions.

[0047] Specifically, to ensure the deterministic timing of instruction execution and adapt to standard bus protocols, the instruction sequence execution controller is designed to employ a specific three-stage pipeline mechanism. The controller strictly divides the lifecycle of a single instruction into a fetch phase, an execution phase, and an I / O wait phase. In the fetch phase, the controller retrieves the instruction code based on the current program counter (PC). In the execution phase, the controller decodes the instruction and drives the bus address and control signals. In the I / O wait phase, the controller only performs bus protocol-level waiting, i.e., waiting for a valid bus ready signal from the bus slave device. Once the bus ready signal is detected as valid, regardless of whether the internal business process of the controlled module (such as simulation training) has actually been completed, the controller immediately latches the data and terminates the current instruction, subsequently outputting an execution completion signal and a calculation result flag. For asynchronous business states that require long waiting times, the system employs a "hardware polling" mechanism: the process control state machine performs logical judgments based on the returned calculation result flags (e.g., the Training Done status bit is 0). If the judgment is not ready, the system forces the next state index to be consistent with the current state index. This causes the state machine to input the same state index to the controller again in the next clock cycle, thereby repeatedly executing the read and judgment instructions until the state meets the conditions before transitioning to a new state.

[0048] In this embodiment, by decoupling the execution cycle of a single instruction from the waiting cycle of business logic, the instruction sequence execution controller is prevented from locking and monopolizing the bus for an extended period due to excessively long response times of the controlled module. This hardware polling mechanism based on a "state loop" allows the bus to be released during polling intervals, thereby allowing the bus arbiter to respond to other high-priority access requests (such as the insertion of external debugging interfaces). While ensuring accurate synchronization of asynchronous states, this significantly improves the utilization rate of the system bus and the flexibility of debugging.

[0049] In one embodiment, the instruction sequence execution controller includes a logic operation unit. This unit performs logical comparisons or arithmetic operations on the values ​​read from the registers and converts the results into a result flag. The result flag is a logical state signal indicating whether the result satisfies a preset condition. It is understood that the result flag is only used to drive the state transitions of the flow control state machine and is not used as a general operation result output. Specifically, the logic operation unit supports a predefined, finite set of operation types, such as addition, subtraction, bitwise AND, bitwise OR, bitwise XOR, and shift operations, but this set does not support multiplication, division, and floating-point operations common in general-purpose processors.

[0050] Specifically, such as Figure 3 As shown, to enable the hardware circuitry to handle complex logic branches, the instruction sequence execution controller integrates a logic operation unit. This logic operation unit is configured to perform logical comparisons (such as bitwise AND and numerical comparisons) or arithmetic operations (such as accumulation and decrement) on register values ​​read through the bus interface. After the operation is completed, the unit converts the original operation result into an operation result flag containing only one or more bits of binary information, namely the all-zero flag (z_flag) and the overflow flag (ov_flag) in the figure.

[0051] For example, when the controller executes a "status bitmask comparison" instruction, the logic unit performs a logical AND operation between the read value of the controlled module's status register and a preset mask. If the result is zero, z_flag is set to a valid level, indicating that the current state has not yet met a specific condition. Similarly, when the controller executes a "timeout count" instruction, if the accumulated value of the internal counter exceeds a preset threshold, ov_flag is set to a valid level, indicating a timeout error has occurred. These operation result flags serve as key logic status signals, synchronously transmitted to the flow control state machine (FSM) along with the execution completion signal (cmd_complete). Upon receiving these signals, the FSM can dynamically select the next state index based on the high or low level of z_flag or ov_flag using internal preset hardware combinational logic circuits (e.g., if z_flag is high, jump to the waiting state; if it is low, jump to the next configuration state), thus implementing a conditional jump control function similar to that in software code at the pure hardware level.

[0052] In this embodiment, by integrating a logic operation unit into the instruction sequence execution controller and introducing a "result flag" (such as an all-zero flag or an overflow flag) feedback mechanism, complex conditional branch control functions are successfully implemented in a pure hardware architecture. Unlike traditional hardware logic that can only be executed in a fixed order, this embodiment allows the flow control state machine to dynamically adjust the state transition path based on real-time register states or operation results (such as waiting timeouts, state comparison consistency, etc.), improving flexibility. At the same time, by abstracting complex numerical comparisons into simple single-bit flag signals, the scale of the logic judgment circuit of the upper-level state machine is greatly simplified, ensuring that nanosecond-level high-speed response and deterministic timing behavior can still be maintained when dealing with complex anomaly detection and flow branching in mixed-signal chips.

[0053] In one embodiment, the circuit further includes a breakpoint controller connected to the instruction sequence execution controller, which is used to store a preset breakpoint instruction index.

[0054] The instruction sequence execution controller also includes a comparator for comparing the index of the current instruction with the breakpoint instruction index in real time during execution. If a match is found, instruction execution is paused, allowing external devices to perform online verification of the chip's internal flow control status or fault location. Thus, the breakpoint controller supports dynamic configuration during chip runtime via the bus interface, enabling non-intrusive process debugging.

[0055] Specifically, to improve the observability and debugging efficiency of the chip during the R&D and testing phases, the hardware logic-based flow control circuit also integrates a breakpoint controller and supporting hardware comparison logic. The breakpoint controller is connected to the instruction sequence execution controller and internally contains one or more configurable breakpoint registers for storing preset breakpoint instruction indices. These breakpoint instruction indices can be pre-written via external debugging interfaces (such as JTAG, I2C, etc.) and point to specific critical operation steps in the instruction sequence (e.g., the moment before a critical simulation module powers on).

[0056] During circuit operation, the comparator inside the instruction sequence execution controller operates in real-time. It performs a hardware-level real-time comparison between the index value of the instruction currently being executed (or about to be fetched) and the breakpoint instruction index stored in the breakpoint controller. Once the two match, the comparator immediately outputs a valid level, triggering the controller to enter a pause state. In the pause state, the clock or state transitions of the instruction sequence execution controller are frozen, maintaining the current context unchanged. This allows external test equipment to read the bus status, register values, and feedback signals from each controlled module, facilitating precise location of timing faults or logic errors by researchers.

[0057] In this embodiment, by introducing a breakpoint control mechanism based on a hardware comparator, the pure hardware control circuit is endowed with "single-step debugging" or "breakpoint debugging" capabilities similar to a software IDE environment. This mechanism allows developers to precisely stop the high-speed control flow at any specified instruction step without disrupting the chip's internal timing state. This enables in-depth analysis and troubleshooting of the "black box" internal hardware state, significantly shortening the Bring-up cycle and fault location time of mixed-signal chips.

[0058] In one embodiment, the circuit further includes a bus arbiter, disposed on the connection path between the bus interface and the instruction sequence execution controller and the external debugging interface;

[0059] The bus arbiter is used to receive read / write requests initiated by the instruction sequence execution controller or the external debugging interface.

[0060] In one embodiment, the external debug interface reuses the chip's serial communication interface, which includes an I2C interface or an SPI interface. Access requests initiated by the external debug interface and access requests initiated by the instruction sequence execution controller converge and are arbitrated at the bus arbitrator.

[0061] Specifically, such as Figure 4 As shown, to ensure both efficient utilization of chip pin resources and deep debug accessibility, the circuit architecture integrates a bus arbiter and a multiplexed external debug interface. The external debug interface physically reuses the chip's original general-purpose serial communication interface (I2C / SPI_PAD). When an external debug host initiates access, the serial data input through this interface is first parsed into parallel data by an internal serial-to-parallel conversion module, then synchronized to the system clock domain by a cross-clock domain synchronization module (sync2clk_rg), and finally converted into an internal bus format (such as AHB format) via a first protocol conversion logic (cfg to ab), serving as the first control source input to the bus arbiter. Correspondingly, the control signals output by the flow control state machine and the instruction sequence execution controller are also converted into an internal bus format via a second protocol conversion logic (to ab), serving as the second control source input to the bus arbiter.

[0062] The bus arbiter is positioned between the two control sources and the downstream bus interface, employing a dynamic arbitration mechanism based on request order to manage bus access. Specifically, when any control source (e.g., the instruction sequence execution controller) initiates a read / write request and the bus is currently idle, the bus arbiter responds to the read / write request and transmits the control signal downstream. If another control source (e.g., the external debug interface) also initiates a read / write request at the same time, the bus arbiter controls the latter to enter a bus waiting state, suspending its handshake signal until the current bus operation is completed and released. The control signal selected by the bus arbiter is ultimately converted by the bus bridge unit (AHB to APB) to access the register group and various digital-to-analog components. Since the communication rate of the external serial interface is lower than that of the on-chip bus, even if an external request is temporarily suspended due to bus contention, there is still a sufficient time window to complete data interaction after the bus is released, thus ensuring the data integrity of bidirectional access.

[0063] In this embodiment, a hardware bus arbitration scheme based on a waiting mechanism is introduced to achieve concurrent coexistence of internal automated process control and external debugging intervention. This scheme eliminates the need for pre-defined mutually exclusive "debug modes" or complex mode-switching logic, allowing the external debugging host to directly observe or correct internal registers in real time via the arbitrator while the chip is running at full speed. This design avoids chip state resets or loss of context due to mode switching, significantly reduces chip packaging costs through pin reuse, and improves the maintainability and troubleshooting efficiency of mixed-signal chips in complex application scenarios.

[0064] In one embodiment, the instruction sequence execution controller includes a readable and writable storage unit for storing the instruction sequence. This readable and writable storage unit is mapped to the bus address space and is used to update or rewrite the instruction sequence through the bus interface. The readable and writable storage unit supports online updates during the operation of the flow control circuit, and update operations and instruction execution operations are accessed without conflict through a hardware interlock mechanism. It is understood that the update or rewrite operations do not change the hardware logic structure of the flow control state machine.

[0065] Specifically, to endow the hardware logic-based flow control circuit with extremely high flexibility and reconfigurability, the instruction sequence execution controller integrates a read-write memory unit, such as static random access memory (SRAM) or a register file. This read-write memory unit is logically directly mapped to the chip's global bus address space, meaning it is treated as a set of register arrays with specific read and write addresses. This implies that although the memory unit is located inside the core of the execution controller, external devices (such as a debugging host connected via the aforementioned multiplexed I2C / SPI interface) or other master control modules within the system can access this address space through standard bus write operations. When it is necessary to modify the chip's initialization process, adjust the waiting timing, or fix defects in the control logic, developers do not need to modify any hardware circuit connections. They only need to write new instruction code data to this mapped address through an external interface to overwrite the original instruction sequence in real time. Once the update is complete, the instruction sequence execution controller will obtain and execute the new instruction code the next time it reads instructions, thereby realizing online updating or rewriting of the control logic.

[0066] Furthermore, while the above embodiments are illustrated using read-write memory units (such as SRAM or register files) to emphasize their flexibility in online updates and debugging, the form of the memory unit is not limited to this in other embodiments of this disclosure. After the chip completes verification and enters the mass production stage, in order to further reduce costs and static power consumption, the memory unit used to store instruction sequences can also be implemented as one-time programmable memory (OTP), mask read-only memory (Mask ROM), or non-volatile flash memory (Flash). In this case, the instruction sequence is fixed before leaving the factory, but the architectural advantages described in this application—namely, achieving efficient control through the decoupling of the hardware state machine and the instruction executor—still apply. This diversity of storage media choices allows this solution to flexibly adapt to the entire lifecycle needs from engineering samples to mass-produced chips.

[0067] In this embodiment, by designing the instruction storage medium as a read-write memory unit mapped to the bus address space, the limitation of traditional pure hardware state machines being fixed once fabricated is overcome. This allows the flow control circuit of this application to maintain the high speed and determinism of hardware execution while possessing online programmability similar to software code. This allows designers to flexibly modify the control timing or adapt to the characteristics of different batches of analog components during the laboratory debugging stage after chip fabrication, and even in actual applications after product delivery, thereby significantly reducing chip R&D costs and mass production risks.

[0068] In one exemplary embodiment, this disclosure also provides a chip, the chip comprising:

[0069] Multiple controlled modules, including analog circuit modules or digital circuit modules, wherein the control inputs and status outputs of the multiple controlled modules are mapped to registers with independent access addresses;

[0070] The process control circuit based on hardware logic as described in any of the above embodiments is connected to the plurality of controlled modules via an internal bus to control the initialization process or working state of the plurality of controlled modules.

[0071] Specifically, the chip's system architecture mainly consists of two parts: one part comprises multiple controlled modules that perform specific signal processing tasks, including but not limited to analog circuit modules (such as phase-locked loops (PLLs), analog-to-digital converters (ADCs), and low-dropout linear regulators (LDOs)) and digital circuit modules (such as digital filters, hardware accelerators, or interface controllers); the other part is the flow control circuit described in the above embodiment. To achieve standardized interconnect control, the control input ports (such as enable switches and parameter configuration words) and status output ports (such as lock signals and FIFO full flags) of the multiple controlled modules are mapped to registers with independent access addresses, collectively forming the chip's internal address space.

[0072] The process control circuit establishes communication connections with all the controlled modules via a high-speed bus (such as AHB, APB, or a custom bus) inside the chip. After the chip is powered on or reset, the process control circuit immediately takes over bus control and automatically initiates read and write operations to these registers with independent addresses according to the pre-stored instruction sequence. This allows for precise control of multiple controlled modules to complete complex power-on initialization processes (such as enabling the power domain according to a specific timing sequence), parameter calibration processes (such as writing trimming codes), or operating state switching (such as switching between low-power mode and high-performance mode) without the intervention of an external microcontroller (MCU).

[0073] In this embodiment, by integrating a dedicated hardware process control circuit within the chip, the SoC system-level self-booting and self-management capabilities are achieved. This completely eliminates the redundant costs associated with external MCUs or expensive on-chip CPU cores for simple initialization control, significantly reducing the chip's die size. Simultaneously, the unified control architecture based on memory mapping decouples the analog and digital components within the chip, facilitating subsequent product iterations and functional expansions, and greatly improving the modularity and time-to-market of the chip design.

[0074] In one exemplary embodiment, such as Figure 5 As shown, this disclosure also provides a process control method, applied to the hardware logic-based process control circuit described in any of the above embodiments, the method comprising:

[0075] S101. Execute the corresponding instruction sequence according to the received current state index, read and write the register based on the independent access address, and output the execution completion signal and operation result flag after the corresponding instruction sequence is executed.

[0076] S102. Output the current state index, and after receiving the execution completion signal, determine the next state through hardware logic circuit based on the calculation result flag.

[0077] Specifically, such as Figure 5 As shown, this method is applied to the hardware logic-based flow control circuit described in any of the foregoing embodiments. The method mainly comprises two core steps completed collaboratively by an instruction sequence execution controller and a flow control state machine. First, in step S101, the instruction sequence execution controller, in response to the received current state index, addresses and retrieves the corresponding instruction sequence from its internal storage unit. Subsequently, the controller parses the instructions one by one and drives the bus interface to perform read and write operations on the registers of each controlled module based on independent access addresses (e.g., issuing configuration parameters or reading status bits). When all instructions in the instruction sequence corresponding to the state index have been executed, the controller generates and outputs an execution completion signal (cmd_complete) and a calculation result flag (such as an all-zero flag z_flag or an overflow flag ov_flag).

[0078] Next, in step S102, the flow control state machine enters a waiting mode after outputting the current state index to the controller. Once the execution completion signal is received, the state machine immediately uses its internal hardware logic circuitry to perform a logical decision on the synchronously received calculation result flag. This hardware logic circuitry determines the index value of the next state within a single clock cycle based on preset Boolean logic rules (e.g., if z_flag is high, it jumps to state A; otherwise, it jumps to state B), and feeds it back to the instruction sequence execution controller, thereby triggering a new round of instruction sequence execution. This method achieves an automated process of "state decision-sequence execution-result feedback-state transition" through hardware closed-loop processing.

[0079] In one embodiment, the step of executing the corresponding instruction sequence includes:

[0080] The instruction sequence includes an instruction fetch phase, an execution phase, and an input / output wait phase.

[0081] During the input / output waiting phase, the system waits for the bus ready signal from the bus interface and executes the current instruction upon receiving the bus ready signal.

[0082] The step of determining the next state based on the calculation result flag via hardware logic circuitry includes:

[0083] If the state of the multiple controlled modules does not meet the preset conditions based on the calculation result flag, then the next state is determined to be the current state.

[0084] Specifically, the method strictly divides the lifecycle of a single instruction into three atomic stages. In the fetch stage, the instruction code is retrieved from the memory unit based on the program counter. In the execution stage, the instruction is decoded, and the bus interface initiates a read / write request. If the current instruction involves querying the status of the controlled module (especially a simulation component), it enters the input / output waiting stage. In this stage, the method does not wait for the controlled module's business status to be ready at the instruction execution level (e.g., waiting for PLL locking or training completion), but only monitors the bus ready signal at the bus protocol level. Once the bus interface reports a valid bus ready signal, indicating that the register read / write operation has been completed at the electrical level, the controller immediately terminates the execution of the current instruction and outputs a flag containing the calculation result information.

[0085] For asynchronous business states requiring sequential waiting, the method employs a "state loop" mechanism for monitoring: After receiving the execution completion signal and the calculation result flag, the process control state machine performs real-time judgment through hardware combinational logic. If the calculation result flag indicates that the controlled module has not yet met the preset conditions (e.g., a specific bit in the status register is still 0), the state machine forces the next state index to point to the current state index. This causes the controller to retrieve and execute the exact same read and calculate instructions again in the next clock cycle. This process repeats continuously, forming a hardware-level state polling, until the controlled module's state meets the conditions, the calculation result flag flips, and the state machine points the next state index to the new operation flow.

[0086] In this embodiment, by decoupling the single-instruction-cycle bus handshake from the long-cycle business state waiting, the instruction sequence execution controller's prolonged monopoly of bus resources due to slow response from the controlled module is avoided. A state loop-based polling mechanism is employed, ensuring the bus has a chance to be released after each instruction execution. This allows the bus arbiter to respond to other high-priority bus access requests (such as external debugging interface intervention) during polling intervals. While ensuring the accuracy of mixed-signal control timing, this significantly improves the system bus throughput and compatibility with concurrent access from multiple masters.

[0087] The scope of this application is defined by the appended claims rather than the foregoing description, and is therefore intended to encompass all variations falling within the meaning and scope of equivalents of the claims. No reference numerals in the claims should be construed as limiting the scope of the claims. Furthermore, it is clear that the word "comprising" does not exclude other units or steps, and the singular does not exclude the plural. Multiple units or devices recited in a device claim may also be implemented by a single unit or device in software or hardware. Terms such as "first," "second," etc., are used only for distinguishing descriptions and do not indicate any particular order, nor should they be construed as indicating or implying relative importance.

[0088] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily made by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims, and the above embodiments should be regarded as exemplary and non-limiting.

Claims

1. A process control circuit based on hardware logic, characterized in that, The process control circuit is integrated inside the chip and is used to control multiple controlled modules. The control inputs and status outputs of the multiple controlled modules are mapped to registers with independent access addresses. The process control circuit includes: The bus interface connects the multiple controlled modules via signal lines and reads and writes the registers based on independent access addresses to control the multiple controlled modules or obtain the status of the multiple controlled modules. An instruction sequence execution controller, connected to the bus interface, is used to store multiple sets of instruction sequences, each set of instruction sequences corresponding to a status index; the instruction sequence execution controller is used to execute the corresponding instruction sequence according to the input current status index, perform read / write operations or logical operations through the bus interface, and output an execution completion signal and an operation result flag after all instructions in the corresponding instruction sequence have been executed; A process control state machine, connected to the instruction sequence execution controller, is used to output the current state index to the instruction sequence execution controller and receive the execution completion signal and the calculation result flag; The process control state machine is implemented using hardware logic circuits. The hardware logic circuits are used to determine the next state based on the calculation result flag after receiving the execution completion signal. The instruction sequence execution controller is used to execute the instructions in the instruction sequence according to the instruction fetch stage, the execution stage, and the input / output waiting stage; During the input / output waiting phase, the instruction sequence execution controller waits for the bus ready signal from the bus interface and completes the execution of the current instruction upon receiving the bus ready signal. The process control state machine is used to determine the next state as the current state if, after reading the value of the register through the instruction sequence execution controller, the state of the multiple controlled modules does not meet the preset conditions based on the calculation result flag.

2. The hardware logic-based flow control circuit according to claim 1, characterized in that, The instruction sequence execution controller includes a logic operation unit, which is used to perform logical comparison or arithmetic operations on the values ​​read from the register, and convert the operation result into an operation result flag; the operation result flag is a logic state signal that characterizes whether the operation result meets preset conditions.

3. The hardware logic-based flow control circuit according to claim 1, characterized in that, The circuit also includes a breakpoint controller, which is connected to the instruction sequence execution controller and is used to store preset breakpoint instruction indexes. The instruction sequence execution controller further includes a comparator, which is used to compare the index of the current instruction with the index of the breakpoint instruction in real time during execution, and pause instruction execution if they match.

4. The hardware logic-based flow control circuit according to claim 3, characterized in that, The circuit also includes a bus arbiter, which is located on the connection path between the bus interface and the instruction sequence execution controller and the external debugging interface; The bus arbiter is used to receive read / write requests initiated by the instruction sequence execution controller or the external debugging interface.

5. The hardware logic-based flow control circuit according to claim 4, characterized in that, The external debugging interface reuses the chip's serial communication interface, which includes an I2C interface or an SPI interface.

6. The hardware logic-based flow control circuit according to claim 1, characterized in that, The instruction sequence execution controller includes a readable and writable storage unit for storing the instruction sequence; the readable and writable storage unit is mapped to the bus address space and is used to update or rewrite the instruction sequence through the bus interface.

7. A chip, characterized in that, The chip includes: Multiple controlled modules, including analog circuit modules or digital circuit modules, wherein the control inputs and status outputs of the multiple controlled modules are mapped to registers with independent access addresses; The hardware logic-based process control circuit according to any one of claims 1 to 6, wherein the process control circuit is connected to the plurality of controlled modules through an internal bus to control the initialization process or working state of the plurality of controlled modules.

8. A process control method, applied to a hardware logic-based process control circuit as described in any one of claims 1 to 6, characterized in that, The method includes: Execute the corresponding instruction sequence according to the received current state index, read and write the register based on the independent access address, and output the execution completion signal and operation result flag after the corresponding instruction sequence is executed; Output the current state index, and after receiving the execution completion signal, determine the next state through hardware logic circuitry based on the calculation result flag; The steps of executing the corresponding instruction sequence include: The instruction sequence includes an instruction fetch phase, an execution phase, and an input / output wait phase. During the input / output waiting phase, the system waits for the bus ready signal from the bus interface and executes the current instruction upon receiving the bus ready signal. The step of determining the next state based on the calculation result flag via hardware logic circuitry includes: If the state of the multiple controlled modules does not meet the preset conditions based on the calculation result flag, then the next state is determined to be the current state.

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