Display panel, display apparatus, manufacturing method and test method

Abstract

Provided in the present invention are a display panel, a display apparatus, a manufacturing method and a test method. The display panel comprises: a base substrate, provided with a display area and a peripheral area surrounding the display area, the peripheral area comprising a lower frame area; a plurality of pixels, located on one side of the base substrate and located in the display area; a plurality of data lines, located on one side of the base substrate and electrically connected to the plurality of pixels, the plurality of data lines extending from the display area to the lower frame area; at least one switch group, each switch group comprising a plurality of switches, the plurality of switches being respectively connected to the plurality of data lines in on a one-to-one basis, and one switch dividing one data line into two segments and being connected to the two segments; and at least one control line, each control line being connected to each switch in one switch group and being used for transmitting to each switch in the corresponding switch group a control signal for controlling on-off of the switch. The present invention can effectively and quickly locate areas where line defects occur, thus significantly improving the efficiency and accuracy of line defect analysis.

Description

Display panel, display device, manufacturing method and testing method

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202410354020.2 filed in China on March 26, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to the field of display technology, and in particular to a display panel, a display device, a manufacturing method, and a testing method. Background Art

[0004] With the rapid development of the AMOLED (Active-matrix organic light-emitting diode) display industry, improving the yield of AMOLED display panels has become one of the biggest obstacles to this growth. Linear defects in AMOLED display panels are the most persistent problem in defect improvement. Currently, line defect analysis relies solely on equipment error analysis, such as AOI (Automated Optical Inspection) defect matching, and FIB (Focused Ion Beam) sectioning, to pinpoint the defect location. However, existing line defect analysis methods are time-consuming and labor-intensive, and are unable to quickly and effectively pinpoint the defect's location. Summary of the Invention

[0005] Embodiments of the present invention provide a display panel, a display device, a manufacturing method, and a testing method for solving the problem that existing testing solutions cannot quickly and effectively locate the location where a line defect occurs in a display panel.

[0006] In order to solve the above-mentioned technical problems, the present invention is achieved as follows:

[0007] In a first aspect, an embodiment of the present invention provides a display panel, including:

[0008] A base substrate having a display area and a peripheral area surrounding the display area, wherein the peripheral area includes a lower frame area;

[0009] A plurality of pixels are located on one side of the base substrate and in the display area;

[0010] a plurality of data lines, located on the one side of the base substrate and electrically connected to the plurality of pixels, the plurality of data lines being configured to provide data signals to the plurality of pixels, the plurality of data lines extending from the display area to the lower frame area;

[0011] at least one switch group, each of the switch groups comprising a plurality of switches, the plurality of switches being connected to the plurality of data lines in a one-to-one correspondence, one of the switches dividing one of the data lines into two segments and being connected to the two segments;

[0012] At least one control line, each of the control lines is connected to each switch in one of the switch groups, and is used to transmit a control signal for controlling the on / off of the switch to each switch in the corresponding switch group.

[0013] Optionally, the switch comprises: an active layer, a gate located on a side of the active layer away from the substrate, and a source and a drain located on a side of the gate away from the substrate;

[0014] The two segments of the data line include a first data line segment and a second data line segment. The switch is located between the first data line segment and the second data line segment. The source is connected to the first data line segment, the drain is connected to the second data line segment, and the gate is connected to the control line.

[0015] Optionally, the multiple switches in each switch group are arranged along a first direction, and the first direction intersects with an extending direction of the data line.

[0016] Optionally, the at least one switch group includes a plurality of switch groups, and the plurality of switch groups are arranged in sequence along an extension direction of the data line.

[0017] Optionally, at least one switch group among the plurality of switch groups is located in the display area.

[0018] Optionally, the display area further includes a camera hole area, at least one of the multiple switch groups is located above the camera hole area, and / or at least one of the multiple switch groups is located below the camera hole area.

[0019] Optionally, the multiple switches of each switch group are located between the multiple pixels.

[0020] Optionally, the lower frame area includes a binding area and a test terminal area, the binding area is located between the display area and the test terminal area, and at least one switch group among the plurality of switch groups is located in the test terminal area.

[0021] Optionally, a plurality of control terminals are further included, and the plurality of control lines are connected to the plurality of control terminals in a one-to-one correspondence.

[0022] Optionally, the plurality of control terminals include a first group of control terminals and a second group of control terminals, which are respectively located in the peripheral areas on opposite sides of the display area.

[0023] Optionally, a plurality of gate lines are further included, wherein the gate lines are electrically connected to the plurality of pixels and are configured to transmit gate signals to the plurality of pixels, and the gate lines and the control lines are provided in the same layer and the same material.

[0024] In a second aspect, an embodiment of the present invention provides a display device, comprising the display panel described in the first aspect.

[0025] In a third aspect, an embodiment of the present invention provides a method for manufacturing a display panel, comprising:

[0026] Providing a base substrate, the base substrate having a display area and a peripheral area surrounding the display area, the peripheral area including a lower frame area;

[0027] forming a plurality of pixels, a plurality of data lines, at least one switch group, and at least one control line on the base substrate;

[0028] Wherein, the plurality of pixels are located in the display area;

[0029] The data lines are electrically connected to the plurality of pixels, the data lines are configured to provide data signals to the plurality of pixels, and the data lines extend from the display area to the lower frame area;

[0030] Each of the switch groups includes a plurality of switches, and the plurality of switches are connected to the plurality of data lines in a one-to-one correspondence; one of the switches divides one of the data lines into two segments and is connected to the two segments;

[0031] Each of the control lines is connected to each switch in one of the switch groups, and is used to transmit a control signal for controlling the on / off of the switch to each switch in the corresponding switch group.

[0032] Optionally, it also includes:

[0033] A plurality of gate lines are formed on the base substrate. The gate lines are electrically connected to the plurality of pixels and are configured to transmit gate signals to the plurality of pixels. The gate lines and the control lines are formed through a single patterning process.

[0034] In a fourth aspect, an embodiment of the present invention provides a display panel testing method for testing the display panel described in the first aspect. The testing method includes:

[0035] detecting the display panel, wherein when detecting the display panel, a control signal for controlling the switch to be turned on is input through the control line;

[0036] In the case where the display panel has at least one dark line passing through it, the switches in the at least one switch group are controlled to be cut off in sequence in the direction from the display area to the lower frame area. After each switch group is cut off, the area where the defective point is located is determined based on whether the dark line disappears.

[0037] In an embodiment of the present invention, by providing at least one switch group connected to the data line, the data line can be divided into multiple segments for control, so that the line defect occurrence area can be effectively and quickly locked, greatly improving the efficiency and accuracy of line defect analysis. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present invention. The same reference symbols are used throughout the drawings to represent the same components. In the drawings:

[0039] FIG1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

[0040] FIG2 is a second structural diagram of a display panel according to an embodiment of the present invention;

[0041] FIG3 is a third structural diagram of a display panel according to an embodiment of the present invention;

[0042] FIG4 is a fourth structural diagram of a display panel according to an embodiment of the present invention;

[0043] 5 is a timing diagram of control signals of a display panel according to an embodiment of the present invention;

[0044] FIG6 is a fifth structural diagram of a display panel according to an embodiment of the present invention;

[0045] FIG7 is a sixth structural diagram of a display panel according to an embodiment of the present invention;

[0046] FIG8 is a schematic flow chart of a method for manufacturing a display panel according to an embodiment of the present invention;

[0047] FIG9 is a schematic diagram of a flow chart of a display panel testing method according to an embodiment of the present invention;

[0048] FIG. 10 is a second flow chart of a method for testing a display panel according to an embodiment of the present invention. DETAILED DESCRIPTION

[0049] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0050] Referring to FIG. 1 , an embodiment of the present invention provides a display panel, including:

[0051] The base substrate 10 includes a display area 10a and a peripheral area surrounding the display area 10a, the peripheral area including a lower frame area 10b. In this embodiment of the present invention, the base substrate can be a flexible substrate or a rigid substrate, such as a glass substrate. The display area 10a is used to set pixels (such as RGB) and pixel driver circuits, while the peripheral area 10b is used to bind driver chips.

[0052] A plurality of pixels P are located on one side of the base substrate 10 and in the display area 10a;

[0053] a plurality of data lines 11 disposed on the one side of the base substrate 10 and electrically connected to the plurality of pixels, the plurality of data lines 11 being configured to provide data signals (Data) to the plurality of pixels, the plurality of data lines 11 extending from the display area 10 a to the lower frame area 10 b;

[0054] At least one switch group 12, each switch group 12 comprising a plurality of switches 12a, each of the plurality of switches 12a being connected to the plurality of data lines 11 in a one-to-one correspondence, and each switch 12a dividing one data line 11 into two segments and connecting the two segments;

[0055] At least one control line 13 , each of which is connected to each switch 12 a in one of the switch groups 12 , and is used to transmit a control signal to each switch 12 a in the corresponding switch group 12 for controlling the on / off of the switch 12 a .

[0056] In an embodiment of the present invention, by providing at least one switch group connected to the data line, the data line can be divided into multiple segments for control, so that the line defect occurrence area can be effectively and quickly locked, greatly improving the efficiency and accuracy of line defect analysis.

[0057] In an embodiment of the present invention, the multiple switches 12a in each switch group 12 are optionally arranged along a first direction, which intersects the extension direction of the data line 11. For example, the first direction may be perpendicular to the extension direction of the data line 11. As shown in FIG1 , the data line extends in a vertical direction, while the multiple switches 12a in the switch group 12 are arranged in a horizontal direction. This arrangement can minimize the space occupied by the switches 12a.

[0058] In an embodiment of the present invention, the at least one switch group 12 optionally includes a plurality of switch groups 12, and the plurality of switch groups 12 are sequentially arranged along the extension direction of the data line. As shown in FIG1 , the display panel includes three switch groups 12. Of course, in other embodiments of the present invention, the number of switch groups 12 may be one, two, or more than three, and the present invention is not limited thereto. Of course, the greater the number of switch groups 12, the more segments the data line 12 is divided into, and the more accurate the detection of defective areas.

[0059] In the embodiment of the present invention, optionally, at least one switch group 12 among the plurality of switch groups 12 is located in the display area 10 a , so that a defect occurrence area of ​​the display area 10 a can be detected.

[0060] Please also refer to Figure 3. In an embodiment of the present invention, the display area 10a optionally also includes a camera hole area (also referred to as a hole area). At least one of the multiple switch groups 12 is located above the camera hole area, and / or at least one of the multiple switch groups 12 is located below the camera hole area. In the embodiment shown in Figure 3, a switch group 12 is provided above and below the camera hole area. Because the camera hole area requires a hole, there is a greater possibility of data line failure, so the switch group 12 is provided in the camera hole area. Ga, Gb, and Gc in Figure 3 represent control terminals, and Gate (a), Gate (b), and Gate (c) represent control lines. The control terminals are connected to the control lines. It should be noted that different control lines can be arranged with cross-insulation (as shown in Figure 3) or without cross-insulation (as shown in Figure 2). The lower pad area is the lower frame area, and the AA area is the display area. As can be seen in Figure 3, the three switch groups 12 divide the display area into three areas: Area 1, Area 2, and Area 3.

[0061] In the embodiment of the present invention, optionally, the multiple switches 12 a of each switch group 12 are located between the multiple pixels P, for example, between two adjacent rows of pixels P.

[0062] In the embodiment of the present invention, optionally, at least one of the plurality of switch groups 12 is located in the lower frame area 10 b , so as to be able to detect a defect occurrence area in the peripheral area 10 b .

[0063] Referring to FIG. 1 and FIG. 2 , in an embodiment of the present invention, the peripheral area 10b optionally includes a bonding area 10b1 and a test terminal area 10b2. The bonding area 10b1 is located between the display area 10a and the test terminal area 10b2, and at least one of the plurality of switch groups 12 is located in the test terminal area 10b2. The bonding area 10b1 is used to provide bonding terminals (pads), etc., to achieve bonding with an external driver chip. In some embodiments, the bonding area 10b1 may include a bending area, a wiring area, and an electrostatic discharge (ESD) area. The test terminal area 10b2 is used to provide test terminals (the portion enclosed by the dashed box in FIG. 1 is a test terminal), such as an ET switch (ET SW), an AT MUX, an AT ESD, and other test terminals. The ET SW is a switch that controls the writing of pixel data voltages when the EAC is turned on. The AT MUX and AT ESD refer to test control and protection circuits used for testing AT equipment within the factory. A switch group 12 is provided in the test terminal area 10b2 to detect whether the defective area of ​​the data line is in the test terminal area 10b2 or the binding area 10b1. A control line 13 is connected to the control terminal, which can be located in the test terminal area 10b2 and is used to input a control signal to the control line 13.

[0064] In the embodiment of the present invention, optionally, the display panel further includes a plurality of control terminals, and the plurality of control lines 13 are connected to the plurality of control terminals in a one-to-one correspondence.

[0065] In the embodiment of the present invention, optionally, referring to FIG. 2 , the plurality of control terminals include a first group of control terminals C1 and a second group of control terminals C2 , which are respectively located in the peripheral areas on opposite sides of the display area.

[0066] Please refer to Figure 4 at the same time. In an embodiment of the present invention, optionally, the display panel further includes a plurality of gate lines 14 (such as Gate (N-2), Gate (N-1), Gate (N), etc. in Figure 4). The gate lines 14 are electrically connected to the plurality of pixels and are configured to transmit gate signals to the plurality of pixels. The gate lines 14 and the control lines 13 are provided in the same layer and material to reduce manufacturing costs. Further optionally, the portion of the gate lines 14 within the display area 10a is parallel to the portion of the control lines 13 within the display area 10a.

[0067] Please refer to Figure 5. In an embodiment of the present invention, when detecting the display panel, a low-level signal (VGL) can be input to the control line 13 (Gate (a), Gate (b) and Gate (c)) to control the switch 12a connected to the control line 13 to be turned on (for example, the switch is a low-temperature polysilicon thin film transistor), so that the data line 11 can normally input the data signal and the entire data line 11 is turned on. When dark lines X (one or more dark lines) appear on the display panel, it is necessary to detect whether the data lines in certain areas are defective, such as detecting whether the data lines above the hole area in Figure 7 are defective. Since the data signal of the data line is input from the ET Switch in the lower frame area, the switch groups can be cut off in sequence from top to bottom to find the defective location. For example, a high-level signal (VGH) can be first input to Gate (a) to cut off the switches in the switch group above the hole area (the first switch group controlled by Gate (a)). If the dark lines X disappear after cutting, it means that the defective location is above the hole area (above the first switch group). If the dark lines X do not disappear after cutting, it means that the defective location is below the hole area (below the first switch group). If the defective location is below the hole area, a high-level signal (VGH) is input to Gate (b) to disconnect the switches in the second switch group controlled by Gate (b). If the X dark line disappears after disconnection, the defective location is between the second switch group controlled by Gate (b) and the first switch group controlled by Gate (a). If the X dark line does not disappear after disconnection, the defective location is below the second switch group controlled by Gate (b). If the defective location is below the second switch group controlled by Gate (b), a high-level signal (VGH) is input to Gate (c) to disconnect the switches in the third switch group controlled by Gate (c). If the X dark line disappears after disconnection, the defective location is between the third switch group controlled by Gate (c) and the second switch group controlled by Gate (b). If the X dark line does not disappear after disconnection, the defective location is below the third switch group controlled by Gate (c).

[0068] Of course, in some embodiments, depending on the type of the switch 12a, inputting a high level signal to the control line 13 can also control the switch 12a connected to the control line 13 to be turned on (eg, the switch is an oxide thin film transistor).

[0069] In the embodiment of the present invention, optionally, the switch includes: an active layer, a gate located on a side of the active layer away from the base substrate 10 , and a source and a drain located on a side of the gate away from the base substrate 10 ;

[0070] Referring to Figure 6 , the two segments of the data line 11 include a first data line segment 11a and a second data line segment 11b. The switch 12a is located between the first data line segment 11a and the second data line segment 11b. The drain 12a4 of the switch 12a is connected to the first data line segment 11a, the source 12a3 of the switch 12a is connected to the second data line segment 11b, and the gate 12a1 of the switch 12a is connected to the control line 13. If only one switch 12a is provided on a data line 11, the switch 12a divides the data line 11 into two segments. If multiple switches 12a are provided on the data line 11, the multiple switches 12a divide the data line 11 into more segments, for example, into a first data segment, a second data segment, a third data segment, and a fourth data segment.

[0071] Please refer to Figures 6 and 7. The switch in the embodiment of the present invention can be a thin film transistor (TFT) switch, including a gate 12a1, an active layer 12a2, a source 12a3 and a drain 12a4, wherein the gate 12a1 is connected to the corresponding control line 13, and the source 12a3 and the drain 12a4 are respectively connected to the same data line. Optionally, the gate 12a1 is provided with the same layer and material as the gate line 14 and the control line 13 to reduce manufacturing costs. Optionally, the source 12a3 and the drain 12a4 are provided with the same layer and material as the data line 11 to reduce manufacturing costs. In Figures 6 and 7, Gate (a), Gate (b) and Gate (c) are control lines 13. The test pad in Figure 6 is a test pad connected to the data line for inputting data signals to the data line.

[0072] Please refer to Figures 2, 4 and 7. In an embodiment of the present invention, optionally, the multiple pixels may include R, G, and B pixels, which may be OLED light-emitting devices, for example. Each of the pixels is connected to a data line 11 for displaying under the drive of a data signal transmitted by the data line 11.

[0073] An embodiment of the present invention further provides a display device, comprising the display panel as described above. The display device may be, for example, a mobile phone, a tablet computer, a personal computer, a television, or the like.

[0074] Referring to FIG. 8 , an embodiment of the present invention further provides a method for manufacturing a display panel, including:

[0075] Step S11: providing a base substrate, wherein the base substrate has a display area and a peripheral area surrounding the display area, wherein the peripheral area includes a lower frame area;

[0076] Step S12: forming a plurality of pixels, a plurality of data lines, at least one switch group and at least one control line on the base substrate;

[0077] Wherein, the plurality of pixels are located in the display area;

[0078] The data lines are electrically connected to the plurality of pixels, the data lines are configured to provide data signals to the plurality of pixels, and the data lines extend from the display area to the lower frame area;

[0079] Each of the switch groups includes a plurality of switches, and the plurality of switches are connected to the plurality of data lines in a one-to-one correspondence; one of the switches divides one of the data lines into two segments and is connected to the two segments;

[0080] Each of the control lines is connected to each switch in one of the switch groups, and is used to transmit a control signal for controlling the on / off of the switch to each switch in the corresponding switch group.

[0081] In an embodiment of the present invention, optionally, the manufacturing method further includes:

[0082] A plurality of gate lines are formed on the base substrate. The gate lines are electrically connected to the plurality of pixels and are configured to transmit gate signals to the plurality of pixels. The gate lines and the control lines are formed through a single patterning process, thereby saving manufacturing costs.

[0083] In an embodiment of the present invention, the switch may optionally be a thin film transistor (TFT) switch, comprising a gate, an active layer, a source electrode, and a drain electrode, wherein the gate electrode is connected to a corresponding control line, and the source electrode and the drain electrode are respectively connected to the same data line. Optionally, the gate electrode, the gate line, and the control line are formed through a single patterning process to reduce manufacturing costs. Optionally, the source electrode, the drain electrode, and the data line are formed through a single patterning process to reduce manufacturing costs.

[0084] The following describes the method for manufacturing a display panel according to an embodiment of the present invention with reference to specific embodiments.

[0085] In one embodiment, a method for manufacturing a display panel includes:

[0086] Step 1: First, a flexible substrate layer (Flexible layer) and a buffer layer (Buffer layer) are formed on a glass substrate;

[0087] Step 2: depositing an active layer on the buffer layer, wherein the active layer is formed of, for example, polysilicon;

[0088] Step 3: Doping the active layer (Vth-doping) to change its electrical characteristics Vth;

[0089] Step 4: Obtaining an active layer (ACT layer) pattern through processes such as coating, developing, etching, and cleaning. The active layer pattern may include the active layer pattern of the switch in the switch group described in the above embodiment;

[0090] Step 5: depositing a gate insulating layer (GI1 layer) on the formed active layer pattern to completely cover the active layer pattern;

[0091] Step 6: A gate metal layer is plated on the gate insulating layer, and a gate metal layer pattern is obtained through processes such as coating, developing, etching, and cleaning. The gate metal layer pattern may include gate patterns of switches in the switch group described in the above embodiment, patterns of control lines described in the above embodiment, and patterns of gate lines, etc.

[0092] Step 7: After forming the gate metal layer pattern, a doping (P-Doping) process is performed using the gate metal layer pattern as a mask to change the electrical properties of the active layer outside the active layer covered by the gate metal layer pattern, thereby reducing its resistance and forming a conductive circuit;

[0093] In some embodiments, a gate insulating layer (GI2 layer) and a gate metal layer (Gate Metal2 layer) may be further formed. The formation method is similar to steps 5 and 6 above.

[0094] Step 8: An interlayer dielectric layer (ILD layer) is plated on the gate metal layer pattern. After processes such as coating, developing, etching, and cleaning, a hole pattern is obtained to connect the subsequently formed source and drain metal layer (SD) with the gate metal layer and the active layer.

[0095] Step 9: A source / drain metal layer (SD) is plated on the interlayer dielectric layer. After processes such as coating, developing, etching, and cleaning, a source / drain metal layer pattern is obtained. The source / drain metal layer pattern may include the source and drain patterns of the switches in the switch group described in the above embodiment, the data line pattern described in the above embodiment, etc.

[0096] Subsequently, a planarization layer (PLN), an anode layer, a pixel definition layer (PDL), a spacer (PS), a light-emitting layer, a cathode layer, and an encapsulation layer may be formed to ultimately form a display panel.

[0097] An embodiment of the present invention further provides a display panel testing method for testing the display panel described in any of the above embodiments. Referring to FIG. 9 , the testing method includes:

[0098] Step S21: detecting the display panel, wherein when detecting the display panel, a control signal for controlling the switch to be turned on is input through the control line;

[0099] Step S22: When the display panel has at least one dark line passing through it, the switches in the at least one switch group are controlled to be cut off in sequence in the direction from the display area to the lower frame area. After each switch group is cut off, the area where the defective point is located is determined based on whether the dark line disappears.

[0100] Referring to Figure 10 , taking the display panel in Figure 3 as an example, during display panel testing, a low-level signal (VGL) can be input to control line 13 (Gate(a), Gate(b), and Gate(c)) to control the switches connected to control line 13 to conduct, thereby allowing data line 11 to normally receive data signals and turning on the entire data line 11. If a dark line (X) appears on the display panel, a high-level signal (VGH) is first input to Gate(a) to disconnect the data line above the aperture area (region 1). Since the data signal in the data line is provided by the ET switch in the lower frame area of ​​the display panel, if the dark line (X) below region 1 disappears after disconnection, while regions 2 and 3 can display normally (region 1 cannot display due to the lack of a data signal), then the defective area is in region 1. If the dark line (X) does not disappear after switching, then the defective area is below region 1. If the defective location is below region 1, input a high-level signal (VGH) to Gate (b) to cut off the data line in region 2. If the X dark line below region 2 disappears after cutting, and region 3 can display normally (at this time, regions 1 and 2 cannot display due to the lack of data signal), the defective location is in region 2. If the X dark line does not disappear after switching, the defective location is below region 2. If the defective location is below region 2, input a high-level signal (VGH) to Gate (c) to cut off the data line in region 3. If the X dark line disappears after cutting, the defective location is in region 3. If the X dark line does not disappear after switching, the defective location is below region 3.

[0101] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0102] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are protected by the present invention.

Claims

1. A display panel, characterized in that: include: A base substrate having a display area and a peripheral area surrounding the display area, wherein the peripheral area includes a lower frame area; A plurality of pixels are located on one side of the base substrate and in the display area; a plurality of data lines, located on the one side of the base substrate and electrically connected to the plurality of pixels, the plurality of data lines being configured to provide data signals to the plurality of pixels, the plurality of data lines extending from the display area to the lower frame area; at least one switch group, each of the switch groups comprising a plurality of switches, the plurality of switches being connected to the plurality of data lines in a one-to-one correspondence, one of the switches dividing one of the data lines into two segments and being connected to the two segments; At least one control line, each of the control lines is connected to each switch in one of the switch groups, and is used to transmit a control signal for controlling the on / off of the switch to each switch in the corresponding switch group.

2. The display panel according to claim 1, wherein: The switch comprises: an active layer, a gate located on a side of the active layer away from the substrate, and a source and a drain located on a side of the gate away from the substrate; The two segments of the data line include a first data line segment and a second data line segment. The switch is located between the first data line segment and the second data line segment. The source is connected to the first data line segment, the drain is connected to the second data line segment, and the gate is connected to the control line.

3. The display panel according to claim 1, wherein: The multiple switches in each of the switch groups are arranged along a first direction, and the first direction intersects with an extending direction of the data lines.

4. The display panel according to claim 1, wherein: The at least one switch group includes a plurality of switch groups, and the plurality of switch groups are sequentially arranged along an extending direction of the data line.

5. The display panel according to claim 4, wherein: At least one switch group among the plurality of switch groups is located in the display area.

6. The display panel according to claim 5, wherein: The display area also includes a camera hole area, at least one switch group among the multiple switch groups is located above the camera hole area, and / or at least one switch group among the multiple switch groups is located below the camera hole area.

7. The display panel according to claim 5 or 6, characterized in that: The multiple switches of each switch group are located between the multiple pixels.

8. The display panel according to claim 5 or 6, characterized in that: The lower frame area includes a binding area and a test terminal area, the binding area is located between the display area and the test terminal area, and at least one switch group among the plurality of switch groups is located in the test terminal area.

9. The display panel according to claim 8, wherein: It also includes a plurality of control terminals, and a plurality of control lines are connected to the plurality of control terminals in a one-to-one correspondence.

10. The display panel according to claim 9, wherein: The plurality of control terminals include a first group of control terminals and a second group of control terminals, which are respectively located in the peripheral areas on opposite sides of the display area.

11. The display panel according to claim 1, wherein It also includes a plurality of gate lines, which are electrically connected to the plurality of pixels and configured to transmit gate signals to the plurality of pixels. The gate lines and the control lines are provided in the same layer and material.

12. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 11.

13. A method for manufacturing a display panel, characterized in that: include: Providing a base substrate, the base substrate having a display area and a peripheral area surrounding the display area, the peripheral area including a lower frame area; forming a plurality of pixels, a plurality of data lines, at least one switch group, and at least one control line on the base substrate; Wherein, the plurality of pixels are located in the display area; The data lines are electrically connected to the plurality of pixels, the data lines are configured to provide data signals to the plurality of pixels, and the data lines extend from the display area to the lower frame area; Each of the switch groups includes a plurality of switches, and the plurality of switches are connected to the plurality of data lines in a one-to-one correspondence; one of the switches divides one of the data lines into two segments and is connected to the two segments; Each of the control lines is connected to each switch in one of the switch groups, and is used to transmit a control signal for controlling the on / off of the switch to each switch in the corresponding switch group.

14. The method for manufacturing a display panel according to claim 13, wherein: Also includes: A plurality of gate lines are formed on the base substrate. The gate lines are electrically connected to the plurality of pixels and are configured to transmit gate signals to the plurality of pixels. The gate lines and the control lines are formed through a single patterning process.

15. A method for testing a display panel, characterized in that: Used for testing the display panel according to any one of claims 1 to 11, the testing method comprising: detecting the display panel, wherein when detecting the display panel, a control signal for controlling the switch to be turned on is input through the control line; In the case where the display panel has at least one dark line passing through it, the switches in the at least one switch group are controlled to be cut off in sequence in the direction from the display area to the lower frame area. After each switch group is cut off, the area where the defective point is located is determined based on whether the dark line disappears.

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