Communication method and communication apparatus

Abstract

The present application provides a communication method and a communication apparatus. The method comprises: a network device sends a synchronization signal block, the synchronization signal block comprising a first synchronization signal and a second synchronization signal, and the first synchronization signal indicating the frequency domain positions of the second synchronization signal and a third synchronization signal; and at the frequency domain position, the network device sends the third synchronization signal, the second synchronization signal and the third synchronization signal indicating physical cell identifiers (PCI) of cells to be accessed. According to the method, by means of introducing the third synchronization signal, a downlink synchronization signal is enabled to indicate more cell PCIs while ensuring low latency.

Description

Communication method and communication device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on March 29, 2024, with application number 202410391258.2 and invention name “A Communication Method and Communication Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of communications, and more particularly, to a communication method and a communication device. Background Art

[0003] The fifth generation new radio (5G NR) communication system introduces the concepts of synchronization signal and PBCH block (SSB). SSB consists of primary synchronization signal (PSS), secondary synchronization signal (SSS) and physical broadcast channel (PBCH). PSS and SSS can be used to enable the terminal device to determine the physical cell identifier (PCI) of the cell to be accessed during downlink synchronization.

[0004] Each 5G NR cell corresponds to a PCI, which is used to distinguish cells on the radio side. Due to the potential increase in communication frequencies and increased path loss in the future, large cities with high user density will require the deployment of a large number of small base stations, so deployment flexibility must be guaranteed. PCI planning to avoid PCI confusion and avoid it can be a critical issue in actual deployment and operation (including dense urban deployments). In most wireless networks worldwide, network quality issues caused by PCI conflicts, confusion, and MOD3 interference, often occur due to inadequate PCI design and optimization.

[0005] Therefore, the number of cell IDs will further increase in the future to facilitate PCI planning. Therefore, how to carry more PCIs in the synchronization signal while ensuring latency is an urgent problem to be solved in this field. Summary of the Invention

[0006] The embodiments of the present application provide a communication method and a communication device, which can carry more PCIs in a synchronization signal while ensuring the delay.

[0007] In a first aspect, a communication method is provided, which includes: a network device sends a synchronization signal block, the synchronization signal block includes a first synchronization signal and a second synchronization signal, the first synchronization signal indicates the frequency domain position of the second synchronization signal and the third synchronization signal; at the frequency domain position, the network device sends a third synchronization signal, the second synchronization signal and the third synchronization signal indicate the physical cell identifier PCI of the cell to be accessed.

[0008] In an embodiment of the present application, a third synchronization signal is introduced into the downlink synchronization signal to carry the cell ID, and the third synchronization signal does not need to indicate the frequency domain position. Since the synchronization signal indicating the frequency domain position needs to perform frequency point search and frequency correction and other operations during detection, its detection complexity is the highest and the detection time is the longest. Therefore, under the same delay, the third synchronization signal can carry more cell IDs than the first synchronization signal, and thus the downlink synchronization signal can indicate more cell PCIs while ensuring the delay.

[0009] In combination with the first aspect, in certain implementations of the first aspect, the second synchronization signal and the third synchronization signal indicate the physical cell identifier PCI of the cell to be accessed, including: the first synchronization signal, the second synchronization signal and the third synchronization signal indicate the physical cell identifier PCI of the cell to be accessed.

[0010] In combination with the first aspect, in certain implementations of the first aspect, the second synchronization signal and the third synchronization signal can indicate the PCIs of N cells, the PCI of the cell to be accessed belongs to the PCIs of N cells, and N is greater than 1008.

[0011] In combination with the first aspect, in certain implementations of the first aspect, the second synchronization signal and the third synchronization signal can indicate the PCIs of N cells, including: the first synchronization signal, the second synchronization signal, and the third synchronization signal can indicate the PCIs of N cells.

[0012] In an embodiment of the present application, the PCI of a cell can be jointly indicated by the first synchronization signal, the second synchronization signal and the third synchronization signal. Since the third synchronization signal is introduced into the downlink synchronization signal to carry the cell ID, adding the third synchronization signal to the downlink synchronization signal to carry the cell ID can indicate more cell PCIs.

[0013] In combination with the first aspect, in some implementations of the first aspect, the first synchronization signal is a primary synchronization signal PSS and / or the second synchronization signal is a secondary synchronization signal SSS.

[0014] In combination with the first aspect, in certain implementations of the first aspect, the third synchronization signal is adjacent to the synchronization signal block in the time domain.

[0015] In an embodiment of the present application, since the third synchronization signal is adjacent to the synchronization signal block in the time domain, the terminal device can more conveniently determine the time domain position of the third synchronization signal when detecting the third synchronization signal, and then the terminal device can obtain the content of the third synchronization signal with lower latency. Therefore, the third synchronization signal is adjacent to the synchronization signal block in the time domain, which increases the efficiency of the downlink synchronization process.

[0016] In combination with the first aspect, in certain implementations of the first aspect, the first synchronization signal indicates a first parameter, the second synchronization signal indicates a second parameter, and the third synchronization signal indicates a third parameter. The first parameter, the second parameter, and the third parameter are used to determine the PCI of the cell to be accessed.

[0017] In combination with the first aspect, in certain implementations of the first aspect, the first parameter belongs to a first parameter set, the second parameter belongs to a second parameter set, and the third parameter belongs to a third parameter set. The first parameter, the second parameter, and the third parameter are used to determine the PCI of the cell to be accessed, including: the first parameter, the second parameter, and the third parameter are used to determine the PCI of the cell to be accessed together with the first value and the second value, wherein the first value and the second value correspond to the number of elements in the two parameter sets in the first parameter set, the second parameter set, and the third parameter set, respectively.

[0018] In conjunction with the first aspect, in some implementations of the first aspect, the value of PCI satisfies Where (m,n,k)∈{0,1,2} 3 And the values ​​of m, n, and k are all different; is the kth parameter, s k is the number of elements in the kth parameter set, is the mth parameter, s m is the number of elements in the mth parameter set, is the nth parameter, s n The number of elements in the nth parameter set.

[0019] It is understandable that under the above PCI determination method, any PCI value can determine a unique Ensure that there is no confusion in the mapping of PCI to sequence selection.

[0020] In an embodiment of the present application, by introducing a third synchronization signal, the downlink synchronization signal can adopt a three-level synchronization architecture, that is, the value of PCI can be jointly determined by three parameters corresponding to the first synchronization signal, the second synchronization signal and the third synchronization signal. Compared with the two-level synchronization architecture, the downlink synchronization signal adopts a three-level synchronization architecture to indicate more cell PCIs.

[0021] In combination with the first aspect, in some implementations of the first aspect, the number of elements in the first parameter set is less than 3.

[0022] In an embodiment of the present application, the first parameter set corresponds to the number of cell IDs carried by the first synchronization signal, and the first synchronization signal is used to determine the frequency domain position, which makes the detection complexity of the first synchronization signal high and the detection time-consuming; therefore, the number of elements in the first parameter set is less than 3, which can reduce the number of sequences to be detected in the first synchronization signal, thereby reducing the overall delay of the downlink synchronization; in addition, when detecting the first synchronization signal, there is no timing prior information, and the second synchronization signal / third synchronization signal may be misdetected as the first synchronization signal, resulting in downlink synchronization failure. Therefore, in order to ensure the accuracy of synchronization in the downlink synchronization signal, the first synchronization signal needs to maintain low cross-correlation with the second and third synchronization signals. When the number of elements in the first parameter set is less than 3, that is, the possible sequence types of the first synchronization signal are less than 3, the second and third synchronization signals only need to maintain low cross-correlation with fewer first synchronization signal sequences, thereby increasing the sequence cross-correlation optimization space of the second and third synchronization signals.

[0023] In combination with the first aspect, in certain implementations of the first aspect, the number of elements in the second parameter set is less than the number of elements in the third parameter set, and the second synchronization signal also indicates index information, which includes subframe index information and / or beam index information of the synchronization signal block.

[0024] In an embodiment of the present application, the second synchronization signal carries fewer cell IDs, so the downlink synchronization signal can indicate index information through the second synchronization signal, thereby reducing the amount of system information carried in the PBCH, so that the PBCH can be transmitted at a lower code rate, thereby improving the demodulation performance of the PBCH.

[0025] In combination with the first aspect, in certain implementations of the first aspect, the third synchronization signal is encoded using a Z4 sequence scrambled by an m-sequence.

[0026] In an embodiment of the present application, the third synchronization signal carrying more cell IDs is encoded using a Z4 sequence. Since the Z4 sequence can ensure low cross-correlation between sequences in the synchronization signal, using the Z4 sequence to encode the third synchronization signal can reduce the error detection rate of the downlink synchronization signal; in addition, since the m sequence has a low-complexity detection algorithm, the network device uses the m sequence to scramble the third synchronization signal encoded using the Z4 sequence, which can reduce the detection complexity of the third synchronization signal.

[0027] In combination with the first aspect, in some implementations of the first aspect, the number of elements in the first parameter set is 1, the second parameter set is {0, 1, 2, ..., L}, and the m-sequence used by the third synchronization signal corresponds to the first cyclic shift parameter m1, and m1 satisfies: The Z4 sequence used by the third synchronization signal corresponds to the second cyclic shift parameter m2, and m2 satisfies: γ is a positive integer, L is a positive integer, and α is a positive integer less than or equal to the length of the third synchronization sequence.

[0028] It should be understood that, in the above cyclic shift parameters, the cyclic shift number of the m sequence is greater than the cyclic shift number of the Z4 sequence, which can reduce the detection degree to the greatest extent.

[0029] In combination with the first aspect, in some implementations of the first aspect, γ is greater than 1.

[0030] In the embodiment of the present application, γ being greater than 1 can increase the interval between adjacent cyclic shifts in the sequence of the third synchronization signal, thereby improving the frequency offset resistance of the third synchronization signal.

[0031] In combination with the first aspect, in certain implementations of the first aspect, the second synchronization signal adopts any one of the following encoding methods: m-sequence, gold sequence, Z4 sequence, and Z4 sequence scrambled by m-sequence.

[0032] In a second aspect, a communication method is provided, which includes: a terminal device receives a synchronization signal block, the synchronization signal block includes a first synchronization signal and a second synchronization signal, the first synchronization signal indicates the frequency domain position of the second synchronization signal and the third synchronization signal; at the frequency domain position, the terminal device receives the third synchronization signal, the second synchronization signal and the third synchronization signal indicate the physical cell identifier PCI of the cell to be accessed.

[0033] In combination with the second aspect, in certain implementations of the second aspect, the second synchronization signal and the third synchronization signal can indicate the PCIs of N cells, the PCI of the cell to be accessed belongs to the PCIs of N cells, and N is greater than 1008.

[0034] In combination with the second aspect, in some implementations of the second aspect, the first synchronization signal is a primary synchronization signal PSS and / or the second synchronization signal is a secondary synchronization signal SSS.

[0035] In combination with the second aspect, in certain implementations of the second aspect, the third synchronization signal is adjacent to the synchronization signal block in the time domain.

[0036] In combination with the second aspect, in certain implementations of the second aspect, the first synchronization signal indicates a first parameter, the second synchronization signal indicates a second parameter, and the third synchronization signal indicates a third parameter. The method also includes: determining the PCI of the cell to be accessed based on the first parameter, the second parameter, and the third parameter.

[0037] In combination with the second aspect, in certain implementations of the second aspect, the PCI of the cell to be accessed is determined based on the first parameter, the second parameter, and the third parameter, including: the terminal device determines the PCI of the cell to be accessed based on the first parameter, the second parameter, the third parameter, the first value, and the second value, wherein the first parameter belongs to the first parameter set, the second parameter belongs to the second parameter set, the third parameter belongs to the third parameter set, and the first value and the second value respectively correspond to the number of elements in two parameter sets in the first parameter set, the second parameter set, and the third parameter set.

[0038] In conjunction with the second aspect, in some implementations of the second aspect, the value of PCI satisfies Where (m,n,k)∈{0,1,2} 3 And the values ​​of m, n, and k are all different; is the kth parameter, s k is the number of elements in the kth parameter set, is the mth parameter, s m is the number of elements in the mth parameter set, is the nth parameter, s n The number of elements in the nth parameter set.

[0039] In combination with the second aspect, in some implementations of the second aspect, the number of elements in the first parameter set is less than 3.

[0040] In combination with the second aspect, in certain implementations of the second aspect, the number of elements in the second parameter set is less than the number of elements in the third parameter set, and the second synchronization signal also indicates index information, which includes subframe index information and / or beam index information of the synchronization signal block.

[0041] In combination with the second aspect, in certain implementations of the second aspect, the third synchronization signal is encoded using a Z4 sequence scrambled by an m-sequence.

[0042] In conjunction with the second aspect, in certain implementations of the second aspect, the number of elements in the first parameter set is 1, the second parameter set is {0, 1, 2, ..., L}, and the m-sequence used by the third synchronization signal corresponds to the first cyclic shift parameter m1, where m1 satisfies: The Z4 sequence used by the third synchronization signal corresponds to the second cyclic shift parameter m2, and m2 satisfies: γ is a positive integer, L is a positive integer, and α is a positive integer less than or equal to the length of the third synchronization sequence.

[0043] In combination with the second aspect, in some implementations of the second aspect, γ is greater than 1.

[0044] In combination with the second aspect, in certain implementations of the second aspect, the second synchronization signal adopts any one of the following encoding methods: m sequence, gold sequence, Z4 sequence, and Z4 sequence scrambled by m sequence.

[0045] Some possible implementation methods and beneficial effects of the second aspect can be referred to the first aspect and will not be repeated here.

[0046] According to a third aspect, a communication device is provided, which includes: a transceiver unit, which is used to send a synchronization signal block, the synchronization signal block including a first synchronization signal and a second synchronization signal, the first synchronization signal indicating the frequency domain positions of the second synchronization signal and the third synchronization signal; the transceiver unit is also used to send a third synchronization signal at the frequency domain position, the second synchronization signal and the third synchronization signal indicating the physical cell identifier PCI of the cell to be accessed.

[0047] In combination with the third aspect, in certain implementations of the third aspect, the second synchronization signal and the third synchronization signal can indicate the PCIs of N cells, the PCI of the cell to be accessed belongs to the PCIs of N cells, and N is greater than 1008.

[0048] In combination with the third aspect, in some implementations of the third aspect, the first synchronization signal is a primary synchronization signal PSS and / or the second synchronization signal is a secondary synchronization signal SSS.

[0049] In combination with the third aspect, in certain implementations of the third aspect, the third synchronization signal is adjacent to the synchronization signal block in the time domain.

[0050] In combination with the third aspect, in certain implementations of the third aspect, the first synchronization signal indicates a first parameter, the second synchronization signal indicates a second parameter, and the third synchronization signal indicates a third parameter. The first parameter, the second parameter, and the third parameter are used to determine the PCI of the cell to be accessed.

[0051] In combination with the third aspect, in certain implementations of the third aspect, the first parameter belongs to a first parameter set, the second parameter belongs to a second parameter set, and the third parameter belongs to a third parameter set. The first parameter, the second parameter, and the third parameter are used to determine the PCI of the cell to be accessed, including: the first parameter, the second parameter, and the third parameter are used to determine the PCI of the cell to be accessed together with the first value and the second value, wherein the first value and the second value correspond to the number of elements in the two parameter sets in the first parameter set, the second parameter set, and the third parameter set, respectively.

[0052] In conjunction with the third aspect, in some implementations of the third aspect, the value of PCI satisfies Where (m,n,k)∈{0,1,2} 3 And the values ​​of m, n, and k are all different; is the kth parameter, sk is the number of elements in the kth parameter set, is the mth parameter, s m is the number of elements in the mth parameter set, is the nth parameter, s n The number of elements in the nth parameter set.

[0053] In combination with the third aspect, in some implementations of the third aspect, the number of elements in the first parameter set is less than 3.

[0054] In combination with the third aspect, in certain implementations of the third aspect, the number of elements in the second parameter set is less than the number of elements in the third parameter set, and the second synchronization signal also indicates index information, which includes subframe index information and / or beam index information of the synchronization signal block.

[0055] In combination with the third aspect, in certain implementations of the third aspect, the third synchronization signal is encoded using a Z4 sequence scrambled by an m-sequence.

[0056] In conjunction with the third aspect, in certain implementations of the third aspect, the number of elements in the first parameter set is 1, the second parameter set is {0, 1, 2, …, L}, and the m-sequence used by the third synchronization signal corresponds to the first cyclic shift parameter m1, where m1 satisfies: The Z4 sequence used by the third synchronization signal corresponds to the second cyclic shift parameter m2, and m2 satisfies: γ is a positive integer, L is a positive integer, and α is a positive integer less than or equal to the length of the third synchronization sequence.

[0057] In combination with the third aspect, in some implementations of the third aspect, γ is greater than 1.

[0058] In combination with the third aspect, in certain implementations of the third aspect, the second synchronization signal adopts any one of the following encoding methods: m sequence, gold sequence, Z4 sequence, and Z4 sequence scrambled by m sequence.

[0059] In a fourth aspect, a communication device is provided, which includes: a transceiver unit, the transceiver unit being used to receive a synchronization signal block, the synchronization signal block including a first synchronization signal and a second synchronization signal, the first synchronization signal indicating the frequency domain positions of the second synchronization signal and the third synchronization signal; the transceiver unit is also used to receive the third synchronization signal at the frequency domain position, the second synchronization signal and the third synchronization signal indicating the physical cell identifier PCI of the cell to be accessed.

[0060] In combination with the fourth aspect, in certain implementations of the fourth aspect, the second synchronization signal and the third synchronization signal can indicate the PCIs of N cells, the PCI of the cell to be accessed belongs to the PCIs of N cells, and N is greater than 1008.

[0061] In combination with the fourth aspect, in some implementations of the fourth aspect, the first synchronization signal is a primary synchronization signal PSS and / or the second synchronization signal is a secondary synchronization signal SSS.

[0062] In combination with the fourth aspect, in certain implementations of the fourth aspect, the third synchronization signal is adjacent to the synchronization signal block in the time domain.

[0063] In combination with the fourth aspect, in certain implementations of the fourth aspect, the first synchronization signal indicates a first parameter, the second synchronization signal indicates a second parameter, and the third synchronization signal indicates a third parameter. The device also includes: a processing unit, which is used to determine the PCI of the cell to be accessed based on the first parameter, the second parameter and the third parameter.

[0064] In combination with the fourth aspect, in certain implementations of the fourth aspect, the processing unit is further used to determine the PCI of the cell to be accessed based on a first parameter, a second parameter, a third parameter, a first value, and a second value, wherein the first parameter belongs to a first parameter set, the second parameter belongs to a second parameter set, the third parameter belongs to a third parameter set, and the first value and the second value correspond to the number of elements in two parameter sets in the first parameter set, the second parameter set, and the third parameter set, respectively.

[0065] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the value of PCI satisfies Where (m,n,k)∈{0,1,2} 3 And the values ​​of m, n, and k are all different; is the kth parameter, s k is the number of elements in the kth parameter set, is the mth parameter, s m is the number of elements in the mth parameter set, is the nth parameter, s n The number of elements in the nth parameter set.

[0066] In combination with the fourth aspect, in some implementations of the fourth aspect, the number of elements in the first parameter set is less than 3.

[0067] In combination with the fourth aspect, in certain implementations of the fourth aspect, the number of elements in the second parameter set is less than the number of elements in the third parameter set, and the second synchronization signal also indicates index information, which includes subframe index information and / or beam index information of the synchronization signal block.

[0068] In combination with the fourth aspect, in certain implementations of the fourth aspect, the third synchronization signal is encoded using a Z4 sequence scrambled by an m-sequence.

[0069] In conjunction with the fourth aspect, in certain implementations of the fourth aspect, the number of elements in the first parameter set is 1, the second parameter set is {0, 1, 2, …, L}, and the m-sequence used by the third synchronization signal corresponds to the first cyclic shift parameter m1, where m1 satisfies: The Z4 sequence used by the third synchronization signal corresponds to the second cyclic shift parameter m2, and m2 satisfies: γ is a positive integer, L is a positive integer, and α is a positive integer less than or equal to the length of the third synchronization sequence.

[0070] In combination with the fourth aspect, in some implementations of the fourth aspect, γ is greater than 1.

[0071] In combination with the fourth aspect, in certain implementations of the fourth aspect, the second synchronization signal adopts any one of the following encoding methods: m sequence, gold sequence, Z4 sequence, and Z4 sequence scrambled by m sequence.

[0072] In a fifth aspect, the present application provides a communication device, including a processor, configured to execute the methods provided in the above aspects.

[0073] For the operations such as sending and acquiring / receiving involved in the processor, unless otherwise specified, or if they do not conflict with their actual functions or internal logic in the relevant descriptions, they can be understood as processor output, reception, input and other operations, and can also be understood as sending and receiving operations performed by the radio frequency circuit and antenna. This application does not limit this.

[0074] Optionally, the communication device further includes: a memory for storing programs; and a processor for executing computer programs or instructions stored in the memory to perform the method provided by any one of the above aspects or its implementation.

[0075] In a sixth aspect, the present application provides a communication system, which includes a terminal device and a network device.

[0076] In a seventh aspect, the present application provides a communication system, which includes the communication device of the third aspect and the communication device of the fourth aspect.

[0077] In an eighth aspect, the present application provides a computer-readable storage medium, which stores a computer program or instruction. When the computer program or instruction runs on a computer, the method provided by any one of the above aspects or its implementation method is executed.

[0078] In a ninth aspect, the present application provides a computer program product comprising instructions, which, when the computer program product is run on a computer, enables the method provided by any one of the above aspects or its implementation to be executed.

[0079] In the tenth aspect, the present application provides a chip, which includes a processor and a communication interface. The processor reads instructions stored in the memory through the communication interface and executes the method provided by any one of the above aspects or its implementation method.

[0080] Optionally, as an implementation method, the chip also includes a memory, in which a computer program or instruction is stored, and the processor is used to execute the computer program or instruction stored in the memory. When the computer program or instruction is executed, the processor is used to execute the method provided by any of the above aspects or its implementation methods.

[0081] The chip may include an input circuit or interface for sending information or data, and an output circuit or interface for receiving information or data. BRIEF DESCRIPTION OF THE DRAWINGS

[0082] FIG1 is a schematic diagram of the architecture of a communication system 1000 used in an embodiment of the present application.

[0083] FIG2 is a basic structure of a feedback shift register applicable to an embodiment of the present application.

[0084] FIG3 is a schematic diagram of a register architecture of a Z_4 sequence applicable to an embodiment of the present application.

[0085] FIG4 shows a time-frequency resource structure of a downlink synchronization signal.

[0086] FIG5 is a flow chart of a communication method provided in an embodiment of the present application.

[0087] FIG6 is a schematic diagram of a time-frequency structure of a downlink synchronization signal provided in an embodiment of the present application.

[0088] FIG7 is a schematic diagram of a synchronization signal block bandwidth design.

[0089] FIG8 is a schematic structural diagram of a communication device provided in an embodiment of the present application.

[0090] FIG9 is a schematic diagram of a communication architecture provided in an embodiment of the present application. DETAILED DESCRIPTION

[0091] The technical solution in this application will be described below with reference to the accompanying drawings.

[0092] FIG1 is a schematic diagram of the architecture of a communication system 1000 used in an embodiment of the present application.

[0093] As shown in Figure 1 , the communication system includes a radio access network (RAN) 100. RAN 100 includes at least one RAN node (e.g., 110a and 110b in Figure 1 , collectively referred to as 110) and may also include at least one terminal (e.g., 120a-120j in Figure 1 , collectively referred to as 120). RAN 100 may also include other RAN nodes, such as wireless relay equipment and / or wireless backhaul equipment (not shown in Figure 1 ). Terminal 120 is wirelessly connected to RAN node 110. Terminals and RAN nodes may be interconnected via wired or wireless connections. Communication system 1000 may also include a core network 200. RAN node 110 is wirelessly connected to core network 200. Core network devices in core network 200 and RAN node 110 in RAN 100 may be separate physical devices, or they may be a single physical device integrating the logical functions of a core network device and a RAN node. Communication system 1000 may also include the Internet 300.

[0094] RAN100 can be an evolved universal terrestrial radio access (E-UTRA) system, a new radio (NR) system, or a future radio access system defined in the 3rd Generation Partnership Project (3GPP), or a WiFi system. RAN100 can also include two or more of the aforementioned different radio access systems. RAN100 can also be an open RAN (O-RAN).

[0095] A RAN node, also known as a radio access network device, RAN entity, or access node, facilitates wireless access to a communication system by a terminal. In one application scenario, a RAN node can be a base station, an evolved NodeB (eNodeB), a transmission reception point (TRP), a next-generation NodeB (gNB) in a fifth-generation (5G) mobile communication system, a next-generation base station in a sixth-generation (6G) mobile communication system, a base station in a future mobile communication system, or an access node in a WiFi system. A RAN node can be a macro base station (such as 110a in Figure 1), a micro base station, an indoor station (such as 110b in Figure 1), a relay node, or a donor node.

[0096] In another application scenario, multiple RAN nodes can collaborate to help terminals achieve wireless access, with different RAN nodes implementing portions of the base station's functions. For example, a RAN node can be a centralized unit (CU), a distributed unit (DU), or a radio unit (RU). The CU implements the base station's radio resource control protocol and packet data convergence protocol (PDCP) functions, as well as the service data adaptation protocol (SDAP) functions. The DU implements the base station's radio link control layer and medium access control (MAC) layer functions, as well as some or all of the physical layer functions. For detailed descriptions of each of the above protocol layers, please refer to the relevant 3GPP technical specifications. The RU can be used to implement the transmission and reception of radio frequency signals. The CU and DU can be two independent RAN nodes, or they can be integrated into the same RAN node, such as in a baseband unit (BBU). The RU can be included in radio frequency equipment, such as a remote radio unit (RRU) or an active antenna unit (AAU). The CU can be further divided into two types of RAN nodes: CU-control plane and CU-user plane.

[0097] In different systems, RAN nodes may have different names. For example, in an O-RAN system, a CU may be called an open CU (O-CU), a DU may be called an open DU (O-DU), and a RU may be called an open RU (O-RU). The RAN node in the embodiments of the present application may be implemented by a software module, a hardware module, or a combination of a software module and a hardware module. For example, the RAN node may be a server loaded with the corresponding software module. The embodiments of the present application do not limit the specific technology and specific device form adopted by the RAN node. For ease of description, the following description takes a base station as an example of a RAN node.

[0098] A terminal is a device with wireless transceiver capabilities that can send signals to a base station or receive signals from a base station. A terminal may also be referred to as a terminal device, user equipment (UE), mobile station, mobile terminal, etc. Terminals can be widely used in various scenarios, such as device-to-device (D2D), vehicle-to-everything (V2X) communication, machine-type communication (MTC), Internet of Things (IoT), virtual reality, augmented reality, industrial control, autonomous driving, telemedicine, smart grid, smart furniture, smart office, smart wearable, smart transportation, smart city, etc. A terminal can be a mobile phone, tablet computer, computer with wireless transceiver capabilities, wearable device, vehicle, airplane, ship, robot, robotic arm, smart home device, etc. The embodiments of this application do not limit the specific technology and specific device form adopted by the terminal.

[0099] Base stations and terminals can be fixed or mobile. They can be deployed on land, indoors or outdoors, handheld or vehicle-mounted; on water; or on aircraft, balloons, and satellites. The embodiments of this application do not limit the application scenarios of base stations and terminals.

[0100] The roles of base stations and terminals can be relative. For example, the helicopter or drone 120i in Figure 1 can be configured as a mobile base station. To terminals 120j accessing the wireless access network 100 via 120i, terminal 120i is a base station. However, to base station 110a, 120i is a terminal, meaning that communication between 110a and 120i occurs via a wireless air interface protocol. Of course, communication between 110a and 120i can also occur via a base station-to-base station interface protocol. In this case, 120i is also a base station relative to 110a. Therefore, base stations and terminals can be collectively referred to as communication devices. 110a and 110b in Figure 1 can be referred to as communication devices with base station functionality, while 120a-120j in Figure 1 can be referred to as communication devices with terminal functionality.

[0101] Communication between base stations and terminals, between base stations, and between terminals can be carried out through authorized spectrum, unauthorized spectrum, or both; communication can be carried out through spectrum below 6 gigahertz (GHz), spectrum above 6 GHz, or spectrum below 6 GHz and spectrum above 6 GHz. The embodiments of the present application do not limit the spectrum resources used for wireless communication.

[0102] In the embodiments of the present application, the functions of the base station may also be performed by a module (such as a chip) in the base station, or by a control subsystem that includes the base station functions. The control subsystem that includes the base station functions here may be a control center in the above-mentioned application scenarios such as smart grid, industrial control, smart transportation, and smart city. The functions of the terminal may also be performed by a module (such as a chip or modem) in the terminal, or by a device that includes the terminal functions.

[0103] In this application, a base station sends downlink signals or downlink information to a terminal, and the downlink information is carried on a downlink channel. The terminal sends uplink signals or uplink information to the base station, and the uplink information is carried on an uplink channel. To communicate with the base station, the terminal needs to establish a wireless connection with the cell controlled by the base station. The cell with which the terminal has established a wireless connection is called the serving cell of the terminal.

[0104] To facilitate understanding of the embodiments of the present application, the following briefly describes the relevant concepts and technologies involved in the present application.

[0105] 1. Physical Cell Identifier (PCI): Each 5G-NR cell can be assigned a PCI, which is used to distinguish cells on the radio side. 5G-NR PCI planning is very similar to PCI planning in long-term evolution (LTE) and scrambling code planning in 3G. Incorrect planning can affect synchronization, demodulation, and handover signaling, and can degrade network performance.

[0106] 2. Primitive polynomial: The following describes the relationship between primitive polynomials and sequence generation recursion formulas. For any length L = 2 r For a binary sequence of -1, the primitive polynomial can be represented by a string of binary vectors, such as f(x) = x 7 +x+1 can be represented as the binary vector 10000011, and can also be further represented as the decimal number 131.

[0107] The relationship between the primitive polynomial and the recursive formula is as follows: f(x) = x 7 The recursive formula corresponding to +x+1 is s(t)+s(t-6)+s(t-7)=0. For binary addition, it is defined as modulo 2 addition, that is, -1=1, 1+1=0, 1+0=1, 0+0=0, so the above formula can be converted into the recursive formula s(t)=s(t-6)+s(t-7).

[0108] In general, for multivariate or binary sequences, consider primitive polynomials: a i ∈{0,1,2,…M}, if it is a binary sequence, M=1, if it is a quaternary sequence, M=3, and so on, the recursive formula is: For quaternion sequences, addition is defined on {0, 1, 2, 3}, that is, the addition result must be modulo 4, that is, -1 = 3, -2 = 2, -3 = 1.

[0109] 3. M-sequence: M-sequence is the abbreviation of the longest linear feedback shift register sequence. It is the longest period sequence generated by a shift register with linear feedback. Generally speaking, the longest period generated by an n-stage linear feedback shift register is equal to 2 n -1.

[0110] FIG2 is a basic structure of a feedback shift register applicable to an embodiment of the present application. Referring to FIG2, the bit data used for initialization of the feedback shift register shown in FIG2 is stored in a memory, and a new value is generated by a feedback function and added to the memory. m sequence is the abbreviation of the longest linear feedback shift register sequence. Assuming that the feedback function is an XOR operation on all bits in the memory, that is, Then the output sequence is Addition and subtraction are both defined on the binary domain.

[0111] The m sequence is determined by the initial bit value stored in the register and the primitive polynomial. The order of the primitive polynomial is the highest power in the polynomial. For example, for the primitive polynomial f(x) = x 11 +x 2 +1, the recursive formula for the output sequence is: a k =a k-2 +a k-11 ,k≥11, the order of the primitive polynomial is 11.

[0112] 4. Gold Sequence: A gold sequence is also a pseudo-random sequence. It can be viewed as the element-by-element XOR of two sequences with different primitive polynomials. The cross-correlation function value of a gold sequence will never exceed the maximum cross-correlation function value between the two original m sequences. Gold sequences have good autocorrelation and cross-correlation properties, and their large number facilitates information carrying.

[0113] 5. Z4 sequence: The Z4 sequence has the same period as the binary gold sequence of the same length, with a value set of {0, 1, 2, 3}. It can be modulated using quadrature phase shift keying (QPSK) to produce a complex signal. Similar to the gold sequence, the Z4 sequence can be generated using a circular shift register. The generation of the Z4 sequence is similar to that of the m-sequence, but differs from it in that it is defined on the four-membered ring {0, 1, 2, 3}. Therefore, addition and subtraction operations must be performed modulo 4. For the specific sequence recursion formula, refer to the above section.

[0114] FIG3 is a schematic diagram of a register architecture of a Z4 sequence applicable to an embodiment of the present application. As shown in FIG3 , the primitive polynomial for generating the Z4 sequence in FIG3 is f(x)=x 3 +2x 2 +x+3. The corresponding recursive formula is s(t)+2s(t-1)+s(t-2)+3s(t-3)=0. By shifting the terms, we get s(t)=2s(t-1)+3s(t-2)+s(t-3). Based on this recursive formula, we can get the complete Z4 sequence.

[0115] 6. Key indicator calculation definition:

[0116] 6.1. Peak to Average Power Ratio (PAPR): For a time domain signal x[n], where n is an integer ranging from 0, 1, 2, ... L-1, PAPR is the logarithm of the ratio of the maximum to the average signal power.

[0117] 6.2. Cross-correlation of PSS and SSS or PSS and TSS:

[0118] Since downlink timing is not obtained when detecting the PSS, all time-domain cyclic shifts must be considered when performing cross-correlation. The specific calculation formula is as follows:

[0119] For time domain sequences s1 and s2 of length L (obtained by IFFT oversampling of frequency domain sequences):

[0120] The value range of τ is [-L, L]; the above cross-correlation values ​​need to be normalized to obtain:

[0121] 6.3. Cross-correlation between SSS or TSS: For the cross-correlation between SSS or TSS, considering that the downlink timing is already obtained based on the PSS, cyclic shift can be ignored. For frequency domain sequences S1 and S2, the cross-correlation is defined as:

[0122] Similar to the above, the cross-correlation between SSS / TSS also needs to be normalized:

[0123] For a UE to access a cell, the first step is to obtain cell information, then perform synchronization operations and collect various cell information. To achieve this, the base station continuously sends broadcast messages while in operation, and the UE continuously attempts to obtain cell information from the base station through a specific operation process. This process is the process of cell search and downlink synchronization.

[0124] Figure 4 shows the time-frequency resource structure of a downlink synchronization signal. Referring to Figure 4, the primary synchronization signal (PSS), secondary synchronization signal (SSS), and physical broadcast channel (PBCH) are collectively referred to as the synchronization signal and PBCH block (SSB). The PSS is primarily used for symbol time synchronization, the SSS is primarily used to provide the physical layer cell identifier, enabling the UE to obtain PCI or precise time synchronization, and the PBCH is primarily used to carry key system messages required for UE access to the network, such as channel resource information. The DMRS for PBCH is primarily used for demodulation reference signals and channel estimation during coherent demodulation. NR downlink synchronization can primarily be accomplished based on the PSS and SSS.

[0125] In NR downlink synchronization, before PSS detection, the user does not know the center frequency of the cell, and the frequency calibration between the terminal and the base station has not been completed. PSS is the signal used by the terminal to determine the center frequency of the cell's carrier, and the detection performance must be guaranteed in the presence of time deviation and frequency deviation. Due to the high operating frequency of NR, the anti-interference performance of the ZC sequence is not as good as the m sequence when the time-frequency deviation is relatively large. NR PSS uses the m sequence. The specific sequence generation formula is as follows: PSS (n) = 1-2x(m) 0≤n<127

[0126] NR SSS sequence uses gold sequence: d SSS (n)=[1-2x0((n+m0)mod 127)][1-2x1((n+m1)mod 127)] 0≤n<127 x0(i+7)=(x0(i+4)+x0(i))mod 2 [x1(6) x1(5) x1(4) x1(3) x1(2) x1(1) x1(0)]=[0 0 0 0 0 0 1]

[0127] The calculation method of cell ID, namely PCI, is:

[0128] The value set of is {0,1,2}, The value set is {0,1,2,…335}, so there are a total of 1008 cell IDs. When detecting, the UE first performs a two-dimensional time-frequency search on the PSS. Specifically, the PSS signal is blindly detected on the synchronization grid defined by the standard. The synchronization raster defines a set of frequencies with a certain interval within the 5G frequency band, which is used to divide the 5G frequency band into several SSB frequency domain positions. After the PSS signal is detected on a certain synchronization grid, it is necessary to first perform frequency correction and then time synchronization. Since the PSS carries There are three possible sequences. UE detects Then, substitute it into the SSS test, once There are 336 possible SSS sequences. The UE needs to use 336 different SSS sequences for cross-correlation detection. The SSS sequence corresponding to the maximum cross-correlation value is the actual transmitted sequence. Because PSS requires frequency search and frequency correction, PSS detection has the highest complexity.

[0129] When detecting the SSS, the base station side may use the m-sequence corresponding to m0 as the scrambling code 1, and then perform Hadamard transform detection on the m-sequence corresponding to m1.

[0130] The base station performs sequence correlation detection based on the fast Hadamard transform (FHT). The matrix consisting of all cyclically shifted versions of the m sequence can be obtained by transforming the Hadamard matrix through row and column transformations. Assuming that the dimension of the Hadamard matrix is ​​N*N, the number of additions required for the Hadamard matrix is ​​Nlog2N. The sequence corresponding to the maximum correlation value is the transmitted sequence.

[0131] The following is an introduction to the relevant detection based on FHT:

[0132] Assume there are 2 K possible sequences for transmission, with the primitive polynomial f(x)=x 3 +x 2 +1, a total of eight sequences can be generated. It can be seen that, except for the all-0 sequence, all other m-sequences are cyclically shifted versions of a certain sequence. For example, the third sequence in the table below is the second sequence cyclically shifted left by one bit. M-sequences have good autocorrelation properties, meaning that correlations between different cyclically shifted versions, or the inner product of vectors, yield small correlation values.

[0133] All cyclic shift versions of the m sequence can form a matrix:

[0134] Adding all 0 vectors to the first row and the first row of the M matrix gives the matrix

[0135] The relationship between the matrix and the Hadamard matrix is ​​as follows:

[0136] Among them, P L and P S It is a permutation matrix with only one 1 in each row and column, and the dimension is 2. n *2 n . H is a Hadamard matrix with a dimension of 2 n *2n , n is the order of the primitive polynomial.

[0137] If the detection complexity is not reduced based on FHT, the received signal can be directly correlated with the M matrix. For example, if the received signal is R = [0, 1, 0, 1, 1, 1, 0], the received signal is converted into a binary phase signal [1, -1, 1, -1, -1, -1, 1]. The elements in the M matrix are also converted into binary phase signals, and all zero elements are added to the first row to obtain M′, M′*R = [-1, -1, 7, -1, -1, -1, -1, -1]. Therefore, the base station side determines that the transmitted m sequence is the third sequence [0, 1, 0, 1, 1, 1, 0] based on the maximum correlation value. The required addition is 2 n *(2 n -1).

[0138] If FHT is used for detection, the received signal and Doing correlation can be converted into P L HP S Since there is only one 1 in each row and column of the row-column permutation matrix, the addition complexity can be ignored, and the addition complexity of multiplying any matrix with the Hadamard matrix is ​​2 n *log2(2 n -1), thus reducing the computational complexity.

[0139] In NR downlink synchronization, each 5G NR cell corresponds to a PCI, which is used to distinguish cells on the wireless side. Since communication frequencies may increase and path losses may increase in the future, large cities with high user density will need to deploy a large number of small base stations, so deployment flexibility needs to be guaranteed. Considering that PCI confusion and PCI planning to avoid PCI confusion may be important issues in actual deployment / operation (including dense deployment in urban areas), and in most wireless networks around the world, network quality problems caused by PCI conflicts, confusion, MOD3 interference, etc. due to inadequate PCI design and optimization have been common. Therefore, the number of cell IDs will increase further in the future to facilitate PCI planning. Therefore, how to carry more PCIs in the synchronization signal is an urgent problem that needs to be solved in this field.

[0140] In view of the above problems, the embodiments of the present application provide a communication method and a communication device, which can carry more PCIs in the synchronization signal while ensuring the delay.

[0141] The technical solution in this application will be described below with reference to the accompanying drawings.

[0142] FIG5 is a flow chart of a communication method 500 provided in an embodiment of the present application.

[0143] In one possible implementation, referring to FIG5 , a communication method 500 includes:

[0144] S501, the network device sends a synchronization signal block, and accordingly, the terminal device receives the synchronization signal block, where the synchronization signal block includes a first synchronization signal and a second synchronization signal, and the first synchronization signal indicates the frequency domain positions of the second synchronization signal and the third synchronization signal.

[0145] S502, at the frequency domain position, the network device sends a third synchronization signal, and correspondingly, the terminal device receives the third synchronization signal. The second synchronization signal and the third synchronization signal indicate the PCI of the cell to be accessed.

[0146] Specifically, when designing the first synchronization signal, the second synchronization signal, and the third synchronization signal, the network device considers the following requirements:

[0147] 1. The first synchronization signal has better time-frequency two-dimensional correlation performance.

[0148] 2. The first synchronization signal has a lower detection delay.

[0149] 3. The first synchronization signal and the second synchronization signal maintain low cross-correlation. When the first synchronization signal is detected, the terminal device does not know the timing and will detect the first synchronization signal at any time. If the correlation value of the first synchronization signal and the second synchronization signal is large, it will cause greater interference.

[0150] 4. The first synchronization signal and the third synchronization signal maintain low cross-correlation, the reason is similar to the third point.

[0151] 5. The second synchronization signal and the third synchronization signal may not maintain a low cross-correlation because the first synchronization signal has already acquired downlink timing.

[0152] 6. Low PAPR of the first synchronization signal / second synchronization signal / third synchronization signal.

[0153] FIG6(a) is a schematic diagram of a time-frequency structure of a downlink synchronization signal provided in an embodiment of the present application, and FIG6(b) is a schematic diagram of another time-frequency structure of a downlink synchronization signal provided in an embodiment of the present application.

[0154] In one possible implementation, the first synchronization signal includes the PSS. The first synchronization signal can be used to indicate the frequency domain position of the SSB and the frequency domain position of the third synchronization signal. In addition, the first synchronization signal can also be used for symbol time synchronization and carry the cell ID.

[0155] Optionally, the frequency domain positions of the first synchronization signal, the second synchronization signal and the third synchronization signal are the same, as shown in (a) and (b) in FIG6 .

[0156] Specifically, the terminal device can blindly detect the first synchronization signal on the standard-defined synchronization raster. The synchronization raster defines a set of frequencies with a certain interval within the 5G frequency band, which is used to divide the 5G frequency band into several synchronization signal block frequency domain positions; after the terminal device detects the first synchronization signal on a certain synchronization raster, it needs to perform frequency domain correction, and then the terminal device can determine the frequency domain positions of the second synchronization signal and the third synchronization signal based on the frequency domain relationship between the second synchronization signal, the third synchronization signal and the first synchronization signal.

[0157] In one possible implementation, the second synchronization signal includes an SSS. The second synchronization signal can be used to carry a cell ID so that a terminal device can obtain a cell PCI. In addition, the second synchronization signal can also be used for fine time synchronization in downlink synchronization.

[0158] It should be understood that the first synchronization signal including PSS and / or the second synchronization signal including SSS is only an example. The first synchronization signal may also include other signals that can be used to indicate the frequency domain position of the second synchronization signal and the third synchronization signal, and the second synchronization signal may also include other signals that can be used to indicate the cell PCI. This application does not limit this.

[0159] Optionally, the SSB includes a first synchronization signal, a second synchronization signal and PBCH, and the PBCH can be used to carry key system messages required for the terminal device to access the network.

[0160] Specifically, to carry more cell IDs, a straightforward approach is to increase the sequence length, which increases the number of available cyclic shifts. However, increasing the sequence length significantly increases detection latency. Smaller-bandwidth synchronization signal blocks can achieve lower access latency because the synchronization signal block bandwidth is designed to ensure that a synchronization signal block can fit within the minimum NR channel bandwidth.

[0161] FIG7 is a schematic diagram of a synchronization signal block bandwidth design.

[0162] Referring to Figure 7, the relationship between the synchronization signal block channel bandwidth and the synchronization grid can satisfy: BW sync ≤(BW c -G c )-F raster ;

[0163] Among them BW c is the minimum channel bandwidth, G c To protect bandwidth, F raster is the frequency interval between adjacent synchronization grids, BW syncFor the synchronization signal block bandwidth, it can be found that the larger the synchronization signal block bandwidth, the smaller the interval of the synchronization grid, then the number of synchronization grids will increase under the same total bandwidth (assuming the sparsity remains unchanged), then the frequency search delay will increase.

[0164] Further, referring to Table 1, considering that the minimum channel bandwidth is 5 MHz, the protection bandwidth is 10%, and the synchronization signal block bandwidth is 2.16 MHz, the maximum synchronization grid interval is Rounded down to 23, when the synchronization signal block bandwidth is 1.08MHz, the maximum synchronization grid interval is Rounded down to 34. The delay gain can be understood as the change in search time caused by the change in PSS bandwidth when the channel bandwidth remains unchanged: That is, the bandwidth synchronization signal block delay benefit is 48%. Therefore, the embodiment of the present application considers increasing the number of synchronization signals in a small bandwidth condition to carry more cell IDs.

[0165] Table 1

[0166] Please continue to refer to (a) and (b) in Figure 6. The third synchronization signal can also be called a tertiary synchronization signal (TSS). The third synchronization signal can include a downlink synchronization signal newly added to the protocol. The third synchronization signal can be used to indicate the PCI of the cell to be accessed together with the second synchronization signal. The third synchronization signal can also be used together with the first synchronization signal and the second synchronization signal to indicate the PCI of the cell to be accessed.

[0167] Specifically, the terminal device can receive the second synchronization signal and the third synchronization signal at the frequency domain position determined by the first synchronization signal, so the detection complexity of the second synchronization signal and the third synchronization signal is lower than that of the first synchronization signal, and thus the second synchronization signal and the third synchronization signal can be used specifically to carry more cell IDs, or the second synchronization signal and the third synchronization signal can be used to carry cell IDs and other indication information.

[0168] Furthermore, the sequence content of the second synchronization signal and the third synchronization signal can correspond to different parameters. The terminal device can obtain the corresponding parameters by detecting the sequences of the second synchronization signal and the third synchronization signal, and calculate the PCI of the cell through the parameters. For example, the second synchronization signal can have 6 possible sequences and carry 6 cell IDs. When the second synchronization signal is determined, the third synchronization signal can have 336 possible sequences and carry 336 cell IDs. At this time, the downlink synchronization signal sent by the network device can indicate a total of 2016 PCIs.

[0169] Furthermore, after the terminal device determines the PCI of the cell to be accessed, it can continue to perform subsequent downlink synchronization processes. For example, the terminal device can perform further synchronization operations and collect various information of the cell to be accessed until the terminal device believes that it is fully aware of the situation of the cell.

[0170] In an embodiment of the present application, a third synchronization signal is introduced into the downlink synchronization signal to carry the cell ID, and the third synchronization signal does not need to indicate the frequency domain position. Since the synchronization signal indicating the frequency domain position needs to perform frequency point search and frequency correction and other operations during detection, its detection complexity is the highest and the detection time is the longest. Therefore, under the same delay, the third synchronization signal can carry more cell IDs than the first synchronization signal, and thus the downlink synchronization signal can indicate more cell PCIs while ensuring the delay.

[0171] In one possible implementation, the third synchronization signal is adjacent to the synchronization signal block in the time domain.

[0172] In one example, the third synchronization signal may be located after the synchronization signal block in the time domain, and its symbol is adjacent to the synchronization signal block, as shown in (a) of Figure 6. In another example, the third synchronization signal may be located before the synchronization signal block in the time domain, and its symbol is adjacent to the synchronization signal block, as shown in (b) of Figure 6.

[0173] Furthermore, when the third synchronization signal is adjacent to the synchronization signal block, the terminal device can directly determine the time domain position of the third synchronization signal based on the time domain position of the synchronization signal block. For example, the terminal device detects that the time domain position of the first synchronization signal is symbol 3. According to the predefined conditions of the protocol, the frequency domain position of the synchronization signal block can be symbol 3 to symbol 5. At this time, the time domain position of the third synchronization signal can be directly determined as symbol 2 or symbol 7.

[0174] It should be understood that the entire downlink synchronization signal shown in (a) or (b) in Figure 6 can also be regarded as a synchronization signal block. In this case, the time domain position of the third synchronization signal can be the first symbol or the last symbol in the synchronization signal block.

[0175] In an embodiment of the present application, since the third synchronization signal is adjacent to the synchronization signal block in the time domain, the terminal device can more conveniently determine the time domain position of the third synchronization signal when detecting the third synchronization signal, and then the terminal device can obtain the content of the third synchronization signal with lower latency. Therefore, the third synchronization signal is adjacent to the synchronization signal block in the time domain, which increases the efficiency of the downlink synchronization process.

[0176] It should be understood that in the embodiment of the present application, the third synchronization signal is adjacent to the synchronization signal block in the time domain only as a preferred example. The time domain position of the third synchronization signal may not be fixed. For example, the third synchronization signal can be placed at any position before or after the synchronization signal block. The time domain position of the third synchronization signal can also be determined based on the mapping relationship between the time domain position of the first synchronization signal and / or the second synchronization signal and the third synchronization signal.

[0177] In a possible implementation, the second synchronization signal and the third synchronization signal can indicate PCIs of N cells, the PCI of the cell to be accessed belongs to the PCIs of N cells, and N is greater than 1008.

[0178] Specifically, in the prior art, when the first synchronization signal is PSS and the second synchronization signal is SSS, the value set of the parameter corresponding to the first synchronization signal is {0, 1, 2}, and the value set of the parameter corresponding to the second synchronization signal is {1, 2, 3, ..., 335}, so the first synchronization signal and the second synchronization signal can indicate a total of 3×336=1008 PCIs.

[0179] Furthermore, the number of cell PCIs that can be indicated by the second synchronization signal and the third synchronization signal can be greater than the number of cell PCIs that can be indicated by the first synchronization signal and the second synchronization signal. For example, the number of elements in the value set of the parameter corresponding to the second synchronization signal is 6, and the number of elements in the value set of the parameter corresponding to the third synchronization signal is 336. At this time, the downlink synchronization signal can indicate a total of 6×336=2016 PCIs; for another example, the number of elements in the value set of the parameter corresponding to the second synchronization signal is 12, and the number of elements in the value set of the parameter corresponding to the third synchronization signal is 336. At this time, the downlink synchronization signal can indicate a total of 12×336=4032 PCIs.

[0180] Optionally, the total number of PCIs that can be indicated by the downlink synchronization signal may include 1500, or 2016, or 4032, etc.

[0181] In a possible implementation, the second synchronization signal and the third synchronization signal indicate the PCI of the cell to be accessed, including: the first synchronization signal, the second synchronization signal, and the third synchronization signal indicate the PCI of the cell to be accessed.

[0182] In a possible implementation, the second synchronization signal and the third synchronization signal can indicate the PCIs of N cells, including: the first synchronization signal, the second synchronization signal, and the third synchronization signal can indicate the PCIs of N cells.

[0183] Specifically, the number of cell PCIs that can be indicated by the first synchronization signal, the second synchronization signal and the third synchronization signal can be greater than the number of cell PCIs that can be indicated by the first synchronization signal and the second synchronization signal. For example, the number of elements in the value set of the parameter corresponding to the first synchronization signal is 3, the number of elements in the value set of the parameter corresponding to the second synchronization signal is 6, and the number of elements in the value set of the parameter corresponding to the third synchronization signal is 336. At this time, the downlink synchronization signal can indicate a total of 3×6×336=6048 PCIs.

[0184] In an embodiment of the present application, the PCI of a cell can be jointly indicated by the first synchronization signal, the second synchronization signal and the third synchronization signal. Since the third synchronization signal is introduced into the downlink synchronization signal to carry the cell ID, adding the third synchronization signal to the downlink synchronization signal to carry the cell ID can indicate more cell PCIs.

[0185] In one possible implementation, the first synchronization signal indicates a first parameter, the second synchronization signal indicates a second parameter, and the third synchronization signal indicates a third parameter. The terminal device determines the PCI of the cell to be accessed based on the first parameter, the second parameter, and the third parameter.

[0186] Specifically, the first parameter, the second parameter and the third parameter may correspond to the sequence contents of the first synchronization signal, the second synchronization signal and the third synchronization signal respectively, and the PCI of the cell to be accessed may be calculated based on the first parameter, the second parameter and the third parameter.

[0187] For example, the terminal device determines that the first parameter is 2 based on the first synchronization signal, the terminal device determines that the second parameter is 3 based on the second synchronization signal, and the terminal device determines that the third parameter is 10 based on the third synchronization signal. Then the PCI value of the cell to be accessed can be obtained by calculating the three parameters {2, 3, 10} through the formula.

[0188] In one possible implementation, the first parameter belongs to a first parameter set, the second parameter belongs to a second parameter set, and the third parameter belongs to a third parameter set. The first parameter, the second parameter, and the third parameter are used to determine the PCI of the cell to be accessed, including: the first parameter, the second parameter, and the third parameter are used to determine the PCI of the cell to be accessed together with the first value and the second value, wherein the first value and the second value correspond to the number of elements in two parameter sets in the first parameter set, the second parameter set, and the third parameter set, respectively.

[0189] Specifically, the first parameter set, the second parameter set and the third parameter set can correspond to the value sets of the first parameter, the second parameter and the third parameter, respectively. For example, the value set of the first parameter is {0, 1, 2}, corresponding to three different sequence contents of the first synchronization signal after the second synchronization signal and / or the third synchronization signal are determined; the value set of the second parameter is {0, 1, 2, 3, 4, 5}, corresponding to three different sequence contents of the first synchronization signal after the first synchronization signal and / or the third synchronization signal are determined; the value combination of the third parameter is {1, 2, 3,…, 335}, corresponding to 336 different sequence contents of the third synchronization signal after the first synchronization signal and / or the second synchronization signal are determined.

[0190] Furthermore, the number of elements in the first parameter set, the second parameter set and the third parameter set corresponds to the number of cell IDs carried by the first synchronization signal, the second synchronization signal and the third synchronization signal, and the number of elements in the parameter set can be used to calculate the PCI of the cell.

[0191] In one possible implementation, the value of PCI satisfies Where (m,n,k)∈{0,1,2} 3 And the values ​​of m, n, and k are all different; is the kth parameter, s k is the number of elements in the kth parameter set, is the mth parameter, s m is the number of elements in the mth parameter set, is the nth parameter, s n The number of elements in the nth parameter set.

[0192] Specifically, in a multi-stage detection architecture, synchronization signals carrying fewer cell IDs are preferentially decoded, and then synchronization signals carrying more cell IDs are serially detected, thereby achieving a lower false detection rate.

[0193] For example, the value set of the first parameter is {0, 1, 2}, the number of elements in the first parameter set is 3, and the terminal device determines that the first parameter is 2 according to the first synchronization signal; the value set of the second parameter is {0, 1, 2, 3, 4, 5}, the number of elements in the second parameter set is 6, and the terminal device determines that the second parameter is 3 according to the second synchronization signal; the value combination of the third parameter is {1, 2, 3, ..., 335}, the number of elements in the third parameter set is 336, and the terminal device determines that the third parameter is 10 according to the third synchronization signal; when k = 1, m = 2, n = 3, s k =3,s m =6, the PCI value satisfies

[0194] In an embodiment of the present application, by introducing a third synchronization signal, the downlink synchronization signal can adopt a three-level synchronization architecture, that is, the value of PCI can be jointly determined by three parameters corresponding to the first synchronization signal, the second synchronization signal and the third synchronization signal. Compared with the two-level synchronization architecture, the downlink synchronization signal adopts a three-level synchronization architecture to indicate more cell PCIs.

[0195] It is understandable that under the above PCI determination method, any PCI value can determine a unique Ensure that there is no confusion in the mapping of PCI to sequence selection.

[0196] In a possible implementation, the number of elements in the first parameter set is less than 3.

[0197] Specifically, when the first synchronization signal and the second synchronization signal carry the cell ID, the value set of the parameter corresponding to the first synchronization signal may be {0, 1, 2}, that is, the number of elements in the first parameter set is equal to 3.

[0198] Furthermore, when the first synchronization signal, the second synchronization signal and the third synchronization signal carry cell IDs, since the third synchronization signal is added to carry the cell ID, the number of elements in the first synchronization signal can be less than 3, and the number of cell IDs that the downlink synchronization signal can carry can be greater than the number of cell IDs carried by the first synchronization signal and the second synchronization signal.

[0199] In a possible implementation, the first synchronization signal does not carry a cell ID, or in other words, the first synchronization signal carries a cell ID.

[0200] It should be understood that the first synchronization signal does not carry a cell ID, the first synchronization signal carries 0 cell IDs, or the first synchronization signal carries one cell ID has the same meaning, that is, during the downlink synchronization process, the network device does not indicate different PCIs by changing the first synchronization signal sequence, or in other words, the terminal device does not need to determine the PCI based on the sequence content of the first synchronization signal.

[0201] Exemplarily, the first synchronization signal carries 0 cell IDs, the second synchronization signal carries 6 cell IDs, the third synchronization signal carries 336 cell IDs, and the downlink synchronization signal carries a total of 2016 IDs.

[0202] Specifically, when the number of cell IDs carried by a downlink synchronization signal increases, the terminal device needs to try more different sequence contents to perform cross-correlation detection on the downlink synchronization signal when detecting the downlink synchronization signal. The sequence corresponding to the maximum cross-correlation value is the sequence of the downlink synchronization signal actually sent by the network device. Therefore, the downlink synchronization signal carrying more cell IDs can bring about an increase in the downlink synchronization delay. Due to the detection complexity brought about by the first synchronization signal determining the frequency domain position, increasing the number of cell IDs carried by the first synchronization signal will significantly increase the downlink synchronization delay.

[0203] Specifically, when the network device generates a downlink synchronization signal, the cross-correlation between the downlink synchronization signals must be considered. For example, as mentioned above, the sequences of the first synchronization signal and the second synchronization signal, as well as the first synchronization signal and the third synchronization signal need to maintain low cross-correlation; the greater number of cell IDs carried by the first synchronization signal means that there are more possible sequence types for the first synchronization signal, and thus the network device needs to keep the sequence content of the second synchronization signal and the third synchronization signal low cross-correlation with more possible sequences.

[0204] In an embodiment of the present application, the first parameter set corresponds to the number of cell IDs carried by the first synchronization signal, and the first synchronization signal is used to determine the frequency domain position, which makes the detection complexity of the first synchronization signal high and the detection time-consuming; therefore, the number of elements in the first parameter set is less than 3, which can reduce the number of sequences to be detected in the first synchronization signal, thereby reducing the overall delay of the downlink synchronization; in addition, when detecting the first synchronization signal, there is no timing prior information, and the second synchronization signal / third synchronization signal may be misdetected as the first synchronization signal, resulting in downlink synchronization failure. Therefore, in order to ensure the accuracy of synchronization in the downlink synchronization signal, the first synchronization signal needs to maintain low cross-correlation with the second and third synchronization signals. When the number of elements in the first parameter set is less than 3, that is, the possible sequence types of the first synchronization signal are less than 3, the second and third synchronization signals only need to maintain low cross-correlation with fewer first synchronization signal sequences, thereby increasing the sequence cross-correlation optimization space of the second and third synchronization signals.

[0205] In one possible implementation, the number of elements in the second parameter set is less than the number of elements in the third parameter set, and the second synchronization signal further indicates index information, which includes subframe index information and / or beam index information of the synchronization signal block.

[0206] It should be understood that since the functions of the second synchronization signal and the third synchronization signal can be the same and are both used to carry PCI, their positions can be swapped, that is, the characteristics involving the second synchronization signal and the characteristics involving the third synchronization signal in the embodiment of the present application can be interchanged with each other, for example, the number of elements in the second parameter set can be greater than the number of elements in the third parameter set, and the third synchronization signal also indicates index information.

[0207] Specifically, the number of elements in the second parameter set is smaller than the number of elements in the third parameter set, that is, the possible sequence types of the second synchronization signal sent by the network device are smaller than the possible sequence types of the third synchronization signal. This can be understood as the number of cell IDs carried by the second synchronization signal sent by the network device is smaller than the number of cell IDs carried by the third synchronization signal.

[0208] Specifically, the index information can be included in the system information carried by PBCH, and the index information can include subframe index information, which is used for the terminal device to obtain information such as frame number, subframe number and time slot number; the index information can also include beam index information of the synchronization signal block, which is used for the terminal device to obtain information such as beam number.

[0209] Specifically, since the number of elements in the second parameter set is smaller than the number of elements in the third parameter set, the possible sequence types of the second synchronization signal sent by the network device are smaller than the possible sequence types of the third synchronization signal. At this time, the second synchronization signal can carry other information through the sequence content that does not carry the cell ID. For example, the second synchronization signal can carry index information in the PBCH.

[0210] For example, the PBCH in the SSB carries 40 bits of system information. The possible sequence types of the second synchronization signal sent by the network device are less than the possible sequence types of the third synchronization signal. The second synchronization signal carries 20 bits of system information originally carried in the PBCH through sequence content that does not carry the cell ID. The PBCH sent by the network device only needs to carry the remaining 20 bits of system information.

[0211] In an embodiment of the present application, the second synchronization signal carries fewer cell IDs, so the downlink synchronization signal can indicate index information through the second synchronization signal, thereby reducing the amount of system information carried in the PBCH, so that the PBCH can be transmitted at a lower code rate, thereby improving the demodulation performance of the PBCH.

[0212] In a possible implementation, the second synchronization signal adopts any one of the following encoding modes: m-sequence, gold sequence, Z4 sequence, and Z4 sequence scrambled by m-sequence.

[0213] In a possible implementation, the third synchronization signal is encoded using a Z4 sequence scrambled by an m sequence.

[0214] Specifically, the first synchronization signal may continue to use the m-sequence of the PSS, and the second synchronization signal or the third synchronization signal may adopt a certain encoding method, which can be understood as the sequence content of the second synchronization signal or the third synchronization signal meets the generation rule of the encoding sequence.

[0215] Specifically, for a length of L=2 r-1 Z4 sequence, whose period is consistent with the gold sequence, has L+1 maximum cross-correlations. The sequence (the cross-correlation value is the minimum cross-correlation value of the binary sequence ). Multi-level detection often leads to a higher false detection rate and requires a cross-correlation performance at least on par with NR PSS / SSS. Therefore, when the second synchronization signal carries fewer cell IDs than the third synchronization signal, the network device only needs to maintain the better correlation performance of the second synchronization signal. The network device may not limit the encoding form of the second synchronization signal. For example, the second synchronization signal may use a Z4 sequence scrambled by m / gold / Z4 / m sequence, etc.; the third synchronization signal carries more cell IDs. Due to the low cross-correlation characteristic of the Z4 sequence, the third synchronization signal may use a Z4 sequence or a Z4 sequence scrambled by an m sequence, where the m sequence is used to reduce the complexity of sequence detection.

[0216] Specifically, the third synchronization signal can be encoded using a Z4 sequence scrambled by an m-sequence, wherein the m-sequence and the Z4 sequence have the same length, and the network device can perform a dot product on the m-sequence and the Z4 sequence element by element to obtain the Z4 sequence scrambled by the m-sequence.

[0217] Furthermore, after the Z4 sequence is scrambled by the m sequence in the third synchronization signal, since the m sequence has a low-complexity detection algorithm, the terminal device can first decode the m sequence when detecting the third synchronization signal, and then decode the Z4 sequence based on the information decoded from the m sequence, thereby achieving a lower detection complexity when detecting the third synchronization signal than directly detecting the Z4 sequence.

[0218] In an embodiment of the present application, the third synchronization signal carrying more cell IDs is encoded using a Z4 sequence. Since the Z4 sequence can ensure low cross-correlation between sequences in the synchronization signal, using the Z4 sequence to encode the third synchronization signal can reduce the error detection rate of the downlink synchronization signal; in addition, since the m sequence has a low-complexity detection algorithm, the network device uses the m sequence to scramble the third synchronization signal encoded using the Z4 sequence, which can reduce the detection complexity of the third synchronization signal.

[0219] In one possible implementation, the number of elements in the first parameter set is 1, the second parameter set is {0, 1, 2, …, L}, and the m-sequence used by the third synchronization signal corresponds to the first cyclic shift parameter m1, where m1 satisfies: The Z4 sequence used by the third synchronization signal corresponds to the second cyclic shift parameter m2, and m2 satisfies: γ is a positive integer, L is a positive integer, and α is a positive integer less than or equal to the length of the third synchronization sequence.

[0220] It should be understood that, among the above cyclic shift parameters, the cyclic shift number of the m sequence is greater than the cyclic shift number of the Z_4 sequence, which can reduce the detection degree to the greatest extent.

[0221] Exemplarily, the cell PCI indication method includes: m1=mod(N ID,3 ,56); N ID,3 ∈{0,1,…335}; N ID,2 ∈{0,1,2,3,4,5}; N ID,1 ∈{0}.

[0222] Among them, N ID,1 Corresponding to the first parameter set, N ID,2 Corresponding to the second parameter set, N ID,3 Corresponding to the third parameter set, m1 corresponds to the cyclic shift of the m sequence in the third synchronization signal, and m2 corresponds to the cyclic shift of the Z4 sequence in the third synchronization signal sequence.

[0223] In one possible implementation, γ is greater than 1.

[0224] Specifically, the size of γ corresponds to the size of the interval between adjacent cyclic shifts in the sequence of the third synchronization signal. When γ is equal to 1, the interval between adjacent cyclic shifts in the sequence of the third synchronization signal is 1. At this time, if there is a frequency deviation of 1 in the frequency domain of the third synchronization signal, the terminal device may easily mistakenly obtain the third parameter corresponding to the third synchronization signal; when γ is greater than 1, the interval between adjacent cyclic shifts in the sequence of the third synchronization signal increases. At this time, if there is a frequency deviation less than γ in the frequency domain of the third synchronization signal, the terminal device will not directly correspond the third synchronization signal after the frequency deviation to the erroneous third parameter, and the terminal device can then correct the frequency deviation through an algorithm.

[0225] In the embodiment of the present application, γ being greater than 1 can increase the interval between adjacent cyclic shifts in the sequence of the third synchronization signal, thereby improving the frequency offset resistance of the third synchronization signal.

[0226] Furthermore, several examples of downlink synchronization signals corresponding to the embodiments of the present application are given below:

[0227] Example 1: The first synchronization signal uses PSS, and the PSS signal uses the m-sequence; the second synchronization signal uses SSS, the SSS signal uses the Z4 sequence scrambled by the m-sequence, and the TSS sequence uses the Z4 sequence scrambled by the m-sequence. The PSS carries 0 IDs, the SSS carries 6 IDs, and the TSS carries 336 IDs (TSS has a total of 336*6 sequences. After the SSS is detected, the TSS still carries 336 IDs), and a total of 2016 IDs are carried.

[0228] Specifically, the sequence of the downlink synchronization signal is generated as follows: m1=mod(N ID,3 ,112); CS=15*[0,1,2,3,4,5]; N ID,3 ∈{0,1,…335}; N ID,2 ∈{0,1,2,3,4,5}; N ID,1 ∈{0}.

[0229] Among them, N ID,1 Corresponding to the first parameter set, N ID,2 Corresponding to the second parameter set, N ID,3 For the third parameter set, m2 and m1 correspond to the cyclic shifts of the Z4 sequence and the m sequence in the TSS, and CS represents the six cyclic shifts of the SSS sequence. The scrambled m sequence used by the SSS and TSS is the PSS sequence.

[0230] Specifically, the initial value and primitive polynomial required for generating the downlink synchronization signal sequence are as follows:

[0231] PSS: primitive polynomial 10000011, initial value [0,1,1,0,1,1,1];

[0232] SSS: Z4 sequence primitive polynomial: 10020013, initial value [1,0,0,0,0,0,0], cyclic shift value 15*[0,1,2,3,4,5];

[0233] TSS: Z4 sequence primitive polynomial: 10020013, initial value [1,0,0,0,0,0,0], where m0 and m1 correspond to the cyclic shifts of the two sequences.

[0234] Further, please refer to Table 2 and Table 3, where Table 2 is the downlink synchronization signal correlation index of the cell ID carried by PSS and SSS in the existing NR, and Table 3 is the downlink synchronization signal correlation index when determining the cell PCI through the first synchronization signal, the second synchronization signal and the third synchronization signal provided in the embodiment of the present application.

[0235] Table 2

[0236] Table 3

[0237] Specifically, in Table 2 and Table 3 and the following tables, 0.5SCS frequency deviation and 1SCS frequency deviation indicate a frequency deviation of 0.5 subcarrier interval or 1 subcarrier interval, and the correlation index between downlink synchronization signals mainly refers to the maximum value column. It can be seen that in the method for determining the cell PCI through the first synchronization signal, the second synchronization signal and the third synchronization signal provided in the embodiment of the present application, the maximum value of the mutual correlation between SSSs obtains a lower mutual correlation value at 0SCS frequency deviation and 0.5SCS frequency deviation, that is, the mutual correlation performance between SSSs is optimized; similarly, the mutual correlation performance between PSS and SSS is also greatly improved, and the mutual correlation between TSSs and the mutual correlation between PSS and TSS are both small.

[0238] Furthermore, the initial value and primitive polynomial required for another possible sequence generation in Example 1 are as follows:

[0239] PSS: primitive polynomial 10000011, initial value [0,1,1,0,1,1,1];

[0240] SSS: Z4 sequence primitive polynomial: 10030203, initial value [1,0,0,0,0,0,0], cyclic shift value 15*[0,1,2,3,4,5];

[0241] TSS: Z4 sequence primitive polynomial: 10020013, initial value [1,0,0,0,0,0,0], where m0 and m1 correspond to the cyclic shifts of the two sequences.

[0242] Further, please refer to Table 4, which is a downlink synchronization signal correlation indicator generated by another method in Example 1 provided in an embodiment of the present application.

[0243] Table 4

[0244] It should be understood that the examples described above and below are illustrations to help readers understand the embodiments of the present application, and the specific sequences applicable to the embodiments of the present application are far more than the examples listed in this article.

[0245] Example 2: The first synchronization signal uses the PSS sequence, the PSS signal uses the m sequence, the second synchronization signal uses the SSS, the SSS signal uses the Z4 sequence scrambled by the m sequence, and the TSS sequence uses the Z4 sequence scrambled by the m sequence. The PSS carries 0 IDs, the SSS carries 12 IDs, and the TSS carries 336 IDs (TSS has a total of 336*12 sequences. After the SSS is detected, the TSS still carries 336 IDs), totaling 4032 IDs.

[0246] Specifically, the sequence of the downlink synchronization signal is generated as follows: m1=mod(N ID,3 ,112) CS=10*[0,1,2,…,11] N ID,3 ∈{0,1,…335} N ID,2 ∈{0,1,2,…,11} N ID,1 ∈{0}

[0247] Where m2 and m1 correspond to the cyclic shifts of the Z4 sequence and the m sequence in the TSS, and CS represents the six cyclic shifts of the SSS sequence. The scrambling m sequence used by the SSS and TSS is the PSS sequence.

[0248] Specifically, the reason why CS=10*[0,1,2,…,11] is because the total number of cyclic shifts increases to 12, and therefore the maximum cyclic shift value cannot exceed the sequence length of 127, otherwise a large cross-correlation value may be generated when there is a frequency offset.

[0249] Specifically, the initial value and primitive polynomial required for generating the downlink synchronization signal sequence are as follows:

[0250] PSS: primitive polynomial 10000011, initial value [0,1,1,0,1,1,1];

[0251] SSS: Z4 sequence primitive polynomial: 10020013, initial value [1,0,0,0,0,0,0], cyclic shift value 10*[0,1,2,…,11];

[0252] TSS: Z4 sequence primitive polynomial: 10020013, initial value [1,0,0,0,0,0,0], where m0 and m1 correspond to the cyclic shifts of the two sequences.

[0253] Further, please refer to Table 5, which is the downlink synchronization signal correlation index in Example 2 provided in an embodiment of the present application.

[0254] Table 5

[0255] In the embodiment of the present application, Example 2 replaces the sequence of the second synchronization signal, wherein the number of cells carried by the second synchronization signal is 12, and the number of cell IDs carried by the second synchronization signal in Examples 1 and 3 is 6. Please refer to Tables 2 to 6. It can be seen that when the number of cell IDs carried by the second synchronization signal doubles, and then the total number of PCIs carried by the downlink synchronization signal doubles, the cross-correlation between SSSs and the cross-correlation between PSS and SSS are still lower than the corresponding indicators in the existing NR, and the cross-correlation between TSSs and the cross-correlation between PSS and TSS remain small.

[0256] Example 3: The first synchronization signal uses the PSS sequence, the PSS signal uses the m sequence, the second synchronization signal uses SSS, the SSS signal uses the Z4 sequence, and the TSS sequence uses the Z4 sequence scrambled by the m sequence. The PSS carries 0 IDs, the SSS carries 6 IDs, and the TSS carries 336 IDs (TSS has a total of 336*6 sequences. After the SSS is detected, the TSS still carries 336 IDs), and a total of 2016 IDs are carried.

[0257] Specifically, the sequence of the downlink synchronization signal is generated as follows: m1=mod(N ID,3 ,112) CS=15*[0,1,2,3,4,5] N ID,3 ∈{0,1,…335} N ID,2 ∈{0,1,2,3,4,5} N ID,1 ∈{0}

[0258] Where m2 and m1 correspond to the cyclic shifts of the Z4 sequence and the m sequence in the TSS, and CS represents the six cyclic shifts of the SSS sequence. The scrambled m sequence used in the TSS is the PSS sequence.

[0259] Specifically, the initial value and primitive polynomial required for generating the downlink synchronization signal sequence are as follows:

[0260] PSS: primitive polynomial 10000011, initial value [0,1,1,0,1,1,1];

[0261] SSS: Z4 sequence primitive polynomial: 10020013, initial value [1,0,0,0,0,0,0], cyclic shift value 15*[0,1,2,3,4,5];

[0262] TSS: Z4 sequence primitive polynomial: 10020013, initial value [1,0,0,0,0,0,0], where m0 and m1 correspond to the cyclic shifts of the two sequences.

[0263] Further, please refer to Table 6, which is the downlink synchronization signal correlation index in Example 3 provided in an embodiment of the present application.

[0264] Table 6

[0265] The method provided in the embodiments of the present application is described in detail above in conjunction with Figures 4 to 7. Below, the apparatus provided in the embodiments of the present application is described in detail in conjunction with Figures 8 and 9. It should be understood that the description of the apparatus embodiment corresponds to the description of the method embodiment. Therefore, for matters not described in detail, reference can be made to the method embodiment above, and for the sake of brevity, they will not be repeated here.

[0266] The device is used to implement the above-mentioned embodiments and related implementation methods, and the details that have been described will not be repeated here. As used below, the term "module" can refer to a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are implemented using software, implementation using hardware, or a combination of software and hardware, is also possible and contemplated.

[0267] FIG8 is a schematic structural diagram of a communication device provided in an embodiment of the present application.

[0268] The communication device 800 includes a transceiver unit 810 and a processing unit 820 , wherein the transceiver unit 810 can be used to implement corresponding communication functions, and the processing unit 820 can be used to perform data processing.

[0269] Optionally, the transceiver unit 810 may also be referred to as a communication interface or communication unit, and may include a transmitting unit and / or a receiving unit. The transceiver unit 810 may be a transceiver (including a transmitter and / or a receiver), an input / output interface (including an input and / or output interface), a pin, or a circuit. The transceiver unit 810 may be configured to perform the transmitting and / or receiving steps in the above-described method embodiments.

[0270] Optionally, the processing unit 820 may be a processor (may include one or more), a processing circuit with processor functions, etc., and may be used to execute other steps except sending and receiving in the above method embodiment.

[0271] Optionally, the communication device 800 further includes a storage unit, which may be a memory, an internal storage unit (e.g., a register, a cache, etc.), an external storage unit (e.g., a read-only memory, a random access memory, etc.), etc. The storage unit is used to store instructions, and the processing unit 820 executes the instructions stored in the storage unit to enable the communication device to perform the above method.

[0272] In one design, the communication device 800 can be used to perform the actions performed by the terminal device in each of the above method embodiments, for example, the communication device 800 can be used to perform the actions performed by the terminal device in the above description. In this case, the communication device 800 can be a component of the terminal device, the transceiver unit 810 is used to perform the transceiver-related operations on the terminal device side in the above method embodiments, and the processing unit 820 is used to perform the processing-related operations of the terminal device in the above method embodiments.

[0273] For example, the transceiver unit 810 is used to receive a synchronization signal block, where the synchronization signal block includes a first synchronization signal and a second synchronization signal, and the first synchronization signal indicates the frequency domain positions of the second synchronization signal and the third synchronization signal.

[0274] It should be understood that the transceiver unit 810 can also perform other operations performed by the terminal device in any of the above methods, which will not be described in detail here.

[0275] In one design, the communication device 800 can be used to perform the actions performed by the network device in each of the above method embodiments, for example, the communication device 800 can be used to perform the actions performed by the network device in the above method. In this case, the communication device 800 can be a component of a terminal device, the transceiver unit 810 is used to perform the transceiver-related operations on the network device side in the above method embodiments, and the processing unit 820 is used to perform the processing-related operations of the network device in the above method embodiments.

[0276] For example, the transceiver unit 810 is used to send a synchronization signal block, where the synchronization signal block includes a first synchronization signal and a second synchronization signal, and the first synchronization signal indicates the frequency domain positions of the second synchronization signal and the third synchronization signal.

[0277] It should be understood that the transceiver unit 810 and the processing unit 820 may also perform other operations performed by the network device in any of the above methods, which will not be described in detail here.

[0278] It should also be understood that the communication device 800 here is embodied in the form of a functional unit. The term "unit" here can refer to an application specific integrated circuit (ASIC), an electronic circuit, a processor (such as a shared processor, a dedicated processor or a group processor, etc.) and a memory for executing one or more software or firmware programs, a combined logic circuit and / or other suitable components that support the described functions. In an optional example, those skilled in the art will understand that the communication device 800 can be specifically a network device in the above-mentioned embodiment, and can be used to execute the various processes and / or steps corresponding to the network device in the above-mentioned method embodiments. To avoid repetition, they will not be described here.

[0279] The communication device 800 of each of the above-mentioned solutions has the function of implementing the corresponding steps performed by the device in the above-mentioned method, or the communication device 800 of each of the above-mentioned solutions has the function of implementing the corresponding steps performed by the access network device in the above-mentioned method. The function can be implemented by hardware, or the corresponding software can be implemented by hardware. The hardware or software includes one or more modules corresponding to the above-mentioned functions; for example, the transceiver unit can be replaced by a transceiver (for example, the sending unit in the transceiver unit can be replaced by a transmitter, and the receiving unit in the transceiver unit can be replaced by a receiver), and other units, such as the processing unit, can be replaced by a processor to respectively perform the sending and receiving operations and related processing operations in each method embodiment.

[0280] In addition, the transceiver unit 810 may also be a transceiver circuit (for example, may include a receiving circuit and a sending circuit), and the processing unit may be a processing circuit.

[0281] It should be noted that the apparatus in FIG8 may be a network element or device in the aforementioned embodiment, or may be a chip or chip system, such as a system on chip (SoC). The transceiver unit may be an input / output circuit or a communication interface; the processing unit may be a processor, microprocessor, or integrated circuit integrated on the chip. This is not limited here.

[0282] FIG9 is a schematic diagram of a communication architecture provided in an embodiment of the present application.

[0283] The communication device 900 shown in Figure 9 includes a processor 910 and, optionally, one or more of a memory 920 and a transceiver 930. The processor 910 is coupled to the memory 920 and configured to execute instructions stored in the memory 920 to control the transceiver 930 to send and / or receive signals.

[0284] It should be understood that the processor 910 and memory 920 described above can be combined into a single processing device, with the processor 910 being configured to execute program code stored in the memory 920 to implement the aforementioned functions. In a specific implementation, the memory 920 can also be integrated into the processor 910 or independent of the processor 910. It should be understood that the processor 910 can also correspond to the various processing units in the aforementioned communication device, and the transceiver 930 can correspond to the various receiving units and transmitting units in the aforementioned communication device.

[0285] It should also be understood that the transceiver 930 may include a receiver (or receiver) and a transmitter (or transmitter). The transceiver may further include an antenna, and the number of antennas may be one or more. The transceiver may also be a communication interface or interface circuit.

[0286] Specifically, the communication device 900 may correspond to a terminal device in the method according to an embodiment of the present application. The communication device 900 may execute the steps performed by the terminal device in the method; the communication device 900 may correspond to a network device in the method according to an embodiment of the present application. The communication device 900 may execute the steps performed by the network device in the method. It should be understood that the specific processes of the above-mentioned corresponding steps have been described in detail in the above-mentioned method embodiment and will not be repeated here for the sake of brevity.

[0287] When the communication device 900 is a chip, the chip includes an interface unit and a processing unit, wherein the interface unit may be an input / output circuit or a communication interface; and the processing unit may be a processor, microprocessor, or integrated circuit integrated on the chip.

[0288] During implementation, each step of the above method can be completed by an integrated logic circuit of the hardware in the processor or by instructions in the form of software. The steps of the method disclosed in conjunction with the embodiments of the present application can be directly embodied as being executed by a hardware processor, or can be executed by a combination of hardware and software modules in the processor. The software module can be located in a storage medium mature in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in conjunction with its hardware. To avoid repetition, it will not be described in detail here.

[0289] It should be noted that the processor in the embodiments of the present application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiment can be completed by an integrated logic circuit of the hardware in the processor or by instructions in the form of software. The above processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component. The various methods, steps, and logic block diagrams disclosed in the embodiments of the present application can be implemented or executed. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in the embodiments of the present application can be directly embodied as being executed by a hardware decoding processor, or can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium mature in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, or electrically erasable programmable memory, registers, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0290] The present application also provides a computer-readable medium having a computer program stored thereon, which implements the functions of any of the above method embodiments when executed by a computer.

[0291] The present application also provides a computer program product, which implements the functions of any of the above method embodiments when executed by a computer.

[0292] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments may be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated therein. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a high-density digital video disc (DVD)), or a semiconductor medium (eg, a solid state disk (SSD)).

[0293] In the embodiments of this application, words such as "exemplary" and "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of the word "exemplary" is intended to present concepts in a concrete way.

[0294] It should be understood that references to "embodiments" throughout this specification mean that a particular feature, structure, or characteristic associated with the embodiment is included in at least one embodiment of the present application. Therefore, various embodiments throughout this specification do not necessarily refer to the same embodiment. Furthermore, these particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0295] It should be understood that in the various embodiments of the present application, the size of the sequence number of each process does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application. The names of all nodes and messages in this application are merely names set by this application for the convenience of description. The names in the actual network may be different. It should not be understood that this application limits the names of various nodes and messages. On the contrary, any name with the same or similar function as the node or message used in this application is regarded as the method or equivalent replacement of this application, and is within the scope of protection of this application.

[0296] It should also be understood that in this application, "when", "if" and "if" all mean that the UE or base station will take corresponding measures under certain objective circumstances. It does not limit the time, and does not require the UE or base station to take judgment actions when implementing it, nor does it mean that there are other limitations.

[0297] Additionally, the terms "system" and "network" are often used interchangeably. The term "and / or" is simply used to describe an association between related objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone.

[0298] As used herein, the term "at least one of" or "at least one of" refers to all or any combination of the listed items. For example, "at least one of A, B, and C" can mean: A alone, B alone, C alone, A and B together, B and C together, and A, B, and C together. As used herein, "at least one" means one or more. "A plurality" means two or more.

[0299] It should be understood that the terms "include", "comprising", "having" and their variations mean "including but not limited to", unless specifically emphasized otherwise.

[0300] It should be understood that in various embodiments of the present application, the first, second, and various numerical numbers are merely distinctions for ease of description and are not intended to limit the scope of the embodiments of the present application.

[0301] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0302] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the description of the corresponding processes and beneficial effects in the aforementioned method embodiments, and will not be repeated here.

[0303] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0304] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0305] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0306] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, part of the technical solution of the present application can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0307] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A communication method, characterized in that: include: Sending a synchronization signal block, where the synchronization signal block includes a first synchronization signal and a second synchronization signal, where the first synchronization signal indicates frequency domain positions of the second synchronization signal and the third synchronization signal; The third synchronization signal is sent at the frequency domain position, and the second synchronization signal and the third synchronization signal indicate a physical cell identifier PCI of a cell to be accessed.

2. The method according to claim 1, characterized in that The second synchronization signal and the third synchronization signal can indicate the PCIs of N cells, the PCI of the cell to be accessed belongs to the PCIs of the N cells, and N is greater than 1008.

3. The method according to claim 1 or 2, characterized in that The first synchronization signal is a primary synchronization signal PSS and / or the second synchronization signal is a secondary synchronization signal SSS.

4. The method according to any one of claims 1 to 3, characterized in that The third synchronization signal is adjacent to the synchronization signal block in the time domain.

5. The method according to any one of claims 1 to 4, characterized in that The first synchronization signal indicates a first parameter, the second synchronization signal indicates a second parameter, and the third synchronization signal indicates a third parameter. The first parameter, the second parameter, and the third parameter are used to determine the PCI of the cell to be accessed.

6. The method according to claim 5, characterized in that The first parameter belongs to a first parameter set, the second parameter belongs to a second parameter set, and the third parameter belongs to a third parameter set, and the first parameter, the second parameter, and the third parameter are used to determine the PCI of the cell to be accessed, including: The first parameter, the second parameter, and the third parameter are used to determine the PCI of the cell to be accessed together with the first value and the second value, wherein the first value and the second value correspond to the number of elements in two parameter sets in the first parameter set, the second parameter set, and the third parameter set, respectively.

7. The method according to claim 6, characterized in that The PCI value satisfies Where (m,n,k)∈{0,1,2} 3 And the values ​​of m, n, and k are all different; is the kth parameter, s k is the number of elements in the kth parameter set, is the mth parameter, s m is the number of elements in the mth parameter set, is the nth parameter, s n is the number of elements in the nth parameter set.

8. The method according to claim 6 or 7, characterized in that The number of elements in the first parameter set is less than 3.

9. The method according to any one of claims 6 to 8, characterized in that The number of elements in the second parameter set is less than the number of elements in the third parameter set, and the second synchronization signal further indicates index information, which includes subframe index information and / or beam index information of the synchronization signal block.

10. The method according to claim 9, characterized in that The third synchronization signal is encoded using a Z4 sequence scrambled by an m sequence.

11. The method according to claim 10, characterized in that The number of elements in the first parameter set is 1, the second parameter set is {0, 1, 2, ..., L}, the m-sequence used by the third synchronization signal corresponds to the first cyclic shift parameter m1, and m1 satisfies: The Z4 sequence used by the third synchronization signal corresponds to the second cyclic shift parameter m2, and m2 satisfies: The γ is a positive integer, the L is a positive integer, and the α is a positive integer less than or equal to the length of the third synchronization sequence.

12. The method according to claim 11, characterized in that The γ is greater than 1.

13. The method according to any one of claims 1 to 12, characterized in that The second synchronization signal adopts any one of the following encoding modes: m sequence, gold sequence, Z4 sequence, and Z4 sequence scrambled by m sequence.

14. A communication method, characterized in that: include: receiving a synchronization signal block, the synchronization signal block including a first synchronization signal and a second synchronization signal, the first synchronization signal indicating frequency domain positions of the second synchronization signal and a third synchronization signal; At the frequency domain position, the third synchronization signal is received, where the second synchronization signal and the third synchronization signal indicate a physical cell identifier (PCI) of a cell to be accessed.

15. The method according to claim 14, characterized in that The second synchronization signal and the third synchronization signal can indicate the PCIs of N cells, the PCI of the cell to be accessed belongs to the PCIs of the N cells, and N is greater than 1008.

16. The method according to claim 14 or 15, characterized in that The first synchronization signal is a primary synchronization signal PSS and / or the second synchronization signal is a secondary synchronization signal SSS.

17. The method according to any one of claims 14 to 16, characterized in that The third synchronization signal is adjacent to the synchronization signal block in the time domain.

18. The method according to any one of claims 14 to 17, characterized in that The first synchronization signal indicates a first parameter, the second synchronization signal indicates a second parameter, and the third synchronization signal indicates a third parameter. The method further includes: Determine the PCI of the cell to be accessed according to the first parameter, the second parameter, and the third parameter.

19. The method according to claim 18, characterized in that The determining, according to the first parameter, the second parameter, and the third parameter, of the PCI of the cell to be accessed includes: Determine the PCI of the cell to be accessed according to the first parameter, the second parameter, the third parameter, a first value, and a second value, wherein the first parameter belongs to a first parameter set, the second parameter belongs to a second parameter set, the third parameter belongs to a third parameter set, and the first value and the second value correspond to the number of elements in two parameter sets of the first parameter set, the second parameter set, and the third parameter set, respectively.

20. The method according to claim 19, wherein The PCI value satisfies Where (m,n,k)∈{0,1,2} 3 And the values ​​of m, n, and k are all different; is the kth parameter, s k is the number of elements in the kth parameter set, is the mth parameter, s m is the number of elements in the mth parameter set, is the nth parameter, s n is the number of elements in the nth parameter set.

21. The method according to claim 19 or 20, characterized in that The number of elements in the first parameter set is less than 3.

22. The method according to any one of claims 19 to 21, characterized in that The number of elements in the second parameter set is less than the number of elements in the third parameter set, and the second synchronization signal further indicates index information, which includes subframe index information and / or beam index information of the synchronization signal block.

23. The method according to claim 22, characterized in that The third synchronization signal is encoded using a Z4 sequence scrambled by an m sequence.

24. The method according to claim 23, wherein The number of elements in the first parameter set is 1, the second parameter set is {0, 1, 2, ..., L}, the m-sequence used by the third synchronization signal corresponds to the first cyclic shift parameter m1, and m1 satisfies: The Z4 sequence used by the third synchronization signal corresponds to the second cyclic shift parameter m2, and m2 satisfies: The γ is a positive integer, the L is a positive integer, and the α is a positive integer less than or equal to the length of the third synchronization sequence.

25. The method according to claim 24, characterized in that The γ is greater than 1.

26. The method according to any one of claims 14 to 25, characterized in that The second synchronization signal adopts any one of the following encoding modes: m sequence, gold sequence, Z4 sequence, and Z4 sequence scrambled by m sequence.

27. A communication device, characterized in that: The communication device is configured to execute the method according to any one of claims 1 to 13 or 14 to 26.

28. A communication device, characterized in that: The communication device includes at least one processor, and the at least one processor is configured to execute a computer program or instruction so that the method according to any one of claims 1 to 13 is executed, or the method according to any one of claims 14 to 26 is executed.

29. The communication device according to claim 28, wherein: The communication device further comprises at least one memory for storing the computer program or instructions.

30. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program or instruction. When the computer program or instruction is executed on a computer, the method according to any one of claims 1 to 13 is executed, or the method according to any one of claims 14 to 26 is executed.

31. A computer program product, characterized in that When the computer program product is run on a computer, the method according to any one of claims 1 to 13 is executed, or the method according to any one of claims 14 to 26 is executed.

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