Method and system for the electrical transmission of symbols

Abstract

The invention also relates to a method and a system for the electrical transmission of symbols from a first subscriber to a second subscriber, which symbols are connected via a common multi-conductor system comprising at least one first electrical conductor, one second electrical conductor and one third electrical conductor, at least three series circuits each formed of an upper electronic switch and a lower electronic switch being operated in the first subscriber, the electrical conductors being connected to the respective series circuit between the upper electronic switch and the lower electronic switch.

Description

[0001] Description

[0002] Method and system for the electrical transmission of symbols

[0003] The problem underlying the invention lies in the electrical transmission of information between two or more devices connected via a common group of electrical conductors (bus). A particular challenge here is increasing the achievable transmission rate while simultaneously ensuring robustness against internal and external interference during operation.

[0004] The invention relates to a system for transmitting symbols between a first subscriber and a second subscriber via a common multi-wire system.

[0005] The invention also relates to a method for the electrical transmission of symbols from a first subscriber to a second subscriber, which are connected via a common multi-conductor system with at least one first electrical conductor, one second electrical conductor and one third electrical conductor, wherein in the first subscriber at least three series circuits each comprising an upper electronic switch and a lower electronic switch are operated, wherein the electrical conductors are connected to the respective series circuit between the upper electronic switch and the lower electronic switch.

[0006] Currently, various approaches exist for implementing wired information transmission. In classic parallel buses, several asymmetric lines are bundled, with each line carrying information in its potential difference to a common reference signal, usually 1 bit per line with a binary level system. A receiver typically evaluates this information using hard decision thresholds. Combined with the often uncontrolled line matching, this type of transmission suffers from high sensitivity to internal and external interference and can typically only be operated at low baud rates due to various high-frequency effects (reflections, limited signal power, crosstalk, EMC interference, etc.).

[0007] Differential line systems, such as LVDS, CML, or PECL, generally do not share these signal integrity issues and allow operation even at very high baud rates. However, these systems scale poorly in terms of information transmission efficiency, cost, and power consumption. Typically, 1 bit of data can be transmitted over a coupled two-wire line, which corresponds to an efficiency of 0.5 bits per line.

[0008] The ET200SP system, a distributed automation system from Siemens, uses a special backplane bus system to solve this problem. Using special coding methods, it has been possible to eliminate many of the signal integrity issues from a conventional parallel bus, thus achieving significant data rates on a reliable, long-distance bus with numerous nodes. However, the system no longer allows for any further (significant) performance improvements.

[0009] EP 1 038 232 B1 describes a communication interface for the serial transmission of digital data or a serial data transmission method for the bit-by-bit transmission of digital data.

[0010] This solution addresses the problem of interference and synchronization in serial data transmission. It consists of a communication interface and a data transmission method that enable interference-free and efficient transmission of digital data. The innovation uses at least three signal lines, each of which can carry a "high" or "low" level. A data bit is encoded by the level change of two of the three lines, with the transitions between the level states defined in a coding scheme. This enables fast synchronization and high data rates, comparable to synchronous transmission, without the disadvantages of clock recovery or asynchronous transmission. Start / stop synchronization is achieved by inverting all levels, which is particularly efficient for short data packets.The invention is particularly suitable for use in automation devices for controlling and monitoring technical processes.

[0011] EP 2 154 590 B1 relates to a method for slot recognition of control modules in a modular control device. Patent EP 2 154 590 B1 describes a method for slot recognition in modular control devices, such as programmable logic controllers (PLCs). The innovation lies in the unique and simplified addressing of control modules via their slots. This is achieved through a special data pattern that is sent over the communication bus and permuted at each slot transition, so that each slot receives a unique pattern. The bus lines are divided into groups within which the permutation takes place, increasing the number of addressable slots. The method enables modules to be changed during operation without the need for reconfiguration.The advantages include high availability and modular expandability of the control unit without active backplane bus components, which increases reliability and minimizes space requirements. User data can be transmitted simultaneously with the address data, increasing system efficiency.

[0012] The method described in EP 0 150 540 A2 relates to data transmission between multiple stations via a shared data bus, where the signals are linked via an OR function. The core of this solution involves the periodic transmission of each data bit within specified subperiods that have a specific relationship to each other. At the beginning of each period, a signal transition is generated that determines the total period duration and the position of the subperiods. In the first subperiod, a signal is sent that indicates the data bus as "occupied." In the second subperiod, the actual data bit is transmitted. In the third subperiod, a signal without information content is sent. The stations are able to determine the period duration from the signal transitions and determine the state of the data bus and the value of the transmitted data bit.This enables efficient data transmission even with different internal clock frequencies of the stations and supports multi-master operation.

[0013] The disclosure in EP 0 977 126 A2 relates to an interface circuit for connecting devices via a bidirectional bus, in particular an I2C bus, which uses a data line and a clock line for signal transmission. The innovation therein lies in the fact that the signals of the I2C bus are divided into transmit and receive branches and transmitted via differential transmitter / receiver modules using differential lines. This enables interference-resistant data transmission even over long distances by minimizing physical interference caused by differential signal transmission. The circuitry on each device includes optocouplers for galvanic isolation and to prevent interference caused by potential differences. The receivers of the bus drivers are constantly active, while the transmitters are only activated when a "0" is transmitted, which is controlled by an enable logic.The differential lines are terminated at their ends by resistors representing the characteristic impedance to generate the bus potentials when the transmitters are deactivated. This interface circuit is particularly suitable for error-free data transmission between devices in microsurgery, such as a TEM insufflation system, while maintaining the transmission frequency and protocols of the I2C bus. The invention enables improved data communication between medical devices, which is crucial for precise and reliable functions.

[0014] DE 60 126 191 T2 presents a CMOS bus driver circuit specifically designed to solve problems that arise when a higher voltage than the supply voltage is applied to the circuit output. This can occur when various integrated circuits with different supply voltages are connected via a bus. The circuit consists of an input stage with two complementary MOS transistors and an output stage, also with two complementary MOS transistors. A key feature of the invention is the integration of an additional MOS transistor between the circuit output and the gate terminal of a transistor in the output stage. This transistor is controlled by the supply voltage and protects the circuit by switching to the conducting state when the voltage at the output is too high, thus blocking the corresponding output transistor.A diode in the input stage prevents current flow toward the transistor connected to the supply voltage, thus protecting against reverse currents. Another MOS transistor in parallel with the diode ensures that the diode is bypassed during normal operation, allowing the circuit to quickly enter the off-state. A blocking circuit section, consisting of an additional MOS transistor, an inverter, and a NOR circuit, places the output stage in a high-impedance state when no enable signal is present, thus preventing current from flowing from the bus into the circuit. This solution allows the circuit to operate reliably even at narrow supply voltage ranges and protects it from damage caused by voltages higher than the supply voltage.

[0015] EP 4 226 254 A1 discloses a method and apparatus for data communication via a serial three-wire bus interface, particularly relevant to the C-PHY interface of the MIPI Alliance. The invention relates to the generation of multiple differential signals, each representing the voltage difference between a pair of wires in a three-wire bus. An essential feature of the invention is the identification of a differential signal with the largest voltage magnitude within a specific time interval, the so-called unit interval (Ul), and the determination of the signal state of the three-wire bus for this Ul based on the identity of the wire pair providing the first differential signal and the polarity of this signal in Ul. The invention enables the generation of a first edge in a clock signal that responds to a transition in the first differential signal during Ul.This improves clock signal recovery and reliable wire state detection at higher data rates. The invention also includes a calibration circuit for adjusting the equalizer circuits in the differential receivers based on the number of LILs during a C-PHY preamble in which the first differential signal has the largest voltage magnitude. The invention is particularly important for improving data transmission and processing in mobile devices such as smartphones and tablets that connect cameras and displays via C-PHY interfaces.

[0016] US 9 692 555 B2 relates to the transmission of information over a multi-wire line, receiving a set of symbols. A key aspect of the invention is the use of a first two-input comparator connected to the multi-wire bus to generate a first output signal based on a comparison of a pair of symbols with different values. An arithmetic circuit receives the symbol pair and generates an arithmetic result, which is then used by a second two-input comparator to generate a second output signal. This second output signal represents a comparison of the arithmetic result with a third symbol that is not part of the pair. The invention makes it possible to reduce the number of comparators required, resulting in a simpler and less energy-intensive system configuration.The invention can also be applied recursively to design larger Sparse Comparator Units (SCUs) from smaller SCUs, increasing the flexibility and scalability of the system.

[0017] The device and method presented in DE 10 2006 061 651 B4 are used to encode blocks of transform coefficients used in digital image compression methods such as JPEG2000. The coefficients are represented by several magnitude bits arranged in bit planes. The encoding device processes these magnitude bits in tuples and encodes them into a data stream. Each magnitude bit belongs to one of three passes. A special feature is the prediction device, which predicts which magnitude bits are to be encoded in the next tuple. This is based on a previous prediction and the status information of the coefficients. The prediction enables the encoding device to efficiently decide which bits should be encoded. The data words are stored in buffers and then entropy encoded, maintaining the order of the passes.The device enables efficient hardware implementation for image compression by reducing the number of processing steps and allowing parallel processing of multiple coefficients. This optimizes computational performance, which is particularly advantageous for complex coefficient bit modeling.

[0018] EP 3 637 715 B1 relates to a transmission device and a reception device designed for the efficient transmission of data streams, in particular image data, over multiple parallel transmission paths (tracks). The invention enables training processing to be performed for synchronization and correction of time differences between the tracks when certain parameters affecting the processing of the physical layer, such as the number of transmission paths or the transmission rate, change. However, if link layer parameters, such as bit length per pixel or number of lines, are changed, the transmission of the data stream can continue without this training processing. This increases efficiency because no unnecessary interruptions occur. The invention also includes methods for signaling parameter changes by using flags or by directly transmitting the changed parameters in the packet header.This technology is particularly relevant for systems that require fast and reliable transmission of large amounts of data, such as in medical imaging or endoscopy systems.

[0019] EP 2 683 124 B1 relates to a transmitting / receiving device for digital data transmissions according to the Low-Voltage Differential Signaling (LVDS) standard, which is used particularly in automation technology. The device comprises a transmitting unit, a receiving unit, and a protocol means. The novelty lies in a special circuit arrangement that enables faster signal settling at the receiving unit and thus ensures error-free signal transmission even over longer data transmission distances. This is achieved by arranging capacitors and resistors in the receiving longitudinal branches, with the values ​​of these components being specifically adapted. In addition, AC coupling means enable potential isolation, which facilitates use in modules with different power supplies.The invention thus addresses the problems of limited cable length and potential difference in conventional LVDS connections and allows for improved and more robust data transmission in automation systems.

[0020] The LVDS driver (Low Voltage Differential Signaling Driver) presented in DE10 155 526 C2 is designed for use with low supply voltages of less than 2V, which is particularly relevant for integrated circuits with high structure density. The invention lies in the use of exclusively PMOS transistors for the pull-up and pull-down functions, which enables symmetrical switching behavior and operation in the linear range. By limiting the maximum amplitude of the control signals to a value just above the turn-on threshold voltage of the transistors, it is ensured that the transistors can effectively switch between the off and on states without the switching quality suffering from low supply voltages.

[0021] The object of the invention is to further develop the already known systems and methods for transmitting symbols in order to achieve an increase in performance in data transmission with regard to data rates.

[0022] The solution to the problem particularly comprises a system for transmitting symbols between a first subscriber and a second subscriber, which are connected via a common multi-conductor system with a first electrical conductor, a second electrical conductor, and a third electrical conductor. The first subscriber comprises a symbol encoder, a power source module, and a control block. The control block has an upper control block and a lower control block. The upper control block is configured to close and open upper switches, and the lower control block is configured to open and close lower switches.The upper switches have at least three upper electronic switches and the lower switches have at least three lower electronic switches. At least three series circuits, each consisting of an upper electronic switch and a lower electronic switch, are arranged, and the electrical conductors are connected to the respective series circuit between the upper electronic switch and the lower electronic switch, wherein the current source module is connected to the series circuits. This object is achieved in that the symbol encoder is designed to provide a current loop control vector for the control block, wherein the control block is designed to switch the electronic switches by means of the current loop control vector, which has a switching combination for the electronic switches, and thus to enable a current flow into the connected electrical conductors.The symbol encoder is designed to determine the current loop control vector such that the symbols to be transmitted are determined and thus encoded by an ordered selection of a conductor pair from a pool of electrical conductors in the multi-conductor system. A conductor pair comprises one of the electrical conductors as a forward conductor of a current from the first subscriber to the second subscriber and another of the electrical conductors as a return conductor. Furthermore, a termination unit is provided, wherein the symbol encoder is designed to provide a termination vector for the termination unit. The termination unit, in turn, is designed to connect a termination resistor network to the electrical conductors of the multi-conductor system by means of a termination switch.The second participant has a comparator network, wherein the comparator network is designed to detect a voltage level between two electrical conductors in order to decode the symbol, wherein the symbol is encoded in the different voltage levels between the electrical conductors.

[0023] For the purposes of the invention, an upper electronic switch and a lower electronic switch are to be understood as a half-bridge consisting of two switches that are connected in series to a voltage source or current source. Accordingly, for the purposes of the invention, the upper electronic switch and the lower electronic switch are each, for example, a semiconductor switch, wherein the upper electronic switch is placed in an upper circuit with respect to a terminating resistor, and the lower electronic switch is placed in a lower circuit with respect to a terminating resistor. One also speaks of a high-side driver (power supply - switch to a first output of the current source module) and a low-side driver (ground - switch to a second output of the current source module). In an advantageous embodiment, the switches can be controlled in such a way that the potential of the current source orVoltage source is not completely switched through and thus different currents can be impressed into the terminating resistor and thus different signal voltages, in particular more than two different signal voltages, can be generated.

[0024] Advantageously, the selective configuration of signal paths is now used to encode a symbol. A basic idea of ​​the method is to encode the transmission information in the ordered selection of one or more conductor pairs from the supply of a multi-conductor system. The information is encoded within the ordered conductor selection. The invention is particularly suitable for use in automation devices for controlling and monitoring technical processes. Conventional digital parallel bus systems offer a high information density per bus line, but are very susceptible to signal integrity problems and therefore cannot be operated with high signaling rates. Single- or multi-point differential conductor systems are very robust against self- and external interference, but do not offer a high information density. Analog or hybrid transmission methods (such asOFDM) solve this problem, but require system components that require significant implementation effort, which also has a noticeable impact on power consumption during operation. The invention now makes it possible to eliminate the disadvantages of conventional methods in a cost-effective, scalable way in a system.

[0025] A further embodiment provides that the symbol encoder is designed to provide a plurality of current loop control vectors, wherein the control block is designed to operate the common multi-conductor system with a plurality of current loops.

[0026] Thus, in a conductor system with N conductors, a total of N*(N-1) different possibilities are available for imprinting a first current loop, which is extracted from the transmit symbol stream by the symbol encoder using a first current loop control vector. The flow of a second current loop can now be selected using the same scheme into a reduced set of conductors, opening up a possibility space of (N-2)*(N-3) for the second current loop control vector. This control vector is also extracted from the transmit symbol stream by the symbol encoder. This process can now be continued for additional current loops, as long as the remaining supply of conductors is sufficiently large. Overall, this rule results in a possibility space of N! / (N - 2L)! symbols for how the L current loops can be imprinted on the N lines.Accordingly, for further coding of the symbols to be transmitted, a selected number L of current loops is determined from the number N of electrical conductors, thus increasing the symbol pool.

[0027] To further increase the symbol pool, the control block and / or the current source module are designed to inject different signal currents into each current loop. When using multiple conductor pairs, it is crucial that their signal currents are different in magnitude and reliably related to each other.

[0028] During receive mode, the comparator network is active and continuously records the relative voltage levels in the multi-wire system in a (digital) receive vector. A symbol decoder determines the output symbol stream from this receive vector. For this purpose, the comparator network is designed to assign the detected voltage levels as elements to a receive vector.

[0029] A further embodiment provides a symbol decoder, the symbol decoder is in turn designed to receive the receive vector and to carry out a maximum determination and a minimum determination on a sequence of the elements of the receive vector, and is further designed to provide a binary sequence in which the maximum level or the minimum level is marked as a position in the sequence.

[0030] The system is further improved by a gradual "reduction of the receive vector"; for this purpose, the system comprises a first discriminator, a second discriminator, a first reducer, and a second reducer. The first discriminator is configured as a min-max line pair discriminator and is thus configured to receive the receive vector and detect the line pair with the respective highest and lowest relative levels in the multi-line system, and is further configured to provide the detection result as first line pair information.The first discriminator is connected to the first reducer and is configured to provide a reduced receive vector using the first line pair information. The second discriminator is configured as a further min-max line pair discriminator and is thus configured to receive the reduced receive vector and detect the conductor pair with the respective highest and lowest relative level in the multi-conductor system with the already detected reduced conductor pair, and is further configured to provide the detection result as second line pair information. The second discriminator is connected to the second reducer and is configured to provide a further reduced receive vector using the second line pair information.

[0031] The present invention allows the construction of a bus-capable multi-conductor system for information transmission using simple, CMOS chip-integrated components. This system achieves similar signal integrity properties and transmission rates as, for example, LVDS, while simultaneously offering significantly more efficient information coding with a disproportionately low increase in power consumption. The following properties are crucial for this: At any given time, only a few current loops of varying strengths are impressed into the conductor system. Because the current loops can be clearly formed on the transmitter side based on their relative current strengths and recognized on the receiver side, information coding is achieved by selecting the individual conductors for the respective forward and return conductors of each current loop. A receiver can identify the individual current loops and determine their flow directions through a fast, iterative process.This requires only simple, purely binary queries using comparators. By using impedance-controlled and low-reflection routing techniques, as well as suitable termination, the transmission system is fundamentally capable of achieving the highest signaling rates with relatively low complexity and moderate power consumption.The object mentioned at the outset is also achieved by a method for the electrical transmission of symbols from a first subscriber to a second subscriber, which are connected via a common multi-conductor system with at least one first electrical conductor, one second electrical conductor and one third electrical conductor, wherein in the first subscriber at least three series circuits each comprising an upper electronic switch and a lower electronic switch are operated, wherein the electrical conductors are connected to the respective series circuit between the upper electronic switch and the lower electronic switch.The symbol to be transmitted is encoded by selecting a switching combination for the electronic switches in that an ordered selection of a conductor pair from a supply of electrical conductors from the multi-conductor system is carried out, whereby a current flows via a current source via a closed upper electronic switch from the first subscriber into one of the electrical conductors as a forward conductor into the multi-conductor system, whereby a terminating resistor network is connected to the electrical conductors of the multi-conductor system, and whereby a current path for the current flowing in the forward conductor is switched to another electrical conductor.The other electrical conductor is then used as a return conductor for the current via a closed lower electronic switch from the first station. In the second station, a voltage level is detected between each pair of electrical conductors to decode the symbol. The symbol is recovered from the different voltage levels between the electrical conductors. This allows for the selective creation of signal paths. The basic idea of ​​the method is to encode the transmission information in the ordered selection of one or more conductor pairs from the pool of the multi-conductor system. The conductor pairs are then used to conduct one or more signal streams.

[0032] In the multi-conductor system with N conductors, there are a total of N*(N-1) different possibilities for imprinting a first current loop. For a second current loop, there are (N-2)*(N-3) possibilities. Overall, according to this rule, there is a possible space of N! / (N - 2L)! symbols for how the current loops can be imprinted on the N lines. L specifies the number of current loops. Accordingly, the shared multi-conductor system is operated with a number N of electrical conductors, with current loops being formed between the first and second participants using the electronic switches of the electrical conductors and the terminating resistor network. For further encoding of the symbols to be transmitted, a selected number L of current loops is determined from the number of electrical conductors, thus increasing the symbol pool.Different signal currents are advantageously impressed into the individual current loops of the selected set L, thus further increasing the symbol pool.

[0033] The voltage levels between the electrical conductors are preferably detected using a comparator network, with the detected voltage levels being assigned as elements to a receive vector. The receive vector can be formed by scanning the individual conductors one after the other according to a convention, with the relative ratios of the voltage levels in the conductor system being detected one after the other in the receive vector. One convention could be the following, based on graph theory: The individual conductors represent nodes arranged on a circular line. In a four-conductor system, you would then have node A, node B, node C, and node D. Starting from node A, edges can be drawn between the nodes in a clockwise direction. Once you have arrived back at the starting node, the diagonals or cross connections can be drawn as edges.Accordingly, the edges represent the voltage levels between the nodes or conductors A->B, B->C, C->D, D->A, A->C, and B->D. A receive vector could look like this:

[0034] Receive vector = {+1V, +2V, -1V, 1V, 1V, 1V}

[0035] However, this convention is not binding; other conventions are also conceivable.

[0036] Preferably, the receive vector is fed to a symbol decoder, wherein, on the one hand, a maximum determination and, on the other hand, a minimum determination are performed on a sequence of the elements of the receive vector, and a binary sequence is provided in each case, in which the maximum level or the minimum level is marked as a position in the sequence. The decoding of the symbols in the symbol decoder can be performed in a multi-stage, iterative process for an unthinned and fully meshed comparator network. For this purpose, a "min-max line pair discriminator" detects the wire pair with the highest and lowest relative levels in the wire system and returns this information as line pair information.

[0037] In the event that several current loops with different signal currents are operated between the first subscriber and the second subscriber, the symbol is decoded as follows: In a first step, the voltage levels between the electrical conductors are detected using a comparator network, the detected voltage levels are assigned to a receive vector as elements; in a second step, the receive vector is fed to a symbol decoder, whereby on the one hand a maximum determination and on the other hand a minimum determination is carried out on a sequence of the elements of the receive vector and in each case a binary sequence is provided in which the maximum level or the minimum level is contained.the minimum level is marked as a position in the sequence; in a third step, the reception vector is reduced by the positions detected in the second step, whereby a reduced reception vector is determined; the reduced reception vector is continued in the first step until the reduced reception vector or a further reduced reception vector corresponds to a multi-conductor system with a number of conductors of N = 3.

[0038] In a preferred implementation with maximum performance, the comparator network contains a comparator for each unique wire pair in the wire system. If fewer comparators than wire pairs are used, this restricts the size of the receive vector as well as the complexity of the symbol decoder and leads to a reduced number of possible symbols, which limits the information throughput of the system. When thinning the comparator network, care should be taken that asymmetric thinning leads to a loss of the interchange tolerance of wires in the multi-wire system and thus the methods for address resolution and slot detection known from EP 2 154 590 B1 may no longer be applicable. A compromise is to thin the wires according to equal distances from one another, which maintains symmetry and thus the interchange tolerance.

[0039] After the first step, it is now known which pair of conductors represents the forward and return conductors for the current loop with the largest loop current. With this information, the receiving network, or rather the receiving vector, can be thinned out around these conductors, i.e., reduced, in preparation for the second step.

[0040] The present invention makes it possible to construct a bus-capable multi-conductor system for information transmission using simple, CMOS chip-integratable components. This system achieves similar signal integrity properties and transmission rates as, for example, LVDS, while simultaneously offering significantly more efficient information coding with a disproportionately low increase in power consumption. For this purpose, a semiconductor component is configured to function as a line driver for electrically transmitting symbols between a first subscriber and a second subscriber, which are connected via a common multi-conductor system with at least one first electrical conductor, one second electrical conductor, and one third electrical conductor. The line driver is configured to implement the method according to the claims.

[0041] Several embodiments of a system for data transmission between a first subscriber and a second subscriber via a common multi-wire system are shown in the drawing, which also explains the method. They show:

[0042] FIG 1 shows the principle of electrical transmission of symbols from a first subscriber to a second subscriber via a common multi-wire system,

[0043] FIG 2 a four-wire system with symbol transmission “BC”,

[0044] FIG 3 the four-wire system from FIG 2 with the symbol transmission “CB”,

[0045] FIG 4 a four-wire system with two current loops,

[0046] FIG 5 shows a typical arrangement of transceivers on a multi-wire system,

[0047] FIG 6 is a block diagram of a transceiver,

[0048] FIG 7 the principle of a control block,

[0049] FIG 8 a comparator network,

[0050] FIG 9 is a block diagram of a symbol encoder,

[0051] FIG 10 is a block diagram of a termination unit,

[0052] FIG 11 an illustration of the comparison relationships for different conductor systems,

[0053] FIG 12 shows a decoding example which extends to Figures 12A, 12B, 12C and 12D,

[0054] FIG 13 is an illustration of a reduction of the reception vector, which extends to Figures 13A, 13B and 13C,

[0055] FIG 14 a possible realization of a comparator,

[0056] FIG 15 a first step of the evaluation of the reception vector with subsequent reduction,

[0057] FIG 16 a second step of reduction

[0058] FIG 17 a tabular overview of the reduction,

[0059] FIG 18 a third step of reduction,

[0060] FIG 19 a fourth step of reduction, FIG 20 a fifth step of reduction,

[0061] FIG 21 an illustration of an integration of units into a transceiver circuit,

[0062] FIG 22 Transceiver circuit on a multi-wire system,

[0063] FIG 23 possible bus topologies,

[0064] FIG 24 a parallel operation of different conductor systems,

[0065] FIG 25 shows a termination in parallel operation, FIG 26 shows a dynamic termination, and

[0066] FIG 27 a mixed operation between LVDS and multi-wire system.

[0067] 1 shows a first subscriber 1 and a second subscriber 2 which can exchange symbols Sym via a common multi-conductor system 200 by means of electrical signal transmission. For this purpose, the first subscriber 1 is connected to the second subscriber 2 via the multi-conductor system 200 by means of a first electrical conductor 201, a second electrical conductor 202 and a third electrical conductor 203. For electrical signal transmission and thus the transmission of symbols Sym, at least three series circuits P1, P2, P3, each consisting of an upper electronic switch A1, B1, C1 and a lower electronic switch A2, B2, C3, are operated in the first subscriber 1. The first electrical conductor 201 is connected between the two switches A1, A2 to the first series circuit P1, comprising a first upper electronic switch A1 and a first lower electronic switch A2.In the second series circuit P2 and the third series circuit P3, a similar procedure is followed with the second electrical conductor 202 and the third electrical conductor 203, respectively. The electrical switches are designed, for example, as C-MOS chip-integratable semiconductor components.

[0068] The symbol Sym to be transmitted (see also FIG 2) is encoded by selecting a switching combination SK for the electronic switches A1, B1, C1, A2, B2, A2 in that an ordered selection of a conductor pair from a supply of electrical conductors 201, 202, 203 from the multi-conductor system 200 is carried out by controlling the corresponding electronic switch A1, B1, C1. Via a current source Q, a current is conducted from the first subscriber 1 via a respectively controlled and thus closed upper electronic switch A1, B1, C1 into one of the electrical conductors 201, 202, 203, which then flows as the forward conductor HL into the multi-conductor system 200.

[0069] In the second participant 2 or outside the second participant 2, a terminating resistor network 501 is connected to the electrical conductors 201, 202, 203 of the multi-conductor system 200, thereby connecting a current path SW for the current I flowing in the forward conductor HL via a star point SP to another electrical conductor 201, 202, 203. The other electrical conductor is then used as a return conductor RL for the current I via a closed lower electronic switch A2, B2, C2 by the first participant 1. To decode the transmitted symbol Sym, a voltage level AB, CB, CA is detected between each two electrical conductors 201, 202, 203 in the second participant 2, and the symbol Sym is recovered from the different voltage levels between the electrical conductors.

[0070] In the termination resistor network 501, the voltages between the electrical conductors 201, 202, 203 are measured.

[0071] FIG. 2 explains the transmission principle described in FIG. 1 in more detail and shows how switching combinations SK are applied to the electronic switches A1, B1, C1, A2, B2, C2 and how a symbol Sym = “BC” can be transmitted.

[0072] According to the invention, a selective creation of signal paths is used. The basic idea of ​​the method is to encode transmission information in an ordered selection of one or more conductor pairs from the pool of the multi-conductor system 200.

[0073] FIG 2 essentially shows the first participant 1 with its upper and lower electronic switches A1, B1, C1, A2, B2, C2, a terminating resistor network 501, an illustration of the voltage taps of the voltage levels AB, BC, CA, CB, DB, AC and a coding rule from which the switching combination SK is obtained.

[0074] The upper electronic switches A1, B1, C1 are designed to connect the electrical conductors 201, 202, 203 to a first output of the power source Q and the lower switches A2, B2, C2 are designed to connect the electrical conductors 201, 202, 203 to a second output of the power source Q

[0075] Assuming that the symbol Sym = "BC" is to be transmitted to the multi-wire system 200, according to the coding rule of a coding table, the symbol Sym = "BC" in the fourth position in the coding table results in a switching combination for "B" = 1011 and a switching combination SK for "C" = 0010. The coding table is divided into switching combinations SK for the upper electronic switches A1, B1, C1, D1 and switching combinations SK for the lower electronic switches A2, B2, C2, D2. As a whole, this will later also be referred to as control block 300, with the upper electronic switches A1, B1, C1 then forming an upper control block 301 and the lower electronic switches A2, B2, C2 then forming a lower control block 302.

[0076] The symbol Sym = "BO" was taken from the coding table, with column GP1 (gate positive 1) and column GN1 (gate negative 1) showing the respective symbols "B" and "C" to be found. There is therefore a switching combination SK for the upper control block 301 and a switching combination SK for the lower control block 302. We will first look at the upper control block 301. If the upper control block 301 receives the switching combination SK = 1011, this means that the first upper electronic switch A1 is controlled with "1", the second upper electronic switch B1 is controlled with "0", the third electronic switch O1 is again controlled with "1", and the fourth electronic switch D1 is also again controlled with "1".Since the electronic switches A1, B, O1, D1 of the upper control block 301 have an inverting input, only the second electronic switch B1 is controlled in such a way that a current I can flow from the current source Q into the multi-wire system 200.

[0077] The current I flows through the closed or controlled second upper electronic switch B1 into the second electrical conductor 202. This second electrical conductor 202 serves as a forward conductor HL for the current I to another participant or a terminating resistor network 501. The current I now flows into the terminating resistor network 501 and can take a current path SW via the third electrical conductor 203 back to the first participant 1 through the resistors connected in a star shape there. Since the switching combination SK = 0010 was selected for the lower control block 302 in the first participant 1, the third lower electrical switch C2 in the lower control block 302 is now controlled in such a way that the current I can flow back to the current source Q.

[0078] To decode the transmitted information, for example in the second subscriber 2 or at any other location, a voltage level AB, BC, CA, etc. is generated and ultimately detected by the terminating resistor network 501 between two electrical conductors 201, 202, 203. The symbol Sym = “BC” can be recovered from the different voltage levels AB, BC, CA between the electrical conductors 201, 202, 203. In the middle of FIG 2, an example graph for a four-wire system N = 4 is shown. In this case, the graph has four nodes corresponding to the four-wire system N = 4, namely a first node A, a second node B, a third node C and a fourth node B. The dashed lines from the graph to the multi-wire system 200 symbolize a tap for the voltage levels. The voltage level AB can be measured between the first node A and the second node B.The first node A is connected to the first electrical conductor 201, and the second node B is connected to the second electrical conductor 202. The voltage level BC can be measured between the second node B and the third node C; for this purpose, the third node C is connected to the third electrical conductor 203. Since the fourth node D is connected to the fourth electrical conductor 204, the voltage level CD between the two respective conductors 203, 204 can be measured between the third node C and the fourth node D. Using this graph for a four-wire system n=4, six different voltage levels can be measured between nodes A, B, C, and D. To the right of the graph, a table with voltage levels as elements is shown. By measuring the voltage levels between conductors 201, 202, 203, and 204, the elements result in a reception vector 402.With the switching combination SK = 1011 and SK = 0010 mentioned at the beginning, the voltages AB, BC, CD, DA, AC, BD specified in the table result between the conductors 201, 202, 203, 204.

[0079] In order to determine which symbol Sym is involved, a minimum determination and a maximum determination are carried out in a symbol decoder 450 (see FIG. 8) on a sequence of the elements of the receive vector 402, and each is provided as a binary sequence max and min, in which the maximum level and the minimum level, respectively, are marked as the position in the sequence of the elements. In our example for the symbol "BC," a maximum results between the two nodes "BC" and a minimum between the two nodes "CD." This results in another vector "010000" and "001000." Using these two min-max vectors, the transmitted symbol Sym can then be read back from a decoding table.

[0080] FIG. 3 illustrates the transmission of the symbol Sym = "CB." Since the switching combinations SK are now different, SK = "1101" and SK = "0100," a different electrical conductor 201, 202, 203, 204 is selected as the forward conductor HL and the return conductor RL for the transmission of the symbol Sym = "CB" in FIG. 3. It is precisely through the different, targeted selection of forward and return conductors HL, RL that a symbol Sym can be encoded by selecting the conductors. The switching combination SK = 1101 turns on the third upper electrical switch C1 in the upper control block 301. The current I now flows via the forward conductor HL through the third electrical conductor 203 to the terminating resistor network 501 and by switching the terminating resistors a current path SW is switched back via the second electrical conductor 202 as a return conductor RL.Since the second lower electrical switch B2 in the lower control block 302 is now activated due to the switching combination SK = 0100, the current I can flow back to the current source Q, thus closing the circuit. To the right of the graph with nodes A, B, C, and D, the voltage levels are shown in a small table, and the maximum and minimum vectors can be read from the receive vector 402.

[0081] FIG. 4 illustrates a principle for increasing the possible symbol pool. According to FIG. 4, a second current loop 122 is impressed between the first station 1 and the second station 2 or a terminating resistor network 501 in addition to a first current loop 121. The first station 1 has a first voltage source Q1 and a second voltage source Q2. The electrical switches in the respective upper control block 301 and the lower control block 302 are designed in duplicate, with separate electrical switches for each current source Q1, Q2. If multiple current loops 121, 122 with different signal currents I1, I2 are operated between the first station 1 and the second station 2, the following procedure is used to decode the symbol Sym:

[0082] In a first step, the voltage levels AB, BC, CA between the electrical conductors 201, 202, 203, 204 or between the nodes A, B, C, D are detected using a comparator network 400. The comparator network 400 is described in more detail later in FIGS. 6 and 8. The detected voltage levels AB, BC, CA are determined as already described with FIGS. 2 and 3, and a reception vector 402 is assigned to the voltage levels AB, BC, CA, wherein the voltage levels AB, BC, CA form the elements of the reception vector 402.

[0083] In a second step, the receive vector 402 is fed to the symbol decoder 450, wherein, firstly, a maximum determination and, secondly, a minimum determination are performed on a sequence of the elements of the receive vector 402, and, in each case, a binary sequence Max, Min is provided. These binary sequences Max, Min (see also FIGS. 2 and 3) describe the maximum level and the minimum level, respectively, as a position in the sequence.

[0084] In a third step, the receive vector 402 is reduced by the positions already detected. With the reduced receive vector 402, a maximum determination and a minimum determination are then performed again. The procedure according to FIG 4 offers the following advantages: For each available conductor pair, an additional current loop can be impressed, thereby increasing the symbol pool. By using currents of different strengths, defined levels also arise between the conductors of the respective currents. These allow later incremental coding and decoding from multiple currents, each in the set of (still) available conductors. In this way, a considerable amount of information can be encoded in a few conductors with low energy consumption. The coding and decoding can also be implemented using purely digital and simple circuits.

[0085] FIG. 5 shows a typical arrangement of transceivers 100 connected to a shared multi-wire system 200. For the purposes of the invention, a transceiver is understood to be a transceiver / receiver; advantageously, the transceiver 100 is implemented in an integrated circuit. This means that the transceiver includes a transmitter, a receiver, a resistor network, and the corresponding control logic. The invention thus describes a transceiver 100 that provides access to a multi-wire system 200 shared with other participants, as well as a coding method for the energy-efficient transmission of information between two or more transceivers 100 via the multi-wire system 200.The present invention allows the construction of a bus-capable multi-conductor system 200 for information transmission using relatively simple and CMOS chip-integrated components. This system achieves similar signal integrity properties and transmission rates as, for example, LVDS, while simultaneously offering significantly more efficient information coding with a disproportionately low increase in power consumption. The following properties are crucial for this:

[0086] 1) At any given time, only a few current loops of varying strength are impressed into the conductor system.

[0087] 2) Since the current loops can be clearly formed on the transmitter side and recognized on the receiver side based on their relative current strengths, the information coding is carried out by selecting the individual conductors for the respective forward and return conductors of each individual current loop.

[0088] 3) A receiver can identify the individual current loops and determine their flow directions through a fast iterative process. This requires only simple, purely binary queries using comparators.

[0089] 4) By using impedance-controlled and low-reflection cable routing techniques as well as suitable termination, the transmission system is fundamentally capable of achieving the highest signaling rates with relatively low complexity and moderate power consumption.

[0090] The coding method then corresponds to the present and claimed method for the electrical transmission of symbols Sym. A transceiver 100 has direct access to the multi-conductor system 200 and provides an interface for control by an information processing system in the form of a symbol stream in the receive and transmit directions, namely a transmit symbol stream 102 and an output symbol stream 103. A control signal 101 serves, for example, to switch between transmit mode, receive mode, termination, and / or dynamic termination. A transceiver 100 comprises a control unit with a symbol encoder 110, a current source module 120, and a corresponding number of control blocks 300 (see FIG. 6). The transceiver 100, shown in principle in FIG. 5, is described in more detail in FIG. 6.A particular advantage of the method is that the transmission information is encoded in the ordered selection of one or more conductor pairs from the supply of the multi-conductor system 200. The individual electrical conductors are used to conduct one or more signal currents. When using multiple conductor pairs, the signal currents can each have different magnitudes and thus be in a reliable, interference-free relationship to each other.

[0091] FIG 6 shows a block diagram of a transceiver 100. A symbol encoder 110 receives as input a transmit symbol stream 102 and additionally a control signal 101. The symbol encoder 110 sends a first current loop control vector 111 to a control block 300. Furthermore, the symbol encoder 110 can send a second current loop control vector 112 to a further control block 300 and, depending on the configuration, up to an x-th current loop control vector 11x to a further control block 300. A first current loop 121 or a second current loop 122 or an x-th current loop 12x is then generated via respective current source modules 120. The corresponding control blocks 300, as described in FIG 2 and FIG 3, transmit the corresponding signal currents via the multi-wire system 200, wherein the voltage levels of the electrical conductors of the multi-wire system 200 are measured in a receiver via a comparator network 400.Thus, a transceiver 100 has a control unit with a symbol encoder 480 (see FIG. 9), one or more coupled current sources, and a corresponding number of control blocks 300, each with an upper control block 301 and a lower control block 302. For receive operation, a comparator network 400 with a symbol decoder 450 is used. FIG. 8 describes the symbol decoder 450 in more detail. The symbol decoder 450 generates the output symbol stream 103.

[0092] A current loop driver is a unit consisting of a coupled current source, namely the current source modules 120, and current distributors, namely the control blocks 300 with their upper control block 301 and their lower control block 302. With the help of these current loop drivers, a directed current of a defined magnitude can be impressed into the multi-conductor system 200 in a variety of ways. Both the forward and return conductors HL, RL of the current I can be freely selected from the N conductors of the multi-conductor system 200. The control block 300 (see FIG. 7) can form a "differential tuple" from at least n = 3 electrical conductors for decoding or coding. In contrast to a differential pair, as known from LVDS technology, more information can now be encoded or decoded because multiple conductor paths can now be selected via the control circuit described above.

[0093] In contrast to the differential pair, the "differential tuple" serves multiple conduction paths via a control circuit, namely control block 300, which controls a bank of half-bridges to establish the current loop through the selected conductor pairs, and then also takes the current intensity into account. The control circuit should ensure that cross-current is excluded by simultaneously selecting the same line on the high- and low-side drivers (upper control block 301 and lower control block 302).

[0094] A minimal transmission channel configuration consists of two transceivers 100, a multi-conductor system 200, and a star-point termination 503. Termination is necessary because it represents the current path SW for the impressed current loops, and the voltage drop across the termination resistors R leads to detectable voltage level differences. In the simplest case, this can be a suitable, permanently effective resistor network. Optionally, however, it is also advantageous to integrate a termination unit 500 into the transceiver 100. This allows the termination resistors R to be selectively connected and disconnected along the multi-conductor system 200. This allows for targeted response to reflections when operating in an extended bus scenario with many distributed devices or transceivers 100.The signal shape can also be specifically influenced by briefly switching the termination of all or individual bus lines on or off. For this purpose, the termination unit 500 can be specifically controlled by the symbol encoder 110 via the termination switches 502 located therein and a termination vector 104. A control block 300 is shown schematically in FIG. 7. An x-th current loop vector 11x is fed to an upper control block 301 and a lower control block 302. The upper control block 301 could also be referred to as a "high-side one hot" encoder, and the lower control block 302 as a "low-side one hot" encoder. The upper control block 301 can close and open upper switches 303 of the half-bridge. The lower control block 302 can open and close lower switches 304. Seven upper switches 303 and seven lower switches 304 are available for seven lines N = 7.Each electrical conductor 201, ..., 207 is thus assigned an upper switch 303 or a lower switch 304. The first electrical conductor 201 then corresponds to node A, and the seventh electrical conductor 207 then corresponds to node G in the graph A, B, C, D, E, F, G.

[0095] FIG 8 shows a comparator network 400, wherein in a seven-wire system N = 7, twenty-one comparators are available. This results in a group of comparators which can be assigned to a distant neighborhood 3D. This also results in a group of comparators which can be assigned to a middle neighborhood 2D, and this results in a group of comparators which can be assigned to a close neighborhood 1D. With regard to a graph A, B, C, D, E, F, G with seven nodes, the distant neighborhood 3D always means a distance of three edges between two nodes, the middle neighborhood 2D means a distance of two edges between two nodes, and the close neighborhood 1D means that the nodes are direct neighbors.

[0096] Reception operation and symbol recognition

[0097] By comparing the voltage levels with the twenty-one comparators, the symbol decoder 450 can provide the output symbol stream 103. In receive mode, the comparator network 400 is active and continuously detects the relative ratios of the voltage levels in the multi-wire system 200, which are then mapped to the digital receive vector 402. The symbol decoder 450 determines the output symbol stream 103 from this receive vector 402. In a preferred implementation for maximum performance, the comparator network 400 includes one comparator 401 for each unique wire pair in the multi-wire system 200. However, it is also possible to reduce the number of comparators required by thinning the comparator network 400. This limits the size of the receive vector 402 as well as the complexity of the symbol decoder 450 and results in a reduced set of possible symbols, which limits the information throughput of the system.When thinning the comparator network 400, care should be taken that asymmetric thinning leads to a loss of the interchange tolerance of lines in the conductor system 200.

[0098] The decoding of the symbols in the symbol decoder 450 can be performed in a multi-stage, iterative process for an undiluted and fully meshed comparator network 400. For this purpose, a first discriminator 461 (see FIG. 9), which operates as a min-max line pair discriminator, detects the wire pair with the respective highest and lowest relative level in the multi-wire system 200 and returns this information as wire pair information 451, 454, 457. In a preferred implementation, a simple multi-input AND logic gate (see FIG. 14) is sufficient, which detects whether a line level is always higher or lower than the level of all other logic lines. An error signal 452, 455, 458 is always active if exactly one maximum and one minimum are not always detected. This can be the case when the bus is at rest or when several current loops 12X with the same current strength are active.In this case, a clear assignment to the individual loops would not be possible.

[0099] FIG. 9 shows a block diagram of a symbol encoder 480. In order to provide a reduced receive vector 453 or an even further reduced receive vector 456 from a receive vector 402, a first discriminator 461, a second discriminator 462, and a third discriminator 463 are provided, with which the multi-stage, iterative process is carried out. The symbol decoder 450 according to FIG. 8 therefore supplies twenty-one values, which are checked by the first discriminator 461, and a first error signal 452 is provided if a minimum and a maximum could not be detected. With the aid of the minimum and maximum evaluation, first line pair information 451 can be provided to the symbol encoder 480 via the first discriminator 461. By means of a first reducer 471, the multi-conductor system 200 with n = 7 is reduced to a multi-conductor system with n = 5.The first reducer 471 provides a reduced receive vector 453. This reduced receive vector 453 is provided to the second discriminator 462 as an input variable for the min-max evaluation. The second discriminator 462 can, in turn, provide a second piece of line pair information 454 to the symbol encoder 480. In a next step, the reduced receive vector 453 is converted into a further reduced receive vector 456 by a second reducer 472. The further reduced receive vector 456 is also checked for minimum and maximum values ​​by a third discriminator 463, whereby the third discriminator 463 provides a third piece of line pair information 457 to the symbol encoder 480.If the first discriminator 461, the second discriminator 462 and / or the third discriminator 463 detect an error in the min-max evaluation, a first error signal 452, a second error signal 455 and / or a third error signal 458 are provided to the symbol encoder 480.

[0100] After the first step, it is now known which pair of wires provides the forward and return conductors for the current loop with the largest loop current. With this information, the receive network can now be thinned out to include these conductors in preparation for the second step. The example in FIG 9 is an n=7 multi-wire system 200 with a total of L=3 current loops. After the first step with detection of the first current loop by nodes B and F, nodes A, C, D, E and G remain. In the same step, the comparators connected to the now removed conductors B and F become obsolete and can be removed from the receive vector 402. The "Reduction of receive vector and network" block removes these excess bits, creating a new, reduced receive vector 453, which, reduced to a new length of ten bits, now corresponds to the receive vector of a five-wire system n=5.Accordingly, the forward and return conductors of the largest remaining current loop can now be found using another "min-max wire pair discriminator." In preparation for a final iteration, the reduced receive vector is again determined based on the determined wire pair information 454. This vector now corresponds to that of a three-wire system n = 3 with nodes A, C, and E.

[0101] The symbol encoder 480 knows the possible variety of line pair information 452, 445, and 458 (A, B, and C) and can easily determine a received symbol from this. If one of the error signals 452, 455, and 458 is active, an error symbol can be generated accordingly. For decoding the output symbol stream 103 from the received vectors 402, no synchronous logic is initially required, which means that clock recovery methods can also be applied to the output symbol stream 103. For this purpose, for example, the least significant error signal, in the example, the third error signal 458, can be used specifically. One possibility for this would be for the transmitter to cyclically interrupt the third current loop control vector 113, thus provoking a clock signal in the third error signal 458.

[0102] FIG. 10 shows a block diagram of a termination unit 500. Termination unit 500 receives a termination vector 104 as an input variable. Termination vector 104 can control termination switches 502 accordingly, so that a termination resistor network 501 is connected to the corresponding electrical conductors 201, ..., 207. Termination switches 502 are assigned to nodes A, , G of the corresponding graphs.

[0103] FIG 11 shows graphs for a different number of electrical conductors in the multi-conductor system 200. For a three-conductor system n = 3, a graph with three nodes A, B, C is used to determine the voltage levels AB, BC, CA. For a multi-conductor system 200 with n = 4 conductors, a graph A, B, C, D with four nodes is used, which already results in seven voltage levels. For a multi-conductor system 200 with n = 5 electrical conductors, a graph A, B, C, D, E with five nodes is used, which now results in ten voltage levels AB, BC, CA ... If the multi-conductor system 200 has n = 7 electrical conductors, this results in twenty-one reference junctions and accordingly twenty-one voltage levels. In this case, the solid arrows between the nodes in the graphs indicate a close neighborhood 1D, the dashed arrows indicate a medium neighborhood 1D, and the dotted connecting arrows indicate a far neighborhood 3D.

[0104] According to FIG. 12, a decoding table for different multi-conductor systems 200 is shown, which extends to FIGS. 12A, 12B, 12C, and 12D. When creating an interactive exemplary embodiment for decoding a different configuration of the multi-conductor system, a table was created in which it is not possible or clear enough to depict the drawing illustrating the invention on a single sheet. Among other things, the table shows the interlinking of individual method steps. In this case, the drawing has been divided into four sheets (12A, 12B, 12C, 12D). The complete figure or drawing can be assembled by placing the four drawing sheets side by side.

[0105] On the far left, the number of conductors in the system and the number of currents applied are indicated. For example, three conductors, one current; four conductors, one current, four conductors, two currents; seven conductors, one current, seven conductors, two currents; seven conductors, three currents. The corresponding symbols to be decoded are also listed in a column. Above the table with the coding and decoding instructions, the block diagram shown in Figure 9 is shown, elongated to symbolize where each step is performed.

[0106] Parameters, Variations, and Performance A key parameter of the invention is N, the number of conductors in a multi-conductor system (200), and L, the number of current loops that can be simultaneously embossed. See, for example, the leftmost column "4 wire, 2 current," i.e., N = 4 and L = 2. Accordingly, four conductors and two current loops are used. All accompanying illustrations take these parameters into account by indicating appropriate adjustments or by presenting an implementation example with specific parameters.

[0107] The symbol set can be estimated from the degrees of freedom in the choice of lines. Thus, in a multi-wire system 200 with N conductors, a total of N*(N-1) different possibilities are available for the imprinting of the first current loop 121, which is extracted from the transmit symbol stream 102 by the current loop control vector 111 of the symbol encoder 110. The flow of a second current loop 122 can now be selected according to the same scheme into a reduced set of N-2 conductors, opening up a possibility space of (N-2)*(N-3) for the second current loop control vector 112. This current loop control vector 112 is also extracted from the transmit symbol stream 102 by the symbol encoder 110. This process can now be continued for further current loops, as long as the remaining conductor set is sufficiently large.

[0108] Overall, this rule results in a total of N! / (N - 2L)! symbols for how the L current loops can be impressed on the N lines. This is possible because the complete information about which current flows through which pair of forward and return conductors is contained in the receive vector 402, for example, if the current loops 121, 122, ..., 12X are implemented with strictly monotonically decreasing currents.

[0109] In a preferred implementation, the symbol encoder 110 also ensures at all times that each electrical line 20X in the multi-wire system 200 is selected by a maximum of only one control block 300, thereby eliminating overlaps of the current loops 121, 122, ..., 12X. This limits the variety of possible voltage levels in the multi-wire system 200 to a maximum of 2*L+1 different amplitudes, which has a positive effect on interference immunity during operation.

[0110] By convention, encoding and decoding begin with the current loop 121, which carries the largest current, and continue strictly in descending order of current amplitude 122, ..., 12X. In the preferred implementation, the current source modules 120 are to be adjusted accordingly to ensure this. Thus, the correct assignment of the detected current paths is possible even with multiple current loops based solely on the level differences in the multi-conductor system 200, which further increases the information density. Decoding is also possible with current loops of equal strength or overlapping, albeit with a reduced symbol set.

[0111] FIG. 13 shows a reduction of a receive vector from an eight-wire system n = 8 down to a two-wire system n = 2. To do this, FIGS. 13A, 13B, and 13C should be viewed side by side. According to FIG. 13A, an eight-wire system N = 8 with the graph A, B, C, D, E, F, G, H is assumed. In the graph, or rather in the multi-wire system 200, the minimum and maximum of the voltage level are shown using a discriminator. It is assumed that the symbol "CF" was transmitted. Thus, a maximum is identified for C and a minimum for F. After the reduction from N = 8 to N = 6, the detected nodes C and F are omitted.

[0112] A further reduction is shown in FIG 13B. In the now existing six-wire system N = 6, a graph A, B, C, D, E, F results, from which the maximum and minimum voltage levels MIN, MAX can then be identified. Now, in the exemplary symbol transmission, it is determined that node F (formerly H) now results in a maximum MAX and node D (formerly E) now results in a minimum MIN. This results in the symbol "CFHE". During the transition from the six-wire system N = 6 with six wires to the four-wire system N = 4, or the corresponding procedural reduction, nodes D and F are omitted. The receive vector has now been reduced to the equivalent of a four-wire system, and the graph A, B, C, D is obtained; see FIG 13C. Here, too, another symbol is decoded using minimum and maximum detection; this now results in the complete receive symbol "CFHEBG".Ultimately, the four-wire system N = 4 is reduced to a two-wire system N = 2.

[0113] In summary, the starting point is a ladder system with eight lines, which is reduced for three reductions with randomly selected max-min pairs per level. A mapping of the lines, i.e., the mapping of nodes (lines) from the larger ladder system to nodes (lines) of the reduced ladder system, is shown as an assignment to the right of the graph. According to FIG 13A, a line mapping 603 represents the assignment of the lines from N = 8 lines to N = 6 lines. A reduction mapping 604 represents the assignment of the bits or positions of the receive vector 402 to the bits or positions of the reduced receive vector 453. In each stage, two lines are marked as MIN and MAX in the complete graph, with the numbered edges (1 to 28) corresponding to the bit numbers on the right side of the reduction mapping 604.These two lines, designated MIN and MAX, are the exemplary recognized decoding results of the respective stages, which must now be reduced from the receive vector 402. The box ("Symbol") contains the designation of the recognized symbol, which is extended in each stage by the newly recognized conductor pair. FIG. 13A for N = 8: "CF", FIG. 13B for N = 6: "CFHE", FIG. 13B for N = 4: "CFHEBG".

[0114] The goal of the reduction is for a subsequent decoder stage in the symbol encoder 480 to again find a complete graph of size (N-2) while maintaining the conductor sequence according to the conductor mapping 603, so that the entire procedure can now be carried out iteratively for increasingly smaller "virtual" conductor systems. Each of the N conductors corresponds to a node in the complete N-graph, and each bit in the receive vector 402 corresponds to a directed edge between two nodes. With each stage, the graph is reduced by the two nodes that are equal to the detected conductors of the detected conductor pair in this stage. The conductors or nodes are detected using the minimum and maximum determination. Accordingly, all edges (bits) that run from or to these nodes (conductors) are eliminated. In FIGS 13A, B, C, the affected conductors or nodes are circled and crossed with an X to illustrate the elimination or reduction.

[0115] The remaining bits or positions also appear in the new graph and are assigned to the corresponding bits or positions of the new reduced receive vector 453 according to the line mapping 603 shown, so that the latter correctly maps the original relationship of the original graph. It should be noted that inversions may occur if the wire order is swapped (edge ​​direction reversed). This occurs, for example, during the transition from the receive vector 402 of an eight-wire system N = 8, bit 23 ("GB") to the reduced receive vector 453 of a six-wire system N = 6, bit 14 ("BE"), since the associated mapping provides for the mapping G -> E and B -> B, i.e. "GB" -> "EB", but the reduced graph provides for the reversed edge direction "BE".

[0116] From this rule, a digital circuit can be derived using design methods known to those skilled in the art, which carries out the corresponding assignments, e.g. by using multiplexer and inverter gates.

[0117] FIG. 14 shows a possible implementation of a comparator. For a four-wire system n = 4 with the graph A, B, C, D, there are six different ways to measure voltage levels. Accordingly, six comparators must be integrated into a circuit. These six comparators are symbolized by the comparator network 400. The voltage levels AB, BC, CA, ... between the electrical conductors 201, 202, 203, 204 or between the nodes are detected by the comparator network 400. The detected voltage levels AB, BC, CA, ... are assigned as elements to a receive vector 402. The receive vector 402 can be formed by scanning the individual conductors one after the other according to a convention, whereby the relative ratios of the voltage levels in the conductor system are also detected one after the other in the receive vector 402. A convention could, for example, be the following, based on graph theory:

[0118] The individual conductors represent nodes arranged on a circular line. In a four-conductor system, you would have node A, node B, node C, and node D. Starting clockwise from node A, edges can be drawn between the nodes. Once you've returned to the starting node, the diagonals or cross connections can be drawn as edges. Accordingly, the edges represent the voltage levels between the nodes or conductors AB, BC, CD, DA, AC, and BD. A possible receive vector could look like this:

[0119] Receive vector = (+1 volt, +2 volt, -1 volt, +1 volt, +1 volt, +1 volt).

[0120] Using a simple AND gate, a maximum and minimum detection are applied to the receive vector. This maximum and minimum detection can be performed using simple AND gates. If a maximum cannot be correctly detected, a first error signal 452 is generated. Otherwise, the output is performed, and if one of the AND gates outputs a signal, it is known which line produced the maximum. The minimum is determined analogously.

[0121] Similar to the reduction shown in FIG. 13, Figures 15 to 20 show a reduction for a seven-wire system starting with the graphs A, B, C, D, E, F, G. For a seven-wire system N = 7, there is a graph with twenty-one edges. This means there are twenty-one voltage levels to be evaluated. Using the min-max evaluation, a minimum and a maximum will always be detectable in the receive vector 402. The graph shown in FIG. 15 accordingly has twenty-one (0 to 20) connections.

[0122] 600, these connections 600 are shown in the graph as edges or interpreted as voltage levels. After the first reduction, FIG 16 shows the transition from a seven-wire system N = 7 to a five-wire system N = 5. Using an assignment table

[0123] 601 , in which a mapping of the nodes from the previously larger graph to the now reduced smaller graph is performed, one can see which nodes from the larger graph have now been eliminated in the reduced graph.

[0124] Furthermore, FIG 17 illustrates a reduction of the receive vector 402 from the seven-wire system N = 7 to the five-wire system N = 5. The reduced receive vector 453 is derived from the receive vector 402. A reduction from 21 bits to 10 bits has taken place. The columns of the table in FIG 17 show this. An edge BC in the seven-wire system becomes the edge A'B' in the five-wire system. With the reduction, a five-wire system N = 5 has been created in FIG 18; here, too, a minimum-maximum determination must be carried out. This is illustrated in FIG 19; here, too, an assignment table 602 (see FIG 20) is shown for mapping from a five-wire system N = 5 to a three-wire system n = 3.

[0125] FIG. 21 illustrates how a transmitting unit TX, a receiving unit RX, and a termination unit 500 can be combined into a transceiver circuit. This combination allows for implementation as an easily scalable IP block for use in a semiconductor component 50. In microelectronics, an IP block—from the English Intellectual Property Core or IP core—refers to a versatile, prefabricated functional block of a chip design (in the sense of blueprints or circuit designs). This chip design accordingly implements the method steps according to the invention. A distinction is made between soft IP and hard IP cores: A soft IP core exists in the form of source code in a special hardware description language such as Verilog or VHTL. It can also be present as a netlist synthesized by the manufacturer, as a textual description of a circuit diagram. In this case, one speaks of firm IP cores.A hard IP core is a block with a pre-finished layout. This allows the user to make little or no changes to the IP and is tied to a process. To protect process secrets, a user often only receives a black-box representation of a purchased hard IP core. The IP block is preferably implemented using Complementary Metal Oxide Semiconductor technology. The abbreviation CMOS is a term for semiconductor components in which both P-channel and N-channel MOSFETs are used on a common substrate. According to FIG. 22, another embodiment of the transceiver unit or a transceiver circuit and a semiconductor component 50 is disclosed. It is possible to work with one current source for a four-wire system N=4, or with two current sources for a four-wire system N=4, in order to impose different current loops.

[0126] FIG. 23 shows possible bus topologies. All bus topologies have in common that at least two participants are connected to a conductor system, in particular a multi-conductor system 200 (bus). For data transmission according to the method and the invention, at least a three-conductor system is required. At least one participant must be connected, functioning as a transmitter, and a resistor network as a receiver. This means that at least one terminating resistor, e.g., referred to as a center termination (or Thevenin equivalent), must be present in the conductor system (bus).

[0127] According to FIG 23, from left to right, a three-wire system, a four-wire system, a seven-wire system and finally a three-wire system with external termination unit are shown.

[0128] FIG. 24 shows parallel operation of different conductor systems. This illustrates that a multi-conductor system with N = 7 conductors can be connected to a seven-conductor system, a four-conductor system, or even a three-conductor system, each with corresponding transceivers. This allows the operation of devices with different numbers of conductors on a shared conductor system (bus). Dividing a large shared conductor system (bus) into several smaller sub-buses is considered advantageous. Devices on independent sub-buses can transmit simultaneously without conflict. A main bus device can participate in all transmission paths, including the transmission paths of the sub-buses.

[0129] FIG 25 proposes termination in parallel operation. For example, the termination can be distributed among the subbuses. As an alternative to separate termination of the main bus, termination sufficient for the operation of the devices on the main bus can also be achieved by connecting the midpoints of the subbus terminations (see dashed line).

[0130] Figure 26 illustrates dynamic termination. Termination using bus termination resistors can also be integrated into the devices and activated as needed. Mixed operation of existing LVDS (Low Voltage Differential System) and the new MLVDS (Multi-Wire Low Voltage Differential System) according to the invention is shown in Figure 27. The innovative semiconductor components can be connected to existing LVDS connections. A transceiver can be operated as an LVDS-RX receiver on any conductor pair. An LVDS-TX transmitter unit can be connected to each current loop in the transceiver.

[0131] The present invention makes it possible to construct a bus-capable multi-conductor system for information transmission using simple and CMOS chip-integrated components, which achieves similar signal integrity properties and transmission rates as, for example, LVDS, but at the same time also has significantly more efficient information coding with a disproportionately low increase in power consumption.

[0132] The following characteristics are crucial for this:

[0133] At any given time, only a few current loops of varying strength are impressed into the conductor system.

[0134] Because the current loops can be clearly formed on the transmitter side and recognized on the receiver side based on their relative current strengths, the information is encoded by selecting the individual conductors for the respective forward and return conductors of each individual current loop.

[0135] A receiver can identify the individual current loops and determine their flow directions through a fast iterative process. This requires only simple, purely binary queries using comparators.

[0136] By using impedance-controlled and low-reflection cable routing techniques, as well as suitable termination, the transmission system is fundamentally capable of achieving the highest signaling rates with relatively low complexity and moderate power consumption.

[0137] Further thoughts and benefits are listed below:

[0138] • At least three conductors in a multi-conductor system (bus) are used for data transmission.

[0139] • A star impedance (termination) allows current flow between all conductors.

[0140] • A current is injected symmetrically into the bus via any two conductors. The impedance of the termination allows the current to be detected as a potential difference between the bus conductors.

[0141] Information is encoded in the ordered leader selection.

[0142] Binary decision makers between all conductors allow the decoding of the symbol from the conductor potentials.

[0143] When two or more unused conductors are connected, the same conductor potentials occur, resulting in a 0 or 1 at the corresponding decision points. Nevertheless, the symbol remains clearly identifiable.

[0144] Swapping the conductor selection between high and low side inverts the potentials in the conductor system and thus also the reception vector, which forms the decision states of the comparators.

[0145] N • (N - 1) possible symbols result from a free choice of N and N - 1 unused conductors.

[0146] An additional current loop can be impressed for each available conductor pair.

[0147] By using currents of different strengths, defined levels are also created between the conductors of the respective currents.

[0148] These allow the incremental coding and decoding of several currents, each in the set of (still) available conductors.

[0149] In this way, a significant amount of information can be encoded in a few conductors with little energy expenditure.

[0150] Coding and decoding is done using purely digital and simple circuits.

[0151] Multiple current loops of varying strength can be achieved by using different current sources or by doubling the high- and low-side transistors with a common current source. (FIG 21)

[0152] The transmitting unit (Tx), receiving unit (Rx) and termination can be combined in one transceiver circuit.

[0153] The termination is activated dynamically as needed to prevent the bus from becoming too low-impedance.

[0154] This allows implementation as an easily scalable IP block for use in integrated circuits.

[0155] At least one termination resistor in the conductor system (bus), e.g. as center termination (Thevenin equivalent) FIG 26.

[0156] Operation of participants with different numbers of conductors on a common conductor system (bus) FIG 24.

[0157] Division of a common large conductor system (bus) into several smaller sub-buses. • Participants on independent sub-buses can transmit simultaneously without conflict.

[0158] • Main bus participants can participate in all transmission paths (including sub-buses).

[0159] • The termination can be distributed among the subbuses. • As an alternative to separate termination of the main bus, termination sufficient for the operation of the devices on the main bus can also be achieved by connecting the midpoints of the subbus terminations (see dashed line) FIG 25, FIG 26.

[0160] • Scheduling can also be integrated into the participants and activated when required.

Claims

Patent claims 1. System for transmitting symbols (Sym) between a first subscriber (1) and a second subscriber (2) via a common multi-conductor system (200) with a first electrical conductor (201), a second electrical conductor (202) and a third electrical conductor (201, 202,..., 207), the first subscriber (1) comprises a symbol encoder (110), a power source module (120) and a control block (300), wherein the control block (300) has an upper control block (301) and a lower control block (302), the upper control block (301) is designed to close and open upper switches (303) to a first output of the power source module (120), the lower control block (302) is designed to open and close lower switches (304) to a second output of the power source module (120), the upper switches (303) have at least three upper electronic switches (A1, B1, C1) and the lower switches (304) have at least three lower electronic switches (A1,B2,C2), at least three series circuits (P1,P2,P3) are arranged, each consisting of an upper electronic switch (A1,B1,C1) and a lower electronic switch (A2,B2,C2), to the respective series circuit (P1,P2,P3) the electrical conductors (201,202,203) are connected between the upper electronic switch (A1,B1,C1) and the lower electronic switch (A2,B2,C2), to which, The current source module (120) is connected to series circuits (P1, P2, P3), characterized in that the symbol encoder (110) is designed to provide a current loop control vector (111) for the control block (300), wherein the control block (300) is designed to switch the electronic switches (A1, B1, C1, A2, B2, C2) by means of the current loop control vector (111), which has a switching combination (SK) for the electronic switches (A1, B1, C1, A2, B2, C2), and thus to establish a current flow in the connected electrical conductors (201, 202, ..,207), the symbol encoder (110) is designed to determine the current loop control vector (111) in such a way that the symbols (Sym) to be transmitted are determined and thereby coded by an ordered selection of a conductor pair from a supply of electrical conductors (201, 202, 203) from the multi-conductor system (200), wherein a conductor pair comprises one of the electrical conductors (201, 202, 203) as a forward conductor (HL) of a current from the first subscriber (1) to the second subscriber (2) and another of the electrical conductors (201, 202, 203) as a return conductor (RL), wherein a termination unit (500) is also provided, wherein. the symbol encoder (110) is designed to provide a termination vector (104) for the termination unit (500), wherein the termination unit (500) is designed to connect a termination resistor network (501) to the electrical conductors (201, 202, 203) of the multi-conductor system (200) by means of a termination switch (502), wherein the second subscriber (2) has a comparator network (400), wherein the comparator network (400) is designed to detect a voltage level (AB, BC, CA) between two electrical conductors (201, 202, 203) in order to decode the symbol (Sym), wherein the coded symbol (Sym) is contained in the different voltage levels (AB, BC, CA) between the electrical conductors (201, 202, 203).

2. System according to claim 1, wherein the symbol encoder (110) is configured to provide a plurality of current loop control vectors (111, 112, 113,..., 11x), wherein the control block (300) is configured to operate the common multi-conductor system (200) with a plurality of current loops (121, 122,..., 127).

3. System according to claim 2, wherein the control block (300) and / or the current source module (120) is designed to impress different signal currents (11, 12,..., Ix) into the individual current loops (121, 122,.., 127).

4. System according to one of claims 1 to 3, wherein the comparator network (400) is designed to assign the detected voltage levels (AB,BC,CA) to a reception vector (402) as elements.

5. System according to one of claims 4, comprising a symbol decoder (450) which is designed to receive the receive vector (402) and to carry out a maximum determination and a minimum determination on a sequence of the elements of the receive vector (402), further designed to provide a binary sequence (MAX.MIN) in which the maximum level or the minimum level is marked as a position in the sequence.

6. System according to claim 5, comprising • a first discriminator (461), • a second discriminator (462), • a first reducer (471), • a second reducer (472), • the first discriminator (461) is designed as a min-max line pair discriminator and is thus designed to receive the reception vector (402) and to detect the line pair with the respective largest and smallest relative level in the multi-line system (200), further designed to provide the detection result as a first line pair information (451), • the first discriminator (461) is connected to the first reducer (471) and is designed to provide a reduced reception vector (453) with the first line pair information (451), • the second discriminator (462) is designed as a further min-max line pair discriminator and is thus designed to receive the reduced reception vector (453) and to detect the conductor pair with the respective largest and smallest relative level in the multi-conductor system (200) with the already detected reduced conductor pair, further designed to provide the detection result as a second line pair information (454), • the second discriminator (462) is connected to the second reducer (472) and is designed to provide a further reduced reception vector (456) with the second line pair information (451).

7. Method for the electrical transmission of symbols (Sym) from a first subscriber (1) to a second subscriber (2) which are connected via a common multi-conductor system (200) with at least one first electrical conductor (201), one second electrical conductor (202) and one third electrical conductor (203), wherein - in the first participant (1), at least three series circuits (P1, P2, P3) are operated, each comprising an upper electronic switch (A1, B1, C1) and a lower electronic switch (A2, B2, C2), wherein the electrical conductors (201, 202, 203) are connected to the respective series circuit between the upper electronic switch (A1, B1, C1) and the lower electronic switch (A2, B2, C2), the upper electronic switches (A1, B1, C1) switch the electrical conductors (201, 202, 203) to or from a first output of the power source (Q) and the lower electronic switches A2, B2, C2 switch the electrical conductors 201, 202, 203 to or from a second output of the power source (Q), characterized in that - the symbol (Sym) to be transmitted is coded by selecting a switching combination (SK) for the electronic switches (A1, B1, C1, A2, B2, C2) by performing an ordered selection of a conductor pair from a supply of electrical conductors (201, 202, 203) from the multi-conductor system (200), wherein a current (I) is supplied via a current source (Q) via a closed upper electronic switch (A1, B1, C1) from the first participant (1) into one of the electrical conductors (201, 202, 203) as a forward conductor (HL) into the multi-conductor system (200), - wherein a termination resistor network (501) is connected to the electrical conductors (201, 202, 203) of the multi-conductor system (200) is switched on, whereby a current path (SW) for the current (I) flowing in the forward conductor (HL) to a further electrical conductor (201, 202, 203) is switched and the further electrical conductor (201, 202, 203) is then used as a return conductor (RL) for the current (I) via a closed lower electronic switch (A2, B2, C2) by the first participant (1), - wherein in the second participant (2) a voltage level (AB,BC,CA) is detected between two electrical conductors (201,202,203) in order to decode the symbol (Sym), wherein from the different voltage levels (AB,BC,CA) between the electrical conductors (201 ,202,203) the symbol (Sym) is recovered.

8. The method according to claim 7, wherein the common multi-conductor system (200) is operated with a number (n) of electrical conductors (201, 202, .., 207), wherein current loops (121, 122, .., 127) are formed between the first subscriber (1) and the second subscriber (2) by means of the electronic switches (A1, B1, C1, A2, B2, C2), the electrical conductors (201, 202, .., 207) and the terminating resistor network (501), wherein for further coding of the symbols (Sym) to be transmitted, a selected quantity (L) of current loops (121, 122, .., 127) is determined from the number (N) of electrical conductors (201, 202, .., 20x), and a symbol pool is thus increased.

9. Method according to claim 8, wherein signal currents (11, 12, .., Ix) of different magnitude are impressed into the individual current loops (121, 122, .., 127) of the selected set (L), thereby further increasing the symbol pool.

10. The method according to any one of claims 7 to 9, wherein the voltage levels (AB,BC,CA) between the electrical conductors (201,202,203) are detected with a comparator network (400), wherein the detected voltage levels (AB,BC,CA) are assigned to a reception vector (402) as elements.

11. The method according to claim 10, wherein the reception vector (402) is supplied to a symbol decoder (450), wherein on the one hand a maximum determination and on the other hand a minimum determination is carried out on a sequence of the elements of the reception vector (402) and a binary sequence (MAX, M IN) is provided in which the maximum level or the minimum level is marked as a position in the sequence.

12. Method according to one of claims 9 to 11, wherein, in the event that several current loops (121, 122, .., 127) with different signal currents (11, 12, .., Ix) are operated between the first subscriber (1) and the second subscriber (2), in order to decode the symbol (Sym) in a) first step, the voltage levels (AB, BC, CA) between the electrical conductors (201, 202, 203) are detected with a comparator network (400), the detected voltage levels (AB, BC, CA) are assigned to a receive vector (402) as elements, b) second step, the receive vector (402) is fed to a symbol decoder (450), wherein on the one hand a maximum determination and on the other hand a minimum determination is carried out on a sequence of the elements of the receive vector (402) and in each case a binary sequence (MAX.MIN) is provided in which the maximum level orthe minimum level is marked as a position in the sequence, c) in the third step, the reception vector (402) is reduced by the positions detected in the second step, a reduced reception vector (453) being determined, the reduced reception vector (402) in the first step being continued until the reduced reception vector (453) or a further reduced reception vector (456) corresponds to a multi-conductor system (200) with a number of conductors of N = 3.

13. A semiconductor component (50) configured as a line driver for electrical transmission of symbols (Sym) between a first subscriber (1) and a second subscriber (2), which are connected via a common multi-conductor system (200) with at least one first electrical conductor (201), a second electrical conductor (202), and a third electrical conductor (201, 202,..., 207), characterized by a configuration for carrying out the method according to one of claims 7 to 12.

Images