Communication device, control method, and program

Abstract

Provided is a first communication device comprising: a communication circuit including a first coil, the communication circuit performing wireless communication with a second communication device via inductive coupling between the first coil and a second coil of the second communication device; and an application means for applying a plurality of voltage patterns to the first coil via the communication circuit, each of the voltage patterns including a first signal portion used for detecting the number of bit errors in the second communication device, and the first signal portion of each of the voltage patterns having different frequency characteristics.

Description

Communication device, control method, and program

[0001] The present invention relates to a communication device, a control method, and a program.

[0002] Techniques for performing wireless communication using coils between multiple semiconductor chips have been known for some time. For example, Patent Document 1 proposes an information processing device that exchanges information between multiple horizontally integrated semiconductor chips via short-range wireless communication.

[0003] Furthermore, a technique for generating a pseudo random signal (Pseudo Random Bit Sequence (PRBS)) is known (Non-Patent Document 1).

[0004] Japanese Patent Application Laid-Open No. 2021-87044

[0005] Yuzo Usui, "PRBS (Pseudo Random Signal)," [online], August 28, 2017, Macnica, Inc., [Retrieved January 18, 2024], Internet <URL: https: / / www.macnica.co.jp / business / semiconductor / articles / basic / 124741 / >

[0006] The positional relationship (distance, angle, etc.) between semiconductor chips may change due to an external force or the like.

[0007] The present invention has been made in view of the above circumstances, and provides a technique for supporting determination of the positional relationship between communication devices such as semiconductor chips.

[0008] In order to solve the above problem, the present invention provides a first communication device comprising: a communication circuit including a first coil, which performs wireless communication with a second communication device via inductive coupling between the first coil and a second coil of a second communication device; and application means which applies a plurality of voltage patterns to the first coil via the communication circuit, each voltage pattern including a first signal portion used to detect the number of bit errors in the second communication device, and application means which apply a plurality of voltage patterns to the first coil via the communication circuit, each voltage pattern including a first signal portion used to detect the number of bit errors in the second communication device, and the first signal portion of each voltage pattern having a different frequency characteristic.

[0009] According to the present invention, it is possible to assist in determining the positional relationship between communication devices such as semiconductor chips.

[0010] Other features and advantages of the present invention will become more apparent from the accompanying drawings and the following detailed description of the preferred embodiment of the present invention.

[0011] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments of the present invention, and are used, together with the description thereof, to explain the principles of the present invention. A conceptual diagram of a communication system composed of multiple communication devices. A diagram showing another example of the configuration of a semiconductor chip 1. A diagram explaining coupling between a transmitting coil 30 and a receiving coil 40 using an equivalent circuit. A conceptual diagram of a bias voltage in a receiving coil 40. A diagram explaining wireless communication utilizing inductive coupling between coils. A diagram explaining wireless communication utilizing inductive coupling between coils. A diagram explaining wireless communication utilizing inductive coupling between coils. A diagram explaining wireless communication utilizing inductive coupling between coils. A diagram explaining wireless communication utilizing inductive coupling between coils. A diagram explaining wireless communication utilizing inductive coupling between coils. A diagram showing an example of a frame format used by the semiconductor chip 1 to transmit and receive data. A diagram showing an example of an evaluation frame format. A diagram showing an example of an evaluation signal table for managing multiple evaluation signals (bit patterns). A flowchart of an evaluation frame transmission process in a sensing process when a method of changing the bit pattern of an evaluation signal is used. A flowchart of an evaluation value acquisition process in a sensing process when a method of changing the bit pattern of an evaluation signal is used. A flowchart of a positional relationship determination process in a sensing process. 1 is a diagram for explaining a method of inverting a part of a voltage pattern. A diagram showing an example of an inversion rule table that manages the voltage inversion rule for the evaluation signal. A flowchart of an evaluation frame transmission process that is part of the sensing process when using a method of inverting a part of the voltage pattern. A flowchart of an evaluation value acquisition process that is part of the sensing process when using a method of inverting a part of the voltage pattern. A diagram for explaining a Return to Zero (RZ) code. A diagram for explaining a Non Return to Zero Inversion (NRZI) code. A diagram for explaining a Manchester code. A diagram showing an example of a transmission line code table that manages multiple transmission line codes. A flowchart of an evaluation frame transmission process that is part of the sensing process when using a method of changing the transmission line code of the evaluation signal. A flowchart of an evaluation value acquisition process that is part of the sensing process when using a method of changing the transmission line code of the evaluation signal. A diagram showing an example of an evaluation frame that includes a field for an evaluation signal ID.FIG. 10 is a diagram showing another example of the format of the evaluation frame. FIG. 11 is a diagram illustrating various specific examples of determination regarding a positional relationship. FIG. 12 is a diagram illustrating various specific examples of determination regarding a positional relationship. FIG. 13 is a diagram illustrating various specific examples of determination regarding a positional relationship. FIG. 14 is a diagram illustrating various specific examples of determination regarding a positional relationship. FIG. 15 is a diagram illustrating various specific examples of determination regarding a positional relationship. FIG. 16 is a diagram illustrating various specific examples of determination regarding a positional relationship. FIG. 17 is a diagram illustrating various specific examples of determination regarding a positional relationship. FIG. 18 is a diagram illustrating various specific examples of determination regarding a positional relationship. FIG. 19 is a diagram illustrating various specific examples of determination regarding a positional relationship. FIG. 1 is a diagram for explaining various specific examples of determination regarding a positional relationship. FIG. 2 is a diagram for explaining various specific examples of determination regarding a positional relationship. FIG. 3 is a diagram for explaining various specific examples of determination regarding a positional relationship. FIG. 4 is a diagram for explaining various specific examples of determination regarding a positional relationship. FIG. 5 is a diagram for explaining various specific examples of determination regarding a positional relationship. FIG. 6 is a diagram for explaining various specific examples of determination regarding a positional relationship. FIG. 7 is a block diagram showing the functional configuration of a semiconductor chip 1.

[0012] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the scope of the invention as claimed, and not all combinations of features described in the embodiments are necessarily essential to the invention. Two or more of the features described in the embodiments may be combined in any desired manner. Furthermore, the same reference numerals are used to designate identical or similar components, and redundant descriptions will be omitted.

[0013] <Configuration of communication system> Fig. 1 is a conceptual diagram of a communication system configured with multiple communication devices. In the example of Fig. 1, the communication devices are semiconductor chips. Although Fig. 1 shows two semiconductor chips (semiconductor chips 1a and 1b), the number of semiconductor chips included in the communication system is not particularly limited, and the communication system may include three or more semiconductor chips.

[0014] In the following description, when it is not necessary to strictly distinguish between the individual semiconductor chips, the semiconductor chips included in the communication system will be collectively referred to as "semiconductor chip 1." In this case, the components of the semiconductor chip 1 shown in FIG. 1 will also be collectively referred to by their reference numerals, with the alphabet removed, such as "processor 10." This also applies to FIG. 2, which will be described later.

[0015] The semiconductor chip 1 includes a processor 10, a memory 20 provided within the processor 10, a transmitting coil 30, a receiving coil 40, a transmitting conversion circuit 50, and a receiving conversion circuit 60. The semiconductor chip 1 operates on power supplied from a power supply device (not shown).

[0016] The processor 10 is, for example, a CPU, and performs various processes by executing programs. The memory 20 stores the programs executed by the processor 10 and various information used by the processor.

[0017] In addition to the CPU, the processor 10 may include a logic circuit block configured to perform signal processing for a specific application. In this case, some or all of the processing described below as being performed by the processor 10 may be performed by the logic circuit block.

[0018] The transmitting conversion circuit 50 transmits data output from the processor 10 to the other semiconductor chip 1 through wireless communication that utilizes inductive coupling between the transmitting coil 30 and the receiving coil 40 of the other semiconductor chip 1. The receiving conversion circuit 60 receives data from the other semiconductor chip 1 through wireless communication that utilizes inductive coupling between the receiving coil 40 and the other semiconductor chip 1. Note that terms that may have the same meaning as "inductive coupling" include "near-field inductive coupling," "near-field magnetic coupling," "magnetic field coupling," "electromagnetic induction," and "magnetic field resonance."

[0019] In the example of Figure 1, the semiconductor chip 1 has a separate coil for transmission (transmission coil 30) and a coil for reception (reception coil 40), but as shown in Figure 2, a configuration in which one coil is used for both transmission and reception may be adopted.

[0020] In the communication system shown in Fig. 2, the semiconductor chip 1 includes a coil 35 that is used for both transmission and reception, instead of the transmitter coil 30 and the receiver coil 40. Also, the semiconductor chip 1 includes a converter circuit 55 that combines the functions of the transmitter conversion circuit 50 and the receiver conversion circuit 60, instead of the transmitter conversion circuit 50 and the receiver conversion circuit 60. When the semiconductor chip 1 in Fig. 2 transmits data, the converter circuit 55 and the coil 35 play the same roles as the transmitter conversion circuit 50 and the transmitter coil 30 of the semiconductor chip 1 in Fig. 1. When the semiconductor chip 1 in Fig. 2 receives data, the converter circuit 55 and the coil 35 play the same roles as the receiver conversion circuit 60 and the receiver coil 40 of the semiconductor chip 1 in Fig. 1.

[0021] In the following, unless otherwise specified, the semiconductor chip 1 will be described assuming that it has the configuration shown in Fig. 1. However, the following description also applies to the case where the semiconductor chip 1 has the configuration shown in Fig. 2. In this case, the following description of the transmitting conversion circuit 50 and the transmitting coil 30 corresponds to the description of the conversion circuit 55 and the coil 35 of the transmitting semiconductor chip 1. Furthermore, the following description of the receiving conversion circuit 60 and the receiving coil 40 corresponds to the description of the conversion circuit 55 and the coil 35 of the receiving semiconductor chip 1.

[0022] 3 is a diagram illustrating the coupling between the transmitter coil 30 and the receiver coil 40 using an equivalent circuit. The transmitter coil 30 is represented by an equivalent circuit including an inductor Ltx, two resistors Rtx, and a capacitor Ctx. The receiver coil 40 is represented by an equivalent circuit including an inductor Lrx, two resistors Rrx, and a capacitor Crx.

[0023] In the equivalent circuit of the receiving coil 40, a bias voltage V is applied to the midpoint of the inductor Lrx. B For example, as shown in Figure 4, a bias voltage V is applied to Port 2, which is the midpoint of a two-turn coil. B This is achieved by applying

[0024] The transmitter coil 30 of a specific semiconductor chip 1 couples with the receiver coil 40 of another nearby semiconductor chip 1. In addition, the transmitter coil 30 of a specific semiconductor chip 1 also couples with the receiver coil 40 of the same semiconductor chip 1. Therefore, for example, the transmitter coil 30a of the semiconductor chip 1a shown in Fig. 1 couples with the receiver coil 40b of the semiconductor chip 1b and also with the receiver coil 40a of the semiconductor chip 1a. The coupling between any transmitter coil 30 and receiver coil 40 can be expressed by the equivalent circuit of Fig. 3, but the coupling coefficient changes depending on the positional relationship (distance, angle, etc.) between the transmitter coil 30 and receiver coil 40.

[0025] In addition, when the semiconductor chip 1 has only one coil as shown in Figure 2, no coupling occurs between two coils within the same semiconductor chip, but coupling occurs between the coils of two adjacent semiconductor chips 1, as in the case of Figure 1.

[0026] In the communication system of FIG. 1, semiconductor chip 1a and semiconductor chip 1b are arranged close to each other so that the coils are coupled between semiconductor chip 1a and semiconductor chip 1b.

[0027] The memory 20 of the semiconductor chip 1 pre-stores identification information (ID) of each semiconductor chip 1 included in the communication system and information (coupling relationship information) indicating the coupling relationships between the semiconductor chips 1 in the communication system. Therefore, by referencing the coupling relationship information, the semiconductor chip 1 can identify other semiconductor chips 1 with which it can directly communicate by inductive coupling in the communication system. For example, in the communication system of Figure 1, the semiconductor chip 1a can identify the semiconductor chip 1b as another semiconductor chip 1 with which it can directly communicate with the semiconductor chip 1a by referencing the coupling relationship information stored in the memory 20a.

[0028] <Wireless communication utilizing inductive coupling between coils> Wireless communication utilizing inductive coupling between coils will be described using an example in which semiconductor chip 1a transmits data to semiconductor chip 1b in the communication system of Fig. 1. In this case, the transmitting conversion circuit 50 and the transmitting coil 30 in Fig. 3 correspond to the transmitting conversion circuit 50a and the transmitting coil 30a of semiconductor chip 1a, respectively. Furthermore, the receiving conversion circuit 60 and the receiving coil 40 in Fig. 3 correspond to the receiving conversion circuit 60b and the receiving coil 40b of semiconductor chip 1b, respectively.

[0029] The processor 10a outputs a bit string representing data to be transmitted as a digital signal (pulse string) represented by two voltage values, High and Low, to the transmitting conversion circuit 50a. The transmitting conversion circuit 50a performs waveform conversion processing, including voltage conversion and pulse waveform shaping, on the pulse string output from the processor 10a, to generate Txdata and In the following explanation, is sometimes written as "Txdata (bar)".

[0030] FIG. 5A is a diagram showing an example of Txdata, and FIG. 5B is a diagram showing an example of Txdata (bar). Txdata has the same pulse waveform as the pulse train output from the processor 10a. Txdata (bar) has a pulse waveform in which the High and Low levels of Txdata are inverted. In the following explanation, it is assumed that the High voltage in the pulse train output from the processor 10a and the High voltage in Txdata are both 1.2 V. However, the High voltage in the pulse train output from the processor 10a and the High voltage in Txdata may be different.

[0031] The transmitting-side conversion circuit 50a applies voltages corresponding to Txdata and Txdata (bar) to the transmitting coil 30a. In the example of FIG. 3, the transmitting-side conversion circuit 50a and the transmitting coil 30a are connected so that Txdata is applied to the upper port of the transmitting coil 30a and Txdata (bar) is applied to the lower port. When Txdata is High and Txdata (bar) is Low, the current Itx in the transmitting coil 30a flows from the upper side to the lower side of the inductor Ltx in FIG. 3. This current corresponds to the period in FIG. 5C when the value of Itx is 5.0 mA. On the other hand, when Txdata is Low and Txdata (bar) is High, the current Itx in the transmitting coil 30a flows from the lower side to the upper side of the inductor Ltx in FIG. 3. This current corresponds to the period in FIG. 5C when the value of Itx is −5.0 mA (the period when the polarity is reversed compared to when Txdata is High and Txdata (bar) is Low).

[0032] When the current Itx flows through the transmitting coil 30a, a voltage corresponding to the transition of the current Itx is induced in the receiving coil 40b. The polarity of the induced voltage differs depending on whether the transition of Txdata is from low to high or from high to low.

[0033] 5D and 5E are diagrams showing examples of the waveform of the voltage induced in the receiving coil 40b. Vrx1 shown in FIG. 5D is the voltage observed at the upper port of the receiving coil 40b, and Vrx2 shown in FIG. 5E is the voltage observed at the lower port of the receiving coil 40b. Vrx1 is the voltage induced in the receiving coil 40b by the bias voltage V B Vrx1 fluctuates in the positive direction with respect to the induced voltage corresponding to the rising edges of the waveform of the current Itx in the transmitting coil 30a, and in the negative direction with respect to the induced voltage corresponding to the falling edges of the waveform of the current Itx in the transmitting coil 30a. Vrx2 fluctuates in the opposite direction to Vrx1 according to the rising and falling edges of the waveform of the current Itx in the transmitting coil 30a. The amplitudes of Vrx1 and Vrx2 are proportional to the magnitude of the current Itx and the coupling coefficient between the transmitting coil 30a and the receiving coil 40b.

[0034] The voltages Vrx1 and Vrx2 of the receiving coil 40b are input to a receiving conversion circuit 60b. For example, a hysteresis comparator can be used as the receiving conversion circuit 60b. The receiving conversion circuit 60b generates a pulse train (Rxdata) represented by two values, High and Low, shown in FIG. 5F, based on the voltages Vrx1 and Vrx2. The pulse train generated by the receiving conversion circuit 60b has a waveform corresponding to the pulse train output by the processor 10a. The receiving conversion circuit 60b inputs the generated pulse train to the processor 10b. In this way, the processor 10b can obtain a pulse train (Rxdata) corresponding to the pulse train (transmitted signal) output by the processor 10a as a received signal received via the receiving conversion circuit 60b.

[0035] The processor 10b samples the pulse train input from the receiving conversion circuit 60b at a predetermined sampling frequency, thereby decoding it into a binary signal train (bit train) represented by 1 (High) or 0 (Low). In the example of Figures 5A to 5F, the sampling frequency is 1 GHz (hence, the sampling period is 1 nanosecond (ns)), and the bit train "01101" is obtained.

[0036] In this way, the semiconductor chip 1a and the semiconductor chip 1b can transmit and receive data via wireless communication that utilizes inductive coupling between the coils.

[0037] <Frame Format for Data Transmission and Reception> Frames having a predetermined format can be used for transmitting and receiving data between semiconductor chips 1. Fig. 6 is a diagram showing an example of a frame format used by the semiconductor chip 1 for transmitting and receiving data. In the example of Fig. 6, the frame has a format including a preamble signal, a frame control signal, a frame length signal, a destination ID signal, a source ID signal, a data signal, and a frame check signal.

[0038] The preamble signal is composed of a predetermined signal sequence (for example, a bit sequence of a specific pattern such as "101101") that indicates the presence of a frame. By detecting the presence of the preamble signal, the processor 10 of the semiconductor chip 1 can detect that another semiconductor chip 1 is transmitting a frame.

[0039] The frame control signal is a signal that indicates the type of frame. Frame types include "information frame," "control frame," "management frame," and "evaluation frame." The frame format following the frame control signal varies depending on the frame type. Figure 6 corresponds to the case where the frame type is an information frame.

[0040] The frame length signal is a control signal that includes information about the length of a frame.

[0041] The destination ID signal indicates the identification information (ID) of the frame's destination semiconductor chip 1. For example, the destination ID signal of a frame transmitted from semiconductor chip 1a to semiconductor chip 1b includes a bit string indicating the ID of semiconductor chip 1b.

[0042] The sender ID signal indicates the ID of the semiconductor chip 1 that transmits the frame. For example, the sender ID signal of a frame transmitted from the semiconductor chip 1a to the semiconductor chip 1b includes a bit string that indicates the ID of the semiconductor chip 1a.

[0043] A data signal is a signal that contains the main body of data (information) to be transmitted, and may also contain a sequence number that indicates the order of the data signal.

[0044] The frame check signal is a signal used to check whether or not there are any errors in the received frame. For example, a cyclic redundancy check (CRC) code is used as the frame check signal. Upon receiving the frame check signal, the semiconductor chip 1 completes the reception of the frame.

[0045] <Outline of Sensing Process and Format of Evaluation Frame> The semiconductor chip 1 can perform sensing process. The sensing process is a process in which a semiconductor chip 1 acquires an evaluation value representing the quality of wireless communication with another semiconductor chip 1, and determines the positional relationship between these two semiconductor chips 1 based on the acquired evaluation value. In the sensing process, an evaluation frame is transmitted from one of the two semiconductor chips 1 to the other. Therefore, the sensing process includes a process in which the transmitting semiconductor chip 1 transmits an evaluation frame to the receiving semiconductor chip 1 (evaluation frame transmission process), a process in which the receiving semiconductor chip 1 acquires an evaluation value (evaluation value acquisition process), and a process in which the receiving semiconductor chip 1 determines the positional relationship (positional relationship determination process).

[0046] 7 is a diagram showing an example of the format of an evaluation frame. The evaluation frame is similar to the information frame in FIG. 6, but the frame control signal sets the frame type to "evaluation frame." The evaluation frame also includes an evaluation signal (first signal portion) instead of a data signal.

[0047] The evaluation signal is a signal used by the semiconductor chip 1 to obtain an evaluation value of wireless communication. In this embodiment, a value based on the number of bit errors in the received evaluation signal is obtained as the evaluation value. The evaluation value based on the number of bit errors may be the number of bit errors itself, or may be a value calculated based on the number of bit errors, such as a bit error rate (BER) calculated by dividing the number of bit errors by the number of bits in the evaluation signal. Furthermore, a block error rate (BLER), a frame error rate (FER), a packet error rate (PER), and the like can also be used as evaluation values ​​based on the number of bit errors, as long as they are values ​​calculated based on the number of bit errors so as to serve as indicators of the number of bit errors in the evaluation signal. For example, when the evaluation value is the number of bit errors, the fewer the number of bit errors, the better the quality of wireless communication is considered to be. Furthermore, when the evaluation value is the BER, the smaller the BER, the better the quality of wireless communication is considered to be.

[0048] A predetermined signal sequence (e.g., a bit sequence with a specific pattern such as "11100111") is set in the evaluation signal. For example, the semiconductor chip 1 can detect the number of bit errors in the evaluation signal by comparing the known evaluation signal with the actually received evaluation signal, and obtain an evaluation value of the wireless communication.

[0049] As described above, the amplitudes of the voltages Vrx1 and Vrx2 input to the receiving conversion circuit 60 are proportional to the magnitude of the current Itx in the transmitting coil 30 and the coupling coefficient between the transmitting coil 30 and the receiving coil 40. When the amplitudes of Vrx1 and Vrx2 are small, the signal is more susceptible to noise and other factors, increasing the probability of bit errors occurring in the received signal. Therefore, the number of bit errors in the evaluation signal varies depending on the coupling coefficient. Furthermore, the coupling coefficient varies depending on the positional relationship (distance, angle, etc.) between the two coils. As a result, the number of bit errors in the evaluation signal varies depending on the positional relationship (distance, angle, etc.) between the two coils. Therefore, the evaluation value not only represents the quality of wireless communication but also serves as an index of the positional relationship between the two semiconductor chips 1. For this reason, the semiconductor chip 1 can determine the positional relationship between the two semiconductor chips 1 based on the evaluation value. For example, if the evaluation value exceeds a predetermined threshold, the semiconductor chip 1 can determine that the positional relationship between the two semiconductor chips 1 has deviated from the desired positional relationship.

[0050] 5A to 5F, the voltage (Txdata and Txdata(bar)) applied (input) to the transmitting coil 30 has a pattern representing the bit string to be transmitted. Therefore, the voltage pattern applied to the transmitting coil 30 has frequency characteristics that correspond to the content (bit pattern) of the bit string to be transmitted.

[0051] Here, the coupling between the transmitting coil 30 and the receiving coil 40 has frequency characteristics. Therefore, the probability of bit errors occurring in the received signal is affected not only by the coupling coefficient based on the positional relationship between the two coils described above, but also by the frequency characteristics of the voltage pattern applied to the transmitting coil 30a and the frequency characteristics of the coupling. Therefore, even if the positional relationship between the two coils does not change, a phenomenon may occur in which the frequency of bit errors occurs relatively high for bit strings transmitted using a particular voltage pattern and relatively low for bit strings transmitted using a different voltage pattern.

[0052] Therefore, the number of bit errors in the evaluation signal is affected by the frequency characteristics of the voltage pattern of the evaluation signal, which may result in a bias in the evaluation value based on the number of bit errors, reducing the accuracy of the determination of the positional relationship between the two semiconductor chips 1.

[0053] Therefore, below, we will explain a sensing process that includes a configuration that reduces the influence of bias on the evaluation value caused by frequency characteristics by using multiple evaluation signals with different frequency characteristics (more precisely, multiple voltage patterns with different frequency characteristics).

[0054] The sensing process of this embodiment is not limited to a configuration using multiple evaluation signals with different frequency characteristics. Even if a configuration is adopted in which the frequency characteristics of the evaluation signals do not change, the acquired evaluation value can be used to determine the positional relationship.

[0055] <Sensing process using multiple evaluation signals with different frequency characteristics> Below, we will explain the sensing process using multiple evaluation signals with different frequency characteristics, using the example of a case where semiconductor chip 1a transmits an evaluation frame to semiconductor chip 1b in the communication system of Figure 1.

[0056] Methods for changing the frequency characteristics of the evaluation signal (more precisely, the frequency characteristics of the voltage pattern into which the evaluation signal is encoded) include, for example, changing the bit pattern of the evaluation signal, inverting part of the voltage pattern, and changing the transmission line code of the evaluation signal. Below, we will explain the use of each method in turn. It is also possible to use a combination of two or three of these three methods.

[0057] Method of changing the bit pattern of the evaluation signal As mentioned above, the voltage pattern has frequency characteristics that correspond to the bit pattern transmitted. Therefore, by changing the bit pattern between multiple evaluation signals, it is possible to change the frequency characteristics between multiple evaluation signals.

[0058] 8 is a diagram showing an example of an evaluation signal table that manages a plurality of evaluation signals (bit patterns). The evaluation signal table includes an index N, an evaluation signal ID, and an evaluation signal (bit pattern). In the example of FIG. 8, three types of evaluation signals are included in the evaluation signal table. A common evaluation signal table is pre-stored in the memory 20 of each semiconductor chip 1 in the communication system. In other words, information on the plurality of bit patterns to be used is shared in advance among the plurality of semiconductor chips 1 included in the communication system.

[0059] 9 is a flowchart of an evaluation frame transmission process in the sensing process when using a method of changing the bit pattern of the evaluation signal, in which evaluation frames containing evaluation signals with different bit patterns are transmitted for each frame.

[0060] In S901, the processor 10a of the semiconductor chip 1a initializes the index N to 1.

[0061] In S902, the processor 10a of the semiconductor chip 1a sets a predetermined bit string indicating the presence of a frame in the "preamble signal" of the evaluation frame in order to generate the evaluation frame (see FIG. 7).

[0062] In S903, the processor 10a sets a bit string representing the "evaluation frame" in the "frame control signal" of the evaluation frame. The processor 10a also references the evaluation signal table stored in the memory 20a and sets a bit string representing the evaluation signal ID corresponding to the current index N (for example, "1100" when N=1) in the "frame control signal" (second signal portion).

[0063] In S904, the processor 10a sets a bit string representing the frame length of the evaluation frame in the "frame length signal" of the evaluation frame.

[0064] In S905, the processor 10a sets a bit string representing the ID of the semiconductor chip 1b, which is the destination of the evaluation frame, in the "destination ID signal" of the evaluation frame.

[0065] In S906, the processor 10a sets a bit string representing the ID of the semiconductor chip 1a in the "source ID signal" of the evaluation frame.

[0066] In S907, the processor 10a refers to the evaluation signal table stored in the memory 20a and sets the bit string representing the evaluation signal corresponding to the current index N (for example, "1100101000110101" when N = 1) as the "evaluation signal" of the evaluation frame.

[0067] In S908, the processor 10a sets a check bit string (for example, a CRC code generated from the bit string that constitutes the frame) in the "frame check signal" of the evaluation frame.

[0068] In S909, the processor 10a transmits an evaluation frame to the semiconductor chip 1b. Specifically, the processor 10a applies Txdata and Txdata(bar) to the transmitting coil 30a by inputting a pulse sequence corresponding to the bit sequence of the evaluation frame to the transmitting conversion circuit 50. As a result, a voltage pattern corresponding to the bit sequence of the evaluation frame is applied (input) to the transmitting coil 30a, thereby achieving wireless transmission of the evaluation frame.

[0069] In S910, the processor 10a updates the index N by calculating "N = (N mod Nmax) + 1." The maximum value of index N (Nmax) is the number of evaluation signals (bit patterns) stored in the evaluation signal table, which is 3 in the example of FIG. 8. "(N mod Nmax)" refers to the remainder obtained by dividing N by Nmax. For example, when N = 1 and Nmax = 3, (N mod Nmax) = 1, so N is updated to 2. Processing then returns to S902, and the next evaluation frame is transmitted by the processes of S902 to S909. Because N has been updated, a bit pattern different from that of the previous evaluation frame is used for the "evaluation signal" of the next evaluation frame. When the evaluation signal table of FIG. 8 is used, N is updated in the order of 1, 2, 3, 1, 2, 3, .... Therefore, three types of bit patterns are repeatedly used as evaluation signals.

[0070] Next, referring to FIG. 10 , the evaluation value acquisition process of the sensing process when using the method of changing the bit pattern of the evaluation signal will be described. In S1001, the processor 10b of the semiconductor chip 1b determines whether a known preamble signal has been detected (i.e., whether the adjacent semiconductor chip 1a is transmitting a frame). Specifically, the processor 10b compares the bit sequence obtained by decoding the pulse sequence (Rxdata) supplied from the receiving conversion circuit 60b at a predetermined sampling frequency with the known preamble signal, and if the two match, determines that the known preamble signal has been detected. The processor 10b repeats the process of S1001 until the preamble signal is detected. When the preamble signal is detected, the process proceeds to S1002.

[0071] In S1002, the processor 10b decodes the frame control signal following the preamble signal and determines whether the frame type is an evaluation frame. If the frame type is an evaluation frame, the process proceeds to S1004; if not, the process proceeds to S1003. Note that if the frame type is an evaluation frame, the frame control signal also includes a bit string representing the evaluation signal ID, and therefore the evaluation signal ID is also obtained by decoding the frame control signal.

[0072] In S1003, the processor 10b performs processing appropriate to the type of frame, and then the process returns to S1001.

[0073] In S1004, the processor 10b decodes the frame length signal and confirms the length of the frame.

[0074] In S1005, the processor 10b decodes the destination ID signal and determines whether the frame is addressed to itself (whether the destination ID is the ID of the semiconductor chip 1b). If the frame is addressed to itself, the process proceeds to S1006; if not, the process returns to S1001.

[0075] In S1006, the processor 10b decodes the sender ID signal and acquires the ID of the semiconductor chip 1 that is the sender of the frame. If the semiconductor chip 1a is the sender of the frame, the ID of the semiconductor chip 1a is acquired.

[0076] In S1007, the processor 10b decodes the evaluation signal and acquires the decoded evaluation signal (received bit string).

[0077] In S1008, the processor 10b acquires an evaluation value based on the evaluation signal ID and the decoded evaluation signal (received bit sequence). Specifically, the processor 10b references an evaluation signal table stored in the memory 20b and acquires a bit sequence corresponding to the evaluation signal ID (i.e., a correct bit sequence). The processor 10b then compares the acquired correct bit sequence with the received bit sequence to detect (count) the number of bit errors and acquire an evaluation value based on the number of bit errors. In the following description, the evaluation value based on the number of bit errors is assumed to be a BER as an example. The processor 10b records the acquired evaluation value in the memory 20b. At this time, the processor 10b associates the reception time of the evaluation frame from which the evaluation value was acquired and the source ID of the evaluation frame with the evaluation value and records them. This allows information indicating time-series changes in the evaluation value corresponding to a specific source to be stored in the memory 20b.

[0078] In S1109, the processor 10b decodes the frame check signal and determines whether the evaluation frame was received without error. Furthermore, the processor 10b may transmit an Acknowledgement (ACK) signal (if the frame check is OK) or a Negative ACK (NACK) signal (if the frame check is NG) to the semiconductor chip 1b depending on the determination result (frame check result). Then, the process returns to S1001.

[0079] Next, the positional relationship determination process of the sensing process will be described with reference to Fig. 11. The positional relationship determination process of Fig. 11 is executed in parallel with the evaluation value acquisition process of Fig. 10. Therefore, evaluation values ​​are repeatedly acquired in parallel with the positional relationship determination process.

[0080] In S1101, the processor 10b of the semiconductor chip 1b determines whether a new evaluation value has been acquired by the evaluation value acquisition process. The processor 10b repeats the process of S1101 until a new evaluation value is acquired. When a new evaluation value is acquired, the process proceeds to S1102.

[0081] In S1102, the processor 10b calculates (obtains) a composite evaluation value by performing a calculation based on the most recently acquired multiple evaluation values, including the new evaluation value. While the specific calculation method is not particularly limited, for example, the processor 10b may calculate the average value of the multiple evaluation values ​​or the sum of the multiple evaluation values ​​as the composite evaluation value. Any method can be used to calculate the composite evaluation value as long as it obtains a value based on the number of bit errors detected in the most recent multiple evaluation signals. In the following, as an example, the composite evaluation value is assumed to be the average value (average BER) of multiple BERs. Furthermore, while the number M (M≧2) of evaluation values ​​used to obtain the composite evaluation value is not particularly limited, the greater the number M of evaluation values ​​used, the greater the effect of reducing the influence of bias in the evaluation values ​​due to frequency characteristics. Furthermore, the case of M=1 is not excluded from this embodiment. Even when M=1, accuracy may be relatively lower compared to when M≧2, but it is still possible to determine the positional relationship based on a single evaluation value.

[0082] The processor 10b may also store the calculated composite evaluation value in the memory 20b in association with the time at which the evaluation frame corresponding to the latest evaluation value was received, thereby recording the time-series change in the composite evaluation value.

[0083] In addition, if the number of acquired evaluation values ​​is smaller than M, the processor 10b may calculate a composite evaluation value based on all acquired evaluation values, or may return processing to S1101 without calculating a composite evaluation value.

[0084] In S1103, the processor 10b makes a determination regarding the positional relationship based on the composite evaluation value. For example, if the composite evaluation value (average BER) exceeds a predetermined threshold (e.g., 0.1), the semiconductor chip 1b can determine that the positional relationship between the semiconductor chip 1b and the semiconductor chip 1a has deviated from the original desired positional relationship. Various specific examples of the determination regarding the positional relationship will be described later.

[0085] In S1104, the processor 10b performs processing related to the determination result regarding the positional relationship. The processing here is not particularly limited, but for example, the processor 10b may transmit the determination result to an external management device (not shown). In this case, the external management device can determine whether the positional relationship between the semiconductor chip 1b and the semiconductor chip 1a is the desired positional relationship based on the received determination result, and can issue a warning to the user as necessary. Then, the processing returns to S1101.

[0086] 5A to 5F, the processor 10b can decode the pulse train input from the receiving conversion circuit 60b into a binary signal train (bit train) represented by 1 (High) or 0 (Low) by sampling it at a predetermined sampling frequency. In the example of FIGS. 5A to 5F, the sampling frequency is 1 GHz (hence, the sampling period is 1 nanosecond (ns)), and the bit train "01101" is obtained.

[0087] Here, the processor 10b does not need to perform sampling over the entire period corresponding to each bit (1 bit period), but can decode the pulse sequence into a bit sequence by performing sampling at a specific timing (sampling timing) within the 1 bit period. For example, as shown by the arrow pointing from top to bottom in Figure 12 (reference numeral 1201), the processor 10b can obtain the bit sequence "10011001" by performing sampling earlier than the center of the 1 bit period. In this case, even if the voltage is inverted during periods other than the sampling timing, the decoded bit sequence does not change.

[0088] FIG. 12 (reference numeral 1202) shows an example in which the voltage of the latter half of a bit period is inverted for some bits. In FIG. 12 (reference numeral 1202), periods indicated by left and right arrows (such as period 1201) indicate periods in which the voltage is inverted. Period 1201 is the latter half of a bit period corresponding to "1," and therefore should have a "High" voltage. However, since period 1201 is outside the sampling timing, the decoded bit is "1," as in the case of FIG. 12 (reference numeral 1201). In the example of FIG. 12 (reference numeral 1202), voltage inversion occurs in the latter half of the bit period corresponding to "1" in the bit pattern "10" and the bit period corresponding to "0" in the bit pattern "01."

[0089] When the voltage in a certain bit period in the voltage pattern is partially inverted, the frequency characteristics of the voltage pattern change. Therefore, by partially inverting the voltage in the period outside the sampling timing, the frequency characteristics of the voltage pattern can be changed without changing the bit pattern.

[0090] 12 (reference numeral 1202), the period in which the voltage is inverted is the latter half (the last 50%) of one bit period, but the voltage can be inverted at any portion as long as it does not include the sampling timing. For example, if the receiving processor 10b is configured to perform sampling at a timing within 15% from the beginning of one bit period, the transmitting processor 10a can invert the voltage at any portion excluding the first 15% of the one bit period.

[0091] FIG. 13 is a diagram showing an example of an inversion rule table that manages the inversion rules for the voltages in the evaluation signals. The inversion rule table includes an index N and an inversion rule. In the example of FIG. 13, three types of inversion rules are included in the inversion rule table. An inversion rule table is pre-stored in the memory 20 of each semiconductor chip 1 in the communication system. Unlike the case of FIG. 8, different inversion rule tables may be stored in the semiconductor chip 1a and the semiconductor chip 1b.

[0092] 14 is a flowchart of the evaluation frame transmission process of the sensing process when using a method of inverting part of the voltage pattern, where Nmax is the number of inversion rules stored in the inversion rule table, which is 3 in the example of FIG.

[0093] In S1403, the processor 10a sets a bit string representing the "evaluation frame" in the "frame control signal" of the evaluation frame. Here, unlike S903 in Fig. 9, the processor 10a does not need to set a bit string representing the evaluation signal ID in the "frame control signal."

[0094] In S1407, the processor 10a sets a bit string representing the evaluation signal (e.g., "10011001") to the "evaluation signal" of the evaluation frame. Unlike S907 in Fig. 9, the same bit pattern can be used as the evaluation signal regardless of the current value of index N.

[0095] In S1409, the processor 10a transmits an evaluation frame to the semiconductor chip 1b. Specifically, the processor 10a applies Txdata and Txdata(bar) to the transmitting coil 30a by inputting a pulse sequence corresponding to the bit sequence of the evaluation frame to the transmitting conversion circuit 50. At this time, the processor 10a refers to the inversion rule table stored in the memory 20a and applies an inversion rule corresponding to the current index N to the voltage of the evaluation signal in the evaluation frame. For example, in the example of FIG. 13, when N = 1, the voltage pattern shown in FIG. 12 (reference numeral 1201) is input to the transmitting coil 30a as Txdata, and when N = 2, the voltage pattern shown in FIG. 12 (reference numeral 1202) is input to the transmitting coil 30a as Txdata. This allows the frequency characteristics of the voltage pattern to be changed for each evaluation frame without changing the bit pattern of the evaluation signal.

[0096] In the example of FIG. 12 (reference numeral 1202), the period during which the voltage is inverted is fixed to the latter half (the last 50%) of one bit period. However, as shown in FIG. 12 (reference numeral 1203), a configuration may be adopted in which the period during which the voltage is inverted varies for each bit. In the example of FIG. 12 (reference numeral 1203), the bits to be inverted are "1" in the bit pattern of "10" and "0" in the bit pattern of "01," as in FIG. 12 (reference numeral 1202). However, the portion to be inverted in each bit period corresponding to the bit to be inverted is determined randomly for each bit (this determination is made so that the portion to be inverted does not include the sampling timing). When such a configuration is adopted, there is no need to store an inversion rule table in the memory 20 of each semiconductor chip 1.

[0097] Next, the evaluation value acquisition process of the sensing process when using the method of inverting part of the voltage pattern will be described with reference to FIG.

[0098] In S1502, the processor 10b decodes the frame control signal following the preamble signal, similar to S1002 in Fig. 10, and determines whether the frame type is an evaluation frame. If the frame type is an evaluation frame, the process proceeds to S1004; if not, the process proceeds to S1003. Note that, unlike S1002 in Fig. 10, an evaluation signal ID is not acquired even if the frame type is an evaluation frame.

[0099] In S1507, the processor 10b decodes the evaluation signal and obtains the decoded evaluation signal (received bit string). Sampling for decoding the evaluation signal is performed at a predetermined sampling timing so as not to fall within a period in which the voltage is inverted. Therefore, the processor 10b can decode the evaluation signal without knowing the inversion rule used on the transmitting side.

[0100] In S1508, the processor 10b compares a predetermined, known, correct bit sequence with the decoded evaluation signal (the received bit sequence) to detect (count) the number of bit errors and obtain an evaluation value based on the number of bit errors. The processor 10b records the obtained evaluation value in the memory 20b. At that time, the processor 10b associates the reception time of the evaluation frame from which the evaluation value was obtained and the sender ID of the evaluation frame with the evaluation value and records them. As a result, information indicating the time series changes in the evaluation value corresponding to a specific sender is stored in the memory 20b.

[0101] As for the positional relationship determination process in the sensing process, the processor 10b executes the process shown in FIG. 11 in the same manner as in the case of using the method of changing the bit pattern of the evaluation signal.

[0102] Method of Changing the Transmission Line Code of the Evaluation Signal In the explanation so far, Non-Return to Zero (NRZ) is used as the transmission line code (encoding method) for wireless communication between the semiconductor chips 1. Other transmission line codes that can be used besides NRZ include, for example, Return to Zero (RZ), Non-Return to Zero Inversion (NRZI), and Manchester code.

[0103] 16A to 16C are diagrams illustrating the Return to Zero (RZ) code, the Non-Return to Zero Inversion (NRZI) code, and the Manchester code. As can be seen from FIGS. 16A to 16C, even if the bit pattern is the same, if the transmission line code is different, the voltage pattern will be different and therefore the frequency characteristics will also be different. Therefore, by changing the transmission line code of the evaluation signal, it is possible to change the frequency characteristics of the voltage pattern representing the evaluation signal without changing the bit pattern.

[0104] 17 is a diagram showing an example of a transmission line code table that manages a plurality of transmission line codes. The transmission line code table includes an index N, an evaluation signal ID, and a transmission line code. In the example of FIG. 17, four types of transmission line codes are included in the transmission line code table. A common transmission line code table is pre-stored in the memory 20 of each semiconductor chip 1 in the communication system. That is, information on the plurality of transmission line codes to be used is shared in advance among the plurality of semiconductor chips 1 included in the communication system.

[0105] 18 is a flowchart of the evaluation frame transmission process in the sensing process when using a method of changing the line code of the evaluation signal. In FIG. 18, Nmax is the number of line codes stored in the line code table, which is 4 in the example of FIG. 17.

[0106] In S1803, the processor 10a sets a bit string representing the "evaluation frame" in the "frame control signal" of the evaluation frame. The processor 10a also references the transmission channel code table stored in the memory 20a and sets a bit string representing the evaluation signal ID corresponding to the current index N (for example, "1100" when N=1) in the "frame control signal."

[0107] In S1807, the processor 10a sets a bit string representing the evaluation signal (e.g., "101100") to the "evaluation signal" of the evaluation frame. Here, unlike S907 in Fig. 9, the same bit pattern can be used as the evaluation signal regardless of the current value of index N.

[0108] In S1809, the processor 10a transmits an evaluation frame to the semiconductor chip 1b. Specifically, the processor 10a applies Txdata and Txdata(bar) to the transmitting coil 30a by inputting a pulse sequence corresponding to the bit sequence of the evaluation frame to the transmitting conversion circuit 50. At this time, the processor 10a references the transmission line code table stored in the memory 20a and encodes the bit sequence of the evaluation signal in the evaluation frame using the transmission line code corresponding to the current index N. This allows the frequency characteristics of the voltage pattern into which the evaluation signal is encoded to be changed for each evaluation frame without changing the bit pattern of the evaluation signal. Note that a predetermined transmission line code (e.g., NRZ) is used for the portions other than the evaluation signal.

[0109] Next, with reference to FIG. 19, an evaluation value acquisition process of the sensing process when using a method of changing the transmission line code of the evaluation signal will be described.

[0110] In S1902, the processor 10b decodes the frame control signal following the preamble signal and determines whether the frame type is an evaluation frame. If the frame type is an evaluation frame, the process proceeds to S1004; if not, the process proceeds to S1003. Note that if the frame type is an evaluation frame, the frame control signal also includes a bit string representing the evaluation signal ID, and therefore the evaluation signal ID is also obtained by decoding the frame control signal.

[0111] In S1907, the processor 10b decodes the evaluation signal based on the evaluation signal ID acquired in S1902 and acquires the decoded evaluation signal (received bit string). Specifically, the processor 10b refers to the line code table stored in the memory 20b and identifies the line code corresponding to the evaluation signal ID. The processor 10b then decodes the evaluation signal in accordance with the identified line code. Note that the processor 10b decodes the parts other than the evaluation signal in accordance with a predetermined line code (e.g., NRZ).

[0112] In S1908, the processor 10b compares a predetermined, known, correct bit sequence with the decoded evaluation signal (the received bit sequence) to detect (count) the number of bit errors and obtain an evaluation value based on the number of bit errors. The processor 10b records the obtained evaluation value in the memory 20b. At that time, the processor 10b associates the reception time of the evaluation frame from which the evaluation value was obtained and the sender ID of the evaluation frame with the evaluation value and records them. As a result, information indicating the time-series changes in the evaluation value corresponding to a specific sender is stored in the memory 20b.

[0113] As for the positional relationship determination process in the sensing process, the processor 10b executes the process shown in FIG. 11 in the same manner as in the case of using the method of changing the bit pattern of the evaluation signal.

[0114] <Modifications on the Method of Notifying Evaluation Signal ID> In the above description, the processor 10a of the semiconductor chip 1a notifies the semiconductor chip 1b of the evaluation signal ID by setting the evaluation signal ID in the frame control signal of the evaluation frame. However, the method of notifying the evaluation signal ID is not limited to the method described above.

[0115] As an example, a configuration can be adopted in which the evaluation signal ID also serves as a signal indicating the frame type. For example, if the signal indicating the frame type is 4 bits, the signal indicating the frame type is defined as follows: "0001" indicates an "information frame," "0010" indicates a "control frame," and "0011" indicates a "management frame." Furthermore, the signal indicating the frame type is defined as follows: "1100," "1101," and "1110," all of which are exemplified as evaluation signal IDs in FIG. 8, indicate an "evaluation frame." In this case, setting the evaluation signal ID in the frame control signal simultaneously means setting a signal indicating "evaluation frame" as the frame type in the frame control signal.

[0116] As another example, as shown in Fig. 20A, a region for the evaluation signal ID (second signal portion) may be provided between the sender ID signal and the evaluation signal of the evaluation frame. In this case, for frames other than the evaluation frame, the region for the evaluation signal ID may be deleted or used for other purposes. For example, for information frames, the region for the evaluation signal ID may be used as part of the region for the data signal.

[0117] By adopting either of the two configurations exemplified above, there is no need to provide additional bits for the evaluation frame in the frame control signal, thereby reducing the number of bits in the frame control signal and reducing wireless communication overhead.

[0118] Alternatively, a configuration may be adopted in which information indicating the change pattern of the evaluation signal is shared in advance between the semiconductor chips 1a and 1b, thereby eliminating the need to notify the evaluation signal ID. For example, the processor 10a of the semiconductor chip 1a transmits information indicating the change pattern of the evaluation signal to the semiconductor chip 1b using an information frame. This allows the processor 10b of the semiconductor chip 1b to know in advance that evaluation signals corresponding to three evaluation signal IDs will be used repeatedly in sequence, for example, in the order of evaluation signal IDs "1100" → "1101" → "1110" → "1100" → "1101" → "1110" → .... Thereafter, each time the processor 10b receives an evaluation frame, it identifies the correct evaluation signal (bit sequence) according to the change pattern of the evaluation signal and obtains an evaluation value by comparing the received bit sequence with the correct bit sequence. Even with this configuration, the number of bits in the frame control signal can be reduced, thereby reducing wireless communication overhead.

[0119] In a configuration that eliminates the need for notification of the evaluation signal ID, if the semiconductor chip 1a and the semiconductor chip 1b remain far apart for a long period of time, numerous bit errors may occur, potentially causing the semiconductor chip 1b to lose track of the timing of the evaluation signal change. Therefore, a configuration may be adopted in which information indicating the evaluation signal change pattern is shared in advance between the semiconductor chip 1a and the semiconductor chip 1b, and the semiconductor chip 1a explicitly notifies the semiconductor chip 1b of the evaluation signal ID. In this configuration, if the semiconductor chip 1b is unable to correctly acquire the evaluation signal ID due to a temporary bit error, it can identify the correct evaluation signal according to the previously shared change pattern and acquire the evaluation value. Furthermore, even if the semiconductor chip 1b loses track of the timing of the evaluation signal change, it can subsequently recognize the timing of the evaluation signal change when it correctly receives the evaluation signal ID.

[0120] <Modifications of the Format of the Evaluation Frame> In the above description, the evaluation frame has the format shown in Fig. 7 or 20A, etc. However, the format of the evaluation frame is not limited to the format shown in Fig. 7 or 20A, etc.

[0121] For example, if the transmission timing of the evaluation frame is shared in advance between the semiconductor chips 1a and 1b, the evaluation frame shown in Fig. 20B can be used. In this case, when a pulse train (Rxdata) is supplied from the receiving conversion circuit 60b at a known timing, the processor 10b of the semiconductor chip 1b determines that the pulse train is an evaluation frame and can obtain the evaluation signal ID and evaluation signal by decoding the pulse train.

[0122] An example of a method for sharing the transmission timing of the evaluation frame between the semiconductor chips 1a and 1b in advance is a method using an information frame (FIG. 6). For example, the processor 10a of the semiconductor chip 1a transmits to the semiconductor chip 1b an information frame in which information indicating the transmission timing is set in the "data signal," such as "after transmitting the information frame, transmit an evaluation frame every 0.2 seconds." By receiving this information frame, the processor 10b of the semiconductor chip 1b can recognize that the evaluation frame will be transmitted every 0.2 seconds, such as 0.2 seconds, 0.4 seconds, 0.6 seconds, and so on, starting from the transmission time of the information frame.

[0123] <Modifications on the Method of Generating Multiple Evaluation Signals> The above describes a configuration in which an evaluation signal table ( FIG. 8 ) that manages multiple evaluation signals (bit patterns) is used to generate multiple evaluation signals with different bit patterns. However, the method of generating multiple evaluation signals with different bit patterns is not limited to the method described above. Other examples include a method that uses a pseudo random bit sequence (PRBS) generator and a method that varies the number of bit repetitions. Each method will be described below in order.

[0124] Method Using a PRBS Generator In this method, each semiconductor chip 1 includes a PRBS generator. The PRBS generator can be implemented using any known technology (for example, the technology disclosed in Non-Patent Document 1). The PRBS generator may be implemented as a dedicated hardware circuit included in the semiconductor chip 1, or may be implemented as a software function executed by the processor 10 of the semiconductor chip 1. In the following description, it is assumed that the PRBS generator is implemented as a software function executed by the processor 10 of the semiconductor chip 1.

[0125] The PRBS generators of the semiconductor chips 1a and 1b are configured to generate bit strings (PRBS) using a common algorithm. A common initial value is set for the PRBS generators of the semiconductor chips 1a and 1b. In this case, the multiple bit strings sequentially generated by the PRBS generator of the semiconductor chip 1a match the multiple bit strings sequentially generated by the PRBS generator of the semiconductor chip 1b. The multiple bit strings sequentially generated in this manner can be used as multiple evaluation signals.

[0126] For example, the processor 10a of the semiconductor chip 1a sets a predetermined initial value in its own PRBS generator and transmits information indicating this initial value to the semiconductor chip 1b using an information frame. The processor 10b of the semiconductor chip 1b then sets the received initial value in its own PRBS generator. Thereafter, when sequentially transmitting multiple evaluation frames, the processor 10a of the semiconductor chip 1a uses each bit sequence sequentially generated by the PRBS generator as an evaluation signal for each evaluation frame. Each time an evaluation frame is received, the processor 10b of the semiconductor chip 1b generates a bit sequence using the PRBS generator and obtains an evaluation value by comparing the decoded evaluation signal (the received bit sequence) with the generated bit sequence (i.e., the correct bit sequence).

[0127] When generating multiple evaluation signals using a PRBS generator in this way, there is no need to store an evaluation signal table ( FIG. 8 ) in the memory 20 of each semiconductor chip 1. This reduces the amount of memory 20 used. Furthermore, because there is no need to include an evaluation signal ID in the evaluation frame, the number of bits in the evaluation frame can be reduced, thereby reducing wireless communication overhead.

[0128] Alternatively, a configuration may be adopted in which multiple initial values ​​are shared in advance between the semiconductor chip 1a and the semiconductor chip 1b, and multiple evaluation signals are generated for each of the multiple initial values ​​using a PRBS generator. For example, the processor 10a of the semiconductor chip 1a uses an information frame to transmit information indicating the initial value X and the initial value Y to the semiconductor chip 1b. Thereafter, when sequentially transmitting multiple evaluation frames, the processor 10a uses a different bit string for each frame as the evaluation signal, such as the bit string generated the first time from the initial value X, the bit string generated the first time from the initial value Y, the bit string generated the second time from the initial value X, the bit string generated the second time from the initial value Y, the bit string generated the third time from the initial value X, etc. This further reduces bias in the frequency characteristics of the evaluation signals.

[0129] ●Method of changing the number of times a bit is repeated By changing the number of times each bit in a specific bit pattern is repeated, it is possible to generate multiple bit patterns that can be used as multiple evaluation signals from a single bit pattern.

[0130] For example, for an 8-bit bit pattern "11001010," if each bit is repeated twice, a 16-bit bit pattern "1111000011001100" is obtained. The original bit pattern "11001010" (repetition count = 1) and the bit pattern "1111000011001100" (repetition count = 2) obtained by repeating the bits can be used as multiple evaluation signals.

[0131] When this method is used, the original bit pattern is shared in advance between the semiconductor chip 1a and the semiconductor chip 1b. For example, the processor 10a of the semiconductor chip 1a uses an information frame to transmit information indicating the original bit pattern to the semiconductor chip 1b. The processor 10a of the semiconductor chip 1a can transmit multiple evaluation signals with different frequency characteristics by changing the number of repetitions from 1, 2, 1, 2, ... each time it transmits an evaluation frame. The processor 10b of the semiconductor chip 1b can generate a correct bit string to be compared with the received bit string from the original bit pattern by changing the number of repetitions from 1, 2, 1, 2, ... each time it receives an evaluation frame.

[0132] In order to unify the number of bits among multiple evaluation signals, a part of a bit pattern obtained by repeating bits may be extracted and used as an evaluation signal. For example, "11110000" extracted from the first 8 bits of the bit pattern "1111000011001100" (number of repetitions = 2) may be used as the bit pattern corresponding to "number of repetitions = 2."

[0133] When generating multiple evaluation signals by changing the number of repetitions of each bit in a specific bit pattern in this way, there is no need to store an evaluation signal table ( FIG. 8 ) in the memory 20 of each semiconductor chip 1. This reduces the amount of memory 20 used. Furthermore, because there is no need to include an evaluation signal ID in the evaluation frame, the number of bits in the evaluation frame can be reduced, thereby reducing wireless communication overhead.

[0134] The processor 10a may include information indicating the number of times a bit is repeated in the evaluation frame, which makes it possible to change the number of times the bit is repeated in any pattern.

[0135] <Modifications Regarding the Length (Number of Bits) of the Evaluation Signal> Generally, the more bits in the evaluation signal, the more accurate the evaluation value can be obtained. However, when the distance between the semiconductor chips 1 is long and the BER is large (e.g., approximately 0.5), increasing the number of bits in the evaluation signal does not significantly improve the accuracy of the evaluation value (BER). Therefore, a configuration may be adopted in which the number of bits in the evaluation signal is changed depending on the evaluation value.

[0136] In this case, the processor 10b of the semiconductor chip 1b acquires the evaluation value and then transmits the acquired evaluation value to the semiconductor chip 1a. For example, the processor 10b can include the evaluation value in an ACK signal or a NACK signal (see S1009 in FIGS. 10, 15, and 19) that is transmitted to the semiconductor chip 1a.

[0137] In addition, if the processor 10a is unable to receive an ACK signal or NACK signal corresponding to the transmitted evaluation frame, the evaluation value (BER) may be determined to be 0.5, since the quality of the wireless communication is likely to be extremely poor.

[0138] The processor 10a of the semiconductor chip 1a compares the received evaluation value with one or more thresholds to determine the number of bits of the evaluation signal of the evaluation frame to be transmitted next. For example, when the evaluation value (BER) is 10 －１０ If the bit count is less than 16, the bit count is determined to be 16. －１０ If the BER is equal to or greater than 0.1 and less than 0.1, the number of bits is determined to be 8, and if the BER is equal to or greater than 0.1, the number of bits is determined to be 4. This prevents the transmission of long evaluation signals in situations where little improvement in the accuracy of the evaluation value can be expected, thereby realizing efficient wireless communication.

[0139] The processors 10a and 10b are configured to acquire an evaluation signal with the longest number of bits that can possibly be determined. For example, when using a PRBS generator, if the longest number of bits is 16, the PRBS generators of the processors 10a and 10b are configured to generate a 16-bit bit string. For example, if the actually determined number of bits is 8, the processors 10a and 10b can use the first 8 bits of the 16-bit bit string generated by the PRBS generator as the evaluation signal. The processor 10b can determine the number of bits of the evaluation signal in the received evaluation frame by subtracting the length of the region other than the evaluation signal from the frame length acquired from the "frame length signal" of the evaluation frame.

[0140] <Various Specific Examples of Determination Regarding Positional Relationship> Here, a specific example of determination regarding the positional relationship performed in S1103 of Fig. 11 will be described. Note that the following description will be given of a case where the semiconductor chip 1b transmits an evaluation frame to the semiconductor chip 1a (hence, a case where the semiconductor chip 1a executes the positional relationship determination process of Fig. 11).

[0141] For example, as shown in Figure 21, consider a case where semiconductor chips 1a and 1b are placed on a measurement target 4, spaced a distance Dx apart in the horizontal direction (X-axis direction). The measurement target 4 is a material that expands and contracts in the X-axis direction, such as an iron rail or steel frame. In this case, when the measurement target 4 expands and contracts in the X-axis direction due to factors such as temperature changes, the distance Dx changes accordingly. As described above, when the distance Dx changes, the coupling coefficient between the semiconductor chip 1a and the semiconductor chip 1b changes, and the number of bit errors in the evaluation signal changes. Therefore, the evaluation value (e.g., BER) and the composite evaluation value (e.g., average BER) based on the number of bit errors also change.

[0142] 22 is a diagram showing an example of the relationship between the distance Dx between the semiconductor chips 1a and 1b and the BER in graph and table form. Information showing the relationship between the distance Dx and the BER can be obtained, for example, by conducting an experiment in advance to measure the BER at multiple distances. The BER obtained here may be the BER based on one evaluation signal, or may be the average BER based on multiple evaluation signals. Therefore, the "BER" shown in FIG. 22 may be the average BER. This also applies to FIG. 23 and subsequent figures.

[0143] As can be seen from Fig. 22, the BER changes significantly at a distance of around 450 µm. Therefore, the BER (1 × 10 －４ ) as a threshold value and stored in advance in the memory 20 of each semiconductor chip 1. In this case, in S1103 of FIG. 11, the processor 10a of the semiconductor chip 1a calculates the average BER (composite evaluation value) acquired in S1102 and the threshold value (1×10 －４ ) it is possible to determine whether the distance Dx is greater than 450 μm. That is, as a determination regarding the positional relationship, it is possible to determine whether the distance Dx is greater than a specific distance (here, 450 μm).

[0144] Also, for example, it is assumed that Dx is less than 450 μm in the original desirable positional relationship. In this case, the processor 10a determines whether the average BER (composite evaluation value) acquired in S1102 is greater than or equal to the threshold value (1×10 －４ ) is exceeded, it can be determined that the positional relationship between the semiconductor chips 1a and 1b has shifted from the original desirable positional relationship.

[0145] In the example of Figure 22, the change in distance Dx occurs in response to expansion and contraction of the measurement object 4, so the communication system including semiconductor chips 1a and 1b can serve as a sensor that detects expansion and contraction of the measurement object 4.

[0146] In the example of FIG. 22, the number of thresholds for BER is 1, but it may be 2 or more. In other words, the number of thresholds L may be any number as long as it is an integer of 1 or more. FIG. 23 is a diagram showing an example in which four thresholds are set for BER. In this example, the four thresholds are set to four BERs (1×10) corresponding to Dx=Dth1 (440 μm), Dth2 (445 μm), Dth3 (450 μm), and Dth4 (460 μm). －８ , 1 x 10 －５ , 1 x 10 －４ , 1 x 10 －３ ) are stored in advance in the memory 20 of each semiconductor chip 1. In this case, by determining where the average BER acquired in S1102 is located in the five sections defined by the four thresholds, it is possible to determine the positional relationship more accurately.

[0147] 23, information showing the relationship between the distance Dx and the BER in detail may be stored in the memory 20 of each semiconductor chip 1. In this case, it becomes possible to determine the positional relationship in more detail.

[0148] In the above description, the determination of the positional relationship is performed based on the distance Dx between the semiconductor chips 1a and 1b in the horizontal direction (X-axis direction). However, in this embodiment, the positional relationship that can be determined is not limited to the distance Dx in the horizontal direction (X-axis direction).

[0149] For example, as shown in Fig. 24A, consider a case where semiconductor chips 1a and 1b are displaced in the Y-axis direction due to the properties of measurement target 4. In this case, as shown in Fig. 24B, by acquiring information indicating the relationship between the displacement amount Dy in the Y-axis direction and the BER through a prior measurement, it is possible to determine a BER threshold value related to the displacement amount Dy and store it in memory 20 of each semiconductor chip 1. This makes it possible to make a judgment related to the displacement amount Dy as a judgment related to the positional relationship.

[0150] As another example, consider the case shown in Figures 25A and 25B, where semiconductor chip 1a is placed on measurement target 4a and semiconductor chip 1b is placed on measurement target 4b. The contact point between measurement target 4a and measurement target 4b corresponds to the midpoint between semiconductor chip 1a and semiconductor chip 1b, and measurement target 4a is configured to rotate around this contact point. When measurement target 4a and measurement target 4b are aligned horizontally, the distance in the X-axis direction between semiconductor chips 1a and 1b is Dx. In this case, as shown in Figure 25C, by obtaining information indicating the relationship between the angle Da of measurement target 4a relative to the X-axis and the BER through prior measurement, a BER threshold value for angle Da can be determined and stored in memory 20 of each semiconductor chip 1. This makes it possible to determine the angle Da as a determination regarding the positional relationship.

[0151] As another example, consider the case where semiconductor chips 1a and 1b are arranged as shown in Figures 26A and 26B. Unlike the case in Figures 25A and 25B, in Figures 26A and 26B, measurement target 4a rotates around the left side as an axis. In this case, as shown in Figure 26C, by obtaining information indicating the relationship between the angle Da of measurement target 4a relative to the X-axis and the BER through a prior measurement, a BER threshold value for angle Da can be determined and stored in memory 20 of each semiconductor chip 1. This makes it possible to make a judgment regarding angle Da as a judgment regarding the positional relationship.

[0152] As another example, consider the case where semiconductor chips 1a and 1b are arranged as shown in FIGS. 27A and 27B. Unlike the case of FIGS. 26A and 26B, in FIGS. 27A and 27B, the measurement target 4a rotates about the Y-axis, which passes through the center of the semiconductor chip 1a in the X-axis direction. In this case, as shown in FIG. 27C, by acquiring information indicating the relationship between the rotation angle Dr of the measurement target 4a relative to the X-axis and the BER through a preliminary measurement, a BER threshold value for the rotation angle Dr can be determined and stored in the memory 20 of each semiconductor chip 1. This makes it possible to determine the positional relationship based on the rotation angle Dr. Note that in this case, when the rotation angle Dr exceeds 90 degrees, the direction of the magnetic flux penetrating the transmitter coil 30a of the semiconductor chip 1a is reversed compared to when the rotation angle Dr is 90 degrees or less. Therefore, the polarity of the voltage induced in the transmitter coil 30a is reversed, and as a result, the polarity of Rxdata is also reversed. Therefore, the processor 10a of the semiconductor chip 1a calculates the BER taking the pulse reversal into account.

[0153] As another example, consider the case where semiconductor chips 1a and 1b are arranged as shown in FIG. 28A. In FIG. 28A, the measurement target 4b rotates about the X-axis axis that passes through the center of the Y-axis direction of the semiconductor chip 1b. In this case, as shown in FIG. 28B, by acquiring information indicating the relationship between the rotation angle Dr of the measurement target 4b relative to the Y-axis and the BER through a preliminary measurement, a BER threshold value for the rotation angle Dr can be determined and stored in the memory 20 of each semiconductor chip 1. This makes it possible to determine the positional relationship based on the rotation angle Dr. Note that in this case, when the rotation angle Dr exceeds 90 degrees, the direction of the magnetic flux penetrating the transmitter coil 30a of the semiconductor chip 1a reverses compared to when the rotation angle Dr is 90 degrees or less. Therefore, the polarity of the voltage induced in the transmitter coil 30a reverses, and as a result, the polarity of Rxdata also reverses. Therefore, the processor 10a of the semiconductor chip 1a calculates the BER taking the pulse reversal into account.

[0154] In the examples described above, the semiconductor chips 1a and 1b are arranged in the X-axis direction on the measurement target 4 (or on the measurement targets 4a and 4b). However, this embodiment is also applicable to the case where the semiconductor chips 1a and 1b are arranged (stacked) in the vertical direction (Z-axis direction).

[0155] For example, consider a case where semiconductor chips 1a and 1b are arranged as shown in Figure 29A. In this example, the distance Dz in the Z-axis direction between semiconductor chips 1a and 1b changes. In this case, as shown in Figure 29B, by obtaining information indicating the relationship between the distance Dz in the Z-axis direction and the BER through a prior measurement, a BER threshold value for the distance Dz can be determined and stored in the memory 20 of each semiconductor chip 1. This makes it possible to make a determination regarding the distance Dz as a determination regarding the positional relationship.

[0156] As another example, consider the case where semiconductor chips 1a and 1b are arranged as shown in Figures 30A and 30B. Unlike the case of Figure 29A, the distance Dz in the Z-axis direction does not change in Figures 30A and 30B. In this situation, the positional relationship between measurement targets 4a and 4b in the X-axis direction changes. In this case, as shown in Figure 30C, by obtaining information indicating the relationship between the displacement amount Dx in the X-axis direction and the BER through prior measurement, a BER threshold value related to the displacement amount Dx can be determined and stored in the memory 20 of each semiconductor chip 1. This makes it possible to determine the displacement amount Dx as a determination regarding the positional relationship.

[0157] As another example, consider the case where semiconductor chips 1a and 1b are arranged as shown in FIGS. 31A and 31B. Unlike the case of FIG. 29A, the distance Dz in the Z-axis direction does not change in FIGS. 31A and 31B. In this situation, the positional relationship between measurement targets 4a and 4b in the Y-axis direction changes. In this case, as shown in FIG. 31C, by obtaining information indicating the relationship between the displacement amount Dy in the Y-axis direction and the BER through prior measurement, a BER threshold value related to the displacement amount Dy can be determined and stored in the memory 20 of each semiconductor chip 1. This makes it possible to determine the displacement amount Dy as a determination regarding the positional relationship.

[0158] As another example, consider the case where semiconductor chips 1a and 1b are arranged as shown in FIGS. 32A and 32B. Unlike the case of FIG. 29A, the distance Dz in the Z-axis direction does not change in FIGS. 32A and 32B. In this situation, the positional relationship between measurement targets 4a and 4b changes in both the X-axis and Y-axis directions. In this case, it is impossible to distinguish between changes in BER due to changes in the positional relationship in the X-axis direction and changes in BER due to changes in the positional relationship in the Y-axis direction. Therefore, attention is focused on the distance Dr between the centers of semiconductor chips 1a and 1b. In this case, as shown in FIG. 32C, by obtaining information indicating the relationship between the distance Dr between the centers of semiconductor chips 1a and 1b and the BER through prior measurement, a BER threshold value for the distance Dr can be determined and stored in the memory 20 of each semiconductor chip 1. This makes it possible to perform a determination regarding the distance Dr as a determination regarding the positional relationship.

[0159] As another example, consider the case where semiconductor chips 1a and 1b are arranged as shown in FIG. 33A. In this example, the measurement target 4a rotates around a line parallel to the X-axis. In this case, as shown in FIG. 33B, by acquiring information indicating the relationship between the rotation angle Da relative to the X-axis and the BER through a prior measurement, a BER threshold value for the rotation angle Da can be determined and stored in the memory 20 of each semiconductor chip 1. This makes it possible to determine the rotation angle Da as a determination regarding the positional relationship. Note that in this case, when the rotation angle Da exceeds 90 degrees, the direction of the magnetic flux penetrating the transmitter coil 30a of the semiconductor chip 1a is reversed compared to when the rotation angle Da is 90 degrees or less. Therefore, the polarity of the voltage induced in the transmitter coil 30a is reversed, and as a result, the polarity of Rxdata is also reversed. Therefore, the processor 10a of the semiconductor chip 1a calculates the BER taking the pulse reversal into account.

[0160] <Functional Configuration of Semiconductor Chip 1> Fig. 34 is a block diagram showing the functional configuration of the semiconductor chip 1. In Fig. 34, a control unit 3401 is realized by the processor 10 executing a program stored in the memory 20.

[0161] The control unit 3401 performs overall control of the semiconductor chip 1. The control unit 3401 also has a function of performing various controls related to wireless communication of the semiconductor chip 1. The functions of performing various controls referred to here include, for example, the following functions, but are not limited to these: - A function of receiving an evaluation value based on the number of bit errors via the communication circuit 3423 and controlling the length of the evaluation signal (see "Variations Related to the Length (Number of Bits) of the Evaluation Signal") - A function of applying (inputting) a voltage pattern (Txdata and Txdata(bar)) to the transmitting coil 30 via the communication circuit 3423 - A function of acquiring a voltage pattern (Rxdata) via the communication circuit 3423 - A function of decoding the voltage pattern (Rxdata) acquired via the communication circuit 3423 - A function of detecting the number of bit errors in the evaluation signal - A function of acquiring (calculating) an evaluation value based on the number of bit errors detected in the evaluation signal and a composite evaluation value based on the number of bit errors detected in multiple evaluation signals - A function of making a judgment regarding the positional relationship between the semiconductor chips 1 based on the evaluation value or the composite evaluation value

[0162] The generating unit 3402 has the function of the PRBS generator described in the "Modification of the Method for Generating Multiple Evaluation Signals." The generating unit 3402 may be implemented as a dedicated hardware circuit included in the semiconductor chip 1, or may be implemented as a software function executed by the processor 10 of the semiconductor chip 1.

[0163] The storage unit 3411 is realized by a part of the storage area of ​​the memory 20. The storage unit 3411 stores various information required for the various processes described above, such as the evaluation signal table (FIG. 8).

[0164] The transmitting circuit 3421 is realized by the transmitting coil 30 and the transmitting-side conversion circuit 50. The transmitting circuit 3421 performs wireless transmission to the other semiconductor chip 1 via inductive coupling between the transmitting coil 30 and the receiving coil 40 of the other semiconductor chip 1.

[0165] The receiving circuit 3422 is realized by the receiving coil 40 and the receiving-side conversion circuit 60. The receiving circuit 3422 performs wireless reception from the other semiconductor chip 1 via inductive coupling between the receiving coil 40 and the transmitting coil 30 of the other semiconductor chip 1.

[0166] The transmitting circuit 3421 and the receiving circuit 3422 form a communication circuit 3423. When the semiconductor chip 1 is configured as shown in FIG. 2, the communication circuit 3423 is realized by the coil 35 and the conversion circuit 55, and the communication circuit 3423 plays the roles of the transmitting circuit 3421 and the receiving circuit 3422.

[0167] Summary of the Embodiments The above-described embodiments make it possible to assist in determining the positional relationship between communication devices such as semiconductor chips.

[0168] The specific configurations of the software (programs) and hardware that implement the various functions described in the above embodiments are not particularly limited. As long as it is technically possible, any software, any hardware, and any combination of any software and any hardware are included in the scope of the above embodiments.

[0169] The above-described embodiments disclose at least the following communication devices, control methods, and programs. [Item 1] A first communication device comprising: a communication circuit including a first coil, the communication circuit performing wireless communication with a second communication device via inductive coupling between the first coil and a second coil of a second communication device; and application means for applying a plurality of voltage patterns to the first coil via the communication circuit, each voltage pattern including a first signal portion used to detect the number of bit errors in the second communication device, the first signal portion of each voltage pattern having a different frequency characteristic. [Item 2] The first communication device according to item 1, wherein a different bit pattern is encoded in the first signal portion of each voltage pattern. [Item 3] The first communication device according to item 2, wherein each voltage pattern includes a second signal portion, the second signal portion including identification information identifying the bit pattern encoded in the first signal portion of a voltage pattern including the second signal portion. [Item 4] The first communication device according to item 1, further comprising: a generating means for pseudo-randomly generating a plurality of bit patterns based on a predetermined initial value, wherein a different one of the plurality of bit patterns is encoded in the first signal portion of each voltage pattern, and the predetermined initial value is shared between the first communication device and the second communication device. [Item 5] The first communication device according to any one of items 1 to 4, wherein the first signal portion includes a pulse train corresponding to a line code, and wherein for at least one of the pulse trains corresponding to the plurality of voltage patterns, a partial period not including a sampling timing in the second communication device has a voltage that is inverted from the voltage corresponding to the line code. [Item 6] The first communication device according to any one of items 1 to 5, wherein the first signal portion of each voltage pattern corresponds to a different line code.[Item 7] The first communication device according to item 6, wherein each voltage pattern includes a second signal portion, and the second signal portion includes identification information for identifying a line code corresponding to the first signal portion of a voltage pattern including the second signal portion. [Item 8] The first communication device according to any one of items 1 to 7, further comprising: a receiving means for receiving, via the communication circuit, an evaluation value based on a number of bit errors detected in the second communication device, which corresponds to the first signal portion of a first voltage pattern among the plurality of voltage patterns; and a control means for controlling, based on the evaluation value, a length of the first signal portion of a second voltage pattern that is applied to the first coil after the first voltage pattern. [Item 9] The first communication device according to any one of items 1 to 8, wherein each voltage pattern includes a plurality of signal portions that constitute a frame having a predetermined format, and the first signal portion of each voltage pattern is one of the plurality of signal portions. [Item 10] A second communication device comprising: a communication circuit including a second coil, the communication circuit performing wireless communication with the first communication device via inductive coupling between the second coil and a first coil of a first communication device; an acquisition means acquiring, via the communication circuit, a plurality of reception voltage patterns corresponding to a plurality of transmission voltage patterns applied to the first coil, wherein each transmission voltage pattern includes a first transmission signal portion used to detect the number of bit errors in the second communication device, and the first transmission signal portion of each transmission voltage pattern has a different frequency characteristic; a detection means detecting, for each reception voltage pattern, the number of bit errors in a first reception signal portion corresponding to the first transmission signal portion; and a determination means making a determination regarding a positional relationship between the first communication device and the second communication device based on the number of bit errors detected in a plurality of first reception signal portions corresponding to the plurality of reception voltage patterns.[Item 11] A second communication device according to Item 10, wherein a different bit pattern is encoded in the first transmission signal portion of each transmission voltage pattern, each transmission voltage pattern includes a second transmission signal portion, and the second transmission signal portion includes identification information that identifies the bit pattern encoded in the first transmission signal portion of the transmission voltage pattern that includes the second transmission signal portion, and the detection means detects the number of bit errors by comparing, for each reception voltage pattern, the bit pattern obtained from the first reception signal portion corresponding to the first transmission signal portion with a bit pattern identified by the identification information obtained from the second reception signal portion corresponding to the second transmission signal portion. [Item 12] A second communication device according to item 10 or 11, wherein the first transmission signal portions of each transmission voltage pattern correspond to different transmission channel codes, each transmission voltage pattern includes a second transmission signal portion, the second transmission signal portion includes identification information for identifying the transmission channel code corresponding to the first transmission signal portion of the transmission voltage pattern including the second transmission signal portion, and the detection means decodes the first reception signal portion corresponding to the first transmission signal portion for each reception voltage pattern based on the transmission channel code identified by the identification information acquired from a second reception signal portion corresponding to the second transmission signal portion. [Item 13] A second communication device according to any one of items 10 to 12, wherein the determination means makes a determination regarding the positional relationship by comparing a combined evaluation value based on the number of bit errors detected in the plurality of first reception signal portions with L thresholds, where L is an integer greater than or equal to 1. [Item 14] The second communication device according to Item 13, wherein L is an integer equal to or greater than 2. [Item 15] The second communication device according to Item 13 or 14, wherein each of the L threshold values ​​is associated with an individual positional relationship between the first communication device and the second communication device.[Item 16] The second communication device according to any one of items 10 to 15, wherein each transmission voltage pattern includes a plurality of transmission signal portions that constitute a frame having a predetermined format, and the first transmission signal portion of each transmission voltage pattern is one of the plurality of transmission signal portions. [Item 17] A control method executed by a first communication device, wherein the first communication device comprises a communication circuit including a first coil, the communication circuit performing wireless communication with the second communication device via inductive coupling between the first coil and a second coil of a second communication device, the control method comprising: an application step of applying a plurality of voltage patterns to the first coil via the communication circuit, each voltage pattern including a first signal portion used to detect the number of bit errors in the second communication device, and the first signal portion of each voltage pattern having a different frequency characteristic. [Item 18] A control method executed by a second communication device, wherein the second communication device comprises a communication circuit including a second coil, and performs wireless communication with the first communication device via inductive coupling between the second coil and a first coil of a first communication device, the control method comprising: an acquisition step of acquiring, via the communication circuit, a plurality of reception voltage patterns corresponding to a plurality of transmission voltage patterns applied to the first coil, wherein each transmission voltage pattern includes a first transmission signal portion used to detect a number of bit errors in the second communication device, and the first transmission signal portion of each transmission voltage pattern has a different frequency characteristic; a detection step of detecting, for each reception voltage pattern, the number of bit errors in a first reception signal portion corresponding to the first transmission signal portion; and a determination step of determining a positional relationship between the first communication device and the second communication device based on the number of bit errors detected in a plurality of first reception signal portions corresponding to the plurality of reception voltage patterns.[Item 19] A program to be executed by a processor of a first communication device, wherein the first communication device comprises a communication circuit including a first coil, the communication circuit performing wireless communication with the second communication device via inductive coupling between the first coil and a second coil of a second communication device, and when the program is executed by the processor, the program causes the processor to execute an application step of applying a plurality of voltage patterns to the first coil via the communication circuit, wherein each voltage pattern includes a first signal portion used to detect the number of bit errors in the second communication device, and the first signal portion of each voltage pattern has a different frequency characteristic. [Item 20] A program to be executed by a processor of a second communication device, wherein the second communication device comprises a communication circuit including a second coil, and performs wireless communication with the first communication device via inductive coupling between the second coil and a first coil of a first communication device; and when the program is executed by the processor, the program causes the processor to execute: an acquisition step of acquiring, via the communication circuit, a plurality of reception voltage patterns corresponding to a plurality of transmission voltage patterns applied to the first coil, wherein each transmission voltage pattern includes a first transmission signal portion used to detect a number of bit errors in the second communication device, and the first transmission signal portion of each transmission voltage pattern has a different frequency characteristic; a detection step of detecting, for each reception voltage pattern, the number of bit errors in a first reception signal portion corresponding to the first transmission signal portion; and a determination step of determining a positional relationship between the first communication device and the second communication device based on the number of bit errors detected in a plurality of first reception signal portions corresponding to the plurality of reception voltage patterns.

[0170] The invention is not limited to the above-described embodiment, and various modifications and variations are possible within the scope of the gist of the invention.

[0171] This application claims priority based on Japanese Patent Application No. 2024-051268, filed March 27, 2024, the entire contents of which are incorporated herein by reference.

[0172] 1... semiconductor chip, 10... processor, 20... memory, 30... transmitting coil, 40... receiving coil, 50... transmitting side conversion circuit, 60... receiving side conversion circuit

Claims

1. A first communication device comprising: a communication circuit including a first coil, the communication circuit performing wireless communication with a second communication device via inductive coupling between the first coil and a second coil of a second communication device; and application means for applying a plurality of voltage patterns to the first coil via the communication circuit, each voltage pattern including a first signal portion used to detect the number of bit errors in the second communication device, the first signal portion of each voltage pattern having a different frequency characteristic.

2. A first communication device according to claim 1, wherein a different bit pattern is encoded in the first signal portion of each voltage pattern.

3. A first communication device according to claim 2, wherein each voltage pattern includes a second signal portion, and the second signal portion includes identification information that identifies a bit pattern encoded in the first signal portion of the voltage pattern including the second signal portion.

4. A first communication device according to claim 1, further comprising generating means for pseudo-randomly generating a plurality of bit patterns based on a predetermined initial value, wherein a different one of the plurality of bit patterns is encoded in the first signal portion of each voltage pattern, and wherein the predetermined initial value is shared between the first communication device and the second communication device.

5. A first communication device according to any one of claims 1 to 4, wherein the first signal portion includes a pulse train corresponding to a transmission line code, and for at least one of the plurality of pulse trains corresponding to the plurality of voltage patterns, a partial period not including a sampling timing in the second communication device has a voltage that is inverted from the voltage corresponding to the transmission line code.

6. A first communication device according to any one of claims 1 to 5, wherein the first signal portions of each voltage pattern correspond to different line codes.

7. A first communication device according to claim 6, wherein each voltage pattern includes a second signal portion, and the second signal portion includes identification information that identifies a transmission line code corresponding to the first signal portion of the voltage pattern including the second signal portion.

8. A first communication device according to any one of claims 1 to 7, further comprising: receiving means for receiving, via the communication circuit, an evaluation value based on the number of bit errors detected in the second communication device, which corresponds to the first signal portion of a first voltage pattern among the plurality of voltage patterns; and control means for controlling, based on the evaluation value, the length of the first signal portion of a second voltage pattern that is applied to the first coil after the first voltage pattern.

9. A first communication device according to any one of claims 1 to 8, wherein each voltage pattern includes a plurality of signal portions constituting a frame having a predetermined format, and the first signal portion of each voltage pattern is one of the plurality of signal portions.

10. A second communication device comprising: a communication circuit including a second coil, which performs wireless communication with the first communication device via inductive coupling between the second coil and a first coil of a first communication device; an acquisition means which acquires, via the communication circuit, a plurality of reception voltage patterns corresponding to a plurality of transmission voltage patterns applied to the first coil, wherein each transmission voltage pattern includes a first transmission signal portion used to detect the number of bit errors in the second communication device, and the first transmission signal portion of each transmission voltage pattern has a different frequency characteristic; a detection means which detects the number of bit errors in a first reception signal portion corresponding to the first transmission signal portion for each reception voltage pattern; and a determination means which determines the positional relationship between the first communication device and the second communication device based on the number of bit errors detected in a plurality of first reception signal portions corresponding to the plurality of reception voltage patterns.

11. A second communication device according to claim 10, wherein a different bit pattern is encoded in the first transmission signal portion of each transmission voltage pattern, each transmission voltage pattern includes a second transmission signal portion, and the second transmission signal portion includes identification information that identifies the bit pattern encoded in the first transmission signal portion of the transmission voltage pattern that includes the second transmission signal portion, and the detection means detects the number of bit errors by comparing, for each reception voltage pattern, the bit pattern obtained from the first reception signal portion corresponding to the first transmission signal portion with the bit pattern identified by the identification information obtained from the second reception signal portion corresponding to the second transmission signal portion.

12. A second communication device according to claim 10 or 11, wherein the first transmission signal portion of each transmission voltage pattern corresponds to a different transmission channel code, each transmission voltage pattern includes a second transmission signal portion, the second transmission signal portion includes identification information that identifies the transmission channel code corresponding to the first transmission signal portion of the transmission voltage pattern including the second transmission signal portion, and the detection means decodes the first reception signal portion corresponding to the first transmission signal portion for each reception voltage pattern based on the transmission channel code identified by the identification information obtained from the second reception signal portion corresponding to the second transmission signal portion.

13. A second communication device according to any one of claims 10 to 12, wherein the determination means makes a determination regarding the positional relationship by comparing a composite evaluation value based on the number of bit errors detected in the plurality of first received signal portions with L threshold values, where L is an integer equal to or greater than 1.

14. The second communication device according to claim 13, wherein L is an integer equal to or greater than 2.

15. A second communication device according to claim 13 or 14, wherein each of the L threshold values ​​is associated with a respective positional relationship between the first communication device and the second communication device.

16. A second communication device according to any one of claims 10 to 15, wherein each transmission voltage pattern includes a plurality of transmission signal portions constituting a frame having a predetermined format, and the first transmission signal portion of each transmission voltage pattern is one of the plurality of transmission signal portions.

17. A control method executed by a first communication device, wherein the first communication device comprises a communication circuit including a first coil, which performs wireless communication with a second communication device via inductive coupling between the first coil and a second coil of a second communication device, and the control method comprises an application step of applying a plurality of voltage patterns to the first coil via the communication circuit, each voltage pattern including a first signal portion used to detect the number of bit errors in the second communication device, and the first signal portion of each voltage pattern having a different frequency characteristic.

18. A control method executed by a second communication device, wherein the second communication device comprises a communication circuit including a second coil, which performs wireless communication with the first communication device via inductive coupling between the second coil and a first coil of a first communication device, the control method comprising: an acquisition step of acquiring, via the communication circuit, a plurality of reception voltage patterns corresponding to a plurality of transmission voltage patterns applied to the first coil, wherein each transmission voltage pattern includes a first transmission signal portion used to detect the number of bit errors in the second communication device, and the first transmission signal portion of each transmission voltage pattern has a different frequency characteristic; a detection step of detecting, for each reception voltage pattern, the number of bit errors in a first reception signal portion corresponding to the first transmission signal portion; and a determination step of determining a positional relationship between the first communication device and the second communication device based on the number of bit errors detected in a plurality of first reception signal portions corresponding to the plurality of reception voltage patterns.

19. A program to be executed by a processor of a first communication device, wherein the first communication device comprises a communication circuit including a first coil, the communication circuit performing wireless communication with the second communication device via inductive coupling between the first coil and a second coil of a second communication device, and when the program is executed by the processor, the program causes the processor to execute an application step of applying a plurality of voltage patterns to the first coil via the communication circuit, each voltage pattern including a first signal portion used to detect the number of bit errors in the second communication device, the first signal portion of each voltage pattern having a different frequency characteristic.

20. A program to be executed by a processor of a second communication device, wherein the second communication device comprises a communication circuit including a second coil that performs wireless communication with the first communication device via inductive coupling between the second coil and a first coil of a first communication device; when executed by the processor, the program causes the processor to execute the following steps: an acquisition step of acquiring, via the communication circuit, multiple received voltage patterns corresponding to multiple transmitted voltage patterns applied to the first coil, wherein each transmitted voltage pattern includes a first transmitted signal portion used to detect the number of bit errors in the second communication device, and the first transmitted signal portion of each transmitted voltage pattern has a different frequency characteristic; a detection step of detecting, for each received voltage pattern, the number of bit errors in a first received signal portion corresponding to the first transmitted signal portion; and a determination step of determining a positional relationship between the first communication device and the second communication device based on the number of bit errors detected in multiple first received signal portions corresponding to the multiple received voltage patterns.

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