Processor and processing method

Abstract

The present technology pertains to a processor and a processing method capable of enhancing resistance to an attack from the outside. In the processor, an execution unit executes an instruction, and a setting register has set therein insertion instruction quantity information related to the quantity of dummy instructions that do not affect the internal state and output of the processor. A dummy instruction insertion unit inserts, into a sequence of instructions to be executed by the execution unit, dummy instructions at the insertion instruction quantity based on the insertion instruction quantity information set in the setting register. The present technology can be applied to a processor such as a CPU, for example.

Description

Processor and processing method

[0001] The present technology relates to a processor and a processing method, and more particularly to a processor and a processing method that can increase resistance to external attacks, for example.

[0002] A technique has been proposed for preventing cryptanalysis attacks by slipping (postponing) the stage that processes an instruction by one cycle (see, for example, Patent Document 1).

[0003] U.S. Patent No. 7,318,145

[0004] There is a demand for processors such as central processing units (CPUs) to be more resistant to external attacks.

[0005] The present technology has been developed in light of such circumstances, and is intended to increase resistance to external attacks.

[0006] The processor of the present technology is a processor that includes an execution unit that executes instructions, a setting register in which insertion instruction number information regarding the number of dummy instructions that do not affect the internal state and output of the processor is set, and a dummy instruction insertion unit that inserts the dummy instructions, the number of which is based on the insertion instruction number information set in the setting register, into the sequence of instructions executed by the execution unit.

[0007] The processing method of the present technology is a processing method including a processor having an execution unit that executes instructions, inserting dummy instructions into a sequence of instructions to be executed by the execution unit, the number of dummy instructions to be inserted being based on insertion instruction number information set in a setting register, in which insertion instruction number information regarding the number of dummy instructions that do not affect the internal state and output of the processor is set.

[0008] In this technology, the dummy instructions having a number of insertion instructions based on the insertion instruction number information set in a setting register in which insertion instruction number information regarding the number of dummy instructions that do not affect the internal state and output of the processor is set are inserted into the sequence of instructions executed by the execution unit.

[0009] The processor may be an independent device or an internal block that makes up a single device.

[0010] 1 is a diagram illustrating an overview of an example configuration of an image sensor to which the present technology can be applied. FIG. 2 is a block diagram illustrating an example configuration of a first embodiment of a microcomputer to which the present technology is applied. FIG. 3 is a block diagram illustrating an example configuration of a CPU 31. FIG. 4 is a diagram illustrating an example of insertion of a dummy instruction in the CPU 31. FIG. 5 is a diagram illustrating example contents stored in a setting register 62. FIG. 6 is a flowchart illustrating an example of processing for setting an insertion interval performed by the dummy instruction insertion unit 41. FIG. 7 is a flowchart illustrating an example of processing for setting the number of insertion instructions performed by the dummy instruction insertion unit 41. FIG. 8 is a flowchart illustrating processing for setting the type of dummy instruction performed by the dummy instruction insertion unit 41. FIG. 9 is a flowchart illustrating processing for setting an operand performed by the dummy instruction insertion unit 41. FIG. 10 is a diagram illustrating an example of generation and insertion of dummy instructions according to an insertion interval and the number of insertion instructions by the dummy instruction insertion unit 41. FIG. 11 is a diagram illustrating the relationship between various settings for dummy instruction insertion processing at the time of startup of the CPU 31 and instruction execution by the CPU 31. FIG. 12 is a diagram illustrating the relationship between various settings for dummy instruction insertion processing and instruction execution by the CPU 31 while the CPU 31 is operating. FIG. 13 is a diagram illustrating an example of insertion of a dummy instruction into a sequence of valid instructions. FIG. 14 is a diagram illustrating another example of insertion of a dummy instruction into a sequence of valid instructions. 10 is a block diagram showing a configuration example of a microcomputer according to a second embodiment to which the present technology is applied;FIG. 11 is a block diagram showing a configuration example of a microcomputer according to a third embodiment to which the present technology is applied;FIG.

[0011] <Outline of image sensors to which this technology can be applied>

[0012] FIG. 1 is a diagram showing an outline of a configuration example of an image sensor to which the present technology can be applied.

[0013] Fig. 1A shows a schematic configuration example of a non-stacked image sensor. As shown in Fig. 1A, the image sensor 10 has a single die (semiconductor substrate) 11. The die 11 is equipped with a pixel region 12 in which pixels are arranged in an array, a control circuit 13 that drives the pixels and performs various other controls, and a logic circuit 14 that processes signals.

[0014] 1B and 1C show a schematic configuration example of a stacked image sensor. As shown in Fig. 1B and 1C, the image sensor 20 is configured as a single semiconductor chip by stacking two dies, a sensor die 21 and a logic die 24, which are electrically connected.

[0015] In FIG. 1B, the sensor die 21 is equipped with the pixel region 12 and the control circuit 13, and the logic die 24 is equipped with the logic circuit 14 including a signal processing circuit that performs signal processing.

[0016] In FIG. 1C, the pixel region 12 is mounted on the sensor die 21, and the control circuit 13 and the logic circuit 14 are mounted on the logic die 24.

[0017] The present technology can be applied to the non-stacked image sensor 10 and the stacked image sensor 20 described above. Furthermore, the present technology can be applied to a two-layer image sensor 20 in which two dies are stacked, as well as a three-layer or more image sensor in which three or more dies are stacked. For example, when the present technology is applied to a three-layer image sensor, the third die can be equipped with, for example, a memory that stores data for signal processing in the logic circuit 14. An image sensor to which the present technology is applied can be installed in, for example, a camera, a mobile terminal (handheld terminal), or various other devices.

[0018] Furthermore, the present technology can be applied to various processors, such as CPUs and DSPs (digital signal processors), that execute programs (each instruction that constitutes a program), in addition to image sensors.

[0019] <First embodiment of a microcomputer to which the present technology is applied>

[0020] FIG. 2 is a block diagram showing a configuration example of a first embodiment of a microcomputer to which the present technology is applied.

[0021] A microcomputer to which the present technology is applied can be mounted, for example, in the logic circuit 14 of the image sensor 10 or 20 in FIG.

[0022] 2, the microcomputer 30 has a CPU 31, a memory 32, and a peripheral device 33. The CPU 31 to the peripheral device 33 are connected to a bus, and can exchange data (including programs, control signals, etc.) with each other via the bus.

[0023] The CPU 31 performs various processes such as signal processing by reading (fetching) a sequence of instructions, which is a program, from the memory 32 (via the bus) and executing it. In this specification, an instruction includes an opcode and, if necessary, an operand.

[0024] The memory 32 is configured, for example, by a ROM (read only memory) or a RAM (random access memory), and stores data necessary for the operation of the CPU 31. The data necessary for the operation of the CPU 31 includes data to be processed by the CPU 31, data obtained as a result of the processing by the CPU 31, programs executed by the CPU 31, etc.

[0025] The peripheral device 33 is, for example, an I / F (interface) such as a GPIO (general purpose input output) for exchanging signals with the outside, or a device such as a timer that enhances the functions of the microcomputer 30.

[0026] In recent years, various attacks, such as fault injection attacks and side channel attacks, have been carried out from outside on processors such as the CPU 31, with the aim of causing them to skip instructions that perform security-critical processing such as signing and verification.

[0027] A fault injection attack is an attack that causes a circuit malfunction by externally irradiating the processor with electromagnetic radiation from outside, for example, from outside the chip on which the processor is mounted. The circuit malfunction causes the processor to skip instructions that it should execute. For example, if an instruction that performs security-critical processing such as signing or verification is skipped, the security-critical processing will be skipped (not executed). A side channel attack is an attack that steals confidential information from an unauthorized input / output port. Side channel attacks include, for example, performing a power analysis of the processor's power consumption from outside and inferring the execution timing of important processing from the results of the power analysis.

[0028] A processor that does not have countermeasures against external attacks (attacks from outside) executes only functionally valid instructions, i.e., instructions that constitute a program (hereinafter also referred to as valid instructions). Therefore, for example, the execution timing of important processing can be easily guessed by a side channel attack. Furthermore, if the execution timing of important processing is accurately guessed, a fault injection attack can be carried out at that execution timing, causing important processing, such as processing related to security functions, to be skipped, thereby breaching the security functions.

[0029] Therefore, for example, one countermeasure against external attacks is to insert dummy instructions into the sequence of valid instructions executed by the processor. A dummy instruction is an instruction that does not affect the internal state and output of the processor.

[0030] The countermeasure method of inserting dummy instructions not only shifts the execution timing of valid instructions, but also generates power consumption that becomes noise in power analysis of the processor's power consumption due to the execution (processing) of the dummy instructions, thereby making it possible to prevent fault injection attacks and side channel attacks from succeeding.

[0031] In Ibex, an existing CPU (core), dummy instructions that do not affect the CPU's internal state or output are inserted into a sequence of valid instructions that are pipelined (processed in a pipelined manner). Ibex uses two types of dummy instructions: multiplication and division. The dummy instruction is inserted once for each valid instruction whose number is equal to a randomly selected value within the range from 0 to a preset maximum value. The maximum value can be selected from 4, 8, 16, or 32. For more information about Ibex, see, for example, https: / / ibex-core.readthedocs.io / en / latest / 03_reference / security.html.

[0032] In Ibex, only one dummy instruction is inserted at a time. Therefore, the execution timing of a valid instruction can only be shifted by one instruction. This increases the probability that a fault injection attack will be successful against a valid instruction (hereinafter referred to as a critical instruction) that performs important processing that needs to be protected. For example, even if a critical instruction is not being executed, if a fault injection attack is performed just before the execution timing of the critical instruction, and multiple instructions are skipped (hereinafter referred to as multiple instruction skip), the critical instruction will be skipped.

[0033] Furthermore, Ibex cannot precisely control the insertion frequency, as it can only insert dummy instructions once per valid instruction number randomly selected from the range of 0 to 4, 8, 16, or 32. This increases the probability that dummy instructions will not be inserted near critical instructions, which increases the probability that a fault injection attack will be successful.

[0034] Furthermore, in Ibex, the types and operands of dummy instructions tend to be biased. In other words, the same type of instruction tends to become a dummy instruction, and the operands do not change. This makes it difficult for differences in power consumption (signal-to-noise ratio (SN) difference) to occur when dummy instructions are executed, making it easier to estimate the execution timing of dummy instructions. As a result, it becomes easier to avoid dummy instructions and perform fault injection attacks.

[0035] Therefore, the CPU 31 incorporates a dummy instruction insertion unit 41 that can precisely control the insertion of dummy instructions. Because the dummy instruction insertion unit 41 has high controllability over the insertion of dummy instructions, it can appropriately insert dummy instructions into the sequence of valid instructions executed by the CPU 31. This makes it possible to improve the CPU 31's resistance (security strength) against external attacks while balancing this with the overhead of executing dummy instructions (resulting in processing delays) to improve that resistance.

[0036] <Configuration example of CPU 31>

[0037] FIG. 3 is a block diagram showing an example of the configuration of the CPU 31.

[0038] In FIG. 3, the CPU 31 includes a CPU core 61 and a setting register 62 .

[0039] The CPU core 61 has a dummy instruction insertion unit 41, a program counter 71, an instruction buffer 72, an interrupt detection unit 73, a decoder 74, a FF (flip flop) 75, an ALU (Arithmetic Logic Unit) 76, a FF 77, a WB (write back) unit 78, and an internal register 79.

[0040] The dummy instruction insertion unit 41 incorporates an LFSR (linear feedback shift register) 51, and generates random numbers (pseudo-random numbers) by providing a seed value to the LFSR 51. The dummy instruction insertion unit 41 sets the number of dummy instructions to be inserted into a sequence of valid instructions at one time and the insertion interval at which dummy instructions are inserted into a sequence of valid instructions, based on the random numbers (pseudo-random numbers) generated by the LFSR 51 and the value stored in a setting register 62. The dummy instruction insertion unit 41 outputs the set number of dummy instructions to the FF 75 at the set insertion interval, thereby inserting the set number of dummy instructions into the sequence of valid instructions (at one time) at the set insertion interval.

[0041] The dummy instruction output by the dummy instruction insertion unit 41 can be generated by the dummy instruction insertion unit 41. In addition, the dummy instruction output by the dummy instruction insertion unit 41 can be randomly selected from a plurality of instructions with fixed operands that are to be used as dummy instructions, which are stored in the dummy instruction insertion unit 41 in advance.

[0042] The program counter 71 outputs an address (ADDR) at which a valid instruction to be executed is stored. The address output by the program counter 71 is supplied (via a bus) to the memory 32. When the address output by the program counter 71 is supplied to the memory 32, the valid instruction (DATA) that constitutes the program and that is stored at that address is read from the memory 32 and supplied (via a bus) to the instruction buffer 72.

[0043] The instruction buffer 72 temporarily stores valid instructions read from the memory 32 and supplies them to the decoder 74 .

[0044] The interrupt detection unit 73 detects an interrupt based on an external interrupt signal (Interrupt), and outputs an interrupt command to be executed to the FF 75 when the interrupt detection unit 73 detects an interrupt.

[0045] The decoder 74 decodes the valid instruction from the instruction buffer 72 and outputs the valid instruction as the decoded result to the FF 75 .

[0046] The FF 75 latches instructions (dummy instructions, interrupt instructions, and valid instructions) from the dummy instruction insertion unit 41, interrupt detection unit 73, and decoder 74, and outputs them to the ALU 76. The FF 75 outputs to the ALU 76, in the following order, with priority: the interrupt instruction from the interrupt detection unit 73, the dummy instruction from the dummy instruction insertion unit 41, and the valid instruction from the decoder 74. As a result, the dummy instruction from the dummy instruction insertion unit 41 is inserted into the sequence of valid instructions.

[0047] The FF 75 latches the stored value of the internal register 79 as necessary and outputs it to the ALU 76 as an operand of a valid instruction.

[0048] The ALU 76 executes the instruction output by the FF 75 and outputs the result of the execution to the FF 77 .

[0049] The FF 77 latches the execution result of the instruction from the ALU 76 and outputs it to the WB unit 78 .

[0050] The WB unit 78 writes (writes back) the execution result of the instruction from the FF 77 to the internal register 79 .

[0051] The internal registers 79 include general-purpose registers, zero registers, and other registers that are common to the processor. The execution results of instructions from FF 77 are written back to the internal registers 79. The execution results of dummy instructions are written back to the zero register of the internal registers 79. As a result, the dummy instructions do not affect the internal state and output of the CPU 31.

[0052] In the setting register 62, for example, information about the number of dummy instructions to be inserted, the insertion interval, and other information about the dummy instructions is set in accordance with user operations or the program executed by the CPU 31.

[0053] In the CPU 31 configured as described above, the CPU core 61 processes instructions (valid instructions) in four stages, for example, fetch (FE_ADDR / DATA), decode (DC), execute (EX), and write back (WB), in the order of instruction processing. Fetch is a stage in which the program counter 71 and the instruction buffer 72 read instructions into the CPU core 61. Decode is a stage in which the decoder 74 decodes (interprets) the instructions. Execute is a stage in which the ALU 76 executes the instructions. Write back is a stage in which the WB unit 78 and the internal register 79 write (write back) the execution results of the instructions.

[0054] The stages of fetching, decoding, executing, and writing back an instruction can be performed each time all stages are performed for a single immediately preceding instruction, or can be performed using pipeline processing. The following description will be given assuming that instructions are pipeline processed. However, this technology can also be applied to a case where the stages of fetching to writing back an instruction are performed each time all stages are performed for a single immediately preceding instruction, that is, a case where fetching to writing back an instruction is performed for the next instruction after fetching to writing back an instruction is completed.

[0055] FIG. 4 is a diagram for explaining an example of insertion of a dummy instruction in the CPU 31. In FIG.

[0056] In FIG. 4, valid instructions #1, #2, . . . are pipelined.

[0057] In Figure 4, FE_A and FE_D represent instruction fetch stages, and DC represents the instruction decode stage. EX represents the instruction execution stage, and WB represents the stage for writing back the execution results of the instruction. In Figure 4, the fetch stage is divided into a stage in which the program counter 71 outputs an address and a stage in which an instruction is read from that address. FE_A represents the stage in which an address is output, and FE_D represents the stage in which an instruction is read. A valid instruction is processed in the order of the fetch (FE_A and FE_D) stage, the decode (DC) stage, the execute (EX) stage, and the write back (WB) stage.

[0058] The dummy instruction insertion unit 41 changes an internal signal, an insertion signal, from L (low) level to H (high) level when it is time to insert a dummy instruction according to the (set) insertion interval of the dummy instruction. The insertion signal is kept at H level for a period of stages equal to the (set) number of dummy instructions to be inserted. In Figure 4, for example, the number of insertion instructions is set to 1, so the insertion signal is kept at H level for only one stage.

[0059] The dummy instruction inserter 41 inserts a dummy instruction into the sequence of valid instructions in accordance with the insertion signal.

[0060] The stage of the dummy instruction does not involve fetching, but starts with decode (DC), followed by execution (EX) and writeback (WB).

[0061] In the dummy instruction decode (DC) stage, the dummy instruction output by the dummy instruction insertion unit 41 is output to FF 75, and further output from FF 75 to the ALU 76. In the dummy instruction execute (EX) stage, the dummy instruction from FF 75 is executed in the ALU 76, and the execution result is output to FF 77. In the dummy instruction write back (WB) stage, the execution result of the dummy instruction output by FF 77 is written to (the zero register of) the internal register 79 in the WB unit 68.

[0062] As described above, processing of the dummy instruction stage begins from the decode (DC) stage. Therefore, at the timing of inserting the dummy instruction, the stages after the decode (DC) of the valid instruction that was supposed to be decoded (DC) are stalled and postponed by a number of stages equal to the number of inserted instructions. In FIG. 4, the valid instruction that was supposed to be decoded (DC) at the timing of inserting the dummy instruction is valid instruction #3, and since the number of inserted instructions is 1, the stages after the decode (DC) of valid instruction #3 are stalled by one stage. The stages of the valid instruction following valid instruction #3 are also stalled as necessary.

[0063] <Setting register 62>

[0064] FIG. 5 is a diagram showing an example of the contents stored in the setting register 62 of FIG.

[0065] In the setting register 62, for example, a 6-bit minimum insertion interval value, a 6-bit insertion interval width, a 6-bit minimum number of inserted instructions, and a 6-bit width of the number of inserted instructions are set.

[0066] The minimum insertion interval value and the insertion interval width are insertion interval information relating to the insertion interval of dummy instructions. The minimum insertion interval value is the minimum value of the insertion interval at which dummy instructions are inserted. The insertion interval width is the width from the minimum value to the maximum value of the insertion interval at which dummy instructions are inserted.

[0067] The dummy instruction insertion unit 41 sets the insertion interval of dummy instructions based on the insertion interval information. For example, the dummy instruction insertion unit 41 can generate a random number in the LFSR 51 within a range based on the insertion interval information, i.e., within a range equal to or greater than the minimum insertion interval value and equal to or less than the minimum insertion interval value plus the insertion interval width, and set the random number as the insertion interval.

[0068] In addition, as the insertion interval information, other information that can specify the minimum and maximum values ​​of the insertion interval at which dummy instructions are inserted, such as the minimum and maximum values ​​of the insertion interval themselves, or the maximum value and insertion interval width, can be used.

[0069] The minimum number of inserted instructions and the range of inserted instructions are information about the number of dummy instructions to be inserted. The minimum number of inserted instructions is the minimum number of dummy instructions to be inserted (at one time) (successively). The range of inserted instructions is the range from the minimum to the maximum number of dummy instructions to be inserted.

[0070] The dummy instruction insertion unit 41 sets the number of dummy instructions to be inserted based on the information on the number of instructions to be inserted. For example, the dummy instruction insertion unit 41 can generate a random number in the LFSR 51 within a range based on the information on the number of instructions to be inserted, i.e., within a range equal to or greater than the minimum number of instructions to be inserted and equal to or less than the minimum number of instructions to be inserted plus the width of the number of instructions to be inserted, and set the random number as the number of instructions to be inserted.

[0071] In addition, other information that can specify the minimum and maximum number of instructions to be inserted into which dummy instructions are to be inserted, such as the minimum and maximum number of instructions to be inserted, or the maximum value and range of the number of instructions to be inserted, can be used as the information on the number of instructions to be inserted.

[0072] <Insertion interval setting>

[0073] FIG. 6 is a flowchart illustrating an example of the process of setting the insertion interval performed by the dummy instruction insertion unit 41.

[0074] In step S11, the dummy instruction insertion unit 41 generates a random number (integer) in the LFSR 51 within the range of the minimum insertion interval value or more and the minimum insertion interval value plus the insertion interval width or less, and the process proceeds to step S12.

[0075] In step S12, the dummy instruction insertion unit 41 sets the random number generated by the LFSR 51 as the insertion interval, and the process ends.

[0076] The insertion interval is set each time the same number of dummy instructions as the number of insertion instructions is inserted (each time the same number of dummy instructions as the number of insertion instructions is attempted to be inserted).

[0077] <Setting the number of insertion commands>

[0078] FIG. 7 is a flowchart illustrating an example of processing for setting the number of instructions to be inserted, which is performed by the dummy instruction inserting unit 41. In FIG.

[0079] In step S21, the dummy instruction insertion unit 41 generates a random number (integer) in the LFSR 51 within the range of the minimum number of instructions to be inserted and the minimum number of instructions to be inserted plus the width of the number of instructions to be inserted, and the process proceeds to step S22.

[0080] In step S22, the dummy instruction insertion unit 41 sets the random number generated by the LFSR 51 as the number of instructions to be inserted, and the process ends.

[0081] The number of inserted instructions is set each time the same number of dummy instructions as the number of inserted instructions are inserted (each time it is attempted to insert the same number of dummy instructions as the number of inserted instructions).

[0082] <Setting the type of dummy instruction>

[0083] FIG. 8 is a flowchart illustrating the process of setting the type of dummy instruction performed by the dummy instruction inserter 41. In FIG.

[0084] The dummy instruction inserting section 41 can set an instruction to be a dummy instruction from among a plurality of types of instructions, that is, can set the type of dummy instruction.

[0085] In step S31, the dummy instruction insertion unit 41 generates a random number within a predetermined range, for example, a 2-bit random number (integer), in the LFSR 51, and the process proceeds to step S32. The number of bits of the random number is determined by the number of types of instructions that can be used as dummy instructions.

[0086] In step S32, the dummy instruction inserter 41 sets the type of instruction corresponding to the random number generated by the LFSR 51 as the type of the dummy instruction, and the process ends.

[0087] For example, as many types of instructions as there are values ​​0, 1, 2, and 3 that can be represented by two bits, i.e., four types of instructions, are prepared as candidate instructions that are candidates for dummy instructions, and each two-bit value is associated with a respective candidate instruction (type). For example, multiplication (mul), division (div), logical sum (and), and shift (sll) can be used as the candidate instruction (type) associated with each two-bit value. The dummy instruction insertion unit 41 sets the candidate instruction type associated with the two-bit random number as the dummy instruction.

[0088] The type of dummy instruction is set for each of the dummy instructions in the number of inserted instructions.

[0089] The candidate instructions are not limited to the four of multiplication, division, logical sum, and shift. That is, the number (types) of candidate instructions can be a number other than four, for example, one, two, three, or five or more. Furthermore, instructions other than multiplication, division, logical sum, and shift can be used as the candidate instructions (types). From the viewpoint of varying the power consumption when dummy instructions are executed, it is desirable to have a certain number of candidate instructions (types of dummy instructions).

[0090] <Operand settings>

[0091] FIG. 9 is a flowchart illustrating the process of setting operands performed by the dummy instruction insertion unit 41. In FIG.

[0092] When generating a dummy instruction, the dummy instruction insertion unit 41 can set the operands of the dummy instruction.

[0093] In step S41, the dummy instruction insertion unit 41 generates a random number within a predetermined range, for example, a 32-bit random number, in the LFSR 51, and the process proceeds to step S42. The number of bits of the random number is determined by the number of bits of the operand taken by the dummy instruction (opcode).

[0094] In step S42, the dummy instruction insertion unit 41 sets the random number generated by the LFSR 51 as the operand of the dummy instruction, and the process ends.

[0095] The operand setting is performed for each of the dummy instructions of the number of inserted instructions. If the dummy instruction is an instruction that takes two source operands, the operand setting is performed twice for that dummy instruction, so that two source operands are set.

[0096] For example, as explained in Figure 8, by setting a dummy instruction using a random number (randomly) from among the relatively large number of candidate instructions, namely, four types of multiplication, division, logical sum, and shift, the noise generated when the dummy instruction is executed increases, making it difficult to distinguish between the dummy instruction and a valid instruction. Also, as explained in Figure 9, by setting the operand of the dummy instruction using a random number, the noise generated when the dummy instruction is executed increases, making it difficult to distinguish between the dummy instruction and a valid instruction. As explained above, by making it difficult to distinguish between the dummy instruction and a valid instruction, it becomes difficult to estimate the execution timing of an important valid instruction that is to be attacked (skipped), making it difficult to carry out a fault injection attack.

[0097] <Example of generating and inserting dummy instructions>

[0098] FIG. 10 is a diagram illustrating an example of the generation and insertion of dummy instructions by the dummy instruction inserting unit 41 in accordance with the insertion interval and the number of instructions to be inserted.

[0099] In the dummy instruction insertion unit 41, the insertion interval and the number of instructions to be inserted are set by the generation of random numbers by the LFSR 51. In Fig. 10, in the initial setting of the insertion interval and the number of instructions to be inserted, both the insertion interval and the number of instructions to be inserted are set to 1. In this case, as the first insertion of a dummy instruction, one dummy instruction is inserted after the first valid instruction #1. This one dummy instruction is generated by setting the type of dummy instruction and operands by the generation of random numbers by the LFSR 51 before the insertion of the dummy instruction.

[0100] After the first dummy instruction is inserted, the insertion interval and the number of instructions to be inserted are set by the generation of a random number by the LFSR 51. In Fig. 10, after the first dummy instruction is inserted, the insertion interval and the number of instructions to be inserted are set to 1 and 0, respectively. In this case, as the second dummy instruction insertion, zero dummy instructions are inserted after the one valid instruction #2 after the first dummy instruction insertion. These zero dummy instructions are generated by setting the type and operand of the dummy instruction by the generation of a random number by the LFSR 51 before the insertion of the dummy instruction. Note that when zero dummy instructions are inserted, no dummy instructions are actually generated or inserted.

[0101] After the second dummy instruction is inserted, the insertion interval and the number of instructions to be inserted are set by the generation of random numbers by the LFSR 51. In Fig. 10, after the second dummy instruction is inserted, the insertion interval and the number of instructions to be inserted are set to 3 and 5, respectively. In this case, as the third dummy instruction insertion, five dummy instructions are inserted after the three valid instructions #3, #4, and #5 after the second dummy instruction insertion. These five dummy instructions are generated by setting the type of dummy instruction and operands by the generation of random numbers by the LFSR 51 before each dummy instruction is inserted.

[0102] Similarly, an insertion interval and the number of instructions to be inserted are set, and the process of generating and inserting the number of dummy instructions to be inserted after the number of valid instructions indicated by the insertion interval is repeated.

[0103] The dummy instruction insertion unit 41 can set either the insertion interval or the number of instructions to be inserted, and fix the other. For example, the dummy instruction insertion unit 41 can set the insertion interval to a predetermined fixed value of 1 or more, and set the number of instructions to be inserted each time the previously set number of dummy instructions is inserted.

[0104] FIG. 11 is a diagram for explaining the relationship between various settings for the dummy instruction insertion process for inserting a dummy instruction into a sequence of valid instructions when the CPU 31 is started, and the execution of instructions by the CPU 31. In FIG.

[0105] When the power supply of the microcomputer 30 is turned on and the CPU 31 starts up, the CPU 31 starts executing (fetching, decoding, executing, and writing back) each valid instruction in the sequence of valid instructions as a predetermined program.

[0106] In parallel with the execution of valid instructions, the CPU 31 performs various settings for the dummy instruction insertion process in step S51, and the process proceeds to step S52. The various settings for the dummy instruction insertion process include, for example, setting a seed value for the LFSR 51, and setting the minimum number of instructions to be inserted, the width of the number of instructions to be inserted, the minimum insertion interval, and the width of the insertion interval in the setting register 62. A value other than 0 is set as the seed value for the LFSR 51.

[0107] In step S52, the CPU 31 turns on the dummy instruction insertion process (the CPU 31 enters a state in which the dummy instruction insertion process is executed).

[0108] Here, immediately after the power of the microcomputer 30 is turned on, the dummy instruction insertion process is turned off (the CPU 31 is in a state where it is not executing the dummy instruction insertion process). That is, after the power of the microcomputer 30 is turned on, various settings for the dummy instruction insertion process are made in step S51, and the dummy instruction insertion process is turned off until the dummy instruction insertion process is turned on in step S52. Therefore, while the seed value of the LFSR 51 and the setting register 62 are being set, no dummy instructions are inserted (the insertion of dummy instructions is turned off). When the dummy instruction insertion process is turned on in step S52, insertion of dummy instructions is performed (started). That is, an insertion interval and the number of instructions to be inserted are set, and dummy instructions of the number of instructions to be inserted are generated and inserted after the number of valid instructions represented by the insertion interval.

[0109] FIG. 12 is a diagram for explaining the relationship between various settings for dummy instruction insertion processing during operation of the CPU 31 and the execution of instructions by the CPU 31. In FIG.

[0110] When various settings for the dummy instruction insertion process are made while the CPU 31 is operating, that is, when various settings for the dummy instruction insertion process are changed while the CPU 31 is operating, the CPU 31 turns off the dummy instruction insertion process in step S61, and the process proceeds to step S62. The CPU 31 is executing valid instructions in parallel, and when the dummy instruction insertion process is turned off, no dummy instructions are inserted thereafter until the dummy instruction insertion process is turned on.

[0111] In step S62, the CPU 31 performs various settings for the dummy instruction insertion process, and the process proceeds to step S63. That is, in step S62, the setting of the seed value of the LFSR 51, and the settings of the minimum number of instructions to be inserted, the width of the number of instructions to be inserted, the minimum insertion interval, and the width of the insertion interval in the setting register 62 are changed.

[0112] In step S63, the CPU 31 turns on the dummy instruction insertion process. Once the dummy instruction insertion process is turned on, dummy instructions are inserted. That is, an insertion interval and the number of instructions to be inserted are set, and the number of dummy instructions to be inserted are generated and inserted after the number of valid instructions represented by the insertion interval. Therefore, while the seed value of the LFSR 51 and the setting register 62 are being set, in this case while the seed value of the LFSR 51 is being set and the setting register 62 is being changed, no dummy instructions are inserted (insertion of dummy instructions is turned off).

[0113] Changing the settings of the minimum number of instructions to be inserted, the width of the number of instructions to be inserted, the minimum insertion interval, and the width of the insertion interval in the setting register 62 changes the range of values ​​that can be set for the number of instructions to be inserted and the insertion interval, and changes the frequency with which dummy instructions are inserted (the density of dummy instructions). Also, changing the setting of the seed value for the LFSR 51 changes the tendency of the random numbers generated by the LFSR 51, which changes the tendency of the number of instructions to be inserted set by the random numbers, the insertion interval, the type of dummy instruction, and the operands.

[0114] The seed value of the LFSR 51 and the setting of the setting register 62 can be set at a predetermined timing during operation of the CPU 31 after the CPU 31 has been started. Since the frequency of dummy instruction insertion can be changed by changing the setting of the setting register 62, the seed value of the LFSR 51 and the setting of the setting register 62 can be set depending on the presence or absence of a critical instruction, which is a valid instruction that performs important processing that needs to be protected (the timing of the critical instruction).

[0115] For example, the setting of the setting register 62 can be changed so that the frequency of inserting dummy instructions is increased before a critical instruction in a sequence of valid instructions. Also, for example, if no other critical instructions appear for a while after a critical instruction in a sequence of valid instructions, the setting of the setting register 62 can be changed so that the frequency of inserting dummy instructions is decreased (immediately) after the critical instruction.

[0116] FIG. 13 is a diagram illustrating an example of inserting a dummy instruction into a sequence of valid instructions.

[0117] Figure 13A shows an example of dummy instruction insertion in Ibex, an existing CPU. In Ibex, only one dummy instruction can be inserted at a time. Therefore, the execution timing of a valid instruction can only be shifted by one instruction before or after the insertion of the latest dummy instruction. Therefore, even if a dummy instruction is inserted immediately before a critical instruction, which is a valid instruction that performs important processing that needs to be protected, and a fault injection attack is performed on that dummy instruction, if multiple instruction skips occur due to the fault injection attack, the critical instruction will be skipped.

[0118] 13B illustrates an example of dummy instruction insertion by the CPU 31 (the present CPU). In the CPU 31, by setting a value of 2 or greater as the minimum number of inserted instructions in the setting register 62, a random number of dummy instructions equal to or greater than the minimum number of inserted instructions is inserted consecutively at one time. Therefore, the execution timing of valid instructions can be shifted by a random number of instructions equal to or greater than the minimum number of inserted instructions before and after the insertion of the latest dummy instruction. Therefore, if a random number of dummy instructions equal to or greater than 2 is inserted immediately before a critical instruction and a fault injection attack is performed on those dummy instructions, even if multiple instructions are skipped due to the fault injection attack, skipping of the critical instruction can be avoided if the fault injection attack is performed on a dummy instruction that is more than one instruction away from the critical instruction among the random number of dummy instructions equal to or greater than 2. This improves resistance to fault injection attacks.

[0119] By setting a large value for the minimum number of inserted instructions slightly before the critical instruction and, if necessary, a small value for the minimum insertion interval, the number of dummy instructions inserted immediately before the critical instruction increases and the insertion interval becomes shorter. In other words, the frequency of dummy instruction insertion increases. In this case, even if multiple instructions are skipped due to a fault injection attack, the skipping of critical instructions can be avoided, and resistance to multiple instruction skipping due to fault injection attacks can be improved.

[0120] FIG. 14 is a diagram illustrating another example of inserting a dummy instruction into a sequence of valid instructions.

[0121] Figure 14A shows an example of dummy instruction insertion in Ibex, an existing CPU. In Ibex, dummy instructions are inserted at a frequency of one per valid instruction randomly selected from the range of 0 to 4, 8, 16, or 32. Therefore, the highest insertion frequency occurs when one dummy instruction is inserted per valid instruction randomly selected from the range of 0 to 4. However, even in such a case, only one dummy instruction may be inserted per four valid instructions. Therefore, the probability of inserting dummy instructions near (around) critical instructions is low, increasing the probability of a successful fault injection attack on a critical instruction.

[0122] B and C in FIG. 14 show an example of inserting a dummy instruction in the CPU 31 (this CPU).

[0123] The CPU 31 sets the number of instructions to be inserted to a random value (random number generated by the LFSR 51) that is equal to or greater than the minimum number of instructions to be inserted and is equal to or less than the minimum number of instructions to be inserted plus the number of instructions to be inserted width. Furthermore, the CPU 31 sets the insertion interval to a random value that is equal to or greater than the minimum insertion interval and is equal to or less than the minimum insertion interval plus the insertion interval width. Therefore, the CPU 31 can finely adjust (control with fine granularity) the frequency of dummy instruction insertion by setting the minimum number of instructions to be inserted and the number of instructions to be inserted width, and / or by setting the minimum insertion interval and the insertion interval width.

[0124] For example, the frequency of dummy instruction insertion can be increased by setting the minimum number of inserted instructions to a large value and the minimum insertion interval and insertion interval width to small values.Furthermore, the frequency of dummy instruction insertion can be decreased by setting the minimum number of inserted instructions and insertion instruction width to small values ​​and the minimum insertion interval to a large value.

[0125] 14B shows an example of dummy instruction insertion with a high insertion frequency. In FIG. 14B, the minimum number of inserted instructions and the width of the number of inserted instructions are set to a large value of 32. The minimum insertion interval and the width of the inserted interval are set to small values ​​of 1 and 2, respectively. In this case, a dummy instruction is inserted for every valid instruction count between 1 and 3, inclusive, where the minimum insertion interval is equal to or greater than 1 and the minimum insertion interval + width of inserted instructions = 1 + 2 = 3. The number of dummy instructions inserted at one time is equal to or greater than 32, the minimum number of inserted instructions, inclusive, and within the range of 64, where the minimum number of inserted instructions + width of inserted instructions = 32 + 32 = 64, inclusive ...

[0126] As shown in B of FIG. 14, by increasing the frequency of inserting dummy instructions slightly before the critical instruction, the protection of the critical instruction can be strengthened.

[0127] 14C shows an example of inserting dummy instructions with a low insertion frequency. In FIG. 14C, the minimum number of inserted instructions and the width of the number of inserted instructions are set to small values ​​of 1 and 2, respectively. The minimum insertion interval and the width of the inserted interval are set to large values ​​of 32. In this case, dummy instructions are inserted for every valid instruction count between 32 and 64, inclusive, within the range of the minimum insertion interval (32) and the minimum insertion interval + the insertion interval width (32 + 32 = 64). The number of dummy instructions inserted at one time is between 1 and 3, inclusive, within the range of the minimum number of inserted instructions (1) and the minimum number of inserted instructions + the width of inserted instructions (1 + 2 = 3).

[0128] When a series of valid instructions that do not require such strong protection are encountered, the overhead of executing dummy instructions (and the resulting processing delay) can be suppressed by reducing the frequency of inserting dummy instructions.

[0129] For the CPU 31, the frequency of dummy instruction insertion can be finely adjusted (controlled) by setting the minimum number of inserted instructions, the width of the number of inserted instructions, and the minimum insertion interval and the width of the insertion interval. The strength of protection for valid instructions can be adjusted by adjusting the frequency of dummy instruction insertion according to the need for protection of valid instructions. For example, the CPU 31 can insert multiple dummy instructions at once to shift the execution timing of important instructions by the amount of multiple dummy instructions, thereby providing strong protection for important instructions. In this case, important instructions can be protected even if multiple instructions are skipped due to a fault injection attack, for example. As described above, the strength of protection for valid instructions can be adjusted by finely adjusting the frequency of dummy instruction insertion. As a result, resistance to external attacks can be improved while suppressing the increase in overhead caused by executing dummy instructions, thereby achieving a balance between resistance to external attacks and overhead.

[0130] In the CPU 31, the operands of the dummy instructions are set by random numbers for each dummy instruction. Therefore, even if the same type of dummy instruction is executed in succession, the operands of each dummy instruction are different. As a result, the noise generated when the dummy instruction is executed increases, making it difficult to distinguish between dummy instructions and valid instructions. By making it difficult to distinguish between dummy instructions and valid instructions, it becomes difficult to estimate the execution timing of an important valid instruction that is to be attacked (skipped), making it difficult to carry out a fault injection attack.

[0131] In the CPU 31, for example, the dummy instruction is not set to the same type of instruction as the valid instruction immediately before the dummy instruction is inserted, but is set using a random number from among four relatively common types of instructions: multiplication, division, logical sum, and shift. Therefore, the possibility of consecutive dummy instructions of the same type is low, and the possibility that consecutive dummy instructions will be of different types is high. Because the possibility of consecutive dummy instructions being of different types is high, the noise generated when the dummy instruction is executed is likely to be large, making it difficult to distinguish between dummy instructions and valid instructions, which makes it difficult to carry out a fault injection attack.

[0132] After the dummy instruction is executed, the CPU 31 writes back the execution result of the dummy instruction. Writing back the execution result of the dummy instruction also generates power consumption that becomes noise in a power analysis of the power consumption of the CPU 31 that is performed as a side-channel attack, so writing back the execution result of the dummy instruction can suppress the success of a side-channel attack.

[0133] <Second embodiment of a microcomputer to which the present technology is applied>

[0134] FIG. 15 is a block diagram showing a configuration example of a second embodiment of a microcomputer to which the present technology is applied.

[0135] In the figure, parts corresponding to those in FIG. 2 are given the same reference numerals, and the description thereof will be omitted below as appropriate.

[0136] 15, a microcomputer 130 includes a memory 32, a peripheral device 33, and a CPU 131. The memory 32, the peripheral device 33, and the CPU 131 are connected to a bus.

[0137] 2 in that it includes a memory 32 and a peripheral device 33. However, the microcomputer 130 differs from the microcomputer 30 in that it includes a CPU 131 instead of the CPU 31.

[0138] The CPU 131 has a dual lockstep configuration. A processor with a dual lockstep configuration has two processor cores, called a primary and a secondary, and synchronizes the clocks of the two processor cores to have each perform the same processing. The processor then compares the processing results of the two processor cores, and if the processing results are the same, it treats the processing results as valid processing results. If the processing results are different, it determines that an error has occurred and takes some kind of recovery measure.

[0139] The CPU 131 has two processor cores, ie, CPU cores 161P and 161S. The CPU 131 also has delay units 166P and 166S, and a check unit 167.

[0140] In the CPU 131, the CPU core 161P as a primary and the CPU core 161S as a secondary perform the same processing (execution of the same command) with a specific number of cycles, for example, two cycles, shifted from each other.

[0141] The CPU cores 161P and 161S are configured in the same manner as the CPU core 61 in Fig. 3. Therefore, the CPU core 161P has a dummy instruction insertion unit 141P similar to the dummy instruction insertion unit 41 (Fig. 3), which in turn has an LFSR 151P similar to the LFSR 51 (Fig. 3). The CPU core 161S also has a dummy instruction insertion unit 141S similar to the dummy instruction insertion unit 41, which in turn has an LFSR 151S similar to the LFSR 51. Furthermore, the CPU cores 161P and 161S have setting registers 162P and 162S, respectively, similar to the setting register 62. The values ​​stored in the setting registers 162P and 162S are assumed to be the same.

[0142] In the CPU cores 161P and 161S, the dummy instruction insertion units 141P and 141S set the same seed value to the identically configured LFSRs 151P and 151S to generate the same series of random numbers. The dummy instruction insertion unit 141P then inserts dummy instructions into the sequence of valid instructions to be executed by the CPU core 161P, similar to the dummy instruction insertion unit 41, based on the random numbers generated by the LFSR 151P and the value stored in the setting register 162P. The dummy instruction insertion unit 141S inserts dummy instructions into the sequence of valid instructions to be executed by the CPU core 161S, similar to the dummy instruction insertion unit 41, based on the random numbers generated by the LFSR 151S and the value stored in the setting register 162S. Therefore, dummy instructions are inserted at the same positions in the sequences of valid instructions to be executed by the CPU cores 161P and 161S, and the CPU cores 161P and 161S perform exactly the same processing.

[0143] The delay unit 166P delays the processing result (the execution result of the instruction) of the CPU core 161P by a predetermined number of cycles corresponding to a specific number of cycles, for example, one cycle, and outputs the result to the check unit 167. The delay unit 166S, like the delay unit 166P, delays the data input to the CPU core 161S by a predetermined number of cycles and outputs the data to the CPU core 161S.

[0144] The check unit 167 compares the processing result of the CPU core 161P received from the delay unit 166P with the processing result of the same processing of the CPU core 161S received from the CPU core 161S, and outputs an error signal if they do not match.

[0145] The CPU 131 can improve resistance to external attacks, similar to the CPU 31. For example, by inserting a dummy instruction, it is possible to suppress the success of a side channel attack, and to prevent important instructions from being skipped due to multiple instruction skips caused by a fault injection attack.

[0146] Furthermore, in the CPU 131, for example, if there is a fault injection attack inside the CPU cores 161P and / or 161S, for example, an attack on FFs (not shown) corresponding to FF75 or FF77 ( FIG. 3 ), the processing results of the CPU cores 161P and 161S will no longer match. In this case, an error signal is output from the check unit 167. Therefore, by taking appropriate recovery measures when an error signal is output, it is possible to prevent malfunctions such as disabling of security functions when there is an attack inside the CPU cores 161P and / or 161S.

[0147] As described above, the CPU 131 with a dual lockstep configuration can also deal with attacks on the inside of the CPU core 161P and / or 161S, and can further increase resistance to external attacks.

[0148] <Third embodiment of a microcomputer to which the present technology is applied>

[0149] FIG. 16 is a block diagram showing a configuration example of a third embodiment of a microcomputer to which the present technology is applied.

[0150] In the figure, parts corresponding to those in FIG. 2 are given the same reference numerals, and the description thereof will be omitted below as appropriate.

[0151] 16, the microcomputer 230 includes a memory 32, a peripheral device 33, a dummy instruction insertion unit 41, and a CPU 231. The memory 32, the peripheral device 33, and the dummy instruction insertion unit 41 are connected to a bus, and the CPU 231 is connected to the dummy instruction insertion unit 41.

[0152] 2 in that it includes a memory 32 and a peripheral device 33. However, the microcomputer 230 differs from the microcomputer 30 in that it includes a CPU 231 instead of the CPU 31.

[0153] The CPU 231 is configured in the same manner as the CPU 31 (FIG. 3). However, although the CPU 31 incorporates a dummy instruction insertion unit 41, the CPU 231 does not incorporate a block corresponding to the dummy instruction insertion unit 41. Therefore, the CPU 231 differs from the CPU 31 which incorporates the dummy instruction insertion unit 41 in that it does not incorporate a block corresponding to the dummy instruction insertion unit 41.

[0154] In the microcomputer 230 , the CPU 231 does not incorporate a block corresponding to the dummy instruction inserting section 41 , so the dummy instruction inserting section 41 is provided externally to the CPU 231 .

[0155] The microcomputer 230 performs the same processing as the microcomputer 30 except that the dummy instruction insertion unit 41 is external to the CPU 231 , and therefore can achieve the same effects as the microcomputer 30 .

[0156] It should be noted that the embodiments of the present technology are not limited to the above-described embodiments, and various modifications are possible within the scope of the present technology.

[0157] For example, the present technology can be configured as a cloud computing system in which a single function is shared and processed collaboratively by a plurality of devices via a network.

[0158] Furthermore, each step described in the above flowchart can be executed by one device, or can be shared and executed by a plurality of devices.

[0159] Furthermore, when one step includes multiple processes, the multiple processes included in that one step can be executed by one device or can be shared and executed by multiple devices.

[0160] Furthermore, the effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0161] The present technology can have the following configurations.

[0162] <1> The processor comprises: an execution unit that executes instructions; a setting register that sets insertion instruction number information related to the number of dummy instructions that do not affect the internal state and output of the processor; and a dummy instruction insertion unit that inserts the dummy instructions, the number of which is based on the insertion instruction number information set in the setting register, into a sequence of instructions to be executed by the execution unit. <2> The processor described in <1>, wherein the dummy instruction insertion unit sets the number of instructions to be inserted to a random number generated within a range based on the insertion instruction number information. <3> The processor described in <1> or <2>, wherein the insertion instruction number information is a minimum value of the number of instructions to be inserted and a range from that minimum value to a maximum value of the number of instructions to be inserted. <4> The processor described in any of <1> to <3>, wherein the dummy instruction insertion unit sets the number of instructions to be inserted each time a dummy instruction of the number of instructions to be inserted is inserted. <5> The processor according to any one of <1> to <4>, wherein insertion interval information regarding the insertion interval of the dummy instructions is set in the setting register, and the dummy instruction insertion unit inserts the dummy instructions at an insertion interval based on the insertion interval information set in the setting register. <6> The processor according to <5>, wherein the dummy instruction insertion unit sets the insertion interval to a random number generated within a range based on the insertion interval information. <7> The processor according to <5> or <6>, wherein the insertion interval information is a minimum value of the insertion interval and a width from the minimum value to a maximum value of the insertion interval. <8> The processor according to any one of <5> to <7>, wherein the dummy instruction insertion unit sets the insertion interval each time the dummy instructions of the number of inserted instructions are inserted. <9> The processor according to any one of <1> to <8>, wherein the dummy instruction insertion unit generates the dummy instructions. <10> The processor according to <9>, wherein the dummy instruction insertion unit sets the type of instruction corresponding to the random number as the type of the dummy instruction. <11> The processor according to <10>, wherein the dummy instruction insertion unit sets, as the type of the dummy instruction, a type corresponding to a random number from among instruction types including multiplication, division, logical AND, and shift.<12> The processor according to <10> or <11>, wherein the dummy instruction insertion unit sets a type of the dummy instruction for each of the dummy instructions of the number of inserted instructions. <13> The processor according to any of <10> to <12>, wherein the dummy instruction insertion unit sets a random number as an operand of the dummy instruction. <14> The processor according to <13>, wherein the dummy instruction insertion unit sets an operand of the dummy instruction for each of the dummy instructions of the number of inserted instructions. <15> The processor according to any of <1> to <14>, wherein the result of execution of the dummy instruction is written back to a zero register. <16> The processor according to any of <1> to <15>, wherein the instructions are pipelined. <17> The processor according to any of <1> to <16>, wherein the setting register is set at startup and at a predetermined timing after startup. <18> The processor according to <17>, wherein the insertion of the dummy instruction is turned off while the setting register is being set. <19> The processor according to any one of <1> to <18>, which has a dual lockstep configuration. <20> A processing method, comprising: a processor having an execution unit that executes instructions, inserting, into a sequence of instructions to be executed by the execution unit, dummy instructions whose number of insertion instructions is based on insertion instruction number information set in a setting register that sets the insertion instruction number information related to the number of dummy instructions that do not affect the internal state and output of the processor.

[0163] 10 Image sensor, 11 Die, 12 Pixel area, 13 Control circuit, 14 Logic circuit, 20 Image sensor, 21 Sensor die, 24 Logic die, 30 Microcomputer, 31 CPU, 32 Memory, 33 Peripheral device, 41 Dummy instruction insertion unit, 51 LFSR, 61 CPU core, 62 Setting register, 71 Program counter, 72 Instruction buffer, 73 Interrupt detection unit, 74 Decoder, 75 FF, 76 ALU, 77 FF, 78 WB unit, 79 Internal register, 130 Microcomputer, 131 CPU, 141P, 141S Dummy instruction insertion unit, 151P, 151S LFSR, 161P, 161S CPU core, 166P, 166S Delay unit, 167 Check unit, 230 Microcomputer, 231 CPU

Claims

1. A processor comprising: an execution unit that executes instructions; a setting register in which information on the number of insertion instructions regarding the number of dummy instructions that do not affect the internal state and output of the processor is set; and a dummy instruction insertion unit that inserts the dummy instructions into the sequence of instructions executed by the execution unit, the number of insertion instructions being based on the information on the number of insertion instructions set in the setting register.

2. The processor according to claim 1, wherein the dummy instruction insertion unit sets the number of instructions to be inserted to a random number generated within a range based on the information on the number of instructions to be inserted.

3. The processor according to claim 1, wherein the information on the number of instructions to be inserted is the minimum value of the number of instructions to be inserted and the range from the minimum value to the maximum value of the number of instructions to be inserted.

4. The processor according to claim 1, wherein the dummy instruction insertion unit sets the number of instructions to be inserted each time a dummy instruction of the number of instructions to be inserted is inserted.

5. The processor according to claim 1, wherein the setting register is set with insertion interval information regarding the insertion interval of the dummy instructions, and the dummy instruction insertion unit inserts the dummy instructions at an insertion interval based on the insertion interval information set in the setting register.

6. The processor according to claim 5, wherein the dummy instruction insertion unit sets the insertion interval to a random number generated within a range based on the insertion interval information.

7. The processor according to claim 5, wherein the insertion interval information is a minimum value of the insertion interval and a width from the minimum value to a maximum value of the insertion interval.

8. The processor according to claim 5, wherein the dummy instruction insertion unit sets the insertion interval each time the dummy instructions of the number of inserted instructions are inserted.

9. The processor according to claim 1, wherein the dummy instruction insertion unit generates the dummy instruction.

10. The processor according to claim 9, wherein the dummy instruction insertion unit sets the type of instruction corresponding to the random number as the type of the dummy instruction.

11. The processor according to claim 10, wherein the dummy instruction insertion unit sets the type of the dummy instruction to a type corresponding to a random number, among instruction types including multiplication, division, logical AND, and shift.

12. The processor according to claim 10, wherein the dummy instruction insertion unit sets a type of the dummy instruction for each of the dummy instructions in the number of inserted instructions.

13. The processor according to claim 10, wherein the dummy instruction insertion unit sets a random number as an operand of the dummy instruction.

14. The processor according to claim 13, wherein the dummy instruction insertion unit sets an operand of the dummy instruction for each of the dummy instructions in the number of inserted instructions.

15. The processor of claim 1, wherein the writeback of the result of execution of the dummy instruction is performed to a zero register.

16. The processor of claim 1, wherein the instructions are configured to be pipelined.

17. The processor according to claim 1, wherein the setting register is configured to be set at startup and at a predetermined timing after startup.

18. The processor of claim 17, wherein the insertion of dummy instructions is turned off during the setting of the configuration register.

19. The processor of claim 1, in a dual lockstep configuration.

20. A processing method comprising a processor having an execution unit that executes instructions, inserting dummy instructions into a sequence of instructions to be executed by the execution unit, the number of dummy instructions to be inserted being based on information on the number of instructions to be inserted set in a setting register, the information on the number of instructions to be inserted relating to the number of dummy instructions that do not affect the internal state and output of the processor.

Images