Superconducting retention memory with non-superconducting write circuit

Abstract

A superconducting memory device includes: at least two superconducting loops, one configured as a readout loop and another configured as a state loop; a non-superconducting input conveying a non-superconducting input signal for writing state to the memory device; at least two superconducting inputs conveying superconducting input signals for reading the state of the memory device; a superconducting output conveying an output of the memory device; first and second Josephson junctions, the state loop including the first Josephson junction, the readout loop including the second Josephson junction; and a non-superconducting write circuit including a write line for conveying a write signal for writing state to the memory device. A state of the memory device is determined based on the presence of single flux quantum in the state loop, a location of the single flux quantum in the superconducting loops, or a direction of rotation of the single flux quantum in the state loop.

Description

SUPERCONDUCTING RETENTION MEMORY WITH NON-SUPERCONDUCTING WRITE CIRCUITCROSS REFERENCE TO RELATED APPLICATION(S)

[0001] This application claims the benefit of and priority under 35 U.S.C. §119 to U.S. provisional patent application no. 63 / 569,794, filed on March 26, 2024, entitled “Single Flux Quantum Retention Memory,” the disclosure of which is incorporated by reference herein in its entirety for all purposes.BACKGROUND

[0002] This application relates generally to superconducting circuits, and more particularly relates to a read only memory (ROM), or write infrequently memory, suitable for application in ROMs, programmable logic arrays (PLA) and field programmable gate arrays (FPGA), implemented using a plurality of superconducting Josephson junctions (JJ), related circuitry, and non-superconducting circuitry.

[0003] Superconducting digital systems are capable of performing computing operations at clock speeds in excess of 100 GHz. In these systems, the circuits comprise superconducting wires and Josephson junctions that together form superconducting loops in which information in the form of a single flux magnetic quantum is encoded and stored.

[0004] The superconducting circuits can be configured to implement traditional logic gates, such as, for example, AND gates, OR gates, flip-flops, etc. These logic gates, in turn, can be configured to implement more complex logic such as, for example, shift registers, counters, processors, etc.

[0005] International Publication No. WO 2023 / 183391A1 to Reohr et al. (“Reohr ‘391”), the disclosure of which is incorporated by reference herein in its entirety, describes illustrative systems, circuits, devices and / or methods for enabling the reliable writing of superconducting memory circuits containing both magnetic Josephson junctions (MJJs) and Josephson junctions or memory circuits containing Josephson junctions exclusively which, along with non- superconducting (e.g., bipolar and / or complementary metal-oxide semiconductor (Bi)CMOS)) write circuits, form an underlying hybrid circuit and methods for writing random-accessmemories (RAMs), and programming and / or enabling one or more functions of superconducting PLAs, FPGAs, and 7r-junction circuits, among other applications.

[0006] However, there exists a need for JJ-based ROM (suitable for application as ROMs, programmable logic arrays (PLAs), and field programmable gate arrays (FPGAs)) that: 1) is sufficiently fast and dense; 2) supports multiple read ports; and 3) can be fabricated in the same process / stack-up as corresponding JJ-based logic circuits.SUMMARY

[0007] The present disclosure, as manifested in one or more embodiments thereof, relates to a read-only memory (ROM), or write infrequently memory, suitable for application in ROMs, programmable logic arrays (PLA) and field programmable gate arrays (FPGA), implemented using a plurality of superconducting Josephson junctions (JJ), related circuitry, and non- superconducting circuitry. Such a memory may be configured to encode information in the form of magnetic flux quantum and may transfer such information based on single flux quantum (SFQ) pulses.

[0008] In contrast to conventional Josephson random-access memory (J SRAM), which requires at least five superconducting loops and associated superconducting control circuitry, a programming path for a memory device according to one or more embodiments of the inventive concept includes no more than two state loops and one or two readout loops (at a minimum), for a total of two or more superconducting loops. Furthermore, a memory circuit according to one or more embodiments includes a non-superconducting circuit which is configured to change the state of the memory device (i.e., write / program) and to direct a write operation to a particular memory device. This novel memory device architecture according to embodiments of the inventive concept achieves a significant reduction in chip area and complexity, among other benefits, with much of the savings in chip area being realized in peripheral circuits of the memory device, thereby providing a highly dense memory not achievable using conventional approaches. Moreover, a load on a global resonant clock network - possibly used to power the memory and coordinate its timing - is reduced significantly using techniques of the inventive concept compared to other approaches (e g., JSRAM).

[0009] In accordance with one or more embodiments, a Josephson junction based memory device is provided. The Josephson junction based memory device includes a plurality of superconducting loops. Each of the plurality of superconducting loops includes at least one Josephson junction. The plurality of superconducting loops are electrically coupled in series together. The plurality of superconducting loops includes one or two state loops and at least one readout loop. The plurality of superconducting loops are configured to store or annihilate magnetic flux quanta in one or more of the superconducting loops in response to a combination of control signals and single flux quantum (SFQ) pulses.

[0010] In accordance with another embodiment, a method for storing digital information in a Josephson junction based memory device is provided. The method includes first providing, to a plurality of superconducting loops, one of which is a state loop, a combination of control signals and single flux quantum (SFQ) pulses and second providing, to a non-superconducting circuit, associated with the state loop, at least one control signal to store digital information in the state loop of the Josephson junction memory device. Each of the plurality of superconducting loops includes at least one Josephson junction. The plurality of superconducting loops are electrically coupled. The plurality of superconducting loops includes one or two state loops and at least one readout loop. The method also includes, in response to the combination of control signals and SFQ pulses, storing or annihilating (i.e., removing) magnetic flux quanta in one or more of the plurality of superconducting loops.

[0011] In accordance with an embodiment of the inventive concept, a superconducting memory includes: a non-superconducting write circuit; one or more superconducting memory device layers sequentially stacked on the non-superconducting write circuit in a vertical direction perpendicular to a surface of the non-superconducting write circuit; and one or more write lines, each of the one or more write lines operatively connecting the non-superconducting write circuit to a corresponding one of the one or more superconducting memory device layers. Each of the one or more superconducting memory device layers comprises one or more superconducting memory devices, each of the one or more superconducting memory devices being configured to store a memory state as a function of at least one write signal provided by the non- superconducting write circuit and conveyed by the one or more write lines.

[0012] In accordance with another embodiment of the inventive concept, a superconducting memory device configured to have its state written at least once includes: at least two superconducting loops electrically coupled to one another, one of the at least two superconducting loops is configured as a readout loop and another of the at least two superconducting loops is configured as a state loop; at least one non-superconducting input configured to convey at least one corresponding non-superconducting input signal provided to the superconducting memory device for writing state to the superconducting memory device; at least two superconducting inputs configured to convey corresponding superconducting input signals provided to the superconducting memory device for reading the state of the superconducting memory device; a superconducting output configured to convey an output of the superconducting memory device; at least first and second Josephson junctions, the state loop including the first Josephson junction and the readout loop including the second Josephson junction; and a non-superconducting write circuit, the non-superconducting write circuit comprising a dedicated write line configured to convey a write signal for writing state to the superconducting memory device. A state of the superconducting memory device is determined based on the presence or absence of single flux quantum in the state loop, a location of the single flux quantum in the at least two superconducting loops, or a direction of rotation of the single flux quantum in the state loop.

[0013] In accordance with yet another embodiment of the inventive concept, a superconducting memory device includes: a plurality of superconducting memory device layers sequentially stacked in a vertical direction perpendicular to a surface of the superconducting memory device, each of the plurality of superconducting memory device layers comprising one or more superconducting memory devices; a shared layer between each pair of vertically adjacent superconducting memory device layers in the plurality of superconducting memory device layers; and a global resonant clock network operatively coupled to at least a subset of the one or more superconducting memory devices in each of the plurality of superconducting memory device layers. The shared layer is configured to implement at least a portion of the global resonant clock network.

[0014] In accordance with still another embodiment of the inventive concept, a mask- programmable memory device includes first and second superconducting memory devices. The first superconducting memory device includes: at least two superconducting loops electricallycoupled to one another, one of the at least two superconducting loops is configured as a first readout loop and another of the at least two superconducting loops is configured as a first state loop; at least two superconducting inputs configured to convey corresponding superconducting input signals provided to the superconducting memory device for reading a state of the first superconducting memory device; a superconducting output configured to convey an output of the first superconducting memory device; at least first and second losephson junctions, the first state loop including the first losephson junction and the first readout loop including the second Josephson junction; and a transformer connected in the first state loop and configured to inject a flux quantum into the first state loop. The second superconducting memory device includes: at least two superconducting loops electrically coupled to one another, one of the at least two superconducting loops is configured as a second readout loop and another of the at least two superconducting loops is configured as a second state loop; at least two superconducting inputs configured to convey corresponding superconducting input signals provided to the second superconducting memory device for reading the state of the second superconducting memory device; a superconducting output configured to convey an output of the second superconducting memory device; and at least third and fourth Josephson junctions, the second state loop including the third Josephson junction and the second readout loop including the fourth Josephson junction. States of the first and second superconducting memory devices are determined based on the presence or absence of single flux quantum in the first and second state loops, respectively, or a direction of rotation of the single flux quantum in the first and second state loops, respectively.

[0015] These and other features and advantages of the present inventive concept will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above, as well as additional features, will be better understood through the following illustrative and non-limiting detailed description of example embodiments, with reference to the appended drawings, wherein like reference numerals (when used) indicate corresponding elements throughout the several views, and in which:.

[0017] FIG. 1 A illustrates a schematic diagram of a Josephson junction based memory device, in accordance with example embodiments;

[0018] FIG. IB illustrates a schematic diagram of an alternative Josephson junction based memory device, in accordance with example embodiments;

[0019] FIG. 2A illustrates a first pass-through path sequence utilizing the Josephson junction based memory device of FIG. 1A, in accordance with example embodiments;

[0020] FIG. 2B illustrates a second pass-through path sequence utilizing the Josephson junction based memory device of FIG. 1A, in accordance with example embodiments;

[0021] FIG. 3A illustrates a read path sequence for reading a one-state utilizing the Josephson junction based memory device of FIG. 1 A, in accordance with example embodiments;

[0022] FIG. 3B illustrates a read path sequence for reading a zero-state utilizing the Josephson junction based memory device of FIG. 1A, in accordance with example embodiments;

[0023] FIG. 4A illustrates a circuit diagram of the Josephson junction based memory device of FIG. 1A, in accordance with example embodiments;

[0024] FIG. 4B illustrates a circuit diagram of the Josephson junction based memory device which is consistent with the illustrative memory device shown in FIG. 4A, except for the omission of a transformer, in accordance with example embodiments;

[0025] FIG. 4C illustrates a circuit diagram of the alternative Josephson junction based memory device of FIG. IB, in accordance with example embodiments;

[0026] FIG.5 illustrates a flux initialization process, in accordance with example embodiments;

[0027] FIG. 6 illustrates a flux initialization process, in accordance with example embodiments;

[0028] FIG. 7 illustrates multiple unit cells sharing the same flux source, in accordance with example embodiments;

[0029] FIG. 8A illustrates an array of unit cells arranged in a word-organized memory fabric, in accordance with example embodiments;

[0030] FIG. 8B illustrates a mask-programmed array of unit cells arranged in a word-organized memory fabric, in accordance with example embodiments;

[0031] FIG. 9 illustrates a partitioned unit cell with separate write path and read path, in accordance with example embodiments;

[0032] FIG. 10A illustrates a schematic diagram of an alternative Josephson junction based memory device, in accordance with example embodiments;

[0033] FIG. 10B illustrates a schematic diagram of an alternative Josephson junction based memory device, in accordance with example embodiments;

[0034] FIG. 11 A illustrates a read path sequence for reading a one-state utilizing the alternative Josephson junction based memory device of FIG. 10, in accordance with example embodiments;

[0035] FIG. 1 IB illustrates a read path sequence for reading a zero-state utilizing the alternative Josephson junction based memory device of FIG. 10, in accordance with example embodiments;

[0036] FIG. 12A illustrates a first read path variation utilizing the alternative Josephson junction based memory device of FIG. 10, in accordance with example embodiments;

[0037] FIG. 12B illustrates a second read path variation utilizing the alternative Josephson junction based memory device of FIG. 10, in accordance with example embodiments;

[0038] FIG. 12C illustrates a third read path variation utilizing the alternative Josephson junction based memory device of FIG. 10, in accordance with example embodiments;

[0039] FIG. 13 A illustrates a read path sequence for reading a one-state utilizing the first read path variation of the alternative Josephson junction based memory device of FIG. 12A, in accordance with example embodiments;

[0040] FIG. 13B illustrates a read path sequence for reading a zero-state utilizing the first read path variation of the alternative Josephson junction based memory device of FIG. 12A, in accordance with example embodiments;

[0041] FIG. 14A illustrates a read path sequence for reading a one-state utilizing the second read path variation of the alternative Josephson junction based memory device of FIG. 12B, in accordance with example embodiments;

[0042] FIG. 14B illustrates a read path sequence for reading a zero-state utilizing the second read path variation of the alternative Josephson junction based memory device of FIG. 12B, in accordance with example embodiments;

[0043] FIG. 15A illustrates a read path sequence for reading a one-state utilizing the third read path variation of the alternative Josephson junction based memory device of FIG. 12C, in accordance with example embodiments;

[0044] FIG. 15B illustrates a read path sequence for reading a zero-state utilizing the third read path variation of the alternative Josephson junction based memory device of FIG. 12C, in accordance with example embodiments;

[0045] FIG. 16 illustrates a circuit diagram of the first read path variation of the alternative Josephson junction based memory device of FIG. 12A, in accordance with example embodiments;

[0046] FIG. 17 illustrates a circuit diagram of the second read path variation of the alternative Josephson junction based memory device of FIG. 12B, in accordance with example embodiments;

[0047] FIG. 18 illustrates a circuit diagram of the third read path variation of the alternative Josephson junction based memory device of FIG. 12C, in accordance with example embodiments;

[0048] FIG. 19 illustrates a schematic diagram of a Josephson junction based memory device, in accordance with example embodiments;

[0049] FIGS. 20A and 20B illustrate write path sequences for writing a one-state and a zerostate, respectively, utilizing the Josephson junction based memory device of FIG. 19, in accordance with example embodiments;

[0050] FIGS. 21 illustrates a sequence for writing a zero-state, reading a zero-state, writing a one-state, and reading a one-state, in which all operations are directed to the Josephson junction based memory device of FIG. 19, in accordance with example embodiments;

[0051] FIG. 22 illustrates a schematic diagram of a Josephson junction based memory device, in accordance with example embodiments;

[0052] FIG. 23 illustrates a circuit diagram of the Josephson junction based memory device of FIG. 22, in accordance with example embodiments;

[0053] FIG. 24A illustrates a first pass-through path sequence utilizing the Josephson junction based memory device of FIG. 22, in accordance with example embodiments;

[0054] FIG. 24B illustrates a second pass-through path sequence utilizing the Josephson junction based memory device of FIG. 22, in accordance with example embodiments;

[0055] FIGS. 25 A and 25B illustrate read path sequences for reading a one-state and a zerostate, respectively, utilizing the Josephson junction based memory device of FIG. 22, in accordance with example embodiments;

[0056] FIGS. 26A and 26B illustrate write path sequences for writing a one-state and a zerostate, respectively, utilizing the Josephson junction based memory device of FIG. 22, in accordance with example embodiments;

[0057] FIG. 27 is a schematic diagram depicting an example memory device integrated with a non-superconducting write circuit, according to one or more embodiments;

[0058] FIG. 28 is a schematic diagram depicting at least a portion of an exemplary retention memory, according to one or more embodiments;

[0059] FIG. 29 is a schematic block diagram depicting at least a memory device portion of an example superconducting memory system, shown in cross section, in accordance with example embodiments;

[0060] FIG. 30 is a schematic block diagram depicting at least a portion of an example superconducting memory, in accordance with example embodiments; and

[0061] FIG. 31 is a schematic block diagram depicting at least a portion of an example superconducting memory, in accordance with example embodiments.

[0062] It is to be appreciated that all the figures are schematic, not necessarily drawn to scale, and may generally only show parts that are necessary to elucidate example embodiments, wherein other parts may be omitted or merely suggested. Elements in the figures are illustratedfor simplicity and clarity. Common but well -understood elements that may be useful or necessary in a commercially feasible embodiment are not necessarily shown in order to facilitate a less hindered view of the illustrated embodiments.DETAILED DESCRIPTION

[0063] Various examples of systems, devices, and / or methods are described herein with reference to the accompanying drawings. Any embodiment, implementation, and / or feature described herein as being an example is not necessarily to be construed as preferred or advantageous over any other embodiment, implementation, and / or feature unless stated as such. Thus, other embodiments, implementations, and / or features may be utilized, and other changes may be made without departing from the scope of the inventive concept described herein.

[0064] Accordingly, the examples described herein are not meant to be limiting. It will be readily understood by those skilled in the art that aspects of the present disclosure, as generally described herein, and illustrated in the figures, can be arranged, substituted, combined, separated, and designed in a wide variety of different configurations. These different configurations are to be considered within the scope of the present inventive concept.

[0065] Further, unless the context suggests otherwise, the features illustrated in each of the figures may be used in combination with one another. Thus, the figures should be generally viewed as component aspects of one or more overall embodiments, with the understanding that not all illustrated features are necessary for each embodiment.

[0066] Additionally, any enumeration of elements, blocks, or steps in this specification or the claims using ordinal terms (e.g., “first,” “second,” etc.) is intended to be for purposes of clarity only. Thus, such enumeration should not be interpreted to require or imply that these elements, blocks, or steps adhere to a particular arrangement or are carried out in a particular order.

[0067] Moreover, terms such as “substantially” or “about” that may be used herein are meant that the recited characteristic, parameter, or value need not be achieved exactly, but that deviations or variations, including, for example, tolerances, measurement error, measurement accuracy limitations and other factors known to those skilled in the art, may occur in amounts that do not preclude the effect the characteristic was intended to provide.

[0068] Further, terms such as “A coupled to B,” “A electrically coupled to B,” etc., do not necessarily mean that items A and B are directly coupled to one another. For example, a first component electrically coupled to a second component is interpreted to mean that the components are either directly coupled (e.g., via a conductor or other element) or coupled to one another via one or more resistors, capacitors, inductors, and / or other active or passive components.

[0069] The potential of superconducting digital technology as a beyond-CMOS technology derives from high energy efficiency, high computational density, and high interconnect bandwidth. The technology is based on a single-flux-quantum (SFQ) pulse, which is fast, low power, and exhibits low-dispersion / low-loss on superconductor transmission lines. Example embodiments involve various combinations of fabrication materials, density, power / clock distribution, logic and memory design, packaging, interfaces, and architecture. Logic devices based on such technologies are projected to have a computational density on par with leadingnode CMOS based on an integration scale up 400 M JJ / cm2and a clock rate of 30 GHz, although embodiments are not limited thereto.

[0070] High performance logic typically requires on-chip memory that 1) is sufficiently fast and dense, 2) supports multiple read ports, and 3) can be fabricated in the same process / stack-up as the logic. With respect to conventional CMOS logic technologies, read-only memory (ROM), suitable for application in programmable logic arrays (PLAs) and field programmable gate arrays (FPGAs), satisfies these requirements. The presently described Josephson junction read-only memory (JROM) fulfills these requirements for superconducting SFQ logic and represents an analogue of ROM.

[0071] X-Y addressing and readout is accomplished in JROM by moving stored SFQ between a series arrangement of adj cent superconducting loops. Conventional Josephson transmission line (JTL) interconnects provide high fan-out across the memory device. The present JROM design is extensible to multiple read ports.

[0072] The JROM design avoids exotic devices such as magnetics and therefore can be fabricated in the same process / stack-up as that of high-performance SFQ logic. JROM stack-up may include non-superconducting devices, such as CMOS. Throughout the present disclosure, the term “non-superconducting,” with reference to devices or elements, may be usedsynonymously with the term “normal metal” and non-superconducting devices such as field effect transistors. A “normal metal” exhibits resistance to electrical current flow, which decreases with temperature, while a “superconducting metal,” below a specific critical temperature, exhibits zero resistance and expels magnetic fields (referred to as the Meissner effect). During system operation, JROM utilizes the native SFQ logic signals and thus avoids the need for potentially complex conversion processes and hardware. The JROM design also avoids physically large components such as transformers, achieving a design density below 3.5 MB / cm2using 193i (i.e., 193 nm) lithography. Wave pipelining allows throughput equal to the clock rate of the logic, with density that is a 500 times advance over conventional devices.Example Josephson Junction Based Memory Devices

[0073] FIG. 1A is a schematic diagram depicting an illustrative Josephson junction based memory device 100, in accordance with example embodiments of the inventive concept. The Josephson junction based memory device 100 includes one or more non-superconducting inputs 160 configured to convey one or more corresponding non-superconducting signals provided to the memory device 1900, a plurality of superconducting inputs (e.g., word read control line 164 (WR) and strobe control line 166 (S) configured to convey corresponding superconducting input signals provided to the memory device 1900, a superconducting output (e.g., superconducting output (Q)), a non-superconducting write circuit 184, and a plurality of superconducting loops 102. Each of the superconducting loops (e.g., superconducting loop 102c, 102d, or 102e) includes at least one Josephson junction (e.g., Josephson junction 104c, and / or 104d). Two adjacent superconducting loops 102 may share a Josephson junction. In one or more embodiments, for example, adjacent superconducting loops 102c and 102d may share Josephson junction 104c, and adjacent superconducting loops 102d and 102e may share Josephson junction 104d. In such scenarios, the plurality of superconducting loops 102 are electrically coupled to one another.

[0074] The non-superconducting write circuit 184 conveys one or more write signal(s) 138 used to write state into a state loop 110 via induction, as will be explained in further detail with respect to the description of FIGS.

[0075] FIG. IB is a schematic diagram of an alternative Josephson junction based memory device 180, in accordance with example embodiments of the inventive concept. The Josephsonjunction based memory device 180 not only includes an additional Josephson junction with respect to the memory device 100 of FIG. 1A (e.g., Josephson junction 182), but also contains different write circuits. In memory device 180, the non-superconducting write circuit 184 is shown directly connected to the state loop 110. In memory device 100 of FIG. 1, write signal(s) 138 would be coupled into the state loop 110 via an integrated transformer within state loop 110. The transformer is not explicitly shown in FIG. 1A for clarity purposes; that will be described in further detail with respect to FIG. 4C. The transformer’s primary or secondary winding is the write line.

[0076] It is important to note that a non-superconducting write circuit can include superconducting wires. It just doesn’t contain superconducting loops.

[0077] Indicated by the inclusion of the non-superconducting write circuit 184 and the additional Josephson junction 182, a distinction between FIGS. 1A and IB arises between their associated write circuit(s) and write method(s). With respect to the read operation, however, their single flux quanta / quantum behaviors may be identical, and thus the illustrative read method of FIGS. 2A through 3B will (and need only) depict the superconducting loops of FIG.1 A, with the understanding that the described example read method may be similarly applied to the memory device 180 shown in FIG. IB.

[0078] Furthermore, with respect to FIGS. 1A and IB, the plurality of superconducting loops 102 may include a state loop 110 and a plurality of readout loops 120. As illustrated in FIG. 1A, the state loop 110 is electrically coupled to the readout loops 120 (e g., 120a and 120b) of a read path. In this configuration, one of the readout loops 120 may be referred to as a “shared loop” (e.g., shared loop 130) as known in the prior art.

[0079] Stated another way, as illustrated in FIGS. 1 A and IB, the plurality of superconducting loops 102 could be electrically coupled in a series arrangement. In some embodiments, the series arrangement may include three superconducting loops (e.g., superconducting loops 102c, 102d, and 102e), of which one is a state loop (e.g., state loop 110) and two are readout loops (e.g., readout loops 102d and 102e), of which one of the readout loops (e.g., 102d) may be a shared loop (e.g., shared loop 130). In other embodiments, the series arrangement may include four superconducting loops, of which two are state loops and two are readout loops, as will be described in further detail in conjunction with FIG. 22. In such scenarios, each superconductingloop of the plurality of superconducting loops 102 has one or two adjacent loops, depending on its arrangement in the Josephson junction based memory device 100. As an example, superconducting loop 102c has one adjacent loop (superconducting loop 102d), superconducting loop 102d has two adjacent loops (superconducting loop 102c and superconducting loop 102e), and superconducting loop 102e has one adjacent loop (superconducting loop 102d). It will be understood that other arrangements of the superconducting loops 102 are possible and contemplated in relation to the present disclosure.

[0080] The Josephson junction based memory device 100 (and 180 in FIG. IB) also includes a plurality of superconducting line(s) for performing a read operation and non-superconducting lines for performing a write operation (and non-superconducting input(s) 160 of 180 in FIG. IB), which are associated with superconducting circuits configured to perform a read (and state storage) operation and with non-superconducting circuits configured to perform a write operation (e g. non-superconducting write circuit 184 in FIG. 1A and IB). In FIG. IB, non- superconducting write circuit 184 may be part of a transformer-based circuit which will be described in further detail with reference to FIGS. 4A and 6. In FIG. IB, the non- superconducting write circuit 184 is coupled to the state loop 110. In some embodiments, each control line of the address and control lines could include a Josephson transmission line and a current-bias source. The current-bias source may furthermore provide an AC signal corresponding to a global resonant clock network 170, which may provide a system -wide clock to help enable operation in a synchronized manner.

[0081] In such embodiments, each address line (e.g., word read control line WR 164) of the plurality of address lines may also include a resistor (not explicitly shown) connected between the Josephson transmission line and a corresponding superconducting loop of the plurality of superconducting loops 102.

[0082] The plurality of superconducting loops 102 are configured to store or annihilate (i.e., remove) magnetic flux quanta (e.g., SFQ 140a or SFQ 140b) in one or more of the superconducting loops in response to a combination of control signals and single flux quantum (SFQ) pulses. The memory device 100 may further include write signal(s) 138 (abbreviated WS) that may be used, for example, to change the state of the memory device 100, as will be described in further detail below.

[0083] In an example embodiment, the control signals could be provided to the superconducting loops 102 by way of a word read control line 164, also referred to as a word read WR, and / or a strobe control line 166, also referred to as a strobe S. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. In one or more embodiments, the strobe control line 166 may be implemented as a bit line in the memory device. Furthermore, at least a subset of the plurality of superconducting loops 102 may be coupled to the global resonant clock network 170 through one or more transformers operably connected to the superconducting loop (as will be described with respect to current sources 406 and 408 of FIG. 4A).

[0084] In some embodiments, the plurality of superconducting loops 102 are configured to shift a magnetic flux quanta (e.g., SFQ 140a) from an initial superconducting loop (e.g., superconducting loop 102e) to an adjacent superconducting loop (e.g., superconducting loop 102d) in response to an SFQ pulse applied to the initial superconducting loop (e.g., 102e). In some embodiments, an SFQ pulse may have an amplitude on the order of about 1 millivolt (mV) and may have a pulse width (i.e., duration) on the order of about 2 picoseconds (ps), although embodiments are not limited thereto.

[0085] In many exemplary embodiments (e.g., 2200 of FIG. 22) of the present disclosure, the flux quantum, in contrast to JSRAM, moves between no more than two state loops (e.g., 2210). Moreover, the FROM write path of 2200 includes non-superconducting circuits, which can move a flux quantum between two state loops (e.g., two state loops 2010 of FIG. 22) and can direct a write operation to a particular memory device. The non-superconducting circuits can enable, for example, a current switch for the selective writing of a memory device among a plurality of memory devices and can shape the signal (write signal WS) applied to the two state loops 2210, supplied via the write line.

[0086] Writing the state of the memory device in Josephson static random-access memory (JSRAM) (see, e.g., U.S. Patent Application Publication No. 2024 / 0038298 to Luo et al. (“Luo”), the disclosure of which is incorporated by reference herein in its entirety) involves moving a flux quantum in all possible transitions of write one and write zero operations among three superconducting loops in a memory device containing five or more superconducting loops, dedicated to write and read the state of the memory device. In some of the exemplaryembodiments (e.g., 100 of FIG. 1 A and 180 of FIG. IB), the FROM state, in contrast to JSRAM, is written into one loop exclusively, and the written state resides in that loop during standby. Distinct from JSRAM, the JROM programming path in the memory device (e.g., Josephson junction based memory device 100 in FIG. 1 A) according to some embodiments of the present inventive concept sets, or does not set, a flux quantum in a single superconducting loop 102c (e.g., state loop 110) in order to program a state of the memory device. Moreover, the JROM programming path may include non-superconducting circuits, which can inject a flux quantum into a state loop (e g., state loop 110) and can direct a write operation to a particular memory device. The non-superconducting circuits can enable, for example, a current switch, which may be integrated with a transformer, as will be described herein below with respect to FIG. 6. Specific read operations and required pass-through action of the memory device will be described in further detail subsequently.

[0087] One operating principle for the read path involves the addition of currents in the Josephson junctions (e.g., Josephson junctions 104c and 104d). Such an operation may involve moving an SFQ one superconducting loop stage to the left if a positive signal current adds constructively to the stored SFQ, which is a persistent current in the superconducting loop. Alternatively, the SFQ will move one superconducting loop stage to the right if a negative signal current adds to a negative current in the stored SFQ.

[0088] Note that strobe (S) signals will pass through to an output (Q) of the Josephson junction based memory device 100 irrespective of the state of the memory device, if the state of the device is not being read out (see, e.g., FIGS. 2A and 2B) via the word read control line 164 of FIGS. 1A and IB. The SFQ pulses, used to read the memory devices 100 and 180 of FIGS. 1A and IB, respectively, are indicated on FIGS. 3A and 3B as “-WR” and “+WR.”

[0089] As previously stated, the Josephson junction based memory device 100 includes write signal(s) 138 that may be used, for example, to set the state of the memory device 100 (e.g., injecting single flux quantum into the state loop 110 in the memory device 100).

[0090] In such a manner, the plurality of superconducting loops 102 may be configured to provide information indicative of a presence of the magnetic flux quanta in one or more of the superconducting loops in response to a combination of control signals and SFQ pulses. A state of the memory device 100 may be represented by the SFQ 140a stored in the leftmostsuperconducting loop 102c (i.e., the state loop 110) of the memory device 100. With regard to the state loop 110, the presence of an SFQ 140a in the superconducting loop 102c may be representative of a zero-state of the memory device 100, and the absence of an SFQ 140a in the superconducting loop 102c may be representative of a one-state of the memory device 100.

[0091] For a write operation according to one or more embodiments, to set the Josephson junction based memory device 100 to a zero-state, a single flux quantum may be injected into the state loop 110; to set the memory device 100 to a one-state, a single flux quantum is not injected into the state loop 110. In accordance with aspects of the inventive concept, the state of the memory device 100 may be changed (i.e., programmed) using non-superconducting circuitry. For a read operation, the SFQ 140b in the superconducting loop 102e enables the read operation, and so the superconducting loop 102e is first initialized with an SFQ pulse before a read operation is performed. The superconducting loops 102d and 102e are used to perform the read operation and may therefore be referred to as readout loops 120, as previously described.

[0092] FIG. 2A illustrates a pass-through path sequence 200 of the one-state (i.e., logic “1” or a strobe) through a memory device storing a one-state utilizing the Josephson junction based memory device 100 of FIG. 1A (or Josephson junction based memory device 180 of FIG. IB), in accordance with example embodiments. Referring to FIGS. 1 A and 2A, the pass-through path sequence 200 shows an example input SFQ pulse sequence configured to move positive and negative SFQ pulses (+Q and -Q, respectively), which represent a prior one-state read from an upstream memory device (e.g., 100), or a strobe signal (if an upstream memory device in an array of memory devices has yet to be accessed), through the Josephson junction based memory device 100.

[0093] It will be understood that the principle of shifting magnetic flux quanta by using SFQ pulses via control lines of superconducting and non-superconducting circuits can be applied more generally to shift magnetic flux between any of the adjacent superconducting loops 102.

[0094] FIG. 2B illustrates a pass-through path sequence 220 through a memory device storing a zero-state utilizing the Josephson junction based memory device 100 of FIG. 1A (or the Josephson junction based memory device 180 of FIG. IB), in accordance with example embodiments. Referring to FIGS. 1A and 2B, pass-through path sequence 220 shows an input SFQ pulse sequence that may be employed to move positive and negative SFQ pulses (+Q and -Q, respectively) through the memory device 100. In this illustrative case, the memory device 100 is initially in a zero- state, as evidenced by the SFQ 140a in the superconducting loop 102c (i.e., state loop 110). Again, the superconducting loop 102e is initialized with an SFQ 140b to enable the read operation. A positive SFQ pulse applied as a positive strobe signal (+S) will move the SFQ from the superconducting loop 102e to the adjacent superconducting loop 102d and will generate a positive SFQ pulse (+Q) as an output of the Josephson junction based memory device 100. When a negative SFQ pulse is applied as a negative strobe signal (-S), the SFQ will move from the superconducting loop 102d to the adjacent superconducting loop 102e and a negative SFQ pulse (-Q) will be generated as an output of the memory device 100.

[0095] A detailed description of the read path for the memory device 100 of FIG. 1 A (or 180 of FIG. IB, henceforward implied by reference to 100) is shown in FIGS. 3A and 3B, according to one or more example embodiments. In one or more embodiments, the design requires two clock cycles to complete a read operation.

[0096] Referring to FIGS. 1A, 3A and 3B, in an example embodiment, the Josephson junction based memory device 100 may provide and receive read control signals by way of a plurality of address lines to at least a portion of the plurality of superconducting loops 102. In an example embodiment, the read control signals may include word read WR, strobe S, and output Q signals. An illustrative read path sequence of control signals is provided subsequently.

[0097] FIG. 3A illustrates a read path sequence 300 for reading a one-state utilizing the Josephson junction based memory device 100 of FIG. 1A, in accordance with example embodiments. The read path sequence 300 provides an illustrative Josephson junction switching sequence when reading a one-state. As with the pass-through path sequence previously described (e.g., 200 shown in FIG. 2A or 220 shown in FIG. 2B), a read operating principle may involve the addition of currents in the Josephson junctions (e.g., Josephson junctions 104c and 104d): the SFQ will move one superconducting loop to the left (e.g., to superconducting loop 102d) if a positive signal current (+S) adds constructively to the stored SFQ, which is a persistent current in the superconducting loop (e.g., loop 102e in FIG. 1A); the SFQ will move one superconducting loop to the right (e.g., superconducting loop 102e in FIG. 1A) if a negative signal current (-S) adds to a negative signal current in the stored SFQ. The Q output is generated only if the S junction switches and moves the stored pulse between superconducting loops.Control signals for the read operation are word read (WR), strobe (S), and output (Q), with positive or negative polarity indicated by (+) or (-), respectively. Note, that word read WR events must enclose strobe S events for this embodiment. For some other embodiments, this restriction is removed. Thus, for AC-powered Josephson junctions where positive and negative pulses occur in opposite halves of a clock cycle, this means that the pair of strobe S events can complete within a clock cycle, but that a pair of word read WR events may require two clock cycles.

[0098] FIG. 3B illustrates a read path sequence 320 for reading a zero-state utilizing the Josephson junction based memory device 100 of FIG. 1A, in accordance with example embodiments. Read path sequence 320 provides the Josephson junction switching sequence when reading a zero-state. A “null” signal (i.e., nothing or no action) is passed to the output Q whenever a positive or negative strobe signal (+S or -S) is applied, since the common Josephson junction 104d shared by the two readout loops 102d and 102e has no current passing through it due to the superposition of adjacent flux quanta in superconducting loops 102d, 102e enclosing the Josephson junction 104d.

[0099] FIG. 4A is a schematic diagram depicting an illustrative memory circuit 400 which may be configured for implementing the Josephson junction based memory device 100 of FIG. 1A, in accordance with example embodiments. The memory circuit 400 includes standard JTL stages along address lines. Current sources 406 and 408 (shown with arrows) may represent AC bias, which allows both positive and negative SFQ pulses to propagate at different times in the clock cycle. In the illustrative memory circuit 400, resistors 410 and 412 couple the superconducting inputs (e.g., word read WR and strobe S inputs) to corresponding internal nodes N1 and N2, respectively, of the Josephson junction based memory device 100. Each junction-resistor pair is considered a decision-making element; if the signal current adds with the same polarity to the current of the stored SFQ in a superconducting loop as seen by the junction (e.g., 104c or 104d shown in FIG. 1A), the signal will trigger the junction to produce an SFQ pulse and move the stored SFQ pulse to an adjacent superconducting loop. Otherwise, the signal voltage will be lost (i.e., dissipated) across the resistor 410, 412. Note, that similar behavior could be achieved by replacing any or all of these coupling resistors with additional Josephson junctions.Transformers (e.g., 404 and 405 shown in FIG. 4A with dots) represent SFQ sources to initialize a “read” flux quantum (e.g., SFQ 140b in superconducting loop 102e shown in FIG. 1A) or toinitialize state (or potentially write new states — only with transformer 404 — as will be described with respect to FIG. 6). Given the presence of a flux quantum (e.g., SFQ 140a in superconducting loop 102c of FIG. 1A), the initial state shown in FIG. 4A corresponds to the zero-state, but other initial states could be used. The current sources 406, 408 represent the AC bias supplied by the on-chip global resonant clock network (e.g., 170 in FIG. 1A). Phasing of the read bias sources may be configured to be consistent with a desired SFQ pulse timing.[00100J FIG. 4B is a schematic diagram depicting an illustrative memory circuit 450 which may be configured for implementing the Josephson junction based memory device 100 of FIG. 1A, according to one or more embodiments. The memory circuit 450 may be consistent with the memory circuit 400 shown in FIG. 4A, except for the disablement or omission (i.e., removal) of the transformer 404 shown in FIG. 4A and its associated SFQ, which enables the illustrative memory circuit 450 to be suitable for use, for example, in mask-programmable memory devices (e.g., mask-programmable logic arrays and mask-programmable read only memories), as a memory device which holds a one-state, in accordance with example embodiments. Given the absence of a flux quantum (e.g., no SFQ in superconducting loop 102c of FIG. 1A), the state shown in the memory circuit 450 of FIG. 4B corresponds to the one-state, the read operation of which is exhibited in FIG. 3A.

[0101] A mask-programmable memory device according to one or more embodiments of the inventive concept includes first and second superconducting memory devices. The first superconducting memory device comprises: at least two superconducting loops electrically coupled to one another, one of the at least two superconducting loops is configured as a first readout loop and another of the at least two superconducting loops is configured as a first state loop; at least two superconducting inputs configured to convey corresponding superconducting input signals provided to the superconducting memory device for reading a state of the first superconducting memory device; a superconducting output configured to convey an output of the first superconducting memory device; at least first and second Josephson junctions, the first state loop including the first Josephson junction and the first readout loop including the second Josephson junction; and a transformer connected in the first state loop and configured to inject a flux quantum into the first state loop. The second superconducting memory device comprises: at least two superconducting loops electrically coupled to one another, one of the at least two superconducting loops is configured as a second readout loop and another of the at least twosuperconducting loops is configured as a second state loop; at least two superconducting inputs configured to convey corresponding superconducting input signals provided to the second superconducting memory device for reading the state of the second superconducting memory device; a superconducting output configured to convey an output of the second superconducting memory device; and at least third and fourth Josephson junctions, the second state loop including the third Josephson junction and the second readout loop including the fourth Josephson junction. States of the first and second superconducting memory devices may be determined based on the presence or absence of single flux quantum in the first and second state loops, respectively, or a direction of rotation of the single flux quantum in the first and second state loops, respectively.

[0102] For the mask-programmable memory device, the superconducting memory device 400 of FIG. 4A is suitable for use as a memory device which holds a zero-state, and the superconducting memory device 450 of FIG. 4B is suitable for use as a memory device which holds a one-state, in accordance with example embodiments. Both superconducting memory devices correspond to the memory device 100 of FIG. 1A, only with non-superconducting input(s) 160, non-superconducting write circuit 184, write line, and write signals 138 omitted (i.e., removed). The pass-through and read sequences for the memory device 100 of FIG. 1A described with respect to FIGS. 2 A through 3B thus apply to the mask programmable memory device.

[0103] FIG. 4C is a schematic diagram depicting an illustrative memory circuit 480 which may be used to implement the alternative Josephson junction based memory device 180 of FIG. IB, in accordance with example embodiments. Referring to FIGS. IB and 4C, the circuit 480 includes standard JTL stages along the address lines. The current sources 406, 408 (shown with arrows) represent AC bias, which allows both positive and negative SFQ pulses to propagate at different times in the clock cycle. As described in connection with FIG. 4A, resistors 410, 412 may be used to couple the superconducting inputs (e.g., WR, S) to the internal nodes of the memory device 180. Each junction-resistor pair is a decision-making element; if the signal current adds with the same polarity to the current associated with the SFQ stored in a superconducting loop 102 as seen by the junction, the signal current will trigger the junction to produce an SFQ pulse and move the stored pulse to an adjacent superconducting loop 102.Otherwise, the signal voltage will be lost across the resistor. Note, that similar behavior could beachieved by replacing any or all of the coupling resistors with additional Josephson junctions. The pulsed voltage source (with a dot) represents an SFQ source configured to establish an SFQ necessary for the read-out operation. The current sources shown in the circuit 480 represent the AC bias supplied by the on-chip global resonant clock network 170. Phasing of the read bias sources is configured to be consistent with a desired SFQ pulse timing.

[0104] In FIG. 4C, the state of the memory device 180, as shown, corresponds to the zero-state because of the presence of an SFQ in the leftmost superconducting loop (102c in FIG. IB). The absence of an SFQ in the leftmost superconducting loop represents a one-state. During a write operation, the non-superconducting write circuit 184 is configured to set the state of the memory circuit 480 to the zero-state from a one-state (no flux quantum) by injecting a counterclockwise flux quantum into the left most superconducting loop (102c in FIG. IB).

[0105] In use, setting an initial state of the memory device does not require the use of pulsed voltage sources. For example, some embodiments may use magnetic coupling provided by way of a control line to initialize the state of the memory device. Various non-limiting methods for setting the initial state of the memory device are shown in connection with FIGS. 5, 6, and 7, according to embodiments of the present invention, which may help to decrease the physical size of the control line and increase the accuracy of the initial state.

[0106] By way of example only and without limitation, FIG. 5 illustrates a flux initialization process 500, in accordance with example embodiments. In this example embodiment, both SFQs may be initialized into the rightmost superconducting loop (e g., 102e in FIG. 1 A) of the unit memory device 100 (see FIG. 1A) so that there is only a single transformer. A reduction in the number of transformers is desirable due to the significant area consumed by a transformer. The current (I) required in a primary wire or loop (or simply “primary”) 502 of the transformer 504 depends on the desired flux () and a mutual inductance (M) in a secondary wire or loop (or simply “secondary”) 506 of the transformer 504, which may be expressed according to the following equation: / = 2 / M [1]In equation [1] above, flux quantum () is expressed in units of milliamperes (mA)-picohenries (pH), mutual inductance (M) is expressed in units of pH, and current (I) is given in units of mA.

[0107] FIG. 6 illustrates a flux initialization process 600, in accordance with example embodiments. As an alternative to the flux initialization process 500 shown in FIG.5, the flux may be initialized in a two-step flux initialization process 600. In a first step 604, depending on a desired datum state, a current of a prescribed polarity, or no current at all (i.e., zero-current), can be selectively applied by enabling or disabling a non-superconducting circuit 602 (represented in FIG. 6 by an n-channel field-effect transistor (NFET)) in the primary loop of a transformer during a cooldown process before the secondary loop of the transformer has reached a superconducting critical temperature. During such a scenario, the secondary loop finds the lowest-energy state where the stored flux is ideally zero, but with magnitude not to exceed half an SFQ. In a second step 606 of the flux initialization process 600, once the secondary loop has reached a superconducting critical temperature, the control current is turned off (e.g., using the non-superconducting circuit 602) and an exact integer number N of SFQ becomes set up in the secondary loop of the transformer (e.g., state loop 110 of FIG. 1A), or none at all (zero SFQ). The number of SFQs is determined by the initial current (I) in the primary of the transformer, which may be expressed according to the following equation:I = / M N<t>0 / M [2]In the equation [2] above, N is an integer representing the number of SFQ set up in the secondary loop of the transformer, <bo represents a flux quantum, M represents mutual inductance between primary and secondary loops of the transformer, and represent desired flux. The large arrow in FIG. 6 indicates a transition from a non-superconducting state to a superconducting state.

[0108] Stated another way, the Josephson junction based memory device 100 in FIG. 1A may include at least one magnetically coupled control line (e.g., write line 138). In such scenarios, the plurality of superconducting loops 102 are configured to provide an initial flux state in response to a two-step flux initialization process. In one or more embodiments, the two-step flux initialization process includes: 1) while cooling down the Josephson junction based memory device, providing an initialization signal via the at least one magnetically coupled control line; and 2) upon reaching a superconducting critical temperature of the Josephson junction based memory device, turning off the initialization signal such that an exact integral number of SFQ is stored in one or more of the superconducting loops.

[0109] For the memory device 100 shown in FIG. 1 A, the following two flux quanta initializations should be considered. A first initialization involves storing of SFQ 140b in superconducting loop 102e to enable the readout operation. A second initialization depends on the state stored in the memory device 100. A zero-state can be “set” into the memory device 100 by storing SFQ 140a in superconducting loop 102c. A one-state can be set by introducing no flux; in other words, a one-state is represented by the absence of SFQ 140a in the superconducting loop 102c. In FIG. 6, the setting of the state of the memory device 100 (and the addressing of a particular memory device) can be handled (i.e., controlled) by the inclusion of the non-superconducting circuit 602, which may be represented by an NFET device, although embodiments are not limited thereto.

[0110] FIG. 7 illustrates an example scenario 700 in which multiple memory devices (e.g., respective memory devices associated with inductor 702 and inductor 704) share the same flux source (e.g., flux source 706), in accordance with example embodiments. In some embodiments, the mutual inductance L' shared by the superconducting loops in the respective memory devices is much less than the total inductance L of each superconducting loop. In such scenarios, a low mutual inductance L' achieves good isolation by approximating a low-impedance source.

[0111] FIG. 8A is a schematic diagram illustrating an array of unit memory devices (e.g., Josephson junction based memory device 100 shown in FIG. 1A being representative of a unit memory device) arranged in a word-organized memory fabric 800, in accordance with example embodiments. Because the read address and data lines use JTLs, the memory fabric is wave- pipelined, and multiple operations can be in flight at once. As illustrated in FIG. 8A, the unit memory devices may be arrayed to produce a word-organized memory fabric. In some embodiments, the address lines may use JTLs that fan out the signals to all memory devices in a vine configuration. It is to be understood that other arrangements of memory device are contemplated for forming the memory fabric 800.

[0112] Stated another way, the series arrangement (e.g., Josephson junction based memory device 100 or 180 in FIGS. 1A or IB) could be considered a unit device. An array of coupled unit devices could form a memory fabric, which can be wave-pipelined. In such scenarios, multiple read operations can be carried out simultaneously across the memory fabric. In variousembodiments, the unit devices of the memory fabric 800 may be coupled to a global resonant clock network (e.g., global resonant clock network 170 shown in FIG. IB).

[0113] A write operation of the word-organized memory fabric 800 according to one or more embodiments may involve non-superconducting circuits which are a part of each memory device, as well as their associated address and data inputs (word write 0, abbreviated WW0; word write 1, abbreviated WW1; bit write 0, abbreviated BW0; and bit write 1, abbreviated BW1), which receive at least one non-superconducting signal. Other signals associated with the write operation of memory fabric 800 have been omitted both for generality and simplicity.

[0114] FIG. 8B is a schematic diagram illustrating a mask-programmed memory device of unit cells (being superconducting memory devices) arranged in a word-organized memory fabric 850, in accordance with example embodiments. Memory devices can be set to a “O”-state (i.e., logic “0”) or a “l”-state (i.e., logic “1”) during cooldown, for example, by storing a flux quantum or no flux quantum (e.g., via circuits 400 and 450 shown in FIGS. 4A and 4B, respectively) in the state loop, respectively.

[0115] Because the read address and data lines use JTLs (data lines starting on “S” and ending on “QI” or “Q2”), the memory fabric 850 may be configured as wave-pipelined for read operations only, and thus multiple read operations can be in flight at once. As illustrated in FIG. 8B, the unit cells may be arrayed to produce the word-organized memory fabric 850. In one or more embodiments, the address lines use JTLs that fan-out the signals to all cells in a vine-type configuration.

[0116] Stated another way, the series arrangement (e.g., Josephson junction based memory device 400 or 450) could be considered a unit cell. An array of coupled unit cells may be configured to form a memory fabric, which can be wave-pipelined. In such scenarios, multiple read operations can be carried out simultaneously across the memory fabric. In various embodiments, the unit cells of the memory fabric 850 in FIG. 8B may be coupled to a global resonant clock network (e.g., global resonant clock network 170 shown in FIGS. 1 A and IB).

[0117] As may be apparent to those skilled in the art, wave-pipelining can be employed through an array of single flux quantum memory cells. This means that the phasing of the AC bias sources can advance with signal latency. In this way, multiple operations may be in flight simultaneously, achieving throughput at the native clock frequency of the logic.

[0118] As described elsewhere herein, the design generalizes to multiple read ports. Any number of read ports can be incorporated into a single design by extension of this methodology, as will become apparent to those skilled in the art given the teachings herein. FIG. 9 illustrates a partitioned unit cell 900 (superconducting memory device) with a separate read path, in accordance with example embodiments.Example Alternative Josephson Junction Based Memory Devices

[0119] By way of example only and without limitation, FIGS. 10A and 10B illustrate a schematic diagrams of alternative Josephson junction based memory devices 1000 and 1050, respectively, in accordance with one or more embodiments. Each of the Josephson junction based memory devices 1000 and 1050 may include at least four superconducting loops, one of which is a state loop 110 (A shared loop 130 is notably part of the readout stages 1002). The alternative memory devices 1000 and 1050 may include one or more non-superconducting inputs 160 configured to convey one or more corresponding non-superconducting signals provided to the memory device 1900, a plurality of superconducting inputs (e.g., word read control line 164 (WR) and strobe control line 166 (S) configured to convey corresponding superconducting input signals provided to the memory device 1900, a superconducting output (e.g., superconducting output (Q)), a non-superconducting circuit 184, a state loop 110, an second superconducting loop , and a superconducting readout stages 1002, comprised of at least two superconducting loops, one of which is a shared loop. The readout stages 1002 may be coupled to a Josephson junction 1004 of the state loop 110. In such examples, the readout stages 1002 may be configured to detect whether or not an SFQ is stored in the state loop 110. In the alternative memory devices 1000 and 1050, the readout stages 1002 is connected to the junction of the state loop 110 and may be configured to detect whether the stored pulse is in the loop during read operations. One potential advantage of the designs of the alternative memory devices 1000 and 1050 is that they support single-cycle reads, as illustrated and described in conjunction with FIGS. HA and 11B.

[0120] As described with respect to memory devices 100 of FIG. 1A and 180 of FIG. IB, the difference between memory devices 1000 and 1050 involve how the write signal WS of each, conveyed by the write line of each, is provided to state loop 110 of each memory device 1000,1050. Indicated by the inclusion of the non-superconducting write circuit 184 and / or theadditional Josephson junction 182, one of two alternative write circuit(s) and associated write method(s) are enabled and indicated consistently from FIG. 10B through FIG. 18. The alternative write circuit involves the inclusion of a transformer 1006 in state loop 110, as described with respect to FIGS. 1A, 4A, and 6. To reduce what would be almost duplication of the read circuit description, the circuit(s) and method(s) of that alternative, memory device 1000 of FIG. 10A, will not be discussed further. With respect to the read operation, however, the single flux quanta / quantum behaviors may be the same, regardless of the particular choice of the already embodied write circuit(s) and method(s).

[0121] It is notable that at least one distinction between FIGS. 1A and IB arises between their associated write circuit(s) and write method(s). With respect to the read operation, however, their single flux quanta / quantum behaviors may be identical, and thus the illustrative read method of FIGS. 2A, 2B, 3 A and 3B, already depicted with reference to the superconducting loops of FIG. 1 A, also apply to the superconducting loops of FIG. IB (with the understanding that the described example read methods may be similarly applied to the memory device 180 shown in FIG. IB). Likewise, the state loop 110 topology can be altered with respect to FIGS. 10A through 18. The overall loop topologies of FIGS. 10B through 18 are similar to FIG. IB in that they both include an identical state loop 110 and a shared loop 130. Still, with this understanding, a modification of the state loop 110 to omit Josephson junction 182 and to include a transformer 1006 within FIGS. 10A through 18 (except FIG. 10B) provides accurate exemplary embodiments for circuits and sequences, which are similar to FIG. 1 A, without what would be almost duplication of schematics and sequences.

[0122] It is important to note that the memory device 1050 of FIG. 10B is shown storing a flux quantum, which represents a zero-state. Likewise, each of the memory device 1200 of FIG 12A, the memory device 1220 of FIG 12B, the memory device 1230 of FIG 12C, the memory device 1800 of FIG 16, the memory device 1700 of FIG 17, and the memory device 1800 of FIG 18 is shown storing a flux quantum in its state loop, which, in each device, represents a zero-state. It is to be appreciated that the definition of a zero-state indicating the storage of a flux quantum or a one-state as indicating the absence of a flux quantum may be arbitrarily assigned; that is, the presence of a flux quantum may represent a one-state and the absence of a stored flux quantum may represent a zero-state in some embodiments.

[0123] FIG. 11 A illustrates an example read path sequence 1100 for reading a one-state utilizing the alternative Josephson junction based memory device 1000 of FIG. 10, in accordance with example embodiments. An applied strobe S input produces the Q output of the same polarity (e.g., a +S input produces a +Q output, and a -S input produces a -Q output). The pair of word read WR events and the pair of strobe S events can all complete within a clock cycle, in contrast to the design of the memory device 100 shown in FIG. 1A.[00124J FIG. 1 IB illustrates an example read path sequence 1120 for reading a zero-state utilizing the alternative Josephson junction based memory device 1000 of FIG. 10, in accordance with example embodiments. Given that a flux quantum is in the state loop (110 in FIG. 10), no flux quantum (i.e., null) is transferred to the Q output, regardless of the polarity of the strobe S input.

[0125] Three functionally equivalent read paths conforming to the second design (e.g., alternative memory device 1000 of FIG. 10) are shown in FIGS. 12A, 12B, and 12C. It will be understood that while three alternative read path variations are described, other alternatives are possible and similarly contemplated, in accordance with embodiments of the inventive concept.

[0126] FIG. 12A illustrates a first read path variation 1200 utilizing the alternative Josephson junction based memory device 1000 of FIG. 10, in accordance with example embodiments. Relative inductance (L) of each of the different superconducting loops is shown. Approximate inductor values are shown for illustration, neglecting second-order effects such as JJ inductance and leakage between superconducting loops, although embodiments are not limited thereto.

[0127] FIG. 12B illustrates a second read path variation 1220 utilizing the alternative Josephson junction based memory device 1000 of FIG. 10, in accordance with example embodiments. Relative inductance (L) of each of the different superconducting loops is shown. Approximate inductor values are shown for illustration, neglecting second-order effects such as JJ inductance and leakage between superconducting loops, although embodiments are not limited thereto.

[0128] FIG. 12C illustrates a third read path variation 1230 utilizing the alternative Josephson junction based memory device 1000 of FIG. 10, in accordance with example embodiments. Relative inductance (L) of the different loops is shown. Approximate inductor values are shown for illustration, neglecting second-order effects such as JJ inductance and leakage betweensuperconducting loops. Illustrative read path sequences for the first, second, and third read path variations 1200, 1220, 1230 are provided in FIGS. 13A, 13B, 14A, 14B, 15A, and 16, according to embodiments of the inventive concept.

[0129] FIGS. 12A, 12B, and 12C each are shown with a flux quantum in the state loop 110, which in this illustrative embodiment corresponds to the zero-state.

[0130] FIG. 13 A illustrates a first read path sequence 1300 for reading a one-state utilizing the first read path variation 1200 of the alternative Josephson junction based memory device 1000 of FIG. 12A, in accordance with example embodiments. In the first read path sequence 1300, when reading a one, the leftmost ‘2L” loop prevents the +WR signal from migrating the output SFQ into the state loop (110 in FIG. 12A).

[0131] FIG. 13B illustrates a second read path sequence 1320 for reading a zero-state utilizing the first read path variation 1200 of the alternative Josephson junction based memory device 1000 of FIG. 12A, in accordance with example embodiments. In the second read path sequence 1320, when reading a zero, the -WR signal moves the SFQ from the input stages into the two 2L loops.

[0132] FIG. 14A illustrates a third read path sequence 1400 for reading a one-state utilizing the second read path variation 1220 of the alternative Josephson junction based memory device 1000 of FIG. 12B, in accordance with example embodiments.

[0133] FIG. 14B illustrates a fourth read path sequence 1420 for reading a zero-state utilizing the second read path variation 1220 shown in FIG. 12B of the alternative Josephson junction based memory device 1000 shown in FIG. 10, in accordance with example embodiments. In the fourth read path sequence 1420, when reading a zero, the -WR signal merges both SFQs into the “2 / 3L” loop.

[0134] FIG. 15A illustrates a fifth read path sequence 1500 for reading a one-state utilizing the third read path variation 1230 shown in FIG. 12C of the alternative Josephson junction based memory device 1000 shown in FIG. 10, in accordance with example embodiments.

[0135] FIG. 15B illustrates a sixth read path sequence 1520 for reading a zero-state utilizing the third read path variation 1230 shown in FIG. 12C of the alternative Josephson junction based memory device 1000 shown in FIG. 10, in accordance with example embodiments. In suchscenarios, when reading a zero, the -WR signal reverses the polarity of the half-SFQ in the loop connected to the input stage.

[0136] FIG. 16 illustrates a schematic diagram of a circuit 1600 for implementing the first read path variation 1200 shown in FIG. 12A of the alternative Josephson junction based memory device 1000 of FIG. 10, in accordance with example embodiments. Circuit 1600 is shown storing a flux quantum in its state loop, which corresponds to a zero-state of the Josephson junction memory device.

[0137] FIG. 17 illustrates a schematic diagram of an example circuit 1700 for implementing the second read path variation 1220 shown in FIG. 12B of the alternative Josephson junction based memory device 1000 shown in FIG. 10, in accordance with example embodiments.Circuit 1700 is depicted as storing a flux quantum in its state loop (110 in FIG. 10), which corresponds to a zero-state of the Josephson junction memory device.

[0138] FIG. 18 illustrates a schematic diagram of an example circuit 1800 for implementing the third read path variation 1230 shown in FIG. 12C of the alternative Josephson junction based memory device 1000 shown in FIG. 10, in accordance with example embodiments. The half SFQ (- T>o) in the inductor loop of inductance L is implemented as two inductors in parallel, each of inductance 2L, with a full SFQ applied to one of the two inductors. Circuit 1800 is shown storing a flux quantum in its state loop (110 in FIG. 10), which corresponds to a zero-state of the Josephson junction memory device.

[0139] FIG. 19 illustrates a schematic diagram of a Josephson junction based memory device 1900, in accordance with example embodiments. Referring to FIG. 19, the memory device 1900 includes one or more non-superconducting inputs 160 configured to convey one or more corresponding non-superconducting signals provided to the memory device 1900, a plurality of superconducting inputs (e.g., a word line WL, a sense enable SE, and an input sense line SL IN) configured to convey corresponding superconducting input signals provided to the memory device 1900, a superconducting output (e.g., SL OUT), a superconducting state loop 1940, and a superconducting readout loop 1950. The memory device 1900 may further include a non- superconducting write circuit 184, which may be similar to the non-superconducting write circuit 184 shown in FIGS. 1A and IB, except that it is configured to reverse a flux quantum 1960 in the state loop 1940, as a means to change the state of the memory device 1900. In this illustrativeembodiment, the non-superconducting write circuit 184 is connected to the state loop 1940, which is coupled to the readout loop 1950.

[0140] Some conventional memory devices (cells), each with one state loop that stores a clockwise or counterclockwise flux quantum, which represents the state of the memory device, are described in a paper entitled, “Very Large Scale Integration of Josephson-Junction-Based Superconductor Random Access Memories,” by Vasili Semenov et. al., IEEE Transactions on Applied Superconductivity, 29(5), pages 1-9, March 14, 2019 (“Semenov”), and in a paper entitled, “Superconductor Bistable Vortex Memory for Data Storage and Readout,” by M. Karamuftuoglu et al., Superconductor Science and Technology, 31(1), December 19, 2024 (“Karamuftuoglu”), the disclosures of which are incorporated by reference herein in their entirety. The storage loop for both devices are similar in their principals of operation to the embodiment of the present disclosure, which, in its illustrative form, more closely resembles Karamuftuoglu. Writing an opposite state into any of the memory devices involves reversing the direction of current flow in its state loop (reversing the direction of rotation of the single flux quantum).

[0141] In contrast to the JSRAM described in Luo and to one or more embodiments of the present disclosure, the memory device 1900 does not include a shared loop (e.g., shared loop 130 in FIGS. 1A and IB) and can therefore be implemented with as few as two superconducting loops.

[0142] The state loop 1940 in the memory device 1900 may include a first inductor 1908, a first Josephson junction 1906 which may be shunted, a second inductor 1910, a second Josephson junction 1912, a third inductor 1914, which may be a shared loop inductor, and a fourth inductor 1916. The readout loop 1950 may include the shared loop inductor 1914, a fifth inductor 1918, a third Josephson junction 1922, a sixth inductor 1930 which is shunted by a first resistor 1929, also a circuit element of the readout loop 1950, a fourth Josephson junction 1924, and a seventh inductor 1920. The shared loop inductor 1914 is the element through which the state loop 1940 sources its state to the readout loop 1950 (e.g., during a read operation of the memory device 1900).

[0143] The memory device 1900 may further include a second resistor 1902 and an eighth inductor 1904 connected in series, which couple the superconducting word line (WL) input to thestate loop 1940, a third resistor 1926 and a ninth inductor 1928 connected in series, which couple the superconducting sense enable (SE) input to the readout loop 1950, and a tenth inductor 1932 and a fourth resistor 1934 connected in series, which couple an internal state of the memory device 1900 to the “sense line” (defined with a direction for simplicity of explanation by superconducting sense line input SL_IN, eleventh inductor 1936, and superconducting sense line output SL OUT). For consistency with Karamuftuoglu, the superconducting inputs and output of the memory device 1900 appear herein as they do in Karamuftuoglu.

[0144] With reference to the descriptions of FIGS. 4A, 4B, 8 and 19, it can be understood that memory device 1900 of FIG. 19, without the non-superconducting write circuit and write line, can implement a mask programmable memory device if inductor in the state loop 1940 (e g., 1910) is replaced by a transformer that, for example, injects either a clockwise or counterclockwise current (defining the flux quantum rotation) in the state loop 1940, during the cool down process.

[0145] By way of example only and without limitation, an example write operation using the illustrative Josephson junction based memory device 1900 of FIG. 19 will now be described, in accordance with example embodiments. FIG. 20A depicts an illustrative write sequence 2000 for writing (i.e., programming) a one-state (“write 1”) to the memory device 1900 of FIG. 19. For the write sequence 2000, the memory device 1900 is assumed to initially be in a zero-state; that is, having a stored flux quantum 1960 (depicted in FIG. 19) present in the superconducting state loop 1940 with a counterclockwise rotation. FIG. 20B depicts an illustrative write sequence 2050 for writing (i.e., programming) a zero-state (“write 0”) to the memory device 1900 of FIG. 19. For the write sequence 2050, the memory device 1900 is assumed to initially be in a one- state; that is, having a stored flux quantum present in the superconducting state loop 1940 with a clockwise rotation.

[0146] Referring to FIGS. 19, 20A and 20B, a positive or negative write signal (+WS or -WS), provided through the write line of the memory device 1900, will inject a corresponding current into the state loop 1940 which, when such current exceeds a critical current of the Josephson junction 1906 in combination with the stored flux quantum (e.g., SFQ 1960 in the superconducting state loop 1940), will effectively reverse the magnetic flux quantum 1960 in thestate loop 1940. It is to be appreciated that the write signals +WS and -WS, appearing in FIGS. 20A and 20B, respectively, may be generated by the non-superconducting write circuit 184.

[0147] Assuming the stored flux quantum (e.g., SFQ 1960) is initially in a counterclockwise rotation as shown in FIG. 20A, an applied positive write signal (+WS) will reverse its rotation, making the stored flux quantum rotate clockwise in the state loop 1940. This write sequence 2000 may be used to change the state of the memory device 1900 from a zero-state to a one- state, as shown in FIG. 20A. Likewise, assuming the stored flux quantum (e.g., SFQ 1960) is initially in a clockwise rotation as shown in FIG. 20B, an applied negative write signal (-WS) will reverse its rotation, making the stored flux quantum rotate counterclockwise in the state loop 1940. This write sequence 2050 may be used to change the state of the memory device 1900 from a one-state to a zero-state, as shown in FIG. 20B. Additional reflected current will dissipate in the resistance of the non-superconducting write circuit 184 and write line.

[0148] FIG. 21 illustrates a sequence for writing a zero-state, reading a zero-state, writing a one-state, and reading a one-state, in which all operations are directed to the illustrative Josephson junction based memory device 1900 of FIG. 19, in accordance with example embodiments. With reference to FIGS. 19 and 21, the write operations, write O and write l are indicated at intervals across each graphical strip (i.e., waveform) as a function of time so that the state, one or zero, of the memory device 1900 is known for each of the read operations, read O and read l , respectively. The vertical axis labeling of each strip reflects the positive and negative current magnitudes (e.g., in milliamps) of IWL, ISE, and ISL, where IWL is the current input through the word line input (WL) to the memory device 1900, ISE is the current input through the sense enable input (SE) to the memory device 1900, and ISL is the current output through the sense line output (SL_OUT) by the memory device 1900.

[0149] By triggering Josephson junction 1922 or 1924 of the readout loop 1950, the stored datum in the state loop 1940 can be read without disturbing the state of the state loop 1940. This is done by sourcing positive current ISE and IWL through the superconducting inputs SE and WL, respectively. The read current, which reflects the state of the memory device 1900, flows out through resistor 1934 to the sense line (SL) along portions of the sense line SL devoted to each memory device 1900. The portion of the sense line SL allotted to the memory device includes the input sense line SL In, an eleventh inductor 1936, and the output sense line SL Out.When a zero is read (i.e., read O), ISL is zero (or in real simulation, close to zero). When a one is read (i.e., read l), the sense line current ISL rises rapidly, plateaus, and later descends. Thus, the current ISL through the sense line SL during the period of the read operation will reflect the state of the memory device 1900.

[0150] It is important to note that during a write operation of memory device 1900, write line WL is not active (i.e., IWL will be at substantially “0” current) in this embodiment. By contrast, the write line WL pulses positive to write a one and negative to write a zero in the memory device of Karamuftuoglu (all in conjunction with BL). (See FIG. 5 of Karamuftuoglu.) In the present disclosure, the positive activation of the write line WL (e.g., IWL equal to 0.1) is constrained to the read operation for memory device 1900 where it can serve to assist in the selection of a memory device within an array. In general, the positive activation of the write line WL assists in the selection of memory device 1900 for a read operation.

[0151] For the memory device 1900, the non-superconducting write circuit 184 may be configured to oversee the write operation of the memory device 1900 exclusively as explained with respect to FIGS. 20A, 20B, and 21. Made clear in the discussion of the memory device 1900, this exclusive oversight of the non-superconducting write circuit 184 holds true for many embodiments of the present disclosure. In one or more embodiments, the non-superconducting write circuit 184 connects to the write line, which conveys a write signal (WS) to one state loop (e g., 110) or two state loops (e g., 2210 of FIG. 22). In contrast to some conventional memory arrangements, of the memory device according to the embodiments of the present disclosure does not require any current to be sourced from a superconducting input during a write operation (e.g., as is required by Luo and Karamuftuoglu for their superconducting random access memories (RAMs)).

[0152] FIG. 22 is a schematic diagram depicting an illustrative Josephson junction based memory device 2200, in accordance with example embodiments of the inventive concept. The Josephson junction based memory device 2200 includes one or more non-superconducting inputs 160 configured to convey one or more corresponding non-superconducting signals provided to the memory device 1900, a plurality of superconducting inputs (e.g., word read control line 164 (WR) and strobe control line 166 (S) configured to convey corresponding superconducting input signals provided to the memory device 1900, a superconducting output (e.g., superconductingoutput (Q)), a non-superconducting write circuit 184, and a plurality of superconducting loops (e.g., 102 and 2200), wherein two of the plurality of superconducting loops are state loops (e.g., two state loops 2210). Each of the superconducting loops (e.g., superconducting loop 102c, 102d, 102e, or 2202) includes at least one Josephson junction (e.g., Josephson junction 104c, and / or 104d). Two adjacent superconducting loops 2200 and 102 may share a Josephson junction. In one or more embodiments, for example, adjacent superconducting loops 2202 and 102c may share Josephson junction 2204b, adjacent superconducting loops 102c and 102d may share Josephson junction 104c, and adjacent superconducting loops 102d and 102e may share Josephson junction 104d. In such scenarios, the plurality of superconducting loops 2202 and 102 are electrically coupled to one another.

[0153] The write lines emerging as dashed arrows from the non-superconducting write circuit 184 of FIG. 22 indicate enablement of vertically stacked superconducting devices associated with FIG. 30. These write lines are labeled as WL_2 through WL_N in FIG. 30. FIG. 22 expresses this enablement succinctly as “adaption of this FIG. for embodiments of FIG. 30: “write line(s) to other vertically stacked memory cells” (cells should be devices in FIG. 22).

[0154] The Josephson junction based memory device 2200 may be configured in a manner similar to the memory device 180 shown in FIG. IB, except that it includes an additional superconducting loop, among other differences. Specifically, the memory device 2200 includes a superconducting write circuit 184, which may be similar to the non-superconducting write circuit 184 shown in FIGS. 1A and IB - with respect to many of the embodiments of the present disclosure, the name non-superconducting write circuit 184 is notably used to describe the circuit’s generic function and the non-superconducting circuit elements (e.g. field effect transistors) - except that the non-superconducting write circuit of FIG. 22 is configured to move a flux quantum between two state loops 2210, instead of just one state loop (110 in FIG. 1A), and a plurality of superconducting loops 2202 and 102 (which includes superconducting loops 102c 102d and 102e).

[0155] In Luo, writing the state of the memory device in JSRAM (see, e.g., U.S. Patent Application Publication No. 2024 / 0038298 to Luo et al.) involves moving a flux quantum in all possible transitions of write one and write zero operations among three superconducting loops in a memory device containing five or more superconducting loops, dedicated to write and read thestate of the memory device. In many exemplary embodiments (e.g., 2200) of the present disclosure, the flux quantum, in contrast to JSRAM, moves between no more than two state loops (e.g., 2210). Moreover, the JROM write path of 2200 includes non-superconducting circuits, which can move a flux quantum between two state loops (e.g., two state loops 2010) and can direct a write operation to a particular memory device. The non-superconducting circuits can enable, for example, a current switch for the selective writing of a memory device among a plurality of memory devices and can shape the non-superconducting signal applied to the two state loops 2210, supplied via the write line.

[0156] Unlike the memory device 180 of FIG. IB which includes a single state loop 110, the memory device 2200 shown in FIG. 22 utilizes two state loops for determining a state of the memory device 2200. Specifically, with reference to FIG. 22, the plurality of superconducting loops 2202 and 102 consists essentially of two state loops 2210 and two readout loops 120, in one or more embodiments. As illustrated in FIG. 22, the two state loops 2210 are adjacent to and electrically coupled to the readout loops 120 of a read path. In this configuration, one of the readout loops 120 can be termed a “shared loop” (e.g., shared loop 130). By requiring only two state loops, the configuration of the memory device 2200 according to embodiments of the inventive concept represents significant advantages over memory devices that include more than two state loops, such as, for example, the memory circuit described in Luo, the disclosure of which is incorporate by reference herein in its entirety. Such advantages include but are not limited to a significant reduction in area for a memory implemented with these superconducting memory devices (the write path is implemented with non-superconducting circuits underneath the superconducting circuits) and a reduction of the resonant clock load by a factor of two.

[0157] Stated another way, as illustrated in FIG. 22, the plurality of superconducting loops 2202 and 102 could be electrically coupled in a series arrangement. In some examples, the series arrangement can include four superconducting loops (e.g., superconducting loops 2202 , 102c, 102d, and 102e), of which two are state loops (e.g., two state loops 2210) and two are readout loops (e.g., readout loops 120a and 120b), with one of the readout loops 120 adjacent to the two state loops 2210 being a shared loop (e.g., shared loop 130). In such illustrative embodiments, each superconducting loop of the plurality of superconducting loops 2202 and 102 has one or two adjacent loops; superconducting loop 2202 has one adjacent superconducting loop (102c), superconducting loop 102c has two adjacent superconducting loops (2202 and 102d),superconducting loop 102d has two adjacent superconducting loops (102c and 102e), and superconducting loop 102e has one adjacent superconducting loop (102d). It will be understood that other arrangements of the superconducting loops 2202 and 102 are possible and contemplated in according with embodiments of the present disclosure.

[0158] The Josephson junction based memory device 2200 according to one or more embodiments may also include a plurality of superconducting input(s) for performing a read operation and one or more non-superconducting inputs for performing a write operation, which are associated with superconducting circuits for a read (and state storage) operation and with non-superconducting circuits for a write operation. In FIG. 22, the superconducting write circuit 184 may be coupled to the two state loops 2210. In some embodiments, each control line of the read address (e.g., word read control line 164) and read control lines may include a JTL and a current-bias source. The current-bias source may be configured to provide an AC signal corresponding to a global resonant clock network 170, which may provide a system -wide clock to facilitate operation of the memory device 2200 in a synchronized manner.

[0159] In some embodiments, each read address line of the plurality of read address lines may also include a resistor (not explicitly shown, by implied) connected between the Josephson transmission line and a corresponding superconducting loop of the plurality of superconducting loops 2202 and 102.

[0160] The plurality of superconducting loops 2202 and 102 may be configured to move (e g., shift) magnetic flux quanta (e.g., SFQ 140a or SFQ 140b) in one or more of the superconducting loops in response to, or as a function of, a combination of control signals and single flux quantum (SFQ) pulses. Moving magnetic flux quanta, in one or more embodiments, may comprise storing (injecting), shifting, and reversing (the circulating current of the BVM memory device from clockwise to counterclockwise or vice versa) the magnetic flux quanta.

[0161] In an example embodiment, the control signals may be provided to the superconducting loops 2202 and 102 by way of a word read control line (WR) 164 and / or a strobe control line (S) 166; an output (Q) of the memory device 2200 may be provided off the strobe control line 166. In one or more embodiments, the strobe control line 166 may be implemented as a bit line in the memory device. Furthermore, the plurality of superconducting loops 2202 and 102 may be coupled to the global resonant clock network 170.

[0162] In some embodiments, the plurality of superconducting loops 2202 and 102 are configured to move (i.e., shift) a magnetic flux quanta (e.g., SFQ 140a) from an initial one of the superconducting loops (e.g., superconducting loop 102e) to an adjacent one of the superconducting loops (e.g., superconducting loop 102d) in response to an SFQ pulse provided to the initial superconducting loop (e.g., 102e), such as via the strobe control line 166 and / or word read control line 164. In some embodiments, the SFQ pulse may have an amplitude on the order of about 1 millivolt (mV) and may have a pulse width (i.e., duration) on the order of about 2 picoseconds (ps), although embodiments are not limited thereto.

[0163] Distinct from JSRAM (see, e.g., U.S. Patent Application Publication No. 2024 / 0038298 to Luo et al.) which requires at least five superconducting loops and associated superconducting control circuitry, the programming path for the memory device 2200 of FIG. 22 includes no more than two state loops 2210 and two readout loops 120, for a total of four or less superconducting loops for the one or more embodiments of the invention, and a non- superconducting circuit (e.g., superconducting write circuit 184), which is configured to change the state of the memory device 2200 (i.e., write / program) and to direct a write operation to a particular memory device. This novel memory device architecture according to embodiments of the inventive concept achieves a significant reduction in chip area and complexity, among other benefits, with much of the savings in chip area being realized in peripheral circuits of the memory device, as will be explained in connection with FIG. 27, thereby providing a highly dense memory device not achievable using conventional approaches. Moreover, the load on the global resonant clock network 170 is reduced significantly (e g., almost cut in half) with respect to JSRAM. The write circuit generating a write signal (WS, delivering through a write line to the superconducting circuit) is the superconducting write circuit 184. The WS signal drive changes in stored state within the memory device as will be explained with respect to FIGS. 26A and 26B.

[0164] As an added benefit, the superconducting write circuit 184 in the memory device 2200 of FIG. 22 does not load a resonant cavity, associated with the global resonant clock network 170, whatsoever. In comparison to JSRAM, only half of the current sources (e.g., two) associated with the global resonant clock network 170 appear in memory device 2300 of FIG. 23. Specifically, the superconducting write circuit 184 used in conjunction with the memory device 2200 may be configured to shift (i.e., move) a flux quantum to change the state of thememory device 2200, associated with the two state loops 2210, as will be described in further detail with respect to FIGS. 26A and 26B. Specific read operations and required pass-through action of the memory device will be described in further detail herein below.

[0165] Note that the strobe (S) signal 166 will pass through to the output (Q) irrespective of the state of the memory device, if the state of the device is not being read out (see, e.g., FIGS. 24A and 24B).

[0166] The memory device 2200 is configured to receive one or more non-superconducting input(s) 160 that may be provided to the superconducting write circuit 184. The non- superconducting input(s) 160 may include, for example, W0, Wl, B0, Bl, pNSSO, and pNSSl shown in FIG. 27, which are the param eter(s) shown in FIG. 28.

[0167] The non-superconducting input(s) 160 may be used by the superconducting write circuit 184 to convey appropriate control signals which may be provided to the Josephson junction 2204b that is shared between the adj cent superconducting loops 2202 and 102c forming the two state loops 2210 to change the state of the memory device 2200. The state of the memory device 2200 may be changed, for example, by moving a single flux quantum (e.g., SFQ 140a) between the two state loops 2210 (adjacent superconducting loops 2202 and 102c).

[0168] The plurality of superconducting loops 2202 and 102 may be configured to provide information indicative of a presence of the magnetic flux quanta (e g., SFQ 140a) in one or more of the superconducting loops in response to a combination of control signals and SFQ pulses. In this manner, a state of the memory device 2200 may be represented by the SFQ 140a stored in one of the two state loops 2210 of the memory device 2200. With regard to the two state loops 2210, if there exists an SFQ 140a in the superconducting loop 102c, this may represent a zerostate of the memory device 2200, and the absence of an SFQ 140a in the superconducting loop 102c may represent a one-state.

[0169] FIG. 23 is a schematic diagram depicting an illustrative memory circuit 2300 configured to implement the Josephson junction based memory device 2200 of FIG. 22, in accordance with example embodiments. The memory circuit 2300 includes standard JTL stages along address lines and a superconducting write circuit 184. Current sources (shown with arrows) included in the memory circuit 2300 represent AC bias, which allows both positive and negative SFQ pulses to propagate at different times in a clock cycle. Resistors may be used tocouple inputs (e.g., word read signal WR and strobe signal S) to internal nodes of the memory circuit 2300. Each Josephson junction-resistor pair functions as a decision-making element.

[0170] Referring to FIGS. 22 and 23, if the signal current applied to a given Josephson junction adds with the same polarity to the current of the stored SFQ in a given superconducting loop as seen by the Josephson junction coupled in the given superconducting loop, the signal will trigger the junction to produce an SFQ pulse and move the stored SFQ pulse to an adjacent superconducting loop. Otherwise, if the signal current is opposite in polarity to the stored SFQ in the given superconducting loop, the signal voltage will be lost across the resistor coupled to the corresponding Josephson junction. Note, that similar behavior could be achieved by replacing any or all these coupling resistors with additional Josephson junctions. The initial state shown in FIG. 23 corresponds to a zero-state, but other initial states could be used. The current sources 406 and 408 represent the AC bias, which may be provided by the on-chip global resonant clock network 170 (see FIG. 22). Phasing of the bias sources may be configured to be consistent with a desired SFQ pulse timing.

[0171] As was described in conjunction with the memory device 100 of FIG. 1A, the embodiments of the memory device 2200 and 2300 shown in FIGS. 22 and 23, respectively, may include a readout circuit, for example like the readout circuit 1002 depicted in FIG. 10, so that the memory device 2200 may be configured to perform single cycle operations.

[0172] Similar to the illustrative pass-through path sequence shown in FIG. 2A, FIG. 24A illustrates a first pass-through path sequence 2400 of the one-state (i.e., logic “1” or a strobe), through a memory device storing a one-state utilizing the illustrative Josephson junction based memory device 2200 of FIG. 22, in accordance with example embodiments. Referring to FIGS. 22 and 24A, the pass-through path sequence 2400 shows an example input SFQ pulse sequence configured to move positive and negative SFQ pulses (+Q and -Q, respectively), which represent a prior one-state read from an upstream memory device (e.g., memory device 2200), or a strobe signal (if an upstream memory device in an array of memory devices, has yet to be accessed), through the memory device 2200.

[0173] Similar to FIG. 2B, FIG. 24B illustrates a second pass-through path sequence 2420 of the one-state (i.e., logic “1” or a strobe), through a memory device storing a zero-state utilizing the illustrative Josephson junction based memory device 2200 of FIG. 22, in accordance withexample embodiments. Referring to FIGS. 22 and 24B, the pass-through path sequence 2420 shows an example input SFQ pulse sequence configured to move positive and negative SFQ pulses (+Q and -Q, respectively), which represent a prior zero-state read from an upstream memory device (e.g. 2200), or a strobe signal (if an upstream memory device in an array of memory devices, has yet to be accessed), through the memory device 2200.

[0174] FIGS. 25 A and 25B illustrate a read path sequence for reading a one-state and a zerostate, respectively, utilizing the Josephson junction based memory device of FIG. 22, in accordance with example embodiments. Referring to FIGS. 22, 25A and 25B, in an example embodiment, the memory device 2200 may provide and receive read control signals by way of the plurality of address lines to at least a portion of the plurality of superconducting loops 2202, 102c, 102d, and 102e. In an example embodiment, the read control signals may include word read WR, strobe S, and output Q. An example read path sequence of control signals is described herein below.

[0175] Similar to FIG. 3 A, in FIG. 25A, a read path sequence 2500 provides a Josephson junction switching sequence when reading a one-state. The leftmost superconducting loop (2202 in FIG. 22) of the state loops (2210 in FIG. 22), which differentiates FIGS. 1 A and IB from FIG. 22, essentially has no impact on the read path sequence 2500.

[0176] Similar to FIG. 3B, in FIG. 25B, a read path sequence 2520 provides a Josephson junction switching sequence when reading a zero-state. A “null” signal (i.e., nothing) is passed to the output Q whenever a positive or negative strobe signal (+S or -S) is applied, since the common Josephson junction 104d (see FIG. 22) shared by the two readout loops 120 (e.g., adjacent superconducting loops 102d and 102e in FIG. 22) has no current passing through it due to the superposition of adjacent flux quanta in superconducting loops 102d, 102e enclosing the Josephson junction 104d. The leftmost superconducting loop 2202 of the two state loops 2210 (see FIG. 22), which differentiates FIGS. 1A and IB from FIG. 22, has essentially no impact on the read path sequence 2520.

[0177] By way of example only and without limitation, an example write operation using the illustrative Josephson junction based memory device 2200 of FIG. 22 will now be described, in accordance with example embodiments. FIG. 26A depicts an illustrative write sequence 2600 for writing (i.e., programming) a one-state (“write 1”) to the memory device 2200 of FIG. 22.For the write sequence 2600, the memory device 2200 is assumed to initially be in a zero-state. FIG. 26B depicts an illustrative write sequence 2620 for writing (i.e., programming) a zero-state (“write 0”) to the memory device 2200 of FIG. 22. For the write sequence 2620, the memory device 2200 is assumed to initially be in a one-state.

[0178] Referring to FIGS. 22, 26A and 26B, a positive or negative write signal (+WS or -WS) provided through the write line of the memory device 2200 will inject a corresponding current into the superconducting the two state loops 2210 which, when such current exceeds a critical current of the Josephson junction 2204b in combination with the stored flux quantum (e.g., SFQ 140a in the superconducting loop 102c), will effectively move (i.e., shift) the magnetic flux quantum to an adjacent superconducting loop (e.g., 2202). It is to be appreciated that the write signals +WS and -WS are generated by a non-superconducting source circuit.

[0179] Assuming the stored flux quantum (e.g., SFQ 140a) is in a counterclockwise rotation, an applied positive write signal (+WS) will move the stored flux quantum to the adjacent left superconducting loop 2202 of the two state loops 2210, if the flux quantum (e.g., SFQ 140a) is initially in the right superconducting loop 102c of the two state loops 2210. This write sequence 2600 may be used to change the state of the memory device 2200 from a zero-state to a one- state, as shown in FIG. 26A. Likewise, an applied write signal (-WS) will move the stored flux quantum in the left superconducting loop 2202 of the two state loops 2210 to the adjacent right superconducting loop 102c of the two state loops 2210. This write sequence 2620 may be used to change the state of the memory device 2200 from a one-state to a zero-state, as shown in FIG. 26B. Additional reflected current will dissipate in the resistance of the superconducting write circuit 184.

[0180] After concluding this operational description of read, write, and pass-through sequences, it is important to recognize that the memory device 2200 of FIG. 22 (2300 of FIG. 23) is topologically distinct from JSRAM as already discussed, but also distinct from the memory circuit(s) described in International Publication No. WO 2023 / 183391A1 to Reohr et al. (Reohr ‘391), the disclosure of which is incorporated herein by reference in its entirety.

[0181] FIG. 27 is a schematic diagram depicting an example memory circuit 2700 integrated with a non-superconducting write circuit, according to one or more embodiments. The memory circuit 2700 may be configured as an array (e.g., in rows and columns), although embodimentsare not limited to an array arrangement. Referring to FIG. 27, the memory circuit 2700 includes a plurality of memory devices 2702, wherein each of the memory devices 2702 may be implemented in a manner consistent with the memory devices according to embodiments of the invention (e.g., memory device 100 shown in FIG. 1A, memory device 180 shown in FIG. IB, memory device 2200 shown in FIG. 22). The memory circuit 2700 may be integrated with a non-superconducting write circuit (e.g., write circuit 2802 of FIG. 28), which may include non- superconducting components, such as, for example, bit decoders and line drivers 2704, non- superconducting word decoders and line drivers 2706, and a non-superconducting pre-non- superconducting source signal (pNSS) generator 2708.

[0182] The memory circuit 2700 may further include a plurality of pre-non-superconducting source signal lines, pNSSO and pNSSl, coupled to the memory devices 2702, for conveying one or more pNSS signals provided by the non-superconducting pre-non-superconducting source signal (pNSS) generator 2708. For example, a first pre-non-superconducting source signal line pNSSO may be coupled to a first memory device 2702 (labeled with address Addr<W0><B0>) and a second memory device (labeled with address Addr<W0>) coupled to the pNSSO line. A second pre-non-superconducting source signal line pNSSl may be coupled to a third memory device 2702 (labeled with address Addr<Wl><B0>) and a fourth memory device 2702 (labeled with address Addr<Wl><Bl>) coupled to the pNSSl line. Although only four memory devices 2702 and two pre-non-superconducting source signal lines (pNSS) are shown for clarity, it is to be appreciated that embodiments are not limited to any specific number or arrangement of memory devices 2702 and / or pre-non-superconducting source signal lines in the memory circuit 2700.

[0183] Each of at least a subset of the memory devices 2702 may include three write (programming) inputs (i.e., non-superconducting input(s) 160 in FIG. 22); namely, an address<word>, an address<bit>, and pre-non-superconducting source signal (pNSS). A portion of each of the memory devices 2702 is formed of non-superconducting circuits, which may reside in (i) a non-superconducting write circuit layer, and (ii) non-superconducting circuits of all the memory devices 2902 of FIG. 29.

[0184] As an added benefit, embodiments of the inventive concept may provide reduction in resonant clock load (e.g., a 50-percent reduction in clock load, in some embodiments), sincethere are only two superconducting control signals — word read WR and strobe S. Conventional JSRAM architectures require at least an additional two superconducting control signals, word write (WW) and bit write (BW) and associated wiring congestion and complexity.

[0185] FIG. 28 is a schematic diagram depicting at least a portion of an exemplary retention memory 2800, according to one or more embodiments. The retention memory 2800 may include at least one retention memory circuit(s) 2804 (e.g., memory fabric 800 in FIG. 8A) and a non- superconducting write circuit 2802 (e.g., including elements formed using CMOS or BiCMOS technology) coupled to the retention memory circuit 2804. The retention memory 2800 may be configured to receive one or more parameter signals (e.g., at a first input port or connection) and one or more input signals (e.g., at a second input port or connection) provided to the retention memory 2800. The retention memory 2800 may be configured to generate one or more transformed signals (e.g., at an output port or connection). The one or more parameter signals provided to the retention memory 2800 may include, for example, non-superconducting input(s) (e.g., 160 in FIG. 22) for selecting one or more individual memory devices in the retention memory circuit(s) 2804 that are to be written and for controlling the shape, size, and / or timing of the waveform associated with the signal(s) applied to the state loop (e.g., 110 in FIG. 1A) that are to be provided during the write operation. The one or more input signals provided to the retention memory 2800 may include, for example, an address or addresses of data to be retrieved from one or more memory devices in the retention memory circuit(s) 2804. The one or more transformed signals output from the retention memory 2800 may include, for example, data read from one or more selected memory devices in the retention memory circuit(s) 2804.

[0186] The non-superconducting write circuit 2802 (where portions of the write circuit 2802 associated with each memory device have been noted as non-superconducting write circuit 184) may be configured to perform a digital-to-analog conversion of the non-superconducting parameter(s) supplied to the retention memory 2800, and to convey an output stimulus 2006 appropriate for adding a flux quantum in the state loop (e.g., 110 in FIG. 1A) of at least one memory device in the retention memory circuit(s) 2804 of the retention memory 2800 (or for moving a flux quantum in state loops of a memory device as discussed with respect to FIG. 22). The output stimulus 2006 generated by the non-superconducting write circuit 2802 may be provided to the retention memory circuit(s) 2804 and may include at least a portion of an address signal, data signal, etc.

[0187] In one or more embodiments, the write circuit 2802 may include non-superconducting bit decoders and line drivers (e.g., 2704 shown in FIG. 27), non-superconducting word decoders and line drivers (e.g., 2706 in FIG. 27), and non-superconducting pre-non-superconducting source signal (pNSS) generators (e.g., 2708 in FIG. 27). The ability to use non-superconducting circuitry in the write circuit 2802 in the retention memory 2800 according to embodiments of the inventive concept may result in a significant savings in chip area, and thus provides a beneficial increase in memory capacity (i.e., density).

[0188] A write operation of the retention memory 2800 can be challenging due, at least in part, to the variable nature associated with the characteristics of each manufactured memory device and of the manufactured write circuit 2802 itself. Therefore, in accordance with one or more embodiments, programming parameters provided to the retention memory 2800 may be configured to vary from one memory device to another, so as to compensate for such manufacturing variability. The programming parameters may specify, for example, specialized timing relationships (e.g., defining a write signal pulse width for the memory device), current magnitudes, voltage magnitudes, etc., that are specifically tailored to write / set (i.e., program) each memory device in the retention memory 2800. These specifically-tailored parameters can assure reliability in programming each unique memory device (e.g., to a one-state or zero-state) through the write circuit 2802, which may have variable characteristics of its own. Thus, for purposes of the present disclosure, it will be assumed that the individual bits of the programming parameters may not necessarily represent states exactly, although they can, particularly when the memory is well-behaved like SRAM.

[0189] Given manufacturing variability considerations, the underlying / controlling state of a memory device (e.g., memory device 100 in FIGS. 1A and IB) of the retention memory circuit(s) 2804 in the retention memory 2800 can be updated at a granularity of one retention memory device at a time, according to aspects of the present disclosure.

[0190] Parametric data can be associated exclusively with writing each (control) memory device in the retention memory circuit(s) 2804 or can be associated with writing multiple memory devices in the retention memory circuit(s) 2804 (more typical of conventional memories). Parametric data, which may be defined as a plurality of Boolean bits stored in an associated memory hierarchy, can collectively define, for example, amplitudes of programmingcurrents, programming current signs (i.e., polarity), and / or precision timing associated with the writing of each memory device in the retention memory circuit(s) 2804. State can also be updated across a plurality of memory devices (e.g., memory device 100 in FIG. 1A) in the retention memory circuit(s) 2804 written substantially concurrently, as overseen (i.e., controlled) by parametric data.

[0191] FIG. 29 is a schematic block diagram depicting at least a memory device portion of an example superconducting memory system 2900, according to one or more embodiments of the inventive concept. The superconducting memory system 2900, which is shown in cross- sectional view, may be configured as a three-dimensional (3D) structure and may include a non- superconducting write circuit layer 2902 and one or more superconducting memory device layers 2904_l through 2904_N sequentially stacked on the non-superconducting write circuit layer 2902 in a vertical direction, where N is an integer (e.g., one or greater) and is indicative of the number of superconducting memory device layers in the superconducting memory system 2900. As used herein, the term “vertical direction” may be defined as a direction perpendicular to a surface of a substrate on which the superconducting memory system 2900 is fabricated. The superconducting memory device layers 2904_l through 2904_N may be referred to collectively as 2904.

[0192] The non-superconducting write circuit layer 2902 may include elements that are formed using, for example, CMOS or BiCMOS technology and may operate at room temperature; that is, operation at the critical superconducting temperature (e.g., typically below 10 degrees Kelvin) is not necessary. Each of the superconducting memory device layers 2904 1 through 2904 N may include a superconducting memory element, such as, for example, the illustrative memory device 100 shown in FIGS. 1A and IB. In one or more embodiments, the superconducting portion of the array of unit devices arranged in the illustrative word-organized memory fabric 800 of FIG. 8A may be implemented using layers devoted to superconducting circuits consistent with the plurality of superconducting memory device layers 2904 in the in the superconducting memory system 2900 of FIG. 29. In general, each of at least a subset of the superconducting memory device layers 2904 may include, for example, a memory device having at least one of the following attributes: single-flux-quanta (SFQ)-based memory devices, multi-flux-quanta (MFQ)-based memory devices, passive memory devices, and actively-clocked memory devices. Furthermore, in one or more embodiments, it is contemplated that the plurality ofsuperconducting memory device layers 2904 may comprise other forms of superconducting circuits which utilize memory devices, such as, but not limited to, FPGAs.

[0193] In embodiments having two or more superconducting memory device layers 2904, the superconducting memory device layers 2904_l through 2904_N may be arranged having a shared layer 2110 between each pair of vertically adjacent superconducting memory device layers 2904 (e.g., between memory device layers 2904_l and 2904_2, or between memory device layers 2904_2 and 2904_3, and so on). In some embodiments, the shared layer 2110 may comprise a Josephson junction layer disposed between vertically adjacent superconducting memory device layers 2904, or the shared layer 2110 may include a portion of the resonant clock network 170 (e.g., depicted in FIG. 22, or depicted in FIGS. 4A, 4B, and 8B, which do not include a non-superconducting write circuit 184 in one embodiment, thereby removing the necessity of layer 2902 of FIG. 29 — also enables vertically stacked JSRAM (Luo)), shared between vertically adjacent superconducting memory device layers 2904. The shared layer 2110 may comprise other shared circuits or devices in addition to or in place of the portion of a resonant clock network, as may become apparent to those skilled in the art.

[0194] A superconducting memory system / device 2900 according to one or more embodiments of the inventive concept includes: a plurality of superconducting memory device layers 2904 sequentially stacked in a vertical direction perpendicular to a surface of the superconducting memory device, each of the plurality of superconducting memory device layers 2904 comprising one or more superconducting memory devices; a shared layer 2110 between each pair of vertically adjacent superconducting memory device layers in the plurality of superconducting memory device layers 2904; and a global resonant clock network (e.g., 170 in FIG. 22) operatively coupled to at least a subset of the one or more superconducting memory devices in each of the plurality of superconducting memory device layers 2904. The shared layer 2110 can be configured to implement at least a portion of the global resonant clock network 170 (FIG. 22).

[0195] With Josephson junction technology, the fanout may be very weak. Therefore, a master word line included in the shared layer 2110 (not explicitly shown, but implied) may be used that is shared between one or more pairs of vertically adjacent superconducting memory device layers of the plurality of superconducting memory device layers 2904, and then the master wordline (e.g., word read line WR of FTG. 1 A) may be routed to each memory device in the superconducting memory device layers 2904 via a branch comprising two JTLs. Unlike each of superconducting memory device layers 2904, the shared layer 2110 may not be an independent physical layer. Rather, the shared layer 2110 may exploit superconductor wires and JJs, for example, from each of the adjacent superconducting memory device layers 2904; that is, the shared layer 2110 may be incorporated into one or both of the vertically adjacent superconducting memory device layers 2904 and thus is shown as a dotted box.

[0196] FIG. 30 is a schematic block diagram depicting at least a portion of an example superconducting memory system 3000, according to one or more embodiments of the inventive concept. The superconducting memory system 3000, which is shown in cross-sectional view, consistent with the superconducting memory system 2900 of FIG. 29, may be configured as a 3D structure comprising a non-superconducting write circuit 184 and one or more superconducting memory device layers 3002_l through 3002_N sequentially stacked on the non-superconducting write circuit layer 184 in a vertical direction, where N is an integer (e.g., one or greater) and is indicative of the number of superconducting memory device layers in the superconducting memory system 3000. The superconducting memory device layers 3002_l through 3002_N may be referred to collectively as 3002. Each of the one or more superconducting memory device layers 3002 may include, for example, a memory device having at least one of the following attributes: SFQ-based memory devices, multi flux quanta (MFQ)-based memory devices, passive memory devices, and actively-energized memory devices.

[0197] Although the superconducting memory device layers 3002 are shown in FIG. 30 as being stacked above the non-superconducting write circuit 184, it is to be appreciated that one or more (or all) of the superconducting memory device layers 3002 may, alternatively or in addition to, be stacked below the non-superconducting write circuit 184. For example, in some embodiments, odd superconducting memory device layers 3002_l, 3002_3, etc., may be sequentially stacked on a top surface of the non-superconducting write circuit 184, and even superconducting memory device layers 3002_2, 3002_4, etc., may be sequentially stacked on a bottom surface, opposite the top surface, of the non-superconducting write circuit 184.However, embodiments of the inventive concept are not limited to any specific arrangement of the superconducting memory device layers 3002 with respect to the non-superconducting write circuit 184.

[0198] The superconducting memory system 3000 further includes a plurality of write lines, WL_1 through WL_N, with each of the write lines WL_1 through WL_N, operatively connecting the non-superconducting write circuit 184 to a corresponding one of the superconducting memory device layers 3002_l through 3002_N, respectively. In embodiments having two or more superconducting memory device layers 3002, since the superconducting memory device layers 3002 are stacked in the vertical direction, the write lines WL_2 through WL_N associated with the superconducting memory device layers 3002_2 through 3002_N, respectively, above a lowermost one of the superconducting memory device layers (e.g., 3002_l) closest to the non-superconducting write circuit 184 are configured to pass through at least one of the superconducting memory device layers 3002. In this regard, at least a given one of the superconducting memory device layers 3002 may be configured having one or more pass- through connections (e g., through-silicon via (TSV), etc.) through which one or more write lines may be routed for electrically connecting the non-superconducting write circuit 184 to one or more corresponding superconducting memory device layers 3002 (e.g., 3002_2 through 3002_N) stacked on the given one of the superconducting memory device layers (e.g., 3002_l). For embodiments in which one or more of the superconducting memory device layers 3002 are stacked on the bottom surface of the non-superconducting write circuit 184, a similar pass- through connection arrangement may be employed. In embodiments including only a single superconducting memory device layer 3002, the pass-through connect! on(s) may be omitted.

[0199] In some embodiments in which a transformer is used for injecting flux quantum in a superconducting loop, such as, for example, in the memory device shown in FIGS. 4A - 4C, the superconducting memory system 3000 may further include one or more return write lines (not explicitly shown, but implied) between the respective superconducting memory device layer(s) 3002 and the non-superconducting write circuit 184.

[0200] FIG. 31 is a schematic block diagram depicting at least a portion of an example superconducting memory system 3100, according to one or more embodiments of the inventive concept. The superconducting memory system 3100, which is shown in cross-sectional view, may be configured as a 3D structure comprising a non-superconducting write row circuit 3104 and one or more superconducting memory device layers 3102 1 through 3102_N sequentially stacked on the non-superconducting write row circuit 3104 in a vertical direction, where N is an integer (e.g., one or greater) and is indicative of the number of superconducting memory devicelayers in the superconducting memory system 3100. The superconducting memory device layers 3102 1 through 3102_N may be referred to collectively as 3102. The superconducting memory device layers 3102 may include, for example, a plurality memory devices having at least one of the following attributes: SFQ-based memory devices, MFQ-based memory devices, passive memory devices, and actively-clocked memory devices.

[0201] The superconducting memory system 3100 may be configured such that superconducting memory devices, which may be MJJ memory devices, in each of the one or more superconducting memory device layers 3102 are disposed along a corresponding row. Consistent with the illustrative superconducting memory system 3000 of FIG. 30, although the superconducting memory device layers 3102 are shown in FIG. 31 as being stacked above the non-superconducting write row circuit 3104, it is to be appreciated that one or more (or even all) of the superconducting memory device layers 3102 may, alternatively or in addition to, be stacked below the non-superconducting write row circuit 3104. By way of example only and without limitation, in some embodiments, odd superconducting memory device layers 3102 1, 3102_3, etc., may be sequentially stacked on a top surface of (i.e., above) the non- superconducting write row circuit 3104, and even superconducting memory device layers 3102_2, 3102_4, etc., may be sequentially stacked on a bottom surface, opposite the top surface, of (i.e., below) the non-superconducting write row circuit 3104. However, embodiments of the inventive concept are not limited to any specific arrangement of the superconducting memory device layers 3102 with respect to the non-superconducting write row circuit 3104.

[0202] In embodiments including a plurality of superconducting memory device layers 3102, the superconducting memory system 3100 comprises a plurality of write row lines WRL_1 through WRL_N connecting the non-superconducting write row circuit 3104 with corresponding superconducting memory device layers 3102 1 through 3102_N, respectively. Unlike the write lines WL_1 through WL_N in the illustrative superconducting memory system 3000 of FIG. 30, the write row lines WRL_1 through WRL_N in the superconducting memory system 3100 may be routed to the different levels of the respective superconducting memory device layers 3102 without necessarily passing through the superconducting memory device layers 3102. Rather, in one or more embodiments, the write row lines WRL 1 through WRL N may be routed outside of an area in which the superconducting memory devices are disposed, thereby eliminating the need for pass-through connections in the superconducting memory device layers 3102. Thesuperconducting memory system 3100 may further comprise a common write row line return connection 3106 operatively connecting each of the superconducting memory device layers 3102 to the non-superconducting write row circuit 3104. Arranged in this manner, the superconducting memory system 3100 may be configured as an MJJ RAM with row selection (with fields), as described, for example, in International Publication No. WO 2024 / 138100A9 to Reohr, the disclosure of which is incorporated herein by reference in its entirety.[00203J While some embodiments have been illustrated and described in detail in the appended drawings and the foregoing description, such illustration and description are to be considered illustrative and not restrictive. Other variations to the disclosed embodiments can be understood and effected in practicing the claims, from a study of the drawings, the disclosure, and the appended claims. The mere fact that certain measures or features are recited in mutually different dependent claims does not indicate that a combination of these measures or features cannot be used. Any reference signs in the claims should not be construed as limiting the scope.

Claims

CLAIMSWhat is claimed is:

1. A superconducting memory device, comprising: a non-superconducting write circuit; one or more superconducting memory device layers sequentially stacked on the non- superconducting write circuit in a vertical direction perpendicular to a surface of the non- superconducting write circuit; and one or more write lines, each of the one or more write lines operatively connecting the non-superconducting write circuit to a corresponding one of the one or more superconducting memory device layers, wherein each of the one or more superconducting memory device layers comprises one or more superconducting memory devices, each of the one or more superconducting memory devices being configured to store a memory state as a function of at least one write signal provided by the non-superconducting write circuit and conveyed by the one or more write lines.

2. The superconducting memory device of claim 1, wherein each of at least a subset of the one or more superconducting memory devices is configured having a maximum of two superconducting state loops.

3. The superconducting memory device of claim 2, wherein each of at least a subset of the one or more superconducting memory devices comprises first and second superconducting readout loops.

4. The superconducting memory device of claim 1, wherein each of at least a subset of the one or more superconducting memory devices is configured having a single superconducting state loop, and wherein the memory state stored in each of at least a subset of the one or more superconducting memory devices is determined as a function of a presence or absence of single flux quantum in the superconducting state loop.

5. The superconducting memory device of claim 4, wherein the superconducting state loop comprises at least a first Josephson junction.

6. The superconducting memory device of claim 5, wherein the superconducting state loop further comprises a second Josephson junction.

7. The superconducting memory device of claim 2, wherein each of at least a subset of the one or more superconducting memory devices is configured having first and second superconducting state loops.

8. The superconducting memory device of claim 1, wherein the one or more superconducting memory device layers comprises a plurality of superconducting memory device layers, the superconducting memory device further comprising a shared layer between each pair of vertically adjacent superconducting memory device layers in the plurality of superconducting memory device layers.

9. The superconducting memory device of claim 1, wherein the one or more superconducting memory device layers comprises a plurality of superconducting memory device layers , and wherein each of the one or more write lines associated with a subset of the plurality of superconducting memory device layers, adjacent to a lowermost one of the plurality of superconducting memory device layers closest in proximity to the non-superconducting write circuit, is configured to pass through at least one of the plurality of superconducting memory device layers.

10. The superconducting memory device of claim 9, wherein at least one of the plurality of superconducting memory device layers comprises at least one pass-through connection configured to provide an electrical path for routing at least one of the one or more write lines between the non-superconducting write circuit and a corresponding one of the plurality of superconducting memory device layers stacked on the lowermost superconducting memory device layer.11 . The superconducting memory device of claim 1, further comprising: one or more write row lines, each of the one or more write row lines operatively connecting the non-superconducting write circuit to a write row line in a corresponding one of the one or more superconducting memory device layers; and a common write row return line electrically connecting the one or more superconducting memory device layers to the non- superconducting write circuit.

12. The superconducting memory device of claim 11, wherein at least one write row line of the one or more write row lines in each superconducting memory device layer of the one or more superconducting memory device layers comprises a plurality of series-connected write lines connecting to each of the one or more superconducting memory devices in the one or more superconducting memory device layers.

13. The superconducting memory device of claim 1, wherein each of the one or more superconducting memory devices in the one or more superconducting memory device layers is connected to and written by a dedicated write line of the one or more write lines.

14. A superconducting memory device configured to have its state written at least once, the superconducting memory device comprising: at least two superconducting loops electrically coupled to one another, one of the at least two superconducting loops is configured as a readout loop and another of the at least two superconducting loops is configured as a state loop; at least one non-superconducting input configured to convey at least one corresponding non-superconducting input signal provided to the superconducting memory device for writing state to the superconducting memory device; at least two superconducting inputs configured to convey corresponding superconducting input signals provided to the superconducting memory device for reading the state of the superconducting memory device; a superconducting output configured to convey an output of the superconducting memory device;at least first and second Josephson junctions, the state loop including the first Josephson junction and the readout loop including the second Josephson junction; and a non-superconducting write circuit, the non-superconducting write circuit comprising a dedicated write line configured to convey a write signal for writing state to the superconducting memory device, wherein a state of the superconducting memory device is determined based on one of a presence or absence of single flux quantum in the state loop, a location of the single flux quantum in the at least two superconducting loops, and a direction of rotation of the single flux quantum in the state loop.

15. The superconducting memory device of claim 14, wherein the number of the at least two superconducting loops in the superconducting memory device is two, three, or four.

16. The superconducting memory device of claim 14, wherein the at least two superconducting loops consists of a first superconducting loop and a second superconducting loop, the first superconducting loop configured as the readout loop and the second superconducting loop configured as the state loop.

17. The superconducting memory device of claim 14, wherein the at least two superconducting loops consist essentially of first and second superconducting loops configured as first and second readout loops, respectively, and a third superconducting loop configured as the state loop.

18. The superconducting memory device of claim 14, wherein the at least two superconducting loops consist essentially of first and second superconducting loops configured as respective readout loops, and third and fourth superconducting loops configured as respective state loops.

19. The superconducting memory device of claim 18, wherein the third and fourth superconducting loops are configured to share the third Josephson junction, and wherein the stateof the superconducting memory device is defined based on the location of the single flux quantum in the third superconducting loop or the fourth superconducting loop.

20. The superconducting memory device of claim 14, further comprising a third Josephson junction, the third Josephson junction being disposed in the state loop opposite the second Josephson junction.

21. The superconducting memory device of claim 17, wherein the second superconducting loop is adjacent to the third superconducting loop and wherein the second superconducting loop is configured as a shared loop.

22. The superconducting memory device of claim 14, further comprising at least one transformer operatively coupled to the non-superconducting write circuit, the transformer being configured to selectively inject flux quantum into the state loop.

23. The superconducting memory device of claim 14, wherein the state loop is configured to at least periodically confine a single flux quantum during at least one of a write operation or a standby operation of the superconducting memory device.

24. A superconducting memory device, comprising: a plurality of superconducting memory device layers sequentially stacked in a vertical direction perpendicular to a surface of the superconducting memory device, each of the plurality of superconducting memory device layers comprising one or more superconducting memory devices; a shared layer between each pair of vertically adjacent superconducting memory device layers in the plurality of superconducting memory device layers; and a global resonant clock network operatively coupled to at least a subset of the one or more superconducting memory devices in each of the plurality of superconducting memory device layers,wherein the shared layer is configured to implement at least a portion of the global resonant clock network.

25. The superconducting memory device of claim 24, further comprising at least one ground plane disposed below or above at least a portion of the global resonant clock network in the vertical direction.

26. The superconducting memory device of claim 24, wherein the shared layer is incorporated into at least one superconducting memory device layer in the pair of vertically adjacent superconducting memory device layers.

27. A mask-programmable memory device, comprising: a first superconducting memory device, the first superconducting memory device comprising: at least two superconducting loops electrically coupled to one another, one of the at least two superconducting loops is configured as a first readout loop and another of the at least two superconducting loops is configured as a first state loop; at least two superconducting inputs configured to convey corresponding superconducting input signals provided to the superconducting memory device for reading a state of the first superconducting memory device; a superconducting output configured to convey an output of the first superconducting memory device; at least first and second Josephson junctions, the first state loop including the first Josephson junction and the first readout loop including the second Josephson junction; and a transformer connected in the first state loop and configured to inject a flux quantum into the first state loop; and a second superconducting memory device, the second superconducting memory device comprising:at least two superconducting loops electrically coupled to one another, one of the at least two superconducting loops is configured as a second readout loop and another of the at least two superconducting loops is configured as a second state loop; at least two superconducting inputs configured to convey corresponding superconducting input signals provided to the second superconducting memory device for reading the state of the second superconducting memory device; a superconducting output configured to convey an output of the second superconducting memory device; and at least third and fourth Josephson junctions, the second state loop including the third Josephson junction and the second readout loop including the fourth Josephson junction, wherein states of the first and second superconducting memory devices are determined based on one of a presence or absence of single flux quantum in the first and second state loops, respectively, and a direction of rotation of the single flux quantum in the first and second state loops, respectively.

28. The mask-programmable memory device of claim 27, wherein a number of the at least two superconducting loops in each of the first and the second superconducting memory devices in the mask-programmable memory device is two or three.

29. The mask-programmable memory device of claim 27, wherein the second superconducting memory device further comprises a transformer connected in the second state loop and configured to inject a flux quantum into the second state loop, the flux quantum in the second state loop having an opposite rotation with respect to the flux quantum in the first state loop.

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