Display driver circuit and display apparatus

Abstract

A display driver circuit (Ddc) and a display apparatus. The display driver circuit (Ddc) comprises multiple frequency division control lines (FL) and multiple cascaded gate driver circuits (GA). The multiple frequency division control lines (FL) transmit frequency division control signals (FD) to the multiple gate driver circuits (GA). Each gate driver circuit (GA) comprises multiple first output modules (20), and the multiple first output modules (20) output multiple first gate control signals (Pscan) having a phase difference.

Description

Display driving circuit and display device

[0001] This application claims priority to Chinese Patent Application No. 202410405954.4 filed on April 3, 2024, and the contents of the above-mentioned Chinese patent application disclosure are hereby incorporated by reference in their entirety as a part of this application. Technical Field

[0002] The present application relates to the field of display technology, and in particular to a display driving circuit and a display device. Background Art

[0003] Controlling a display panel to have different refresh rates for different display areas, thereby implementing a zoned and frequency-controlled design, can reduce power consumption. However, the gate drive circuits that support this zoned and frequency-controlled design for display panels include a large number of transistors. The gate drive units, including multi-stage gate drive circuits, occupy a significant portion of the display panel's border space during layout design, hindering the realization of a narrow-border design for the display panel. SUMMARY OF THE INVENTION

[0004] Embodiments of the present application provide a display driving circuit and a display device, which can reduce the layout space occupied by a gate driving unit including a multi-stage gate driving circuit.

[0005] An embodiment of the present application provides a display driver circuit including a gate driver unit, the gate driver unit comprising a plurality of frequency division control lines and a plurality of cascaded gate driver circuits, the plurality of frequency division control lines being configured to transmit frequency division control signals to the plurality of gate driver circuits. Each gate driver circuit includes a node control module, a plurality of first output modules, and at least one first frequency division module.

[0006] The node control module is electrically connected to the first and second nodes of the gate drive circuit at this level. The node control module is configured to control the signals transmitted to the first and second nodes based on the corresponding first clock signal and the start signal. Each first output module is electrically connected to the first and second nodes. Each first output module is configured to output a first gate control signal based on the corresponding second clock signal, the frequency division control signal, and the signals at the first and second nodes. At least one first frequency division module is electrically connected to the first node, the second node, and at least one first output module. The first frequency division module is configured to control the signal transmission between the first node and the corresponding first output module based on the frequency division control signal and the signal at the second node. The multiple first output modules are configured to output multiple first gate control signals with phase differences.

[0007] The present application provides a display device comprising any of the above-mentioned display driver circuits and a display panel. The display panel is electrically connected to the display driver circuit, and the display panel includes a plurality of sub-pixels, each of which includes a light-emitting device, a driving transistor, and a data transistor; the driving transistor is configured to generate a driving current to drive the light-emitting device to emit light, and the data transistor is configured to transmit a data signal to the control terminal of the driving transistor. The first gate control signals output by the multiple first output modules of the same gate driver circuit are electrically connected to the control terminals of the data transistors of the sub-pixels in adjacent rows, and each first gate control signal is electrically connected to the control terminal of the data transistor of at least one row of sub-pixels. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG1 is a block diagram of a display driving circuit according to an embodiment of the present application;

[0009] FIG2 is a block diagram of a gate drive circuit according to an embodiment of the present invention;

[0010] 3A to 3E are schematic diagrams showing connections between a multi-stage gate drive circuit and a clock line according to an embodiment of the present application;

[0011] FIG4 is a schematic structural diagram of a gate drive circuit provided in an embodiment of the present application;

[0012] 5A to 5E are timing diagrams of corresponding gate drive circuits provided in embodiments of the present application;

[0013] FIG6 is a schematic diagram of a display device provided in an embodiment of the present application;

[0014] FIG7 is a schematic structural diagram of a pixel driving circuit provided in an embodiment of the present application;

[0015] FIG8 is a timing diagram of a corresponding pixel driving circuit provided in an embodiment of the present application;

[0016] FIG9 is a schematic diagram of the high-frequency and low-frequency image display principles provided by an embodiment of the present application. Modes for Carrying Out the Invention

[0017] To make the purpose, technical solutions and effects of this application clearer and more specific, the following further describes this application in detail with reference to the accompanying drawings and examples. It should be understood that the specific examples described herein are only used to explain this application and are not intended to limit this application.

[0018] The present application provides a display driver circuit and a display device. The display driver circuit includes multiple frequency division control lines and multiple cascaded gate driver circuits. The multiple frequency division control lines transmit frequency division control signals to the multiple gate driver circuits. Each gate driver circuit includes a node control module, multiple first output modules, and at least one first frequency division module. The node control module controls the signals transmitted to the first node and the second node of the gate driver circuit at this stage based on a corresponding first clock signal and a start signal. The first frequency division module controls the signal transmission between the first node and the at least one first output module based on the frequency division control signal and the signal of the second node. Each first output module outputs a first gate control signal based on the corresponding second clock signal, the frequency division control signal, and the signal of the first node and the second node. The multiple first output modules output multiple first gate control signals with phase differences. By having each gate driver circuit include multiple first output modules, and the multiple first output modules output multiple first gate control signals with phase differences, the number of gate driver circuits included in the gate driver unit is reduced, thereby reducing the layout space occupied by the gate driver unit.

[0019] Specifically, Figure 1 is a principle block diagram of a display driving circuit provided in an embodiment of the present application. The present application provides a display driving circuit, including a gate driving unit GM, wherein the gate driving unit GM includes multiple frequency division control lines FL and multiple cascaded gate driving circuits GA. The multiple frequency division control lines FL are configured to transmit the frequency division control signal FD to the multiple gate driving circuits GA, and the multiple gate driving circuits GA output multiple first gate control signals Pscan.

[0020] FIG2 is a principle block diagram of a gate driving circuit provided in an embodiment of the present application. Each gate driving circuit GA includes a node control module 10 , a plurality of first output modules 20 and at least one first frequency dividing module 30 .

[0021] The node control module 10 is electrically connected to the first node K1 and the second node K2 of the current-stage gate drive circuit GA. The node control module 10 is configured to control the signals transmitted to the first node K1 and the second node K2 according to the corresponding first clock signal XCK and the start signal STV.

[0022] Each first output module 20 is electrically connected to a first node K1 and a second node K2. Each first output module 20 is configured to output a first gate control signal Pscan based on a corresponding second clock signal CK, a frequency division control signal FD, and signals at the first and second nodes K1 and K2. IN1 and INX represent input terminals of the first output module 20 for receiving the second clock signal CK.

[0023] The first frequency dividing module 30 is electrically connected to the first node K1, the second node K2, and at least one first output module 20. The first frequency dividing module 30 is configured to control signal transmission between the first node K1 and the corresponding first output module 20 based on the frequency dividing control signal FD and the signal at the second node K2. The multiple first output modules 20 are configured to output multiple first gate control signals Pscan with phase differences.

[0024] By making each gate driving circuit GA include multiple first output modules 20 at the same time, and the multiple first output modules 20 output multiple first gate control signals Pscan with phase differences, the number of gate driving circuits GA included in the gate driving unit GM is reduced, thereby reducing the layout space occupied by the gate driving unit GM.

[0025] Optionally, each gate drive circuit GA includes X first output modules 20, and the phase difference between the first clock signals XCK corresponding to two adjacent stages of the gate drive circuit GA is XH (as shown in Figures 5A to 5E described below). This allows the X first output modules 20 of each stage of the gate drive circuit GA to control the level of the first gate control signal Pscan during the corresponding valid level output period. That is, taking the current stage of the gate drive circuit GA and the first stage of the gate drive circuit GA cascaded before the current stage of the gate drive circuit GA as examples, the X first output modules 20 of the current stage of the gate drive circuit GA only begin to output the corresponding first gate control signal Pscan after the X first output modules 20 of the first stage of the gate drive circuit GA cascaded before the current stage of the gate drive circuit GA have all output the corresponding first gate control signal Pscan. Where X ≥ 2, and H is the unit time duration.

[0026] Optionally, each gate driving circuit GA is electrically connected to N clock lines, so as to transmit the corresponding first clock signal XCK and second clock signal CK to the gate driving circuit GA through the N clock lines, where N=X+1.

[0027] Optionally, the gate drive circuit GA includes two first output modules 20 (i.e., X=2), the gate drive circuit GA is electrically connected to three clock lines (i.e., N=3), one of the three clock lines transmits the corresponding first clock signal XCK to the gate drive circuit GA, and the other two clock lines of the three clock lines transmit the corresponding second clock signal CK to the gate drive circuit GA.

[0028] Optionally, in order to make the phase difference of the first gate control signals Pscan output by multiple first output modules 20 of the same gate drive circuit GA the same, the phase difference between the second clock signal CK received by a first output module 20 and the first clock signal XCK corresponding to the gate drive circuit GA can be equal to the minimum phase difference of the multiple second clock signals CK, while the phase difference between the second clock signal CK received by the remaining first output modules 20 among the multiple first output modules 20 and the first clock signal XCK corresponding to the gate drive circuit GA is greater than the minimum phase difference.

[0029] For example, the gate drive circuit GA includes two first output modules 20. The gate drive circuit GA corresponds to a first clock signal XCK and two second clock signals CK. The phase difference between the two second clock signals CK is 1H (that is, the minimum phase difference is 1H). The phase difference between the second clock signal CK corresponding to one first output module 20 and the first clock signal XCK is also equal to 1H, and the phase difference between the second clock signal CK corresponding to the other first output module 20 and the first clock signal XCK is equal to 2H.

[0030] For example, the gate drive circuit GA includes three first output modules 20, and the gate drive circuit GA corresponds to a first clock signal XCK and three second clock signals CK (recorded as the first sub-signal, the second sub-signal and the third sub-signal). The phase difference between the first sub-signal and the second sub-signal is 1H, the phase difference between the second sub-signal and the third sub-signal is 1H, and the phase difference between the third sub-signal and the first sub-signal is 2H, that is, the minimum phase difference of the multiple second clock signals CK is 1H. The phase difference between the second clock signal CK corresponding to one first output module 20 and the first clock signal XCK is also equal to 1H, and the phase differences between the second clock signals CK corresponding to the other two first output modules 20 and the first clock signal XCK are 2H and 3H respectively.

[0031] Optionally, the phase difference between the second clock signal CK received by a first output module 20 among the multiple first output modules 20 of a gate drive circuit GA and the first clock signal XCK corresponding to the gate drive circuit GA can be equal to XH, so that the phase difference between the adjacent levels of first gate control signals Pscan output by two adjacent levels of gate drive circuits GA and the phase difference between the adjacent levels of first gate control signals Pscan output by the same gate drive circuit GA tend to be consistent.

[0032] Optionally, the phase difference between the second clock signal CK and the first clock signal XCK received by the plurality of first output modules 20 is in a range of xH to ​​XH, where x represents the minimum phase difference, and x>0.

[0033] Optionally, the multi-stage gate driving circuit GA may share clock signals transmitted by multiple clock lines as the corresponding first clock signal XCK and second clock signal CK, so as to reduce power consumption of the display driving circuit.

[0034] Optionally, in the same gate drive circuit GA, the phase difference between the first gate control signals Pscan output by the two first output modules 20 can be RH, so that within the phase difference interval of the first clock signal XCK applied to the two adjacent gate drive circuits GA, the X first output modules 20 of the same gate drive circuit GA can all output the first gate control signal Pscan. Wherein, 1≤R <X。

[0035] For example, the gate driving circuit GA includes two first output modules 20 , and the phase difference between the first gate control signals Pscan output by the two first output modules 20 is 1H.

[0036] For example, the gate drive circuit GA includes three first output modules 20, and the three first output modules include a first sub-output module, a second sub-output module and a third sub-output module. The phase difference between the first gate control signal Pscan output by the first sub-output module 201 and the second sub-output module 202 is 1H, the phase difference between the first gate control signal Pscan output by the second sub-output module 202 and the third sub-output module is 1H, and the phase difference between the first gate control signal Pscan output by the first sub-output module 201 and the third sub-output module is 2H.

[0037] Figures 3A to 3E are schematic diagrams illustrating the connection between a multi-stage gate drive circuit GA and a clock line according to an embodiment of the present application. In particular, IN1 to IN3 represent input terminals of a first output module 20 corresponding to receiving the second clock signal CK, and XIN represents an input terminal of the gate drive circuit GA corresponding to receiving the first clock signal XCK.

[0038] Optionally, each gate drive circuit GA includes X first output modules 20. The multi-stage gate drive circuit GA is electrically connected to Y clock lines. The Y clock lines transmit corresponding first clock signals XCK and second clock signals CK to the multi-stage gate drive circuit GA, so that the multiple gate drive circuits GA share the clock signals provided by the Y clock lines to control the output of multiple first gate control signals Pscan. Where X ≥ 2 and Y > X.

[0039] Optionally, Y=2X, so that the multiple gate driving circuits GA are equipped with Y clock lines, and the first gate control signals Pscan output by the multiple-stage gate driving circuits GA have the same phase difference in sequence.

[0040] When multiple clock lines are multiplexed to transmit the corresponding first clock signal XCK and second clock signal CK to the multi-stage gate drive circuit GA, some clock lines need to provide the first clock signal XCK and the second clock signal CK to the corresponding gate drive circuit GA at the same time, while some clock lines only need to provide the second clock signal CK to the corresponding gate drive circuit GA. Therefore, the corresponding loads on the multiple clock lines are inconsistent, which will result in differences in the output waveforms of multiple clock signals, thereby affecting the consistency of the quality of the first gate control signal Pscan output by the multi-stage gate drive circuit GA.

[0041] In order to ensure that the first gate control signal Pscan output by the multi-stage gate driving circuit GA has good quality consistency, a clock line may be separately provided to provide the first clock signal XCK to the multi-stage gate driving circuit GA.

[0042] That is, each gate drive circuit GA includes X first output modules 20, and the multi-stage gate drive circuit GA is electrically connected to multiple clock lines. Z of the multiple clock lines transmit corresponding first clock signals XCK to the multi-stage gate drive circuit GA, and Y of the multiple clock lines transmit corresponding second clock signals CK to the multi-stage gate drive circuit GA; where X ≥ 2, Z ≥ 2, and Y > X.

[0043] Optionally, Z=2, so that the multi-stage gate driving circuit GA shares the clock signals transmitted by two clock lines as the corresponding first clock signal XCK.

[0044] 3A , the design of using Y clock lines to transmit the corresponding first clock signal XCK and second clock signal CK to the multi-stage gate driving circuit GA will be described.

[0045] For example, each gate driver circuit GA includes two first output modules 20 (i.e., X=2), so that each gate driver can output two first gate control signals Pscan. Accordingly, the Y clock lines include a first clock line CKL1, a second clock line CKL2, a third clock line CKL3, and a fourth clock line CKL4. The first clock line CKL1 transmits the corresponding second clock signal CK to a first output module 20 of the 2k+1-stage gate driver circuit GA(2k+1), and the second clock line CKL2 transmits the corresponding second clock signal CK to another first output module 20 of the 2k+1-stage gate driver circuit GA(2k+1). The third clock line CKL3 transmits the corresponding second clock signal CK to a first output module 20 of the 2k+2-stage gate driver circuit GA(2k+2), and the fourth clock line CKL4 transmits the corresponding second clock signal CK to another first output module 20 of the 2k+2-stage gate driver circuit GA(2k+2). This ensures that the phase difference between the two first gate control signals Pscan output by each gate driver circuit GA remains the same. Where k≥0.

[0046] Please continue to refer to Figure 3A. The third clock line CKL3 transmits the corresponding first clock signal XCK to the 2k+1-th gate driving circuit GA(2k+1), and the first clock line CKL1 transmits the corresponding first clock signal XCK to the 2k+2-th gate driving circuit GA(2k+2), so that the phase difference between the first clock signals XCK corresponding to the two adjacent gate driving circuits GA is XH, so that the X first output modules 20 of each gate driving circuit GA can effectively output the first gate control signal Pscan.

[0047] The following describes a design for transmitting the corresponding first clock signal XCK to the multi-stage gate drive circuit GA using Z clock lines in conjunction with FIG3B . Optionally, the Z clock lines include a fifth clock line CKL5 and a sixth clock line CKL6. The fifth clock line CKL5 transmits the corresponding first clock signal XCK to the 2k+1-stage gate drive circuit GA(2k+1); and the sixth clock line CKL6 transmits the corresponding first clock signal XCK to the 2k+2-stage gate drive circuit GA(2k+2). This allows the odd-stage gate drive circuit GA to use the clock signal transmitted by the fifth clock line CKL5 as the first clock signal XCK, while the even-stage gate drive circuit GA to use the clock signal transmitted by the sixth clock line CKL6 as the first clock signal XCK. This ensures that the loads corresponding to the Z clock lines and the Y clock lines are similar, thereby ensuring that the quality of the first gate control signal Pscan output by the multi-stage gate drive circuit GA is consistent.

[0048] The inventors conducted simulation verification on the design shown in Figure 3B. The simulation results show that using a separate clock line to provide the first clock signal XCK to the multi-stage gate drive circuit GA can make the load deviation less than 10%, and make the quality of the first gate control signal Pscan output by the multi-stage gate drive circuit GA consistent.

[0049] Figures 3C through 3E illustrate a design where each gate driver circuit GA includes three first output modules 20 (e.g., the three first output modules 20 include a first sub-output module, a second sub-output module, and a third sub-output module). Y clock lines are used to transmit the corresponding first clock signal XCK and second clock signal CK to the multi-stage gate driver circuits GA. Specifically, the Y clock lines include a first clock line CKL1, a second clock line CKL2, a third clock line CKL3, a fourth clock line CKL4, a seventh clock line CKL7, and an eighth clock line CKL8.

[0050] Please continue to refer to Figure 3C. The first clock line CKL1 transmits the corresponding second clock signal CK to the first sub-output module of the 2k+1-level gate drive circuit GA(2k+1), the second clock line CKL2 transmits the corresponding second clock signal CK to the second sub-output module of the 2k+1-level gate drive circuit GA(2k+1), and the third clock line CKL3 transmits the corresponding second clock signal CK to the third sub-output module of the 2k+1-level gate drive circuit GA(2k+1); the fourth clock line CKL4 transmits the corresponding second clock signal CK to the first sub-output module of the 2k+2-level gate drive circuit GA(2k+2), the seventh clock line CKL7 transmits the corresponding second clock signal CK to the second sub-output module of the 2k+2-level gate drive circuit GA(2k+2), and the eighth clock line CKL8 transmits the corresponding second clock signal CK to the third sub-output module of the 2k+2-level gate drive circuit GA(2k+2).

[0051] Please continue to refer to Figure 3D. The seventh clock line CKL7 transmits the corresponding second clock signal CK to the first sub-output module of the 2k+1-level gate drive circuit GA(2k+1), the eighth clock line CKL8 transmits the corresponding second clock signal CK to the second sub-output module of the 2k+1-level gate drive circuit GA(2k+1), the first clock line CKL1 transmits the corresponding second clock signal CK to the third sub-output module of the 2k+1-level gate drive circuit GA(2k+1); the second clock line CKL2 transmits the corresponding second clock signal CK to the first sub-output module of the 2k+2-level gate drive circuit GA(2k+2), the third clock line CKL3 transmits the corresponding second clock signal CK to the second sub-output module of the 2k+2-level gate drive circuit GA(2k+2), and the fourth clock line CKL4 transmits the corresponding second clock signal CK to the third sub-output module of the 2k+2-level gate drive circuit GA(2k+2).

[0052] Please continue to refer to Figure 3E. The eighth clock line CKL8 transmits the corresponding second clock signal CK to the first sub-output module of the 2k+1-level gate drive circuit GA(2k+1), the first clock line CKL1 transmits the corresponding second clock signal CK to the second sub-output module of the 2k+1-level gate drive circuit GA(2k+1), and the second clock line CKL2 transmits the corresponding second clock signal CK to the third sub-output module of the 2k+1-level gate drive circuit GA(2k+1); the third clock line CKL3 transmits the corresponding second clock signal CK to the first sub-output module of the 2k+2-level gate drive circuit GA(2k+2), the fourth clock line CKL4 transmits the corresponding second clock signal CK to the second sub-output module of the 2k+2-level gate drive circuit GA(2k+2), and the seventh clock line CKL7 transmits the corresponding second clock signal CK to the third sub-output module of the 2k+2-level gate drive circuit GA(2k+2).

[0053] Among them, when the period of the clock signals transmitted by the Y clock lines is EH (as shown in Figures 5A to 5E described later), E=2X, and the phase difference between two adjacent clock signal lines of the Y clock signal lines is equal, the design shown in Figures 3C to 3D can be adopted to make the phase difference between the first gate control signals Pscan output by the first sub-output module and the second sub-output module in the same gate drive circuit GA equal to the phase difference between the first gate control signals Pscan output by the second sub-output module and the third sub-output module; and the phase difference between the first gate control signals Pscan output by the first sub-output modules of two adjacent gate drive circuits GA is equal to XH, the phase difference between the first gate control signals Pscan output by the second sub-output modules of two adjacent gate drive circuits GA is equal to XH, and the phase difference between the first gate control signals Pscan output by the third sub-output modules of two adjacent gate drive circuits GA is equal to XH.

[0054] If the periods of the clock signals transmitted by Y clock lines are all FH, the phase difference between the clock signal transmitted by the first clock line CKL1 and the clock signal transmitted by the second clock line CKL2 is 1H, the phase difference between the clock signal transmitted by the second clock line CKL2 and the clock signal transmitted by the third clock line CKL3 is 1H, the phase difference between the clock signal transmitted by the third clock line CKL3 and the clock signal transmitted by the fourth clock line CKL4 is 1H, the phase difference between the clock signal transmitted by the fourth clock line CKL4 and the clock signal transmitted by the seventh clock line CKL7 is 1H, and the seventh clock line CKL8 is 1H. The phase difference between the clock signal transmitted by the clock line CKL7 and the clock signal transmitted by the eighth clock line CKL8 is 1H, and the phase difference between the clock signal transmitted by the eighth clock line CKL8 and the clock signal transmitted by the first clock line CKL1 is 1H. By adopting the designs shown in FIG3C and FIG3D , the phase difference between the first gate control signals Pscan output by the first sub-output module and the second sub-output module in the same gate drive circuit GA is 1H, and the phase difference between the first gate control signals Pscan output by the second sub-output module and the third sub-output module is 1H. Furthermore, the phase difference between the first gate control signals Pscan output by the first sub-output modules of two adjacent gate drive circuits GA is 3H, the phase difference between the first gate control signals Pscan output by the second sub-output modules of two adjacent gate drive circuits GA is 3H, and the phase difference between the first gate control signals Pscan output by the third sub-output modules of two adjacent gate drive circuits GA is 3H.

[0055] Optionally, each gate drive circuit GA includes three first output modules 20, and when the Y clock lines include a first clock line CKL1, a second clock line CKL2, a third clock line CKL3, a fourth clock line CKL4, a seventh clock line CKL7 and an eighth clock line CKL8, the fourth clock line CKL4 transmits the corresponding first clock signal XCK to the 2k+1-level gate drive circuit GA(2k+1), and the first clock line CKL1 transmits the corresponding first clock signal XCK to the 2k+2-level gate drive circuit GA(2k+2), so that the X first output modules 20 of each level of gate drive circuit GA can effectively output the first gate control signal Pscan.

[0056] Optionally, when each gate drive circuit GA includes three first output modules 20, the corresponding first clock signal XCK can be transmitted to the 2k+1-level gate drive circuit GA(2k+1) through the fifth clock line CKL5, and the corresponding first clock signal XCK can be transmitted to the 2k+2-level gate drive circuit GA(2k+2) through the sixth clock line CKL6, so that the loads corresponding to multiple clock lines are similar, thereby improving the quality consistency of multiple first gate control signals Pscan.

[0057] Optionally, when multiple gate drive circuits GA reuse clock signals provided by multiple clock lines, if the period of the clock signal provided by each clock line is EH, the number X of first output modules 20 included in each gate drive circuit GA is less than E, so that the first output module 20 of each gate drive circuit GA can effectively output the first gate control signal Pscan, where E ≥ 2.

[0058] Optionally, to ensure that each first output module 20 in the same gate drive circuit GA can effectively output the first gate control signal Pscan, each gate drive circuit GA may include at most E-1 first output modules 20. That is, a gate drive circuit GA may include 2 to E-1 (i.e., X = 2 to E-1) first output modules 20.

[0059] Figure 4 is a schematic diagram of the structure of a gate drive circuit provided by an embodiment of the present application. Figure 4 illustrates only a first-level gate drive circuit GA including two first output modules 20, and does not necessarily mean that a gate drive circuit GA must include two first output modules 20. In Figure 4 , p ≥ 1 and q ≥ 1.

[0060] Continuing to refer to FIG. 4 , each first output module 20 includes a first output transistor To1 , a second output transistor To2 , and a first capacitor C1 .

[0061] The control end of the first output transistor To1 is electrically connected to the corresponding first frequency dividing module 30, the input end of the first output transistor To1 is configured to receive the corresponding second clock signal CK, and the output end of the first output transistor To1 is electrically connected to the first output end Pout of the current level gate drive circuit GA outputting the first gate control signal Pscan.

[0062] The control terminal of the second output transistor To2 is electrically connected to the second node K2, the input terminal of the second output transistor To2 is electrically connected to the first power terminal PVGH, and the output terminal of the first output transistor To1 is electrically connected to the corresponding first output terminal Pout;

[0063] A first end of the first capacitor C1 is electrically connected to the control end of the first output transistor To1 , and a second end of the first capacitor C1 is electrically connected to the corresponding first output end Pout.

[0064] 4 , at least one first output module 20 includes a first switch transistor Ts1, a control end of the first switch transistor Ts1 being electrically connected to the second node K2 of the front-stage gate drive circuit GA, an input end of the first switch transistor Ts1 being electrically connected to the corresponding first frequency dividing module 30, and an output end of the first switch transistor Ts1 being electrically connected to the control end of the corresponding first output transistor To1.

[0065] Optionally, the switch control signal SC received by the control end of the eleventh transistor T11 of the first-stage gate drive circuit GA(1) to the second-stage gate drive circuit GA(2) corresponds to the low-level signal VGL, and the control end of the eleventh transistor T11 of each stage of the gate drive circuit GA located after the second-stage gate drive circuit GA(2) is electrically connected to the second node K2 of the first two stages of the gate drive circuit GA (e.g., the control end of the eleventh transistor T11 of the p-stage gate drive circuit GA(p) is electrically connected to the second node K2(p-2) of the p-2-stage gate drive circuit GA(p-2), as shown in FIG. 3A to FIG. 3E ).

[0066] Optionally, in the same gate driving circuit GA, the switch control signals SC corresponding to the plurality of first switch transistors Ts1 may be the same, so as to reduce control complexity.

[0067] Optionally, in the same gate drive circuit GA, the switch control signals SC corresponding to the multiple first switch transistors Ts1 may also be different, so that in the same gate drive circuit GA, the time when each first output module 20 outputs the first gate control signal Pscan can be independently controlled.

[0068] Optionally, to ensure that the first gate control signals Pscan output by the multiple first output modules 20 of the same gate drive circuit GA have similar characteristics, the design parameters of the first output transistors To1 of the multiple first output modules 20 of the same gate drive circuit GA (such as the aspect ratio and size of the transistor channel) remain the same, the design parameters of the second output transistors To2 of the multiple first output modules 20 of the same gate drive circuit GA remain the same, the design parameters of the first capacitors C1 of the multiple first output modules 20 of the same gate drive circuit GA (such as the size and capacitance) remain the same, and the design parameters of the first switch transistors Ts1 of the multiple first output modules 20 of the same gate drive circuit GA remain the same.

[0069] 2 , at least one gate driving circuit GA includes a first control module 40 , which is configured to control signal transmission between the first power terminal PVGH and the at least one first output module 20 according to the corresponding first clock signal XCK and the potential of the second node K2 .

[0070] Continuing to refer to FIG. 4 , the first control module 40 includes a second switch transistor Ts2 and a third switch transistor Ts3 .

[0071] The control terminal of the second switch transistor Ts2 receives the corresponding first clock signal XCK, and the input terminal of the second switch transistor Ts2 is electrically connected to the input terminal of at least one first switch transistor Ts1.

[0072] The control end of the third switch transistor Ts3 is electrically connected to the second node K2 , the input end of the third switch transistor Ts3 is electrically connected to the first power end PVGH, and the output end of the third switch transistor Ts3 is electrically connected to the output end of the second switch transistor Ts2 .

[0073] Continuing to refer to FIG. 4 , the first frequency dividing module 30 includes a first frequency dividing transistor Tf1 , a second frequency dividing transistor Tf2 , and a second capacitor C2 .

[0074] The control terminal of the first frequency-dividing transistor Tf1 is electrically connected to the second node K2 of the current-stage gate driving circuit, and the input terminal of the first frequency-dividing transistor Tf1 is electrically connected to the corresponding frequency-dividing control line FL.

[0075] The control end of the second frequency dividing transistor Tf2 is electrically connected to the output end of the first frequency dividing transistor Tf1 , the input end of the second frequency dividing transistor Tf2 is electrically connected to the first node K1 , and the output end of the second frequency dividing transistor Tf2 is electrically connected to the corresponding first output module 20 .

[0076] A first end of the second capacitor C2 is electrically connected to the control end of the second frequency-dividing transistor Tf2 , and a second end of the second capacitor C2 is electrically connected to the output end of the second frequency-dividing transistor Tf2 .

[0077] Optionally, the multiple frequency division control lines FL include a first frequency division control line FL1, and the input terminals of the first frequency division transistors Tf1 of the multiple gate driving circuits GA are electrically connected to the first frequency division control line FL1 to reduce the number of frequency division control lines FL used by the gate driving unit GM.

[0078] Optionally, a first frequency dividing module 30 may be provided corresponding to each first output module 20, so that each first output module 20 controls the level of the first gate control signal Pscan outputted by the first frequency dividing module 30. Accordingly, a different frequency dividing control signal is applied to each first output module 20, so that the level of the first gate control signal Pscan outputted by each first output module 20 in the same gate drive circuit GA can be independently controlled.

[0079] For example, the gate drive circuit GA includes two first output modules 20 and two first frequency division modules 30. The two first output modules 20 include a first sub-output module 201 and a second sub-output module 202, and the two first frequency division modules 30 include a first sub-frequency division module and a second sub-frequency division module. The first sub-frequency division module is configured to control the level of the first gate control signal Pscan output by the first sub-output module 201, and the second sub-frequency division module is configured to control the level of the first gate control signal Pscan output by the second sub-output module 202. Therefore, the first sub-frequency division module of the multi-stage gate drive circuit GA can be connected to one frequency division control line FL, and the second sub-frequency division module of the multi-stage gate drive circuit GA can be connected to another frequency division control line FL.

[0080] To further reduce the layout space occupied by the display driving circuit, the same gate driving circuit GA can output a second gate control signal Nscan in addition to a plurality of first gate control signals Pscan with phase differences, thereby widening the applicable range of the gate driving unit GM.

[0081] Continuing to refer to FIG. 2 , each gate driving circuit GA further includes a second output module 50 and a second frequency dividing module 60 .

[0082] The second output module 50 is electrically connected to the first node K1 , and is configured to output a second gate control signal Nscan according to the corresponding frequency-divided control signal and the signal at the first node K1 .

[0083] The second frequency dividing module 60 is electrically connected to the first node K1, the second node K2 and the second output module 50. The second frequency dividing module 60 is configured to control signal transmission between the first node K1 and the second output module 50 according to the corresponding frequency dividing control signal and the signal of the second node K2.

[0084] Optionally, please continue to refer to FIG. 4 , the second frequency dividing module 60 includes a third frequency dividing transistor Tf3 , a fourth frequency dividing transistor Tf4 and a third capacitor C3 .

[0085] The control terminal of the third frequency-dividing transistor Tf3 is electrically connected to the second node K2 , and the input terminal of the third frequency-dividing transistor Tf3 is electrically connected to the corresponding frequency-dividing control line FL.

[0086] The control terminal of the fourth frequency-dividing transistor Tf4 is electrically connected to the output terminal of the third frequency-dividing transistor Tf3 , the input terminal of the fourth frequency-dividing transistor Tf4 is electrically connected to the first node K1 , and the output terminal of the fourth frequency-dividing transistor Tf4 is electrically connected to the corresponding second output module 50 ;

[0087] A first end of the third capacitor C3 is electrically connected to the control end of the fourth frequency-dividing transistor Tf4 , and a second end of the third capacitor C3 is electrically connected to the output end of the fourth frequency-dividing transistor Tf4 .

[0088] Optionally, in order to reduce the number of frequency division control lines FL used by the gate driving unit GM and to achieve independent control of the level states of the first gate control signal Pscan and the second gate control signal Nscan output by the gate driving unit GM, in the same gate driving circuit GA, the first frequency division module 30 and the second frequency division module 60 provide corresponding frequency division control signals through different frequency division control lines FL.

[0089] That is, the plurality of frequency-dividing control lines FL include a second frequency-dividing control line FL2 , and the input terminals of the third frequency-dividing transistors Tf3 of the plurality of gate driving circuits GA are electrically connected to the second frequency-dividing control line FL2 .

[0090] Continuing to refer to FIG. 4 , the second output module 50 includes a third output transistor To3 and a fourth output transistor To4 .

[0091] The control end of the third output transistor To3 is electrically connected to the output end of the fourth frequency-dividing transistor Tf4, the input end of the third output transistor To3 is electrically connected to the second power supply end NVGH, and the output end of the third output transistor To3 is electrically connected to the second output end Nout of the current-stage gate drive circuit GA that outputs the second gate control signal Nscan.

[0092] The control end of the fourth output transistor To4 is electrically connected to the first node K1 , the input end of the fourth output transistor To4 is electrically connected to the third power end NVGL, and the output end of the fourth output transistor To4 is electrically connected to the second output end Nout.

[0093] Optionally, referring to FIG. 2 , at least one gate driving circuit GA includes a second control module 70 , which is configured to control signal transmission between the first power supply terminal PVGH and the second output module 50 according to the corresponding first clock signal XCK and the potential of the second node K2 .

[0094] Optionally, please continue to refer to FIG. 4 , the second control module 70 includes a fourth switch transistor Ts4 and a fifth switch transistor Ts5 .

[0095] A control terminal of the fourth switch transistor Ts4 receives the corresponding first clock signal XCK, and an input terminal of the fourth switch transistor Ts4 is electrically connected to the input terminal of the third output transistor To3 .

[0096] The control terminal of the fifth switch transistor Ts5 is electrically connected to the second node K2 , the input terminal of the fifth switch transistor Ts5 is electrically connected to the first power terminal PVGH, and the output terminal of the fifth switch transistor Ts5 is electrically connected to the output terminal of the fourth switch transistor Ts4 .

[0097] Continuing to refer to FIG. 4 , the node control module 10 includes a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , and a sixth transistor T6 .

[0098] The control terminal of the first transistor T1 is configured to receive a corresponding start-up signal STV, and the input terminal of the first transistor T1 is electrically connected to the third power terminal NVGL or the fourth power terminal PVGL.

[0099] The control end of the second transistor T2 is electrically connected to the first control end of the first transistor T1 , the input end of the second transistor T2 is electrically connected to the first power end PVGH, and the output end of the second transistor T2 is electrically connected to the output end of the first transistor T1 .

[0100] The control end of the third transistor T3 is configured to receive the corresponding first clock signal XCK, the input end of the third transistor T3 is electrically connected to the output end of the first transistor T1 , and the output end of the third transistor T3 is electrically connected to the first node K1 .

[0101] The control end of the fourth transistor T4 is electrically connected to the first node K1 , the input end of the fourth transistor T4 is electrically connected to the fourth power supply end PVGL, and the output end of the fourth transistor T4 is electrically connected to the second node K2 .

[0102] The control end of the fifth transistor T5 is electrically connected to the first node K1 , the input end of the fifth transistor T5 is electrically connected to the first power end PVGH, and the output end of the fifth transistor T5 is electrically connected to the second node K2 .

[0103] The control end of the sixth transistor T6 is electrically connected to the second node K2 , the input end of the sixth transistor T6 is electrically connected to the third power supply end NVGL, and the output end of the sixth transistor T6 is electrically connected to the first node K1 .

[0104] Optionally, the first-stage gate driving circuit GA(1) among the plurality of gate driving circuits GA uses the start signal stv as the start signal STV, as shown in FIG. 3A to FIG. 3E , so that the first-stage gate driving circuit GA(1) controls the signal transmitted to the first node K1 according to the corresponding first clock signal XCK and the start signal stv.

[0105] Optionally, an n-th-stage gate driver circuit GA(n) among the multiple gate driver circuits GA uses the nA-th-stage second gate control signal Nscan(nA) output by the nA-th-stage gate driver circuit GA(nA) as a start signal STV, so that the n-th-stage gate driver circuit GA(n) controls the signal transmitted to the first node K1 of the n-th-stage gate driver circuit GA(n) according to the corresponding first clock signal XCK and the nA-th-stage second gate control signal Nscan(nA) output by the nA-th-stage gate driver circuit GA(nA). Where n>1, A≥1.

[0106] Optionally, to reduce the load corresponding to the second output terminal Nout of the gate drive circuit GA, the n-th gate drive circuit GA(n) among the multiple gate drive circuits GA controls the signal transmitted to the first node K1 of the n-th gate drive circuit GA(n) based on the corresponding first clock signal XCK and the potential of the second node K2 of the nA-th gate drive circuit GA(nA). As shown in FIG4 , the p-th gate drive circuit GA(n) controls the signal transmitted to the first node K1 of the p-th gate drive circuit GA(p) based on the corresponding first clock signal XCK and the potential of the second node K2(p-1) of the p-1-th gate drive circuit GA(p-1).

[0107] Optionally, please continue to refer to FIG. 4 , the node control module 10 includes a seventh transistor T7 and an eighth transistor T8 .

[0108] The control terminal of the seventh transistor T7 is configured to receive the corresponding first clock signal XCK, and the output terminal of the seventh transistor T7 is electrically connected to the first node K1.

[0109] The control end of the eighth transistor T8 is electrically connected to the second node K2 , the input end of the eighth transistor T8 is electrically connected to the first power end PVGH, and the output end of the eighth transistor T8 is electrically connected to the input end of the seventh transistor T7 .

[0110] Optionally, referring to FIG. 4 , at least one gate driving circuit GA further includes a reset module 80 electrically connected to the first node K1. The reset module 80 is configured to control signal transmission between the first power terminal PVGH and the first node K1 according to a reset control signal Ctl.

[0111] Optionally, the reset module includes a reset transistor Tre, a control terminal of the reset transistor Tre is configured to receive a reset control signal Ctl, an input terminal of the reset transistor Tre is electrically connected to the first power terminal PVGH, and an output terminal of the reset transistor Tre is electrically connected to the first node K1.

[0112] Optionally, when the gate driving unit GM is applied to a display device, the reset module 80 is configured to be enabled when the display device is powered on and / or during a blanking interval.

[0113] It is understandable that each transistor included in the gate driving circuit GA may be one of a P-type transistor and an N-type transistor. The semiconductor of each transistor included in the gate driving circuit GA may be one of a silicon semiconductor and an oxide semiconductor.

[0114] Optionally, in some embodiments, at least one of the first transistor T1 , the fourth transistor T4 , the sixth transistor T6 , the seventh transistor T7 , the second switch transistor Ts2 , the fourth switch transistor Ts4 and the fourth output transistor To4 may have only one or two control terminals.

[0115] Optionally, in some embodiments, the first transistor T1 , the fourth transistor T4 , the sixth transistor T6 , the seventh transistor T7 , the second switch transistor Ts2 , the fourth switch transistor Ts4 and the fourth output transistor To4 are N-type transistors, and the remaining transistors are P-type transistors.

[0116] Optionally, in some embodiments, the voltage corresponding to the fourth power terminal PVGL is smaller than the voltage corresponding to the first power terminal PVGH, and the voltage corresponding to the third power terminal NVGL is smaller than the voltage corresponding to the second power terminal NVGH.

[0117] 5A to 5E are timing diagrams of a corresponding gate drive circuit GA provided in an embodiment of the present application, wherein the second transistor T2, the third transistor T3, the fifth transistor T5, the eighth transistor T8, the first switch transistor Ts1, the third switch transistor Ts3, the fifth switch transistor Ts5, the first frequency-dividing transistor Tf1 to the fourth frequency-dividing transistor Tf4, and the first output transistor To1 to the third output transistor To3 are P-type transistors, and the first transistor T1, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the second switch transistor Ts2, the fourth switch transistor Ts4, and the fourth output transistor To4 are N-type transistors. The multi-stage gate drive circuit GA includes two first output modules 20, the two first output modules 20 share a first frequency-dividing module 30, the two first output modules 20 include a first sub-output module 201 and a second sub-output module 202, and the third clock line CKL3 is sent to the first of the p-stage gate drive circuit GA(p). The sub-output module 201 transmits the corresponding second clock signal CK, the fourth clock line CKL4 transmits the corresponding second clock signal CK to the second sub-output module 202 of the p-th level gate drive circuit GA(p), the first clock line CKL1 transmits the corresponding second clock signal CK to the first sub-output module 201 of the p+1-th level gate drive circuit GA(p+1), and the second clock line CKL2 transmits the corresponding second clock signal CK to the second sub-output module 202 of the p+1-th level gate drive circuit GA(p+1); the first clock line CKL1 or the sixth clock line CKL6 transmits the corresponding first clock signal XCK to the p-th level gate drive circuit GA(p), and the third clock line CKL3 or the fifth clock line CKL5 transmits the corresponding first clock signal XCK to the p+1-th level gate drive circuit GA(p+1). The multi-level gate drive circuit GA adopts the design method shown in Figure 3A or Figure 3B to illustrate the working principle of the gate drive unit GM. Among them, the second output module 50 of the p-th level gate drive circuit GA outputs the p-th level second gate control signal Nscan(p), the first sub-output module 201 of the p-th level gate drive circuit GA outputs the q-th level first gate control signal Pscan(q), and the second sub-output module 202 of the p-th level gate drive circuit GA outputs the q+1-th level first gate control signal Pscan(q+1); p≥1, q=2p-1.

[0118] Continuing with Figures 3A-3B, 4, and 5A, in the first phase t1, the first clock signal CK1 transmitted by the first clock line CKL1 and the sixth clock signal CK6 transmitted by the sixth clock line CKL6 are at a low level, the second clock signal CK2 transmitted by the second clock line CKL2 is at a high level, the third clock signal CK3 transmitted by the third clock line CKL3 and the fifth clock signal CK5 transmitted by the fifth clock line CKL5 are at a high level, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 is at a high level. The second node K2(p-1) of the p-1-th gate driver circuit GA(p-1) and the second node K2(p-2) of the p-2-th gate driver circuit GA(p-2) are at a high level. The first frequency division control signal FD1 transmitted by the first frequency division control line FL1 and the second frequency division control signal FD2 transmitted by the second frequency division control line FL2 are at a low level.

[0119] In the p-th stage gate drive circuit GA(p), the first transistor T1, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the third output transistor To3, the second frequency-dividing transistor Tf2, and the fourth frequency-dividing transistor Tf4 are turned on, and the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, the first switching transistor Ts1, the second switching transistor Ts2, the third switching transistor Ts3, the fourth switching transistor Ts4, the fifth switching transistor Ts5, the first frequency-dividing transistor Tf1, the third frequency-dividing transistor Tf3, the fourth output transistor To4, the first output transistor To1, and the second output transistor To2 are turned off. The p-th stage second gate control signal Nscan(p), the q-th stage first gate control signal Pscan(q), and the q+1-th stage first gate control signal Pscan(q+1) are all high.

[0120] In the p+1-th stage gate drive circuit GA(p+1), the first transistor T1 is turned on, the third transistor T3 is turned off, the p+1-th stage second gate control signal Nscan(p+1) maintains a low level, the q+2-th stage first gate control signal Pscan(q+2) and the q+3-th stage first gate control signal Pscan(q+3) maintain a high level. In the p+2-th stage gate drive circuit GA(p+2), the second transistor T2 is turned on, the third transistor T3 is turned off, the p+2-th stage second gate control signal Nscan(p+2) maintains a low level, the q+4-th stage first gate control signal Pscan(q+4) and the q+5-th stage first gate control signal Pscan(q+5) maintain a high level. The p+3th level second gate control signal Nscan(p+2) to the p+6th level second gate control signal Nscan(p+6) maintain a low level, and the q+6th level first gate control signal Pscan(q+6) to the q+13th level first gate control signal Pscan(q+13) maintain a high level.

[0121] Phase 2 t2: The first clock signal CK1 and the sixth clock signal CK6 are high, the second clock signal CK2 is high, the third clock signal CK3 and the fifth clock signal CK5 are low, and the fourth clock signal CK4 is high. The second node K2(p-1) of the p-1th gate driver circuit GA(p-1) and the second node K2(p-2) of the p-2th gate driver circuit GA(p-2) are high. The first frequency division control signal FD1 and the second frequency division control signal FD2 are low.

[0122] In the p-th stage gate drive circuit GA(p), the first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the third output transistor To3, the second frequency-dividing transistor Tf2, the fourth frequency-dividing transistor Tf4, the second switch transistor Ts2, and the fourth switch transistor Ts4 are turned on, and the second transistor T2, the third transistor T3, the fourth transistor T4, the eighth transistor T8, the first switch transistor Ts1, the third switch transistor Ts3, the fifth switch transistor Ts5, the first frequency-dividing transistor Tf1, the third frequency-dividing transistor Tf3, the fourth output transistor To4, the first output transistor To1, and the second output transistor To2 are turned off. The p-th stage second gate control signal Nscan(p), the q-th stage first gate control signal Pscan(q), and the q+1-th stage first gate control signal Pscan(q+1) are all high.

[0123] The p+1th level gate drive circuit GA(p+1) performs actions similar to those performed by the p-th level gate drive circuit GA(p) in the first stage t1 in the second stage t2, the p+2th level gate drive circuit GA(p+2) performs actions similar to those performed by the p+1th level gate drive circuit GA(p+1) in the first stage t1 in the second stage t2, and so on, to obtain the actions performed by the p+3th level gate drive circuit GA(p+3) to the p+6th level gate drive circuit GA(p+6) in the second stage t2.

[0124] Phase 3 t3: The first clock signal CK1 and the sixth clock signal CK6 are high, the second clock signal CK2 is high, the third clock signal CK3 and the fifth clock signal CK5 are low, and the fourth clock signal CK4 is high. The second node K2(p-1) of the p-1th gate driver circuit GA(p-1) and the second node K2(p-2) of the p-2th gate driver circuit GA(p-2) are low. The first frequency division control signal FD1 and the second frequency division control signal FD2 are low.

[0125] In the p-th stage gate drive circuit GA(p), the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the first switching transistor Ts1, the second switching transistor Ts2, the fourth switching transistor Ts4, the second frequency-dividing transistor Tf2, the fourth frequency-dividing transistor Tf4, the third output transistor To3, and the first output transistor To1 are turned on, and the first transistor T1, the third transistor T3, the fourth transistor T4, the eighth transistor T8, the third switching transistor Ts3, the fifth switching transistor Ts5, the first frequency-dividing transistor Tf1, the third frequency-dividing transistor Tf3, the fourth output transistor To4, and the second output transistor To2 are turned off. The p-th stage second gate control signal Nscan(p) and the q+1-th stage first gate control signal Pscan(q+1) are high, and the q-th stage first gate control signal Pscan(q) is low.

[0126] In the p+1th level gate drive circuit GA(p+1), the first transistor T1, the third transistor T3, and the first switching transistor Ts1 are turned on, and thus, the first output transistor To1 and the third output transistor To3 are turned on, and the p+1th level second gate control signal Nscan(p+1), the q+2th level first gate control signal Pscan(q+2), and the q+3th level first gate control signal Pscan(q+3) maintain a high level.

[0127] The p+2-th level gate drive circuit GA(p+2) performs actions similar to those performed by the p-th level gate drive circuit GA(p) in the second stage t2 in the third stage t3, the p+3-th level gate drive circuit GA(p+3) performs actions similar to those performed by the p+1-th level gate drive circuit GA(p+1) in the second stage t2 in the third stage t3, and so on, to obtain the actions performed by the p+3-th level gate drive circuit GA(p+3) to the p+6-th level gate drive circuit GA(p+6) in the second stage t2.

[0128] The fourth stage t4: the first clock signal CK1 and the sixth clock signal CK6 have a high level, the second clock signal CK2 has a high level, the third clock signal CK3 and the fifth clock signal CK5 have a high level, the fourth clock signal CK4 has a low level, the second node K2(p-1) of the p-1th level gate drive circuit GA(p-1) ~ the second node K2(p-2) of the p-2th level gate drive circuit GA(p-2) have a low level, and the first frequency division control signal FD1 and the second frequency division control signal FD2 have a low level.

[0129] In the p-th stage gate drive circuit GA(p), the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the first switching transistor Ts1, the second switching transistor Ts2, the fourth switching transistor Ts4, the second frequency-dividing transistor Tf2, the fourth frequency-dividing transistor Tf4, the third output transistor To3, and the first output transistor To1 are turned on, and the first transistor T1, the third transistor T3, the fourth transistor T4, the eighth transistor T8, the third switching transistor Ts3, the fifth switching transistor Ts5, the first frequency-dividing transistor Tf1, the third frequency-dividing transistor Tf3, the fourth output transistor To4, and the second output transistor To2 are turned off. The p-th stage second gate control signal Nscan(p) and the q-th stage first gate control signal Pscan(q) have a high level, and the q+1-th stage first gate control signal Pscan(q+1) has a low level.

[0130] In the p+1th level gate drive circuit GA(p+1), the second transistor T2 and the third transistor T3 are turned off, the first output transistor To1 and the third output transistor To3 are turned on, and the p+1th level second gate control signal Nscan(p+1), the q+2th level first gate control signal Pscan(q+2) and the q+3th level first gate control signal Pscan(q+3) maintain a high level.

[0131] In the p+2-th level gate drive circuit GA(p+2) and the p+3-th level gate drive circuit GA(p+3), the second transistor T2, the third transistor T3, and the first output transistor To1 are turned off, and the third output transistor To3 is turned on. The p+2-th level second gate control signal Nscan(p+2) to the p+3-th level second gate control signal Nscan(p+3) and the q+4-th level first gate control signal Pscan(q+4) to the q+7-th level first gate control signal Pscan(q+7) maintain a high level.

[0132] In the p+4th-level gate drive circuit GA(p+2) to the p+6th-level gate drive circuit GA(p+3), the third transistor T3 is turned off, the second output transistor To2 and the fourth output transistor To4 are turned on, and the p+4th-level second gate control signal Nscan(p+4) to the p+6th-level second gate control signal Nscan(p+6) and the q+8th-level first gate control signal Pscan(q+8) to the q+13th-level first gate control signal Pscan(q+13) maintain a high level.

[0133] Fifth stage t5: the first clock signal CK1 and the sixth clock signal CK6 have a low level, the second clock signal CK2 has a high level, the third clock signal CK3 and the fifth clock signal CK5 have a high level, the fourth clock signal CK4 has a high level, the second node K2(p-1) of the p-1th level gate drive circuit GA(p-1) ~ the second node K2(p-2) of the p-2th level gate drive circuit GA(p-2) have a low level, and the first frequency division control signal FD1 and the second frequency division control signal FD2 have a low level.

[0134] In the p-th stage gate drive circuit GA(p), the second transistor T2, the third transistor T3, the fourth transistor T4, the eighth transistor T8, the first switching transistor Ts1, the third switching transistor Ts3, the fifth switching transistor Ts5, the second output transistor To2, the fourth output transistor To4, and the first to fourth frequency-dividing transistors Tf1 to Tf4 are turned on. The first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the second switching transistor Ts2, the fourth switching transistor Ts4, the first output transistor To1, and the third output transistor To3 are turned off. The p-th stage second gate control signal Nscan(p) has a low level, and the q-th stage first gate control signal Pscan(q) and the q+1-th stage first gate control signal Pscan(q+1) have a high level.

[0135] The p+1th level gate drive circuit GA(p+1) performs an action similar to the action performed by the p-th level gate drive circuit GA(p) in the third stage t3 in the fifth stage t5, the p+2th level gate drive circuit GA(p+2) performs an action similar to the action performed by the p+1th level gate drive circuit GA(p+1) in the third stage t3 in the fifth stage t5, and so on, to obtain the actions performed by the p+3th level gate drive circuit GA(p+3) to the p+6th level gate drive circuit GA(p+6) in the second stage t2.

[0136] The sixth stage t6: the first clock signal CK1 and the sixth clock signal CK6 have a high level, the second clock signal CK2 has a low level, the third clock signal CK3 and the fifth clock signal CK5 have a high level, the fourth clock signal CK4 has a high level, the second node K2(p-1) of the p-1th level gate drive circuit GA(p-1) ~ the second node K2(p-2) of the p-2th level gate drive circuit GA(p-2) have a low level, the first frequency division control signal FD1 has a high level, and the second frequency division control signal FD2 has a low level.

[0137] In the p-th stage gate driving circuit GA(p), the third transistor T3 is turned off, the p-th stage second gate control signal Nscan(p) has a low level, and the q-th stage first gate control signal Pscan(q) and the q+1-th stage first gate control signal Pscan(q+1) have a high level.

[0138] The p+1-th stage gate driver circuit GA(p+1) performs an operation similar to the operation performed by the p-th stage gate driver circuit GA(p) in the fourth stage t4 during the sixth stage t6. The p+2-th stage gate driver circuit GA(p+2) performs an operation similar to the operation performed by the p+1-th stage gate driver circuit GA(p+1) in the fourth stage during the sixth stage t6. The p+3-th stage gate driver circuit GA(p+3) performs an operation similar to the operation performed by the p+2-th stage gate driver circuit GA(p+2) in the fourth stage t4 during the sixth stage t6. The p+4-th stage gate driver circuit GA(p+4) performs an operation similar to the operation performed by the p+3-th stage gate driver circuit GA(p+3) in the fourth stage t4 during the sixth stage t6.

[0139] In the p+5th stage gate drive circuit GA(p+5), the first transistor T1, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, the second switching transistor Ts2, the fourth switching transistor Ts4, the fifth switching transistor Ts5, the third switching transistor Ts3, the second output transistor To2, the fourth output transistor To4, the first frequency-dividing transistor Tf1, the third frequency-dividing transistor Tf3, and the fourth frequency-dividing transistor Tf4 are turned on. The second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the first switching transistor Ts1, the second frequency-dividing transistor Tf2, the first output transistor To1, and the third output transistor To3 are turned off. The p+5th stage second gate control signal Nscan(p+5) has a low level, and the q+10th stage first gate control signal Pscan(q+10) and the q+11th stage first gate control signal Pscan(q+11) have a high level.

[0140] In the p+6th-stage gate drive circuit GA(p+6), the second transistor T2, the second output transistor To2, and the fourth output transistor To4 are turned on, and the third transistor T3, the first output transistor To1, and the third output transistor To3 are turned off. The p+6th-stage second gate control signal Nscan(p+6) has a low level, and the q+12th-stage first gate control signal Pscan(q+12) and the q+13th-stage first gate control signal Pscan(q+13) have a high level.

[0141] The seventh stage t7: the first clock signal CK1 and the sixth clock signal CK6 have a high level, the second clock signal CK2 has a high level, the third clock signal CK3 and the fifth clock signal CK5 have a low level, the fourth clock signal CK4 has a high level, the second node K2(p-1) of the p-1th level gate drive circuit GA(p-1) ~ the second node K2(p-2) of the p-2th level gate drive circuit GA(p-2) have a low level, the first frequency division control signal FD1 has a high level, and the second frequency division control signal FD2 has a low level.

[0142] In the p-th stage gate driving circuit GA(p), the third transistor T3 is turned off, the p-th stage second gate control signal Nscan(p) has a low level, and the q-th stage first gate control signal Pscan(q) and the q+1-th stage first gate control signal Pscan(q+1) have a high level.

[0143] The p+1th-stage gate driver circuit GA(p+1) performs an operation similar to that performed by the p-stage gate driver circuit GA(p) in the fifth stage t5 during the seventh stage t7. The p+2th-stage gate driver circuit GA(p+2) performs an operation similar to that performed by the p+1th-stage gate driver circuit GA(p+1) in the fifth stage t5 during the seventh stage t7. The p+3th-stage gate driver circuit GA(p+3) performs an operation similar to that performed by the p+2th-stage gate driver circuit GA(p+2) in the fifth stage t5 during the fifth stage t5. The p+4th-stage gate driver circuit GA(p+4) performs an operation similar to that performed by the p+3th-stage gate driver circuit GA(p+3) in the fifth stage t5 during the seventh stage t7.

[0144] In the p+5th stage gate drive circuit GA(p+5), the first transistor T1, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the fourth frequency-dividing transistor Tf4, and the third output transistor To3 are turned on, and the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, the first switching transistor Ts1, the second switching transistor Ts2, the third switching transistor Ts3, the fourth switching transistor Ts4, the fifth switching transistor Ts5, the first frequency-dividing transistors Tf1 to Tf3, the fourth output transistor To4, the first output transistor To1, and the second output transistor To2 are turned off. The p+5th stage second gate control signal Nscan(p+5), the q+10th stage first gate control signal Pscan(q+10), and the q+11th stage first gate control signal Pscan(q+11) are all high.

[0145] In the p+6th stage gate drive circuit GA(p+6), the first transistor T1, the second output transistor To2, and the fourth output transistor To4 are turned on, and the third transistor T3, the first output transistor To1, and the third output transistor To3 are turned off. The p+6th stage second gate control signal Nscan(p+6) has a low level, and the q+12th stage first gate control signal Pscan(q+12) and the q+13th stage first gate control signal Pscan(q+13) have a high level.

[0146] The eighth stage t8: the first clock signal CK1 and the sixth clock signal CK6 have a low level, the second clock signal CK2 has a high level, the third clock signal CK3 and the fifth clock signal CK5 have a high level, the fourth clock signal CK4 has a high level, the second node K2(p-1) of the p-1th level gate drive circuit GA(p-1) ~ the second node K2(p-2) of the p-2th level gate drive circuit GA(p-2) have a low level, the first frequency division control signal FD1 has a high level, and the second frequency division control signal FD2 has a low level.

[0147] The pth-stage second gate control signal Nscan(p) to the p+4th-stage second gate control signal Nscan(p+4) have a low level, and the q+1th-stage first gate control signal Pscan(q+1) to the q+9th-stage first gate control signal Pscan(q+9) have a high level.

[0148] In the p+5th stage gate drive circuit GA(p+5), the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the first switch transistor Ts1, the second switch transistor Ts2, the fourth switch transistor Ts4, and the third output transistor To3 are turned on, while the first transistor T1, the third transistor T3, the fourth transistor T4, the eighth transistor T8, the third switch transistor Ts3, the fifth switch transistor Ts5, the first frequency-dividing transistors Tf1 to Tf4, the fourth output transistor To4, the first output transistor To1, and the second output transistor To2 are turned off. The p+5th stage second gate control signal Nscan(p+5) and the q+10th stage first gate control signal Pscan(q+10) to the q+11th stage first gate control signal Pscan(q+11) are all high.

[0149] In the p+6th level gate drive circuit GA(p+6), the first transistor T1 is turned on, the third transistor T3, the p+6th level second gate control signal Nscan(p+6), the q+12th level first gate control signal Pscan(q+12) and the q+13th level first gate control signal Pscan(q+13) have a high level.

[0150] Ninth stage t9: the first clock signal CK1 and the sixth clock signal CK6 have a high level, the second clock signal CK2 has a low level, the third clock signal CK3 and the fifth clock signal CK5 have a high level, the fourth clock signal CK4 has a high level, the second node K2(p-1) of the p-1th level gate drive circuit GA(p-1) ~ the second node K2(p-2) of the p-2th level gate drive circuit GA(p-2) have a low level, the first frequency division control signal FD1 has a high level, and the second frequency division control signal FD2 has a low level.

[0151] The pth-stage second gate control signal Nscan(p) to the p+4th-stage second gate control signal Nscan(p+4) have a high level, and the q+1th-stage first gate control signal Pscan(q+1) to the q+9th-stage first gate control signal Pscan(q+9) have a high level.

[0152] The p+5th stage gate driver circuit GA(p+5) performs operations similar to those performed in the eighth stage t8 during the ninth stage t9. The p+5th stage second gate control signal Nscan(p+5) is at a low level, and the q+10th stage first gate control signal Pscan(q+10) to the q+11th stage first gate control signal Pscan(q+11) are at a high level. The p+6th stage gate driver circuit GA(p+6) performs operations similar to those performed in the eighth stage t8 during the ninth stage t9. The p+6th stage second gate control signal Nscan(p+6), the q+12th stage first gate control signal Pscan(q+12), and the q+13th stage first gate control signal Pscan(q+13) are at a high level.

[0153] Therefore, according to the analysis of FIG5A , by controlling the first frequency-dividing control signal FD1 to jump from a low-level active level state to a high-level inactive level state, the multiple gate drive circuits GA can be caused to change from outputting a low-level first gate control signal Pscan to outputting a non-low-level first gate control signal Pscan. Therefore, by controlling the level state of the first frequency-dividing control signal FD1, the level states of the multiple first gate control signals Pscan can be controlled to control whether the first gate control signals Pscan output by the multiple gate drive circuits GA have valid pulses. By adjusting the level change timing of the first frequency-dividing control signal FD1, the multi-stage first gate control signals Pscan can be controlled to not have valid pulses at the beginning of corresponding different stages.

[0154] Similarly, the corresponding working principles of the plurality of gate driving circuits GA when the first frequency-dividing control signal FD1 changes from a high level to a low level can also be obtained.

[0155] Continuing to refer to Figures 3A to 3B, 4, and 5B, when the second frequency-dividing control signal FD2 is at a low level and the first frequency-dividing control signal FD1 is at a low level, the operating principles of the p-th stage gate driver circuit GA(p) to the p+6-th stage gate driver circuit GA(p+6) corresponding to the first stage t1 to the fifth stage t5 can be understood by referring to the description corresponding to the first stage t1 to the fifth stage t5 in Figure 5A. Therefore, the description of the transition of the second frequency-dividing control signal FD2 from a low level to a high level will begin with the sixth stage t6 in Figure 5B.

[0156] In the sixth stage t6, the first clock signal CK1 and the sixth clock signal CK6 have a high level, the second clock signal CK2 has a low level, the third clock signal CK3 and the fifth clock signal CK5 have a high level, the fourth clock signal CK4 has a high level, the second node K2(p-1) of the p-1th level gate drive circuit GA(p-1) to the second node K2(p-2) of the p-2th level gate drive circuit GA(p-2) have a low level, the first frequency division control signal FD1 has a high level, and the second frequency division control signal FD2 has a low level.

[0157] The p-th stage second gate control signal Nscan(p) has a low level, and the q-th stage first gate control signal Pscan(q) and the q+1-th stage first gate control signal Pscan(q+1) have a high level.

[0158] In the p+1th level gate drive circuit GA(p+1) to the p+4th level gate drive circuit GA(p+4), the second frequency-dividing transistor Tf2, the fourth frequency-dividing transistor Tf4, and the third output transistor To3 are turned on, the p+1th level second gate control signal Nscan(p+1) to the p+4th level second gate control signal Nscan(p+4) have a high level, the q+2th level first gate control signal Pscan(p+2) and the q+4th level first gate control signal Pscan(p+4) to the p+13th level first gate control signal Pscan(p+13) have a high level, and the q+3th level first gate control signal Pscan(p+3) has a low level.

[0159] In the p+5th stage gate drive circuit GA(p+5), the first transistor T1, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, the second switching transistor Ts2, the fourth switching transistor Ts4, the fifth switching transistor Ts5, the third switching transistor Ts3, the second output transistor To2, the fourth output transistor To4, and the first to third frequency-dividing transistors Tf1 to Tf3 are turned on. The second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the first switching transistor Ts1, the fourth frequency-dividing transistor Tf4, the first output transistor To1, and the third output transistor To3 are turned off. The p+5th stage second gate control signal Nscan(p+5) has a low level, and the q+10th stage first gate control signal Pscan(q+10) and the q+11th stage first gate control signal Pscan(q+11) have a high level.

[0160] In the p+6th-stage gate drive circuit GA(p+6), the second transistor T2, the second output transistor To2, and the fourth output transistor To4 are turned on, and the third transistor T3, the first output transistor To1, and the third output transistor To3 are turned off. The p+6th-stage second gate control signal Nscan(p+6) has a low level, and the q+12th-stage first gate control signal Pscan(q+12) and the q+13th-stage first gate control signal Pscan(q+13) have a high level.

[0161] The seventh stage t7: the first clock signal CK1 and the sixth clock signal CK6 have a high level, the second clock signal CK2 has a high level, the third clock signal CK3 and the fifth clock signal CK5 have a low level, the fourth clock signal CK4 has a high level, the second node K2(p-1) of the p-1th level gate drive circuit GA(p-1) ~ the second node K2(p-2) of the p-2th level gate drive circuit GA(p-2) have a low level, the first frequency division control signal FD1 has a high level, and the second frequency division control signal FD2 has a low level.

[0162] The p-th level second gate control signal Nscan(p) to the p+1-th level second gate control signal Nscan(p+1) have a low level, the q-th level first gate control signal Pscan(q) to the q+3-th level first gate control signal Pscan(q+3) have a high level, the q+5-th level first gate control signal Pscan(p+5) to the p+13-th level first gate control signal Pscan(p+13) have a high level, and the q+4-th level first gate control signal Pscan(p+4) has a low level.

[0163] In the p+5th stage gate drive circuit GA(p+5), the first transistor T1, the third transistor T3, the fifth transistor T5, the sixth transistor T6, and the second frequency-dividing transistor Tf2 are turned on, and the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, the first switching transistor Ts1, the second switching transistor Ts2, the third switching transistor Ts3, the fourth switching transistor Ts4, the fifth switching transistor Ts5, the first frequency-dividing transistor Tf1, the third frequency-dividing transistor Tf3, the fourth frequency-dividing transistor Tf4, the third output transistor To3, the fourth output transistor To4, the first output transistor To1, and the second output transistor To2 are turned off. The p+5th stage second gate control signal Nscan(p+5) has a low level, and the q+10th stage first gate control signal Pscan(q+10) and the q+11th stage first gate control signal Pscan(q+11) have a high level.

[0164] In the p+6th-stage gate drive circuit GA(p+6), the second transistor T2, the second output transistor To2, and the fourth output transistor To4 are turned on, and the third transistor T3, the first output transistor To1, and the third output transistor To3 are turned off. The p+6th-stage second gate control signal Nscan(p+6) has a low level, and the q+12th-stage first gate control signal Pscan(q+12) and the q+13th-stage first gate control signal Pscan(q+13) have a high level.

[0165] Therefore, according to the analysis of FIG5B , by controlling the second frequency-dividing control signal FD2 to jump from a low-level active level state to a high-level inactive level state, the multiple gate drive circuits GA can be caused to change from outputting a low-level second gate control signal Nscan to outputting a non-low-level second gate control signal Nscan. Thus, by controlling the level state of the second frequency-dividing control signal FD2, the level states of the multiple second gate control signals Nscan can be controlled to control whether the second gate control signals Nscan output by the multiple gate drive circuits GA have valid pulses. By adjusting the level change moment of the second frequency-dividing control signal FD2, the multi-stage second gate control signals Nscan can be controlled to not have valid pulses at the beginning of corresponding different stages.

[0166] Similarly, the corresponding working principles of the plurality of gate driving circuits GA when the second frequency-dividing control signal FD2 changes from a high level to a low level can also be obtained.

[0167] Similarly, referring to the analysis of FIG. 5A and FIG. 5B , it can be seen that when the gate drive circuit GA includes three first output modules 20 and adopts the design shown in FIG. 3C , the timing of the plurality of first gate control signals Pscan and the second gate control signal Nscan is shown in FIG. 5C , where CK7 is the clock signal transmitted by the seventh clock line CKL7 , and CK8 is the clock signal transmitted by the eighth clock line CKL8 .

[0168] Similarly, referring to the analysis of FIG. 5A to FIG. 5B , it can be obtained that the gate drive circuit GA includes three first output modules 20, and when the design shown in FIG. 3D is adopted, the timing of multiple first gate control signals Pscan and second gate control signals Nscan is shown in FIG. 5D .

[0169] Similarly, referring to the analysis of FIG. 5A to FIG. 5B , it can be obtained that the gate drive circuit GA includes three first output modules 20, and when the design shown in FIG. 3E is adopted, the timing of multiple first gate control signals Pscan and second gate control signals Nscan is shown in FIG. 5E .

[0170] It can be understood that in the same gate drive circuit GA, when multiple first output modules 20 are controlled using multiple first frequency-division control signals FD1, the multiple first frequency-division control signals FD1 can be independent of each other in the transition moments between the low level and the high level, so as to achieve independent control of whether the first gate control signal Pscan output by each first output module 20 has a valid level.

[0171] It can be understood that the level change time of the second frequency-division control signal FD2 may be the same as or different from the level change time of the first frequency-division control signal FD1 .

[0172] It can be understood that by adjusting the level change moments of the second frequency-division control signal FD2 and the first frequency-division control signal FD1 , the display panel using the gate driving unit GM can achieve frequency-division control at different positions.

[0173] FIG6 is a schematic diagram of a display device provided in an embodiment of the present application. The present application further provides a display device, wherein the display device includes mobile terminals such as mobile phones, laptop computers, wearable devices, etc., and also includes televisions, desktop computers, etc.

[0174] As shown in FIG6 , the display device includes any of the above-mentioned display driving circuits Ddc and a display panel DP.

[0175] The display panel DP is electrically connected to the display driving circuit Ddc. The display panel DP includes a plurality of sub-pixels Spi. The plurality of sub-pixels Spi are used to implement a display function of the display panel DP.

[0176] The gate driving unit GM of the display driving circuit Ddc is used to provide a plurality of first gate control signals Pscan to the display panel DP, so as to control the display panel DP to realize display.

[0177] 7 is a schematic structural diagram of a pixel driving circuit provided in an embodiment of the present application. Each sub-pixel Spi includes a light-emitting device and a pixel driving circuit for driving the light-emitting device to emit light. The pixel driving circuit includes a driving transistor Tdr and a data transistor Tda.

[0178] Optionally, the light emitting device Di includes a light emitting diode. Optionally, the light emitting device Di includes an organic light emitting diode, a sub-millimeter light emitting diode, a micro light emitting diode, etc.

[0179] The driving transistor Tdr and the light emitting device Di are electrically connected between a first voltage terminal Vdd and a second voltage terminal Vss. The driving transistor Tdr is configured to generate a driving current to drive the light emitting device Di to emit light.

[0180] Optionally, the input terminal of the driving transistor Tdr is electrically connected to the first voltage terminal Vdd, the output terminal of the driving transistor Tdr is electrically connected to the anode of the light-emitting device Di, the cathode of the light-emitting device Di is electrically connected to the second voltage terminal Vss, and the voltage supplied by the first voltage terminal Vdd is greater than the voltage supplied by the second voltage terminal Vss.

[0181] The data transistor Tda is configured to transmit a data signal to the control terminal of the driving transistor Tdr. The input terminal of the data transistor Tda is configured to receive a data signal transmitted by the corresponding electrically connected data line DL, and the output terminal of the data transistor Tda is electrically connected to the input terminal of the driving transistor Tdr.

[0182] Among them, multiple first output modules 20 of the same gate drive circuit GA are electrically connected to the control ends of the data transistors Tda of multiple adjacent rows of sub-pixels Spi, and each first output module 20 is electrically connected to the control end of the data transistor Tda of at least one row of sub-pixels Spi, so as to utilize multiple first gate control signals Pscan to control the conduction state of the data transistors Tda of multiple sub-pixels Spi, thereby controlling the frequency of refreshing the display data of multiple sub-pixels Spi, so as to enable the display panel DP to realize the design of zoned and frequency-controlled display.

[0183] Optionally, each first output module 20 is electrically connected to the control end of the data transistor Tda of a row of sub-pixels Spi, and the same gate drive circuit GA includes X first output modules 20. The X first output modules 20 in the same gate drive circuit GA are electrically connected to the control ends of the data transistors Tda of the sub-pixels Spi in X adjacent rows, so that the data transistors Tda of the adjacent multiple rows of sub-pixels Spi can be turned on or off in sequence according to multiple first gate control signals Pscan with phase differences, thereby controlling the adjacent multiple rows of sub-pixels Spi to sequentially implement a data signal refresh operation when display data needs to be refreshed.

[0184] For example, each gate driving circuit GA includes two first output modules 20 , and the two first output modules 20 in the same gate driving circuit GA are electrically connected to the control terminals of the data transistors Tda of the sub-pixels Spi in two adjacent rows.

[0185] For another example, each gate driving circuit GA includes three first output modules 20 . The three first output modules 20 in the same gate driving circuit GA are electrically connected to the control terminals of the data transistors Tda of the sub-pixels Spi in three adjacent rows.

[0186] Optionally, the same gate drive circuit GA includes X first output modules 20. When each first output module 20 is electrically connected to the control terminal of the data transistor Tda of a row of sub-pixels Spi, the Kth-stage gate drive circuit GA can be electrically connected to the control terminals of the data transistors Tda of the sub-pixels Spi in the Lth to L+(X-1)th rows, so that the multiple sub-pixels Spi can be driven using a progressive scanning technique. Here, K ≥ 1, and L = XK-(X-1).

[0187] For example, the K-th level gate driver circuit GA includes two first output modules 20, each of which includes a first sub-output module 201 and a second sub-output module 202. The first sub-output module 201 is electrically connected to the control terminal of the data transistor Tda of the sub-pixel Spii located in the L-th row, and the second sub-output module 202 is electrically connected to the control terminal of the data transistor Tda of the sub-pixel Spii located in the L+1-th row, so as to provide a first gate control signal Pscan to the control terminal of the data transistor Tda of the sub-pixel Spii located in the L-th row through the first sub-output module 201 of the K-th level gate driver circuit GA, and provide a first gate control signal Pscan to the control terminal of the data transistor Tda of the sub-pixel Spii located in the L+1-th row through the second sub-output module 202 of the K-th level gate driver circuit GA. Wherein, K ≥ 1, L = 2K - 1, L is an odd number, and the sub-pixel Spii in the L-th row is adjacent to the sub-pixel Spii in the L+1-th row.

[0188] For example, the K-th stage gate driving circuit GA includes three first output modules 20, and the three first output modules 20 include a first sub-output module 201, a second sub-output module 202, and a third sub-output module. The first sub-output module 201 is electrically connected to the control end of the data transistor Tda of the sub-pixel Spii located in the L-th row, the second sub-output module 202 is electrically connected to the control end of the data transistor Tda of the sub-pixel Spii located in the L+1-th row, and the third sub-output module is electrically connected to the control end of the data transistor Tda of the sub-pixel Spii located in the L+2-th row. A first gate control signal Pscan is provided to the control end of the data transistor Tda of the sub-pixel Spii located in the Lth row through the first sub-output module 201 of the Kth-level gate drive circuit GA, a first gate control signal Pscan is provided to the control end of the data transistor Tda of the sub-pixel Spii located in the L+1th row through the second sub-output module 202 of the Kth-level gate drive circuit GA, and a first gate control signal Pscan is provided to the control end of the data transistor Tda of the sub-pixel Spii located in the L+2th row through the third sub-output module of the Kth-level gate drive circuit GA. Wherein, K ≥ 1, L = 3K-2, and the sub-pixel Spii in the L+1th row is adjacent to both the sub-pixel Spii in the Lth row and the sub-pixel Spii in the L+2th row.

[0189] It can be understood that, in some embodiments, each first output module 20 may also be electrically connected to the control terminals of the data transistors Tda of the multiple rows of sub-pixels Spi.

[0190] Optionally, the display panel DP includes multiple first scan lines SL1 and a source driver chip, the control end of the data transistor Tda of multiple sub-pixels Spi receives the required first gate control signal Pscan through the corresponding first scan line SL1, and the source driver chip is connected to multiple data lines DL to output multiple data signals.

[0191] 7 , at least one sub-pixel Spi includes a compensation transistor Tc, an input terminal of the compensation transistor Tc being electrically connected to an output terminal of the driving transistor Tdr, an output terminal of the compensation transistor Tc being electrically connected to a control terminal of the driving transistor Tdr, and a control terminal of the compensation transistor Tc being configured to receive a first scan signal Scan1.

[0192] Optionally, the display panel DP includes a plurality of second scan lines SL2 , and the control terminals of the compensation transistors Tc of the plurality of sub-pixels Spi receive the required first scan signals Scan1 through the corresponding second scan lines SL2 .

[0193] In some embodiments, the gate drive circuit GA can output a second gate control signal Nscan in addition to multiple first gate control signals Pscan. Therefore, the second output module 50 of each gate drive circuit GA can be controlled to output the second gate control signal Nscan to the compensation transistors Tc of multiple sub-pixels Spi in adjacent rows, thereby reducing the number of gate drive units GM required to match the sub-pixels Spi. In other words, the second gate control signal Nscan output by the gate drive circuit GA is used as the first scan signal Scan1 to control the operating state of the compensation transistors Tc.

[0194] Optionally, when the same gate drive circuit GA includes X first output modules 20, the second output module 50 of the gate drive circuit GA can output a second gate control signal Nscan to the compensation transistors Tc of multiple sub-pixels Spi in X adjacent rows, so that the number of rows of sub-pixels Spi driven by the second gate control signal Nscan output by the same gate drive circuit GA matches the number of rows of sub-pixels Spi driven by the first gate control signal Pscan.

[0195] Optionally, when the second output module 50 of the gate driving circuit GA outputs the second gate control signal Nscan to the compensation transistors Tc of multiple sub-pixels Spi in adjacent rows, the first gate control signal Pscan and the second gate control signal Nscan received by the same sub-pixel Spii can be output by the same gate driving circuit GA, so that the data transistor Tda and the compensation transistor Tc of the same sub-pixel Spii can have a common conduction time, so that the data signal can be transmitted to the control end of the driving transistor Tdr, thereby realizing the refresh operation of the display data of the sub-pixel Spii.

[0196] Optionally, when the same gate driver circuit GA includes X first output modules 20, the Kth-stage gate driver circuit GA can be electrically connected to the control terminals of the compensation transistors Tc of the sub-pixels Spi in the Lth to L+(X-1)th rows, so that the data transistor Tda and the compensation transistor Tc of each sub-pixel Spi have the same conduction time. Here, K ≥ 1, and L = XK-(X-1).

[0197] 7 , at least one sub-pixel Spi includes a reset transistor Tr, an input end of the reset transistor Tr is electrically connected to the reset line VLr, an output end of the reset transistor Tr is electrically connected to the control end of the drive transistor Tdr, and the control end of the reset transistor Tr is configured to receive a second scan signal Scan2.

[0198] Optionally, the display panel DP includes a plurality of third scan lines SL3 , and the control ends of the reset transistors Tr of the plurality of sub-pixels Spi receive the required second scan signal Scan2 through the corresponding third scan lines SL3 .

[0199] In some embodiments, when the gate drive circuit GA simultaneously outputs multiple first gate control signals Pscan and second gate control signals Nscan, the second output module 50 of each gate drive circuit GA outputs the second gate control signal Nscan to the control terminals of the reset transistors Tr of multiple sub-pixels Spi in adjacent rows, thereby reducing the number of gate drive units GM required to match the sub-pixels Spi. That is, the second gate control signal Nscan output by the gate drive circuit GA is used as the second scan signal Scan2 to control the operating state of the reset transistor Tr.

[0200] Optionally, when the same gate drive circuit GA includes X first output modules 20, the K-2-th level gate drive circuit GA can be electrically connected to the control end of the reset transistor Tr of the L-th to L+(X-1)-th rows of sub-pixels Spi, so that the data transistor Tda and reset transistor Tr of each sub-pixel Spi have independent conduction time.

[0201] It can be understood that if only one gate driving unit GM that simultaneously outputs multiple first gate control signals Pscan and second gate control signals Nscan is provided in the display device, the multiple second gate control signals Nscan can be used individually to control the compensation transistors Tc of multiple sub-pixels Spi, can also be used individually to control the reset transistors Tr of multiple sub-pixels Spi, and can also be used simultaneously to control the compensation transistors Tc and reset transistors Tr of multiple sub-pixels Spi.

[0202] Optionally, when multiple second gate control signals Nscan are simultaneously used to control the compensation transistors Tc and reset transistors Tr of multiple sub-pixels Spi, the second gate control signals Nscan corresponding to the compensation transistors Tc and reset transistors Tr in the same sub-pixel Spi can be supplied by gate drive circuits GA of different stages. The configuration of this can be referred to in related designs and will not be further described here.

[0203] Therefore, each gate driving circuit GA can output the second gate control signal Nscan to the control terminals of the compensation transistors Tc or the reset transistors Tr of the plurality of sub-pixels Spi in the adjacent rows.

[0204] Optionally, the second gate control signal Nscan output by the multi-stage gate drive circuit GA in the same gate drive unit GM can be output to transistors of the same action type (i.e., the second gate control signal Nscan output by the multi-stage gate drive circuit GA in the same gate drive unit GM are all output to the compensation transistor Tc, or are all output to the reset transistor Tr).

[0205] Optionally, in some embodiments, two gate driving units GM that simultaneously output multiple first gate control signals Pscan and second gate control signals Nscan may be further provided to respectively control the reset transistor Tr and the compensation transistor Tc using the second gate control signals Nscan output by the two gate driving units GM, and the data transistor Tda may be controlled using the first gate control signal Pscan output by the two gate driving units GM or one of the two gate driving units GM.

[0206] For example, the display driving circuit Ddc includes two gate driving units GM, and the two gate driving units GM include a first gate driving unit and a second gate driving unit. The control terminals of the compensation transistors Tc of the plurality of sub-pixels Spi are configured to receive the second gate control signal Nscan output by the plurality of gate driving circuits GA of the first gate driving unit, and the control terminals of the reset transistors Tr of the plurality of sub-pixels Spi are configured to receive the second gate control signal Nscan output by the plurality of gate driving circuits GA of the second gate driving unit. The control terminals of the data transistors Tda of the plurality of sub-pixels Spi are configured to receive the first gate control signal Pscan output by the plurality of gate driving circuits GA of the first gate driving unit and / or the first gate control signal Pscan output by the plurality of gate driving circuits GA of the second gate driving unit.

[0207] Optionally, the compensation transistor Tc and the reset transistor Tr are silicon transistors or oxide transistors, and are P-type or N-type transistors. Optionally, to reduce leakage from the control terminal of the drive transistor Tdr to the output terminal of the drive transistor Tdr and the reset line VLr, the compensation transistor Tc and the reset transistor Tr are oxide transistors. To be compatible with existing process technologies, the compensation transistor Tc and the reset transistor Tr are N-type transistors. It is understood that the active layer of the oxide transistor includes indium gallium zinc oxide, etc.

[0208] 7 , at least one sub-pixel Spi further includes a first initial transistor Ti1 , a first light emission control transistor Te1 , a second light emission control transistor Te2 , and a first storage capacitor Cst1 .

[0209] The input terminal of the first initial transistor Ti1 is configured to receive the first initial signal transmitted by the first initial line VL1, the output terminal of the first initial transistor Ti1 is electrically connected to the anode of the light emitting device Di, and the control terminal of the first initial transistor Ti1 is configured to receive the third scan signal Scan3.

[0210] An input terminal of the first light emitting control transistor Te1 is electrically connected to the first voltage terminal Vdd, and an output terminal of the first light emitting control transistor Te1 is electrically connected to an input terminal of the driving transistor Tdr.

[0211] An input terminal of the second light emitting control transistor Te2 is electrically connected to an output terminal of the driving transistor Tdr, and an output terminal of the second light emitting control transistor Te2 is electrically connected to an anode of the light emitting device Di.

[0212] A first end of the first storage capacitor Cst1 is electrically connected to the first voltage terminal Vdd, and a second end of the first storage capacitor Cst1 is electrically connected to the control terminal of the driving transistor Tdr.

[0213] Optionally, the multiple scan lines include multiple fourth scan lines SL4 and multiple light-emitting control lines EML, the multiple fourth scan lines SL4 are electrically connected to the control ends of the first initial transistors Ti1 of the multiple sub-pixels Spi, the multiple light-emitting control lines EML are electrically connected to the control ends of the first light-emitting control transistors Te1 and the control ends of the second light-emitting control transistors Te2 of the multiple sub-pixels Spi, and the control ends of the first initial transistors Ti1 of the multiple sub-pixels Spi receive the required third scan signal Scan3 through the corresponding fourth scan lines SL4.

[0214] Optionally, in some embodiments, the sub-pixel Spi further includes a second storage capacitor Cst2, a first end of the second storage capacitor Cst2 is electrically connected to the control end of the data transistor Tda, and a second end of the second storage capacitor Cst2 is electrically connected to the control end of the driving transistor Tdr.

[0215] Optionally, in some embodiments, to improve the threshold voltage shift of the driving transistor Tdr caused by display frequency switching, the sub-pixel Spi further includes a second initialization transistor Ti2, the input terminal of the second initialization transistor Ti2 being configured to receive a second initialization signal transmitted by the second initialization line VL2, and the output terminal of the second initialization transistor Ti2 being electrically connected to the input terminal of the driving transistor Tdr. Optionally, the plurality of fourth scan lines SL4 are electrically connected to the control terminals of the second initialization transistors Ti2 of the plurality of sub-pixels Spi.

[0216] FIG8 is a timing diagram of a corresponding pixel driving circuit provided in an embodiment of the present application. The operating principle of the pixel driving circuit is described below, taking as an example an example where the compensation transistor Tc and the reset transistor Tr are N-type transistors, and the driving transistor Tdr, the data transistor Tda, the first emission control transistor Te1, the second emission control transistor Te2, the first initial transistor Ti1, and the second initial transistor Ti2 are P-type transistors.

[0217] In the first reset phase Si1, the emission control signal EM transmitted by the emission control line EML and the first gate control signal Pscan received by the data transistor Tda are high, the second scan signal Scan2 received by the reset transistor Tr and the first scan signal Scan1 received by the compensation transistor Tc are low, and the third scan signal Scan3 is low. The first initial signal transmitted by the first initial line VL1 is transmitted to the anode of the light-emitting device Di to reset the anode potential of the light-emitting device Di. The second initial signal transmitted by the second initial line VL2 is transmitted to the input and output terminals of the driving transistor Tdr to reset the potentials of the input and output terminals of the driving transistor Tdr.

[0218] In the second reset phase Si2, the second scan signal Scan2, the emission control signal EM, the first gate control signal Pscan, and the third scan signal Scan3 are at a high level, and the first scan signal Scan1 is at a low level. The reset transistor Tr is turned on, and the reset signal Vr is transmitted to the gate of the drive transistor Tdr to reset the potential of the control terminal of the drive transistor Tdr.

[0219] During the data writing phase Sw, the first scan signal Scan1, the emission control signal EM, and the third scan signal Scan3 are high, while the second scan signal Scan2 and the first gate control signal Pscan are low. The data transistor Tda and the compensation transistor Tc are turned on, and the data signal is transmitted to the control terminal of the drive transistor Tdr.

[0220] Among them, between the second reset stage Si2 and the data writing stage Sw, it can also include a stage of controlling the reset transistor Tr and the compensation transistor Tc to be turned on at the same time, so that the reset signal Vr can be transmitted to the output end and input end of the driving transistor Tdr, thereby realizing the potential reset of the output end and input end of the driving transistor Tdr.

[0221] In the third reset stage Si3, the light-emitting control signal EM and the first gate control signal Pscan are at a high level, the second scan signal Scan2, the first scan signal Scan1, and the third scan signal Scan3 are at a low level, the first initial signal is transmitted to the anode of the light-emitting device Di, and the second initial signal is transmitted to the input and output ends of the driving transistor Tdr.

[0222] In the light-emitting stage Sd, the first gate control signal Pscan and the third scan signal Scan3 are at a high level, the light-emitting control signal EM, the second scan signal Scan2, and the first scan signal Scan1 are at a low level, the first light-emitting control transistor Te1 and the second light-emitting control transistor Te2 are turned on, and the driving transistor Tdr generates a driving current to drive the corresponding light-emitting device Di to emit light.

[0223] In the fourth reset stage Si4 and the fifth reset stage Si5, the light-emitting control signal EM and the first gate control signal Pscan are at a high level, the second scan signal Scan2, the first scan signal Scan1, and the third scan signal Scan3 are at a low level, the first initial signal is transmitted to the anode of the light-emitting device Di, and the second initial signal is transmitted to the input and output ends of the driving transistor Tdr.

[0224] The write frame WF includes a first reset phase Si1, a second reset phase Si2, a data write phase Sw, a third reset phase Si3, and a light emitting phase Sd. The hold frame HF includes a fourth reset phase Si4, a fifth reset phase Si5, and a light emitting phase Sd.

[0225] FIG9 is a schematic diagram of the high-frequency and low-frequency picture display principles provided by an embodiment of the present application, and illustrates the writing frame WF and the holding frame HF by taking the display panel DP realizing a static picture display as an example.

[0226] When the display panel DP displays at a high frequency (such as 120 Hz), the display panel DP needs to perform 120 display data refresh operations within 1 second, that is, 120 frames are included in 1 second, and the display data is refreshed for each frame (that is, the sub-pixel Spi corresponding to each frame matches the timing of the write frame WF shown in Figure 8). When the display panel DP displays at a low frequency (such as 1 Hz), the display panel DP also includes 120 frames within 1 second, but only the first frame performs the display data refresh operation (that is, the sub-pixel Spi only matches the timing of the write frame WF shown in Figure 8 for the first frame F1). The 119 consecutive frames after the first frame F1 all maintain the picture data signal of the first frame and do not perform the display data refresh operation (that is, the sub-pixel Spi corresponding to the 119 consecutive frames after the first frame F1 all match the timing of the hold frame HF shown in Figure 8). Among them, the frame in which the display data is refreshed can be recorded as the write frame WF, and the frame in which the display data is not refreshed can be recorded as the hold frame HF. Therefore, during the write frame WF, the first scan signal Scan1 corresponding to the compensation transistor Tc, the second scan signal Scan2 corresponding to the reset transistor Tr, and the first gate control signal Pscan corresponding to the data transistor Tda must all be at an active level to overwrite the original data signal stored at the control terminal of the drive transistor Tdr with the newly written data signal, allowing the sub-pixel Spi to display again according to the newly written data signal during the write frame WF. During the hold frame HF, the first scan signal Scan1 corresponding to the compensation transistor Tc and the second scan signal Scan2 corresponding to the reset transistor Tr of some sub-pixels Spi remain at an inactive level, turning off the compensation transistor Tc and the reset transistor Tr, so that no new data signal is stored at the control terminal of the drive transistor Tdr. During the hold frame HF, the first gate control signal Pscan corresponding to the data transistor Tda can maintain the same frequency as during the write frame WF. Alternatively, during the hold frame HF, the first gate control signal Pscan corresponding to the data transistor Tda can be maintained at an inactive level so that the frequency of the first gate control signal Pscan corresponding to the data transistor Tda during the hold frame HF is lower than the frequency during the write frame WF.

[0227] Optionally, in some embodiments, in the hold frame HF, the data transistor Tda is turned on according to the corresponding first gate control signal Pscan to reset the potential of the input end of the driving transistor Tdr using the signal transmitted by the data line DL electrically connected to the data transistor Tda.

[0228] Optionally, in some embodiments, in the holding frame HF, the data transistor Tda remains cut off according to the corresponding first gate control signal Pscan, and the second initial transistor Ti2 has a turn-on period according to the corresponding third scan signal Scan3, so as to utilize the second initial signal transmitted by the second initial line VL2 electrically connected to the second initial transistor Ti2 to reset the potential of the input terminal of the driving transistor Tdr.

[0229] Taking the matching design of each gate driving circuit GA including two first output modules 20 as an example, combined with the analysis of FIG. 5A to FIG. 5B and FIG. 8 , the principle of frequency division display achieved by the display panel DP using the display driving circuit Ddc is described.

[0230] In the first frame F1 of a display cycle, in order to write new data signals to the control terminals of the drive transistors Tdr of the multiple sub-pixels Spi, the first frequency-division control signal FD1 and the second frequency-division control signal FD2 are controlled to maintain an effective level state, and the multiple rows of sub-pixels Spi in the display panel DP all undergo the writing frame WF stage shown in Figure 8. A display cycle may include one frame or multiple frames. When a display cycle includes one frame, the frame corresponds to the writing frame WF for the multiple rows of sub-pixels Spi. When a display cycle includes multiple frames, the first frame F1 corresponds to the writing frame WF for the multiple rows of sub-pixels Spi.

[0231] In the second frame F2 of a display cycle, if the sub-pixels Spi in the 1st row through the L-1st row of sub-pixels Spi in the display panel DP are displayed at a high frequency, and the sub-pixels Spi in the Lth row and subsequent rows of sub-pixels Spi are displayed at a low frequency, then the second scan signal Scan2, the first scan signal Scan1, and the first gate control signal Pscan applied to the sub-pixels Spi in the 1st row through the L-1st row of sub-pixels Spi must all have valid pulses, causing the sub-pixels Spi in the 1st row through the L-1st row of sub-pixels Spi to all undergo the write frame WF phase shown in FIG8 . However, the second scan signal Scan2, the first scan signal Scan1, and the first gate control signal Pscan applied to the sub-pixels Spi in the Lth row and subsequent rows of sub-pixels Spi do not need to have valid pulses, causing the sub-pixels Spi in the Lth row and subsequent rows of sub-pixels Spi to all undergo the hold frame HF phase shown in FIG8 . The second frame F2 is located after the first frame F1.

[0232] Therefore, for the sub-pixels Spi in the 1st row through the L-1st row, the second frame F2 is still a write frame WF; however, for the sub-pixels Spi in the Lth row and the multiple rows of sub-pixels Spi thereafter, the second frame F2 is a hold frame HF. Therefore, corresponding to the second frame F2, the control terminals of the drive transistors Tdr of the sub-pixels Spi in the 1st row through the L-1st row have data signals written to them, while the control terminals of the drive transistors Tdr of the sub-pixels Spi in the Lth row and the multiple rows of sub-pixels Spi thereafter do not have data signals written to them. Consequently, the refresh frequencies corresponding to the sub-pixels Spi in the 1st row through the L-1st row differ from those of the sub-pixels Spi in the Lth row and the multiple rows of sub-pixels Spi thereafter in the second frame F2, enabling the display panel DP to implement a frequency division display function.

[0233] Similarly, when the gate driving circuit includes three or more first output modules 20 , a design for controlling the display panel to realize the frequency division display function can also be obtained.

[0234] It should be noted that when the gate drive unit uses Y clock lines to transmit the corresponding first clock signal XCK and second clock signal CK to the multi-stage gate drive circuit GA, the inconsistent loads on the multiple clock lines can cause display differences in the display panel using the gate drive unit. For example, when a display panel uses the design corresponding to the gate drive unit shown in FIG. 3A , the display effect of the odd-numbered rows of the display panel will be different from the display effect of the even-numbered rows.

[0235] By using Z of the multiple clock lines to transmit the corresponding first clock signal XCK to the multi-stage gate drive circuit GA, and Y of the multiple clock lines to transmit the corresponding second clock signal CK to the multi-stage gate drive circuit GA, the loads corresponding to the Z and Y clock lines can be made similar. Therefore, the display panel using this gate drive unit design has a smaller display difference. For example, when the display panel uses the gate drive unit design shown in FIG3B , the display difference between odd and even rows in the display panel is smaller, which is conducive to improving display quality.

[0236] It should be noted that the H (i.e., unit duration) mentioned above may correspond to the row cycle duration.

[0237] Because each gate driving circuit included in the gate driving unit is provided with a plurality of first output modules, and the plurality of first output modules in the same gate driving circuit output a plurality of first gate control signals with phase differences that can be used in the display device, so that the display panel can realize a frequency division display design. Therefore, when the display device applies any of the above-mentioned display driving circuits, the layout space occupied by the gate driving unit can be reduced, which is beneficial to reducing the border width of the display panel, making it easy for the display panel to realize a narrow border design, and is also beneficial to reducing driving power consumption. The display device adopts the display driving circuit of the present application, which can further compress the border size of the display panel by about 100 microns. Compared with the display device adopting the display driving circuit having one first output module and one second output module, the display device adopts the display driving circuit of the present application, which can compress the border size of the display panel by about 60 microns.

[0238] This document uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for technical personnel in this field, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A display driving circuit, wherein: The gate drive unit includes a plurality of frequency division control lines and a plurality of cascaded gate drive circuits, wherein the plurality of frequency division control lines are configured to transmit frequency division control signals to the plurality of gate drive circuits, and each gate drive circuit includes: a node control module, electrically connected to the first node and the second node of the gate drive circuit of this stage, and configured to control the signals transmitted to the first node and the second node according to the corresponding first clock signal and the start signal; a plurality of first output modules, each of the first output modules being electrically connected to the first node and the second node, and each of the first output modules being configured to output a first gate control signal according to a corresponding second clock signal, the frequency division control signal, and signals at the first node and the second node; at least one first frequency division module, electrically connected to the first node, the second node, and at least one first output module, and configured to control signal transmission between the first node and the corresponding first output module according to the frequency division control signal and the signal of the second node; The plurality of first output modules are configured to output a plurality of first gate control signals with phase differences.

2. The display driving circuit according to claim 1, wherein: Each of the gate driving circuits includes X first output modules, and a phase difference between the first clock signals corresponding to two adjacent gate driving circuits is XH; wherein X≥2, and H is a unit time length.

3. The display driving circuit according to claim 2, wherein: The multiple stages of the gate driving circuits are electrically connected to Y clock lines, and the Y clock lines transmit the corresponding first clock signal and the second clock signal to the multiple stages of the gate driving circuits; wherein Y=2X.

4. The display driving circuit according to claim 1, wherein: The multi-stage gate drive circuit is electrically connected to the multiple clock lines, Z of the multiple clock lines transmit the corresponding first clock signal to the multi-stage gate drive circuit, and Y of the multiple clock lines transmit the corresponding second clock signal to the multi-stage gate drive circuit; wherein Z=2, Y=2X.

5. The display driving circuit according to any one of claims 3 to 4, wherein: Each of the gate drive circuits includes two of the first output modules; the Y clock lines include a first clock line, a second clock line, a third clock line, and a fourth clock line; In which, the first clock line transmits the corresponding second clock signal to a first output module of the gate drive circuit of the 2k+1th level, and the second clock line transmits the corresponding second clock signal to another first output module of the gate drive circuit of the 2k+1th level; the third clock line transmits the corresponding second clock signal to a first output module of the gate drive circuit of the 2k+2th level, and the fourth clock line transmits the corresponding second clock signal to another first output module of the gate drive circuit of the 2k+2th level, k≥0.

6. The display driving circuit according to claim 5, wherein: The third clock line transmits the corresponding first clock signal to the gate driving circuit of the 2k+1th level; the first clock line transmits the corresponding first clock signal to the gate driving circuit of the 2k+2th level.

7. The display driving circuit according to claim 5, wherein: The Z clock lines include a fifth clock line and a sixth clock line; The fifth clock line transmits the corresponding first clock signal to the gate driving circuit at the 2k+1th level; and the sixth clock line transmits the corresponding first clock signal to the gate driving circuit at the 2k+2th level.

8. The display driving circuit according to claim 1, wherein: Each of the first output modules includes: a first output transistor, wherein a control terminal of the first output transistor is electrically connected to the corresponding first frequency dividing module, an input terminal of the first output transistor is configured to receive the second clock signal, and an output terminal of the first output transistor is electrically connected to a first output terminal of the gate driving circuit of the current stage for outputting the first gate control signal; a second output transistor, wherein a control terminal of the second output transistor is electrically connected to the second node, an input terminal of the second output transistor is electrically connected to the first power terminal, and an output terminal of the first output transistor is electrically connected to the first output terminal; and A first capacitor, wherein a first end of the first capacitor is electrically connected to the control end of the first output transistor, and a second end of the first capacitor is electrically connected to the first output end.

9. The display driving circuit according to claim 8, wherein: At least one of the first output modules includes a first switching transistor, the control end of the first switching transistor is electrically connected to the second node of the previous gate drive circuit, the input end of the first switching transistor is electrically connected to the corresponding first frequency division module, and the output end of the first switching transistor is electrically connected to the control end of the first output transistor.

10. The display driving circuit according to claim 9, wherein: At least one of the gate drive circuits comprises: a second switch transistor, wherein a control terminal of the second switch transistor receives the corresponding first clock signal, and an input terminal of the second switch transistor is electrically connected to an input terminal of at least one of the first switch transistors; a third switch transistor, wherein the control end of the third switch transistor is electrically connected to the second node, the input end of the third switch transistor is electrically connected to the first power end, and the output end of the third switch transistor is electrically connected to the output end of the second switch transistor.

11. The display driving circuit according to claim 1, wherein: The plurality of frequency division control lines include a first frequency division control line; the first frequency division module includes: a first frequency-dividing transistor, wherein a control terminal of the first frequency-dividing transistor is electrically connected to the second node; a second frequency-dividing transistor, wherein a control terminal of the second frequency-dividing transistor is electrically connected to the output terminal of the first frequency-dividing transistor, an input terminal of the second frequency-dividing transistor is electrically connected to the first node, and an output terminal of the second frequency-dividing transistor is electrically connected to the corresponding first output module; and a second capacitor, wherein a first end of the second capacitor is electrically connected to the control end of the second frequency-dividing transistor, and a second end of the second capacitor is electrically connected to the output end of the second frequency-dividing transistor; The input terminals of the first frequency-dividing transistors of the plurality of gate driving circuits are electrically connected to the first frequency-dividing control line.

12. The display driving circuit according to claim 1, wherein: Each of the gate drive circuits further includes: a second output module electrically connected to the first node and configured to output a second gate control signal according to the corresponding frequency-divided control signal and the signal of the first node; and The second frequency division module is electrically connected to the first node, the second node and the second output module, and is configured to control signal transmission between the first node and the second output module according to the corresponding frequency division control signal and the signal of the second node.

13. The display driving circuit according to claim 12, wherein: The plurality of frequency division control lines include a second frequency division control line; the second frequency division module includes: a third frequency-dividing transistor, wherein a control terminal of the third frequency-dividing transistor is electrically connected to the second node; a fourth frequency-dividing transistor, wherein a control terminal of the fourth frequency-dividing transistor is electrically connected to the output terminal of the third frequency-dividing transistor, an input terminal of the fourth frequency-dividing transistor is electrically connected to the first node, and an output terminal of the fourth frequency-dividing transistor is electrically connected to the corresponding second output module; and a third capacitor, wherein a first end of the third capacitor is electrically connected to the control end of the fourth frequency-dividing transistor, and a second end of the third capacitor is electrically connected to the output end of the fourth frequency-dividing transistor; Wherein, the input terminals of the third frequency-dividing transistors of the plurality of gate driving circuits are electrically connected to the second frequency-dividing control line.

14. The display driving circuit according to claim 13, wherein: The second output module includes: a third output transistor, wherein a control terminal of the third output transistor is electrically connected to the output terminal of the fourth frequency-dividing transistor, an input terminal of the third output transistor is electrically connected to the second power supply terminal, and an output terminal of the third output transistor is electrically connected to the second output terminal of the gate driving circuit of this stage for outputting the second gate control signal; a fourth output transistor, wherein the control terminal of the fourth output transistor is electrically connected to the first node, the input terminal of the fourth output transistor is electrically connected to the third power supply terminal, and the output terminal of the fourth output transistor is electrically connected to the second output terminal.

15. The display driving circuit according to claim 14, wherein: At least one of the gate drive circuits comprises: a fourth switch transistor, wherein a control terminal of the fourth switch transistor receives the corresponding first clock signal, and an input terminal of the fourth switch transistor is electrically connected to the input terminal of the third output transistor; a fifth switch transistor, wherein the control terminal of the fifth switch transistor is electrically connected to the second node, the input terminal of the fifth switch transistor is electrically connected to the first power supply terminal, and the output terminal of the fifth switch transistor is electrically connected to the output terminal of the fourth switch transistor.

16. The display driving circuit according to claim 1, wherein: The node control module includes: a first transistor, wherein a control terminal of the first transistor is configured to receive the corresponding start signal, and an input terminal of the first transistor is electrically connected to the third power terminal or the fourth power terminal; a second transistor, wherein a control terminal of the second transistor is electrically connected to the first control terminal of the first transistor, an input terminal of the second transistor is electrically connected to the first power terminal, and an output terminal of the second transistor is electrically connected to the output terminal of the first transistor; a third transistor, wherein a control terminal of the third transistor is configured to receive the corresponding first clock signal, an input terminal of the third transistor is electrically connected to the output terminal of the first transistor, and an output terminal of the third transistor is electrically connected to the first node; a fourth transistor, wherein a control terminal of the fourth transistor is electrically connected to the first node, an input terminal of the fourth transistor is electrically connected to the fourth power supply terminal, and an output terminal of the fourth transistor is electrically connected to the second node; a fifth transistor, wherein a control terminal of the fifth transistor is electrically connected to the first node, an input terminal of the fifth transistor is electrically connected to the first power terminal, and an output terminal of the fifth transistor is electrically connected to the second node; a sixth transistor, wherein a control terminal of the sixth transistor is electrically connected to the second node, an input terminal of the sixth transistor is electrically connected to the third power supply terminal, and an output terminal of the sixth transistor is electrically connected to the first node.

17. The display driving circuit according to claim 16, wherein: The node control module includes: a seventh transistor, wherein a control terminal of the seventh transistor is configured to receive the corresponding first clock signal, and an output terminal of the seventh transistor is electrically connected to the first node; an eighth transistor, wherein the control end of the eighth transistor is electrically connected to the second node, the input end of the eighth transistor is electrically connected to the first power supply end, and the output end of the eighth transistor is electrically connected to the input end of the seventh transistor.

18. A display device, wherein: include: The display driving circuit according to any one of claims 1 to 17; a display panel electrically connected to the display driving circuit, comprising a plurality of sub-pixels, each of the sub-pixels comprising a light-emitting device, a driving transistor, and a data transistor; the driving transistor being configured to generate a driving current to drive the light-emitting device to emit light, and the data transistor being configured to transmit a data signal to a control terminal of the driving transistor; Among them, multiple first output modules of the same gate driving circuit are electrically connected to the control ends of the data transistors of the adjacent rows of sub-pixels, and each first output module is electrically connected to the control ends of the data transistors of at least one row of sub-pixels.

19. The display device according to claim 18, wherein Each first output module is electrically connected to the control end of the data transistor of the sub-pixels in a row; each gate drive circuit includes two first output modules, and the two first output modules in the same gate drive circuit are electrically connected to the control ends of the data transistors of the sub-pixels in two adjacent rows.

20. The display device according to claim 18, wherein At least one of the sub-pixels includes a compensation transistor and a reset transistor, wherein an input terminal of the compensation transistor is electrically connected to an output terminal of the driving transistor, an output terminal of the compensation transistor is electrically connected to a control terminal of the driving transistor, an input terminal of the reset transistor is electrically connected to a reset line, and an output terminal of the reset transistor is electrically connected to the control terminal of the driving transistor; Each of the gate driving circuits outputs a second gate control signal to the control terminals of the compensation transistors or the reset transistors of a plurality of the sub-pixels in adjacent rows.

21. The display device according to claim 20, wherein The display driving circuit includes two gate driving units, and the two gate driving units include a first gate driving unit and a second gate driving unit; Among them, the control ends of the compensation transistors of the multiple sub-pixels correspond to receiving the second gate control signals output by the multiple gate driving circuits of the first gate driving unit, and the control ends of the reset transistors of the multiple sub-pixels correspond to receiving the second gate control signals output by the multiple gate driving circuits of the second gate driving unit; the control ends of the data transistors of the multiple sub-pixels correspond to receiving the first gate control signals output by the multiple gate driving circuits of the first gate driving unit, and / or receive the first gate control signals output by the multiple gate driving circuits of the second gate driving unit.

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