Display apparatus

Abstract

A display apparatus. Control ends of compensation transistors (Tc) of a plurality of sub-pixels (Spi) are correspondingly and electrically connected to first output ends (O1) of multi-stage first gate driving circuits (GA1); control ends of reset transistors (Tr) of the plurality of sub-pixels (Spi) are correspondingly and electrically connected to first output ends (O1) of multi-stage second gate driving circuits (GA2); with respect to a same sub-pixel (Spi), the frequency of a second gate control signal (Nscan2) received by the reset transistor (Tr) is the same as the frequency of a first gate control signal (Nscan1) received by the compensation transistor (Tc).

Description

Display device

[0001] This application claims priority to Chinese Patent Application No. 202410404491.X filed on April 3, 2024. The contents of the above-mentioned Chinese patent application disclosure are hereby incorporated by reference in their entirety as a part of this application. Technical Field

[0002] The present application relates to the field of display technology, and in particular to a display device. Background Art

[0003] In a pixel drive circuit, the compensation transistor and reset transistor, electrically connected to the control terminal of the drive transistor, are often controlled using gate control signals output by different stages of gate drive circuits within the same gate drive unit. The reset transistor is turned on before the compensation transistor, allowing the reset signal to act on the control terminal of the drive transistor, resetting the potential of the control terminal of the drive transistor. However, when a display panel uses different display frequencies for different display areas, some sub-pixels in the display panel corresponding to the frequency division position may experience display anomalies because the gate control signal used by the compensation transistor is low-frequency, while the gate control signal used by the reset transistor is still high-frequency. SUMMARY OF THE INVENTION

[0004] An embodiment of the present application provides a display device that can improve the problem of display abnormality in some sub-pixels corresponding to frequency division positions in a display panel.

[0005] An embodiment of the present application provides a display device comprising a display panel and a gate driver module. The display panel comprises a plurality of sub-pixels, at least one of which comprises a light-emitting device, a driving transistor, a compensation transistor, and a reset transistor. The driving transistor is configured to generate a driving current to drive the light-emitting device to emit light. The output terminal of the reset transistor and the output terminal of the compensation transistor are electrically connected to the control terminal of the driving transistor. The input terminal of the compensation transistor is electrically connected to the output terminal of the driving transistor. The input terminal of the reset transistor is configured to receive a reset signal. The gate driver module is electrically connected to the display panel and comprises a plurality of frequency-dividing control lines for transmitting frequency-dividing control signals, a first gate driver unit, and a second gate driver unit. The plurality of frequency-dividing control signals include a first frequency-dividing control signal and a second frequency-dividing control signal. The first gate driver unit comprises a plurality of cascaded first gate driver circuits, and the second gate driver unit comprises a plurality of cascaded second gate driver circuits. The first gate driver circuit is configured to control the level of a generated first gate control signal according to the first frequency-dividing control signal, and the second gate driver circuit is configured to control the level of a generated second gate control signal according to the second frequency-dividing control signal. In which, the first gate driving circuit and the second gate driving circuit both include a first output end, the control ends of the compensation transistors of the multiple sub-pixels are electrically connected to the first output ends of the multi-stage first gate driving circuit to receive multiple first gate control signals; the control ends of the reset transistors of the multiple sub-pixels are electrically connected to the first output ends of the multi-stage second gate driving circuit to receive multiple second gate control signals; in the same sub-pixel, the frequency of the second gate control signal received by the reset transistor is the same as the frequency of the first gate control signal received by the compensation transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] 1A and 1B are schematic structural diagrams of a display device provided in an embodiment of the present application;

[0007] 2A and 2B are schematic structural diagrams of sub-pixels provided in embodiments of the present application;

[0008] FIG3 is a schematic diagram showing the connection between a sub-pixel and a gate driving module provided in the related art;

[0009] 4A and 4B are timing diagrams corresponding to sub-pixels provided in the related art;

[0010] 5A and 5B are schematic structural diagrams of a first gate driving unit and a second gate driving unit provided in an embodiment of the present application;

[0011] 6A and 6B are schematic structural diagrams of a gate drive circuit provided in an embodiment of the present application;

[0012] FIG7 is a schematic diagram of the high-frequency and low-frequency image display principles provided by an embodiment of the present application;

[0013] 8A to 8D are timing diagrams of a first gate control signal and a second gate control signal provided in an embodiment of the present application;

[0014] FIG9 is a timing diagram of sub-pixels corresponding to a writing frame and a holding frame provided in an embodiment of the present application. Modes for Carrying Out the Invention

[0015] To make the purpose, technical solutions and effects of this application clearer and more specific, the following further describes this application in detail with reference to the accompanying drawings and examples. It should be understood that the specific examples described herein are only used to explain this application and are not intended to limit this application.

[0016] The present application provides a display device, wherein a first gate driving unit includes a plurality of cascaded first gate driving circuits, a second gate driving unit includes a plurality of cascaded second gate driving circuits, the first gate driving circuit controls the level of a first gate control signal generated according to a first frequency-divided control signal, and the second gate driving circuit controls the level of a second gate control signal generated according to a second frequency-divided control signal, the control terminals of the compensation transistors of the plurality of sub-pixels are electrically connected to the first output terminals of the multi-stage first gate driving circuit outputting the first gate control signal, and the control terminals of the reset transistors of the plurality of sub-pixels are electrically connected to the first output terminals of the multi-stage second gate driving circuit outputting the second gate control signal, so that the reset transistors and the compensation transistors are electrically connected to each other. The compensation transistor and the reset transistor are no longer controlled by the gate control signal generated by the same gate driving unit, but are controlled by gate control signals generated by different gate driving units, so that the reset transistor of one sub-pixel and the compensation transistor of another sub-pixel no longer have a synchronous working state due to being controlled by the same gate control signal, but the working states of the reset transistor and the compensation transistor of different sub-pixels are independent, and then, in conjunction with the first frequency-dividing control signal and the second frequency-dividing control signal, the frequency of the second gate control signal received by the reset transistor in the same sub-pixel is the same as the frequency of the first gate control signal received by the compensation transistor, thereby improving the problem of display abnormality in some sub-pixels at corresponding frequency-dividing positions in the display panel.

[0017] Specifically, FIG. 1A to FIG. 1B are schematic structural diagrams of a display device provided in an embodiment of the present application. The present application provides a display device including a display panel DP and a gate driving module GM, wherein the gate driving module GM is electrically connected to the display panel DP.

[0018] Optionally, the display panel DP includes a self-luminous display panel.

[0019] The display panel DP includes a plurality of sub-pixels Spi. The gate driving module GM is electrically connected to the plurality of sub-pixels Spi to cooperate with the plurality of sub-pixels Spi to enable the display panel DP to achieve a display function.

[0020] Optionally, the display panel DP includes a plurality of scan lines, and the gate driving module GM is electrically connected to the plurality of sub-pixels Spi through the plurality of scan lines.

[0021] 2A and 2B are schematic structural diagrams of sub-pixels Spi provided in an embodiment of the present application. At least one sub-pixel Spi includes a light-emitting device Di, a driving transistor Tdr, a compensation transistor Tc, and a reset transistor Tr.

[0022] Optionally, the light emitting device Di includes a light emitting diode. Optionally, the light emitting device Di includes an organic light emitting diode, a sub-millimeter light emitting diode, a micro light emitting diode, etc.

[0023] The driving transistor Tdr and the light emitting device Di are electrically connected between a first voltage terminal Vdd and a second voltage terminal Vss. The driving transistor Tdr is configured to generate a driving current to drive the light emitting device Di to emit light.

[0024] Optionally, the input terminal of the driving transistor Tdr is electrically connected to the first voltage terminal Vdd, the output terminal of the driving transistor Tdr is electrically connected to the anode of the light-emitting device Di, the cathode of the light-emitting device Di is electrically connected to the second voltage terminal Vss, and the voltage supplied by the first voltage terminal Vdd is greater than the voltage supplied by the second voltage terminal Vss.

[0025] An input terminal of the reset transistor Tr is configured to receive a reset signal transmitted by the reset line VLr, and an output terminal of the reset transistor Tr is electrically connected to a control terminal of the driving transistor Tdr.

[0026] The input terminal of the compensation transistor Tc is electrically connected to the output terminal of the driving transistor Tdr, and the output terminal of the compensation transistor Tc is electrically connected to the control terminal of the driving transistor Tdr.

[0027] Optionally, the compensation transistor Tc and the reset transistor Tr are silicon transistors or oxide transistors, and are P-type or N-type transistors. Optionally, to reduce leakage from the control terminal of the drive transistor Tdr to the output terminal of the drive transistor Tdr and the reset line VLr, the compensation transistor Tc and the reset transistor Tr are oxide transistors. To be compatible with existing process technologies, the compensation transistor Tc and the reset transistor Tr are N-type transistors.

[0028] It can be understood that the active layer of the oxide transistor includes indium gallium zinc oxide and the like.

[0029] Optionally, the multiple scan lines include multiple first scan lines GL1 and multiple second scan lines GL2, the control ends of the compensation transistors Tc of the multiple sub-pixels Spi are electrically connected to the multiple first scan lines GL1, and the control ends of the reset transistors Tr of the multiple sub-pixels Spi are electrically connected to the multiple second scan lines GL2.

[0030] Please continue to refer to Figures 1A to 1B and Figures 2A to 2B. The display panel DP includes multiple data lines DL, and at least one sub-pixel Spi also includes a data transistor Tda. The input end of the data transistor Tda is configured to receive a data signal transmitted by the corresponding electrically connected data line DL, and the output end of the data transistor Tda is electrically connected to the input end of the driving transistor Tdr.

[0031] Optionally, the plurality of scan lines include a plurality of third scan lines GL3, and the control terminals of the data transistors Tda of the plurality of sub-pixels Spi are electrically connected to the plurality of third scan lines GL3. The display device includes a source driver chip SDC, which is connected to the plurality of data lines DL to output a plurality of data signals.

[0032] 2A to 2B , at least one sub-pixel Spi further includes a first initial transistor Ti1 , a first light emission control transistor Te1 , a second light emission control transistor Te2 , and a first storage capacitor Cst1 .

[0033] An input terminal of the first initial transistor Ti1 is configured to receive a first initial signal transmitted by the first initial line VL1 , and an output terminal of the first initial transistor Ti1 is electrically connected to the anode of the light emitting device Di.

[0034] An input terminal of the first light emitting control transistor Te1 is electrically connected to the first voltage terminal Vdd, and an output terminal of the first light emitting control transistor Te1 is electrically connected to an input terminal of the driving transistor Tdr.

[0035] An input terminal of the second light emitting control transistor Te2 is electrically connected to an output terminal of the driving transistor Tdr, and an output terminal of the second light emitting control transistor Te2 is electrically connected to an anode of the light emitting device Di.

[0036] A first end of the first storage capacitor Cst1 is electrically connected to the first voltage terminal Vdd, and a second end of the first storage capacitor Cst1 is electrically connected to the control terminal of the driving transistor Tdr.

[0037] Optionally, the multiple scan lines include multiple fourth scan lines GL4 and multiple light-emitting control lines EL, the multiple fourth scan lines GL4 are electrically connected to the control end of the first initial transistor Ti1 of the multiple sub-pixels Spi, and the multiple light-emitting control lines EL are electrically connected to the control end of the first light-emitting control transistor Te1 and the control end of the second light-emitting control transistor Te2 of the multiple sub-pixels Spi.

[0038] Optionally, please continue to refer to Figure 2B, the sub-pixel Spi further includes a second storage capacitor Cst2, a first end of the second storage capacitor Cst2 is electrically connected to the control end of the data transistor Tda, and a second end of the second storage capacitor Cst2 is electrically connected to the control end of the driving transistor Tdr.

[0039] Optionally, in order to improve the threshold voltage offset of the driving transistor Tdr caused by the display frequency switching, the sub-pixel Spi also includes a second initial transistor Ti2, the input end of the second initial transistor Ti2 is configured to receive the second initial signal transmitted by the second initial line VL2, and the output end of the second initial transistor Ti2 is electrically connected to the input end of the driving transistor Tdr, as shown in Figure 2B.

[0040] Optionally, the plurality of fourth scan lines GL4 are electrically connected to the control terminals of the second initial transistors Ti2 of the plurality of sub-pixels Spi.

[0041] Figure 3 is a schematic diagram of the connection between subpixels and a gate driver module, as provided in the related art. In the related art, the gate driver module GM includes a first sub-gate driver unit gm1, a second sub-gate driver unit gm2, and a third sub-gate driver unit gm3. The first sub-gate driver unit gm1 includes multiple cascaded first sub-gate driver circuits ga1, the second sub-gate driver unit gm2 includes multiple cascaded second sub-gate driver circuits ga2, and the third sub-gate driver unit gm3 includes multiple cascaded third sub-gate driver circuits ga3. The multiple first sub-gate driver circuits ga1 are configured to provide gate control signals to the reset transistors Tr and compensation transistors Tc of the multiple sub-pixels Spi. The multiple second sub-gate driver circuits ga2 are configured to provide gate control signals to the second initialization transistors Ti2 of the multiple sub-pixels Spi. The multiple third sub-gate driver circuits ga3 are configured to provide light emission control signals to the first and second light emission control transistors Te1 and Te2 of the multiple sub-pixels Spi. The data transistor Tda can be controlled by the gate control signal output by the first sub-gate driver unit gm1 or by the gate control signals output by other gate driver units. The first initial transistor Ti1 can share a gate control signal provided by the same gate drive unit as the data transistor Tda, or a corresponding gate control signal can be provided by the third sub-gate drive unit gm3. In the same sub-pixel Spi, the gate control signal received by the control terminal of the compensation transistor Tc and the gate control signal received by the control terminal of the reset transistor Tr are generated by first sub-drive circuits at different levels. For example, the gate control signal received by the control terminal of the reset transistor Tr of the sub-pixel Spi in the nth row of the display panel DP is generated by the first sub-gate drive circuit at the n-2th level, while the gate control signal received by the control terminal of the compensation transistor Tc of the sub-pixel Spi in the nth row is generated by the first sub-gate drive circuit at the nth level. The first sub-gate drive unit gm1 adopts a bilateral drive design.

[0042] Figures 4A and 4B are timing diagrams corresponding to the subpixel Spi provided in the related art. Pscan corresponds to the gate control signal received by the control terminal of the first initial transistor Ti1 and the control terminal of the second initial transistor Ti2, Pscan_T2 corresponds to the gate control signal received by the control terminal of the data transistor Tda, Nscan_T3 corresponds to the gate control signal received by the control terminal of the compensation transistor Tc, Nscan_T4 corresponds to the gate control signal received by the control terminal of the reset transistor Tr, and EM corresponds to the gate control signal received by the control terminals of the first emission control transistor Te1 and the second emission control transistor Te2.

[0043] When the sub-pixel Spi is displayed using the timing diagram shown in FIG4A , since the gate control signals corresponding to the reset transistor Tr and the compensation transistor Tc have two valid pulses, the display panel DP cannot achieve zone-by-zone frequency display using the timing diagram shown in FIG4A . When the sub-pixel Spi is displayed using the timing diagram shown in Figure 4B, even if the gate control signals corresponding to the reset transistor Tr and the compensation transistor Tc have one valid pulse, since in the same sub-pixel Spi, the gate control signal received by the control end of the compensation transistor Tc and the gate control signal received by the control end of the reset transistor Tr are provided by different levels of first sub-gate driving circuits ga1, and the reset transistor Tr is turned on before the compensation transistor Tc, therefore, in some rows near the frequency division position of the corresponding display panel DP, the reset transistor Tr in the sub-pixel Spi is turned on according to the corresponding gate control signal, so that the potential of the control end of the driving transistor Tdr is reset, and the compensation transistor Tc remains cut off because the corresponding gate control signal becomes low frequency, so that no new data information in the sub-pixel Spi is stored in the control end of the driving transistor Tdr, and no original data signal is retained at the control end of the driving transistor Tdr, resulting in display abnormality in the sub-pixel Spi.

[0044] In order to enable a display panel DP to implement zoned frequency display and to improve the problem of abnormal display of sub-pixels Spi in some rows of the display panel DP corresponding to frequency division positions, the present application provides a display device.

[0045] 1A to 1B , the gate driving module GM includes a plurality of frequency-dividing control lines FL, a first gate driving unit GM1 and a second gate driving unit GM2 .

[0046] The plurality of frequency division control lines FL transmit a plurality of frequency division control signals, and the plurality of frequency division control signals include a first frequency division control signal NF1 and a second frequency division control signal NF2.

[0047] The first gate driving unit GM1 includes a plurality of cascaded first gate driving circuits GA1 , and the first gate driving circuit GA1 is configured to control the level of the generated first gate control signal Nscan1 according to the first frequency-divided control signal NF1 .

[0048] The second gate driving unit GM2 includes a plurality of cascaded second gate driving circuits GA2 , and the second gate driving circuit GA2 is configured to control the level of the generated second gate control signal Nscan2 according to the second frequency-divided control signal NF2 .

[0049] The first gate drive circuit GA1 and the second gate drive circuit GA2 both include a first output terminal O1 , which outputs a first gate control signal Nscan1 , and a second gate drive circuit GA2 outputs a second gate control signal Nscan2 .

[0050] Optionally, the first output terminals O1 of the plurality of first gate driving circuits GA1 are electrically connected to the plurality of sub-pixels Spi through the plurality of first scan lines GL1, and the first output terminals O1 of the plurality of second gate driving circuits GA2 are electrically connected to the plurality of sub-pixels Spi through the plurality of second scan lines GL2.

[0051] Please continue to refer to Figures 1A to 1B and Figures 2A to 2B. The control ends of the compensation transistors Tc of multiple sub-pixels Spi are electrically connected to the first output end O1 of the multi-stage first gate driving circuit GA1, and the control ends of the reset transistors Tr of multiple sub-pixels Spi are electrically connected to the first output end O1 of the multi-stage second gate driving circuit GA2, so that the reset transistor Tr and the compensation transistor Tc are no longer controlled by the gate control signal generated by the same gate driving unit, but the compensation transistor Tc and the reset transistor Tr are controlled by the gate control signals generated by different gate driving units, so that the reset transistor Tr of one sub-pixel Spi and the compensation transistor Tc of another sub-pixel Spi are no longer in a synchronized working state due to being controlled by the same gate control signal, but the working states of the reset transistors Tr and the compensation transistors Tc of different sub-pixels Spi are independent. Moreover, since the first gate drive circuit GA1 can realize the level control of the first gate control signal Nscan1 according to the first frequency-division control signal NF1, and the second gate drive circuit GA2 can realize the level control of the second gate control signal Nscan2 according to the second frequency-division control signal NF2, the first frequency-division control signal NF1 and the second frequency-division control signal NF2 can make the frequency of the second gate control signal Nscan2 received by the reset transistor Tr in the same sub-pixel Spii the same as the frequency of the first gate control signal Nscan1 received by the compensation transistor Tc, so that the conduction frequency of the reset transistor Tr and the compensation transistor Tc in the same sub-pixel Spii is the same, thereby improving the problem of abnormal display of the sub-pixel Spii in some sub-pixels Spi at the corresponding frequency-division position in the display panel DP because the gate control signal used by the compensation transistor Tc is low-frequency, while the gate control signal used by the reset transistor Tr is still high-frequency.

[0052] Alternatively, referring to Figures 1A and 1B , the display panel DP includes a display area AA and a first non-display area DA1 and a second non-display area DA2 located on opposite sides of the display area AA. A plurality of sub-pixels Spi are located in the display area AA, a first gate driver unit GM1 is located in the first non-display area DA1, and a second gate driver unit GM2 is located in the second non-display area DA2. By separately disposing the first and second gate driver units GM1 and GM2 in the first non-display area DA1 and the second display area DA2, the bezel size of the display panel DP can be reduced.

[0053] Accordingly, because the control terminals of the compensation transistors Tc of the plurality of sub-pixels Spi are electrically connected to the first output terminals O1 of the multi-stage first gate drive circuit GA1, and the control terminals of the reset transistors Tr of the plurality of sub-pixels Spi are electrically connected to the first output terminals O1 of the multi-stage second gate drive circuit GA2, a unilateral drive design is implemented for the compensation transistors Tc of the plurality of sub-pixels Spi, and a unilateral drive design is implemented for the reset transistors Tr of the plurality of sub-pixels Spi. That is, the multi-stage first gate drive circuit GA1 is electrically connected to the control terminals of the compensation transistors Tc of the plurality of sub-pixels Spi via a unilateral drive method, and the multi-stage second gate drive circuit GA2 is electrically connected to the control terminals of the reset transistors Tr of the plurality of sub-pixels Spi via a unilateral drive method. This is beneficial for reducing the bezel size of the display panel DP.

[0054] Optionally, to save power and reduce the frame size of the display panel DP, a single gate driver circuit can be configured to simultaneously output multiple gate control signals. Accordingly, the multiple gate control signals output by the single gate driver circuit can be used to control the conduction states of different transistors in the same sub-pixel Spi.

[0055] For example, the first gate driver circuit GA1 includes a second output terminal O2, and the second output terminal O2 of the first gate driver circuit GA1 outputs a third gate control signal Pscan1. The control terminals of the data transistors Tda of the plurality of sub-pixels Spi are electrically connected to the second output terminals O2 of the plurality of first gate driver circuits GA1, so that the data transistors Tda of the plurality of sub-pixels Spi are controlled by the third gate control signal Pscan1 output by the plurality of first gate driver circuits GA1.

[0056] For example, the second gate driver circuit GA2 includes a second output terminal O2, and the second output terminal O2 of the second gate driver circuit GA2 outputs a fourth gate control signal Pscan2. The control terminals of the data transistors Tda of the plurality of sub-pixels Spi are electrically connected to the second output terminals O2 of the plurality of second gate driver circuits GA2, so that the data transistors Tda of the plurality of sub-pixels Spi are controlled by the fourth gate control signal Pscan2 output by the plurality of second gate driver circuits GA2.

[0057] For example, the first gate driver circuit GA1 and the second gate driver circuit GA2 both include a second output terminal O2. The second output terminal O2 of the first gate driver circuit GA1 outputs the third gate control signal Pscan1, and the second output terminal O2 of the second gate driver circuit GA2 outputs the fourth gate control signal Pscan2. The control terminals of the data transistors Tda of the plurality of sub-pixels Spi are electrically connected to the second output terminals O2 of the plurality of first gate driver circuits GA1 and / or the second output terminals O2 of the plurality of second gate driver circuits GA2.

[0058] That is, in a sub-pixel Spi, the control end of the data transistor Tda can be electrically connected to the second output end O2 of the corresponding first gate drive circuit GA1, or can be electrically connected to the second output end O2 of the corresponding second gate drive circuit GA2, or can be electrically connected to both the second output end O2 of the corresponding first gate drive circuit GA1 and the second output end O2 of the corresponding second gate drive circuit GA2. Therefore, in a sub-pixel Spi, when the control end of the data transistor Tda is electrically connected to the second output end O2 of the corresponding first gate drive circuit GA1 or the second output end O2 of the corresponding second gate drive circuit GA2, a single-sided drive design is formed; and in a sub-pixel Spi, when the control end of the data transistor Tda is electrically connected to both the second output end O2 of the corresponding first gate drive circuit GA1 and the second output end O2 of the corresponding second gate drive circuit GA2, a double-sided drive design is formed. Optionally, the second output terminals O2 of the plurality of first gate driving circuits GA1 are electrically connected to the plurality of sub-pixels Spi through the plurality of third scan lines GL3; the second output terminals O2 of the plurality of second gate driving circuits GA2 are electrically connected to the plurality of sub-pixels Spi through the plurality of third scan lines GL3.

[0059] Figures 5A and 5B are schematic diagrams of the structures of the first and second gate drive units provided in embodiments of the present application, and Figures 6A and 6B are schematic diagrams of the structures of the gate drive circuits provided in embodiments of the present application. The circuit structure of at least one of the first gate drive circuit GA1 and the second gate drive circuit GA2 is shown in Figures 6A and 6B. In Figures 6A and 6B, O21 and O22 each represent a second output terminal, and Cka and CKb each represent a second clock signal.

[0060] At least one of the first gate driving circuit GA1 and the second gate driving circuit GA2 includes a node control module 10 , a first frequency division control module 20 and a first output module 30 .

[0061] The node control module 10 is electrically connected to the first node K1 of the gate driving circuit at this stage. The node control module 10 is configured to control the signal of the first node K1 according to the corresponding start signal STV and the first clock signal XCK.

[0062] Alternatively, referring to FIG5A and FIG5B , the first-stage first gate driver circuit GA1(1) among the plurality of first gate driver circuits GA1 uses the first start signal stv1 as the start signal STV, so that the first-stage first gate driver circuit GA1(1) controls the signal of the first node K1 of the first-stage first gate driver circuit GA1(1) according to the corresponding first clock signal XCK and the first start signal stv1. The first-stage second gate driver circuit GA2(1) among the plurality of second gate driver circuits GA2 uses the second start signal stv2 as the start signal STV, so that the first-stage second gate driver circuit GA2(1) controls the signal of the first node K1 of the first-stage second gate driver circuit GA2(1) according to the corresponding first clock signal XCK and the second start signal stv2.

[0063] Optionally, the M-th first gate drive circuit GA1(M) among the multiple first gate drive circuits GA1 uses the MA-th first gate control signal Nscan1(MA) output by the MA-th first gate drive circuit GA1(MA) as the start signal STV, so that the M-th first gate drive circuit GA1(M) controls the signal of the first node K1 of the M-th first gate drive circuit GA1(M) according to the corresponding first clock signal XCK and the MA-th first gate control signal Nscan1(MA) output by the MA-th first gate drive circuit GA1(MA). Wherein, M>1, A≥1. The Nth-stage second gate drive circuit GA2(N) among the plurality of second gate drive circuits GA2 uses the NBth-stage second gate control signal Nscan2(NB) output by the NBth-stage second gate drive circuit GA2(NB) as the start signal STV, so that the Nth-stage second gate drive circuit GA2(N) controls the signal of the first node K1 of the Nth-stage second gate drive circuit GA2 according to the corresponding first clock signal XCK and the NBth-stage second gate control signal Nscan2(NB) output by the NBth-stage second gate drive circuit GA2(NB). Wherein, N>1, B≥1.

[0064] For example, the first-stage first gate control signal Nscan1(1) outputted from the first output terminal O1 of the first-stage first gate driver circuit GA1(1) can be used as the start signal STV by the second-stage first gate driver circuit GA1. Similarly, a cascade arrangement of multiple second gate driver circuits GA2 can also be obtained.

[0065] It should be noted that the first M-stage gate drive circuit in the multi-stage gate drive circuit can be called a virtual gate drive circuit (the gate drive circuit shown in the dotted box included in the gate drive unit in Figures 1A to 1B) to provide a corresponding start signal STV to the gate drive circuit cascaded thereafter.

[0066] Alternatively, please continue to refer to Figures 6A and 6B, which illustrate the structure of the node control module 10 by taking one of the p-th level first gate drive circuit GA1(p) and the p-th level second gate drive circuit GA2(p) as an example. When Figures 6A and 6B correspond to representing the p-th level first gate drive circuit GA1(p), O1(p-1) represents the first output terminal of the p-1-th level first gate drive circuit GA1(p-1). When Figures 6A and 6B correspond to representing the p-th level second gate drive circuit GA2(p), O1(p-1) represents the first output terminal of the p-1-th level second gate drive circuit GA2(p-1). Where p≥1. When p=1, O1(p-1) corresponds to the first start signal stv1 or the second start signal stv2.

[0067] As shown in FIG. 6A and FIG. 6B , the node control module 10 includes a first transistor T1 , a second transistor T2 , and a third transistor T3 .

[0068] The first control terminal and the second control terminal of the first transistor T1 are configured to receive a corresponding start signal STV, and the input terminal of the first transistor T1 is electrically connected to the first power terminal PVGL.

[0069] The control end of the second transistor T2 is electrically connected to the first control end of the first transistor T1 , the input end of the second transistor T2 is electrically connected to the second power supply end PVGH, and the output end of the second transistor T2 is electrically connected to the output end of the first transistor T1 .

[0070] The control end of the third transistor T3 is configured to receive the corresponding first clock signal XCK, the input end of the third transistor T3 is electrically connected to the output end of the first transistor T1 , and the output end of the third transistor T3 is electrically connected to the first node K1 .

[0071] Optionally, the node control module 10 is also electrically connected to the third node K3 of the gate drive circuit at this level, and the node control module 10 is configured to control the electrical connection between the second power terminal PVGH or the third power terminal NVGL and the first node K1 according to the potential of the third node K3.

[0072] Optionally, the node control module 10 includes a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6.

[0073] The first control terminal and the second control terminal of the fourth transistor T4 are configured to receive a corresponding first clock signal XCK, and the output terminal of the fourth transistor T4 is electrically connected to the first node K1. The control terminal of the fifth transistor T5 and the first control terminal and the second control terminal of the sixth transistor T6 are electrically connected to the third node K3. The input terminal of the fifth transistor T5 is electrically connected to the second power supply terminal PVGH, the output terminal of the fifth transistor T5 is electrically connected to the input terminal of the fourth transistor T4, the input terminal of the sixth transistor T6 is electrically connected to the third power supply terminal NVGL, and the output terminal of the sixth transistor T6 is electrically connected to the first node K1.

[0074] 6A-6B , the node control module 10 is configured to control signal transmission between the first power terminal PVGL or the second power terminal PVGH and the third node K3 according to the signal of the first node K1 .

[0075] Optionally, the node control module 10 further includes a seventh transistor T7 and an eighth transistor T8.

[0076] The first control terminal and the second control terminal of the seventh transistor T7 are electrically connected to the first node K1, the input terminal of the seventh transistor T7 is electrically connected to the first power supply terminal PVGL, the output terminal of the seventh transistor T7 is electrically connected to the third node K3, the control terminal of the eighth transistor T8 is electrically connected to the first node K1, the input terminal of the eighth transistor T8 is electrically connected to the second power supply terminal PVGH, and the output terminal of the eighth transistor T8 is electrically connected to the third node K3.

[0077] 6A and 6B , the first frequency division control module 20 is electrically connected to the first node K1, the second node K2, and the third node K3 of the gate drive circuit at this stage. The first frequency division control module 20 is configured to control signal transmission between the first node K1 and the second node K2 based on the signal of the third node K3 and the corresponding frequency division control signal.

[0078] Optionally, the first frequency-dividing control module 20 includes a first frequency-dividing transistor Tf1 , a second frequency-dividing transistor Tf2 , and a first capacitor C1 .

[0079] The control end of the first frequency-dividing transistor Tf1 is electrically connected to the third node K3 of the gate drive circuit at this level, and the input end of the first frequency-dividing transistor Tf1 is configured to receive the corresponding frequency-dividing control signal (that is, the input end of the first frequency-dividing transistor Tf1 in the first gate drive circuit GA1 is configured to receive the first frequency-dividing control signal NF1, and the input end of the first frequency-dividing transistor Tf1 in the second gate drive circuit GA2 is configured to receive the second frequency-dividing control signal NF2).

[0080] The control end of the second frequency dividing transistor Tf2 is electrically connected to the output end of the first frequency dividing transistor Tf1 , the input end of the second frequency dividing transistor Tf2 is electrically connected to the first node K1 , and the output end of the second frequency dividing transistor Tf2 is electrically connected to the second node K2 .

[0081] A first end of the first capacitor C1 is electrically connected to the control end of the second frequency-dividing transistor Tf2 , and a second end of the first capacitor C1 is electrically connected to the second node K2 .

[0082] 6A to 6B , the first output module 30 is electrically connected to the first node K1, the second node K2 and the first output end O1. The first output module 30 is configured to control the gate control signal outputted by the first output end O1 according to the signals of the first node K1 and the second node K2.

[0083] Optionally, the first output module 30 includes a first output transistor To1 and a second output transistor To2 .

[0084] The first control terminal and the second control terminal of the first output transistor To1 are electrically connected to the first node K1 , and the input terminal of the first output transistor To1 is electrically connected to the third power terminal NVGL.

[0085] The control end of the second output transistor To2 is electrically connected to the second node K2, the input end of the second output transistor To2 is electrically connected to the fourth power supply end NVGH, and the output end of the second output transistor To2 and the output end of the first output transistor To1 are electrically connected to the first output end O1 of the gate drive circuit of this stage.

[0086] Optionally, a first frequency-dividing control signal NF1 may be provided for each first gate drive circuit GA1 to implement level control of the first gate control signal Nscan1 output by each first gate drive circuit GA1. Similarly, a second frequency-dividing control signal NF2 may be provided for each second gate drive circuit GA2 to implement level control of the second gate control signal Nscan2 output by each second gate drive circuit GA2.

[0087] Optionally, to reduce the number of frequency division control signals used by the display device, the first frequency division control modules 20 of multiple cascaded first gate drive circuits GA1 can share the same frequency division control signal to implement level control of multiple first gate control signals Nscan1. Similarly, the first frequency division control modules 20 of multiple cascaded second gate drive circuits GA2 can share the same frequency division control signal to implement level control of multiple second gate control signals Nscan2.

[0088] To enable the display panel DP to achieve frequency division display, the on-time and on-duration of the compensation transistor Tc and the reset transistor Tr in the same sub-pixel Spi are different. Therefore, the frequency division control signal applied by the first frequency division control module 20 for controlling the plurality of cascaded second gate drive circuits GA2 is different from the frequency division control signal applied by the first frequency division control module 20 for controlling the plurality of cascaded first gate drive circuits GA1.

[0089] Continuing with Figures 5A and 5B , the multiple frequency-division control lines FL include a first frequency-division control line FL1 and a second frequency-division control line FL2. The first frequency-division control line FL1 transmits a first frequency-division control signal NF1, and the second frequency-division control line FL2 transmits a second frequency-division control signal NF2. A first frequency-division control module 20 of the multi-stage first gate drive circuit GA1 is electrically connected to the first frequency-division control line FL1, while a first frequency-division control module 20 of the multi-stage second gate drive circuit GA2 is electrically connected to the second frequency-division control line FL2. This reduces the number of frequency-division control signals used in the display device while enabling independent operation of the compensation transistors Tc and reset transistors Tr of the multiple sub-pixels Spi.

[0090] Optionally, referring to Figures 6A and 6B, at least one gate drive circuit further includes a first control module 40. The first control module 40 is electrically connected to the third node K3 of the gate drive circuit at the current stage and the second node K2 of the gate drive circuit at the current stage GDC. The first control module 40 is configured to control signal transmission between the second power supply terminal PVGH and the second node K2 based on the corresponding first clock signal XCK and the potential of the third node K3.

[0091] Optionally, the first control module 40 includes a ninth transistor T9 and a tenth transistor T10.

[0092] The first control terminal and the second control terminal of the ninth transistor T9 are configured to receive the corresponding first clock signal XCK, and the output terminal of the ninth transistor T9 is electrically connected to the second node K2.

[0093] The control end of the tenth transistor T10 is electrically connected to the third node K3 of the current gate driving circuit, the input end of the tenth transistor T10 is electrically connected to the second power supply end PVGH, and the output end of the tenth transistor T10 is electrically connected to the input end of the ninth transistor T9.

[0094] Since the gate control signal received by the control end of the data transistor Tda can be provided by at least one of the first gate driving unit GM1 and the second gate driving unit GM2, at least one of the first gate driving circuit GA1 included in the first gate driving unit GM1 and the second gate driving circuit GA2 included in the second gate driving unit GM2 can also include a second output module 50 to provide the required gate control signal to the data transistor Tda of the corresponding sub-pixel Spi through the second output module 50.

[0095] The second output module 50 is electrically connected to the first node K1, the third node K3, and the second output terminal O2 of the current-stage gate driver circuit. The second output module 50 is configured to control the gate control signal output by the second output terminal O2 based on the signals at the first and third nodes K1 and K3 and the corresponding second clock signal CK. Continuing with Figures 6A and 6B , the second output module 50 includes a third output transistor To3, a fourth output transistor To4, and a second capacitor C2.

[0096] The control terminal of the third output transistor To3 is electrically connected to the first node K1 , and the input terminal of the third output transistor To3 is configured to receive the corresponding second clock signal CK.

[0097] The control end of the fourth output transistor To4 is electrically connected to the third node K3, the input end of the fourth output transistor To4 is electrically connected to the second power supply end PVGH, and the output end of the fourth output transistor To4 and the output end of the third output transistor To3 are electrically connected to the second output end O2 of the current-stage gate drive circuit GDC.

[0098] A first end of the second capacitor C2 is electrically connected to the control end of the third output transistor To3 , and a second end of the second capacitor C2 is electrically connected to the second output end O2 of the current-stage gate driving circuit GDC.

[0099] Optionally, the first gate driving circuit GA1 includes X second output modules 50 and X second output terminals O2 , and each second output module 50 is electrically connected to a corresponding second output terminal O2 , where X≥1.

[0100] That is, as shown in FIG. 6A , a single first gate driving circuit GA1 may include a second output module 50 , so that the single first gate driving circuit GA1 can simultaneously output a first gate control signal Nscan1 and a third gate control signal Pscan1 .

[0101] Optionally, as shown in FIG6B , to reduce the border size of the display panel DP, a single first gate driving circuit GA1 may include multiple second output modules 50 so that the single first gate driving circuit GA1 can simultaneously output a first gate control signal Nscan1 and multiple third gate control signals Pscan1.

[0102] Optionally, in order to improve the utilization rate of the multiple second output modules 50 of the first gate drive circuit GA1, when the first gate drive circuit GA1 includes multiple second output modules 50 (i.e., X>1), the X second output modules 50 of the same first gate drive circuit GA1 are configured to output multiple third gate control signals Pscan1 with phase differences, so that the data transistors Tda driven by the multiple third gate control signals Pscan1 output by the same first gate drive circuit GA1 can be turned on in different time periods, thereby reducing the power consumption of the display device.

[0103] Similarly, the second gate driving circuit GA2 includes X second output modules 50 and X second output terminals O2 , and each second output module 50 is electrically connected to a corresponding second output terminal O2 , where X≥1.

[0104] That is, as shown in FIG. 6A , a single second gate driving circuit GA2 may include a second output module 50 , so that the single second gate driving circuit GA2 can simultaneously output a second gate control signal Nscan2 and a fourth gate control signal Pscan2 .

[0105] Optionally, as shown in FIG6B , in order to reduce the border size of the display panel DP, a single second gate driving circuit GA2 may include multiple second output modules 50 so that the single second gate driving circuit GA2 can simultaneously output a second gate control signal Nscan2 and multiple fourth gate control signals Pscan2.

[0106] Optionally, in order to improve the utilization rate of the multiple second output modules 50 of the second gate drive circuit GA2, when the second gate drive circuit GA2 includes multiple second output modules 50 (i.e., X>1), the X second output modules 50 of the same second gate drive circuit GA2 are configured to output multiple fourth gate control signals Pscan2 with phase differences, so that the data transistors Tda driven by the multiple fourth gate control signals Pscan2 output by the same second gate drive circuit GA2 can be turned on in different time periods, thereby reducing the power consumption of the display device.

[0107] Optionally, each second output terminal O2 can be electrically connected to the control terminal of the data transistor Tda of a plurality of sub-pixels Spii located in at least one row, so that each third gate control signal Pscan1 output by the first gate driving circuit GA1 or each fourth gate control signal Pscan2 output by the second gate driving circuit GA2 can drive the data transistor Tda of at least one row of sub-pixels Spii.

[0108] Optionally, in order to enable multiple rows of sub-pixels Spi to be driven by corresponding gate control signals in sequence at the same time interval, the phase difference between the first clock signals corresponding to two adjacent first gate drive circuits GA1 is XH, and the phase difference between the first clock signals corresponding to two adjacent second gate drive circuits GA2 is XH; H represents the unit time length.

[0109] Optionally, H may be set to correspond to the length of the row cycle.

[0110] Optionally, each third gate control signal Pscan1 output by the first gate drive circuit GA1 and / or each fourth gate control signal Pscan2 output by the second gate drive circuit GA2 can drive the data transistor Tda of a row of sub-pixels Spii, and the control end of the data transistor Tda of the sub-pixels Spii located in the Lth row to the L+X-1th row is electrically connected to the X second output ends O2 of the Kth-level first gate drive circuit GA1 and / or the X second output ends O2 of the Kth-level second gate drive circuit GA2; wherein, K≥1, L= XK-(X-1). If the first gate driving circuit GA1 and the second gate driving circuit GA2 both include a second output module 50 (i.e., X=1), at least one of the second output terminal O2 of the K-th level first gate driving circuit GA1(K) and the second output terminal O2 of the K-th level second gate driving circuit GA2(K) is electrically connected to the control terminal of the data transistor Tda of the sub-pixel Spii located in the L-th row (i.e., the K-th row), so that the data transistors Tda of multiple sub-pixels Spii can match the gate control signals used by the compensation transistor Tc and the reset transistor Tr, thereby completing the transmission of the data signal.

[0111] For example, the first gate driving circuit GA1 and the second gate driving circuit GA2 both include two second output modules 50 (i.e., X=2), and at least one of the second output terminal O2 of the K-th level first gate driving circuit GA1(K) and the second output terminal O2 of the K-th level second gate driving circuit GA2(K) is electrically connected to the control terminal of the data transistor Tda of the sub-pixel Spii located in the L-th row (i.e., the 2K-1 row) to the L+1-th row (i.e., the 2K row), so that the data transistor Tda of multiple sub-pixels Spii can match the gate control signals used by the compensation transistor Tc and the reset transistor Tr, thereby completing the transmission of the data signal.

[0112] Optionally, according to the number of second output modules 50 included in the gate driving unit, the compensation transistor Tc and the reset transistor Tr may be controlled to apply gate control signals of different levels to implement the operation of refreshing display data of the sub-pixel Spi.

[0113] Continuing with FIG1A , the first gate driver circuit GA1 and the second gate driver circuit GA2 each include a second output module 50 (i.e., X=1). The control terminal of the compensation transistor Tc of the sub-pixel Spi in the Lth row is electrically connected to the first output terminal O1 of the first gate driver circuit GA1 in the K+Ath stage, and the control terminal of the reset transistor Tr of the sub-pixel Spi in the Lth row is electrically connected to the first output terminal O1 of the second gate driver circuit GA2 in the KBth stage. Where A≥1 and B≥1.

[0114] It should be noted that the K+A-th level first gate drive circuit GA1 (K+A) represents the first gate drive circuit GA1 that is cascaded after the K-th level first gate drive circuit GA1 (K), and the difference in the number of stages between it and the K-th level first gate drive circuit GA1 (K) is A; the KB-th level second gate drive circuit GA2 (KB) represents the second gate drive circuit GA2 that is cascaded before the K-th level second gate drive circuit GA2 (K), and the difference in the number of stages between it and the K-th level second gate drive circuit GA2 (K) is B. Therefore, when K=1, the KB-th level second gate drive circuit GA2 (KB) represents the second gate drive circuit GA2 that is cascaded before the 1st level second gate drive circuit GA2 (1), and the difference in the number of stages between it and the 1st level second gate drive circuit GA2 (1) is B. Therefore, the first-level second gate drive circuit GA2 of the second gate drive circuit GA2 may not correspond to the 1st level second gate drive circuit GA2 (1).

[0115] Optionally, A=1, B=3. That is, the control end of the compensation transistor Tc of the sub-pixel Spi in the K-th row is electrically connected to the first output end O1 of the first gate drive circuit GA1 (K+1) of the K+1-th level, and the control end of the reset transistor Tr of the sub-pixel Spi in the K-th row is electrically connected to the first output end O1 of the second gate drive circuit GA2 (K-3) of the K-3-th level, so that the display panel DP can use the gate control signals received by the compensation transistor Tc and the reset transistor Tr to control the multiple sub-pixels Spi to achieve zoned frequency display.

[0116] When the first gate driver circuit GA1 includes multiple second output modules 50 (i.e., X≥2), the control terminals of the compensation transistors Tc of the sub-pixels Spi in the Lth to L+X-1th rows are electrically connected to the first output terminal O1 of the K+Cth stage first gate driver circuit GA1, where C≥0.

[0117] 1B , the first gate driving circuit GA1 includes two second output modules 50 , wherein the control terminals of the compensation transistors Tc of the sub-pixels Spi located in the Lth row (i.e., corresponding to the 2K-1th row) to the L+X-1th row (i.e., corresponding to the 2Kth row) are electrically connected to the first output terminal O1 of the Kth stage first gate driving circuit GA1 (i.e., C=0).

[0118] For another example, the first gate driving circuit GA1 includes three second output modules 50, and the control terminals of the compensation transistors Tc of the sub-pixels Spi located in the Lth row (i.e., corresponding to the 3K-2 row) to the L+X-1th row (i.e., corresponding to the 3Kth row) are electrically connected to the first output terminal O1 of the Kth stage first gate driving circuit GA1.

[0119] The control terminal of the compensation transistor Tc of the sub-pixel Spi in the Lth row is electrically connected to the first output terminal O1 of the first gate driver circuit GA1 of the K+Ath stage, and the control terminal of the reset transistor Tr of the sub-pixel Spi in the Lth row is electrically connected to the first output terminal O1 of the second gate driver circuit GA2 of the KBth stage. Where A≥1, B≥1.

[0120] When the second gate driving circuit GA2 includes multiple second output modules 50 (ie, X≥2), the control terminal of the reset transistor Tr of the sub-pixel Spi in the Lth row is electrically connected to the first output terminal O1 of the KDth stage second gate driving circuit GA2, where D≥0.

[0121] As shown in FIG1B , the second gate driving circuit GA2 includes two second output modules 50 , wherein the control terminals of the compensation transistors Tc of the sub-pixels Spi located in the Lth row (i.e., corresponding to the 2K-1th row) to the L+X-1th row (i.e., corresponding to the 2Kth row) are electrically connected to the first output terminal O1 of the K-2th level second gate driving circuit GA2 (i.e., D=2).

[0122] For another example, the second gate driving circuit GA2 includes three second output modules 50, and the control end of the reset transistor Tr of the sub-pixel Spi located in the Lth row (i.e. corresponding to the 3K-2 row) to the L+X-1th row (i.e. corresponding to the 3K row) is electrically connected to the first output end O1 of the K-2th level second gate driving circuit GA2.

[0123] Optionally, to further reduce the power consumption of the display device, the first gate drive circuit GA1 and / or the second gate drive circuit GA2 including the second output module 50 may also include a second frequency division control module 60 to achieve frequency control of the gate control signal output from the second output terminal O2 of the gate drive circuit.

[0124] The second frequency division control module 60 is electrically connected to the node control module 10 through the first node K1 and the third node K3 of the gate drive circuit of this stage, and is electrically connected to the second output module 50 through the fourth node K4 of the gate drive circuit of this stage. The second frequency division control module 60 is configured to control the signal transmission between the first node K1 and the fourth node K4 according to the corresponding frequency division control signal, thereby controlling the electrical connection between the second output module 50 and the first node K1 through the second frequency division control module 60, and the second output module 50 is configured to control the gate control signal output by the second output terminal O2 according to the signals of the third node K3 and the fourth node K4 and the corresponding second clock signal CK.

[0125] Optionally, please continue to refer to FIG. 6A to FIG. 6B , the second frequency-dividing control module 60 includes a third frequency-dividing transistor Tf3 , a fourth frequency-dividing transistor Tf4 and a third capacitor C3 .

[0126] The control terminal of the third frequency-dividing transistor Tf3 is electrically connected to the third node K3 of the gate driving circuit at this stage, and the input terminal of the third frequency-dividing transistor Tf3 is configured to receive a corresponding frequency-dividing control signal.

[0127] The control terminal of the fourth frequency-dividing transistor Tf4 is electrically connected to the output terminal of the third frequency-dividing transistor Tf3 , the input terminal of the fourth frequency-dividing transistor Tf4 is electrically connected to the first node K1 , and the output terminal of the fourth frequency-dividing transistor Tf4 is electrically connected to the fourth node K4 .

[0128] A first end of the third capacitor C3 is electrically connected to the control end of the fourth frequency-dividing transistor Tf4 , and a second end of the third capacitor C3 is electrically connected to the fourth node K4 .

[0129] Optionally, a frequency division control signal may be provided corresponding to each second frequency division control module 60 to control the frequency of the gate control signal outputted from the second output terminal O2 by the corresponding gate driving circuit.

[0130] Optionally, to reduce the number of frequency-division control signals used by the display device, the second frequency-division control modules 60 of multiple cascaded first gate drive circuits GA1 can share the same frequency-division control signal, thereby utilizing the single frequency-division control signal to control the levels of multiple third gate control signals Pscan1. Similarly, the second frequency-division control modules 60 of multiple cascaded second gate drive circuits GA2 can share the same frequency-division control signal, thereby utilizing the single frequency-division control signal to control the levels of multiple fourth gate control signals Pscan2. Optionally, when the first gate drive circuit GA1 includes a second output module 50, the first gate drive circuit GA1 can include a second frequency-division control module 60, and the second frequency-division control modules 60 of the multiple cascaded first gate drive circuits GA1 share the same frequency-division control signal, thereby reducing the number of frequency-division control signals used by the display device.

[0131] Optionally, when the first gate drive circuit GA1 includes multiple second output modules 50 (i.e., X ≥ 2), the first gate drive circuit GA1 may include at least one second frequency division control module 60. Specifically, the first gate drive circuit GA1 may include a second frequency division control module 60 to control the level of the third gate control signal Pscan output by the multiple second output modules 50. The first gate drive circuit GA1 may include multiple second frequency division control modules 60 to control the level of the third gate control signal Pscan output by the multiple second output modules 50, thereby independently controlling the level states of the multiple third gate control signals Pscan.

[0132] Optionally, when the first gate driving circuit GA1 is provided with a plurality of second frequency division control modules 60 , each second frequency division control module 60 is configured to control the level of the third gate control signal Pscan output by a corresponding second output module 50 according to the corresponding frequency division control signal.

[0133] Optionally, when the first gate driver circuit GA1 includes multiple second output modules 50 (i.e., X ≥ 2) and a second frequency-division control module 60, the second frequency-division control modules 60 of the multiple cascaded first gate driver circuits GA1 may share the same frequency-division control signal. For example, the second frequency-division control modules 60 of the multiple stages of first gate driver circuits GA1 may be electrically connected to the third frequency-division control line FL3 to reduce the number of frequency-division control signals used by the display device.

[0134] Optionally, when the first gate drive circuit GA1 includes multiple second output modules 50 (i.e., X≥2), when the first gate drive circuit GA1 includes multiple second frequency division control modules 60, the frequency division control signals applied by the multiple second frequency division control modules 60 included in the same first gate drive circuit GA1 may be different.

[0135] For example, each first gate drive circuit GA1 includes two second output modules 50 and two second frequency division control modules 60. The two second output modules 50 include a first sub-output module and a second sub-output module. The two second frequency division control modules 60 include a first sub-frequency division control module and a second sub-frequency division control module. The first sub-frequency division control module is configured to control the level of the third gate control signal Pscan output by the first sub-output module based on a frequency division control signal, and the second sub-frequency division control module is configured to control the level of the third gate control signal Pscan output by the second sub-output module based on another frequency division control signal. The second output terminal corresponding to the first sub-output module can be O21 in FIG. 6B , and the second output terminal corresponding to the second sub-output module can be O22 in FIG. The second clock signal input terminal corresponding to the first sub-output module can be CKa in FIG. 6B , and the second clock signal input terminal corresponding to the second sub-output module can be CKb in FIG. 6B .

[0136] Optionally, the first sub-frequency division control modules of multiple cascaded first gate driving circuits GA1 share the same frequency division control signal, and the second sub-frequency division control modules of multiple cascaded first gate driving circuits GA1 share the same frequency division control signal to reduce the number of frequency division control signals used by the display device.

[0137] Similarly, when the second gate driving circuit GA2 includes X second output modules 50 , the number of second frequency division control modules 60 corresponding to the second gate driving circuit GA2 and the settings of the adapted frequency division control signals can also be obtained.

[0138] When the sub-pixel Spi needs to refresh its display data, the data transistor Tda must be turned on so that the data signal can be transmitted to the control terminal of the drive transistor Tdr. Therefore, the gate control signal corresponding to the data transistor Tda must also have a valid level during a specific period (such as the data writing phase described below). Therefore, the frequency-division control signal used to control the first frequency-division control module 20 can be different from the frequency-division control signal used to control the second frequency-division control module 60. This allows the levels of the gate control signal output from the first output terminal O1 and the gate control signal output from the second output terminal O2 in the same gate drive circuit to be independently controlled.

[0139] Accordingly, please continue to refer to Figures 5A to 5B. The multiple frequency division control lines FL include a third frequency division control line FL3, which transmits a third frequency division control signal PF1. Each first gate driver circuit GA1 includes a second frequency division control module 60. The second frequency division control module 60 of the multi-stage first gate driver circuit GA1 is electrically connected to the third frequency division control line FL3, so as to reduce the number of frequency division control signals used in the display device while making the working states of the data transistors Tda and the compensation transistors Tc of the multiple sub-pixels Spi independent.

[0140] Correspondingly, the plurality of frequency division control lines FL include a fourth frequency division control line FL4, which transmits a fourth frequency division control signal PF2. Each second gate drive circuit GA2 includes a second frequency division control module 60. The second frequency division control module 60 of the multi-stage second gate drive circuit GA2 is electrically connected to the fourth frequency division control line FL4, so as to reduce the number of frequency division control signals used in the display device while making the working states of the data transistors Tda and the reset transistor Tr of the plurality of sub-pixels Spi independent.

[0141] Correspondingly, the multiple frequency division control lines FL include a third frequency division control line FL3 and a fourth frequency division control line FL4, the second frequency division control module of the multi-level first gate drive circuit GA1 is electrically connected to the third frequency division control line FL3, and the second frequency division control module of the multi-level second gate drive circuit GA2 is electrically connected to the fourth frequency division control line FL4, so as to reduce the number of frequency division control signals used by the display device while making the working states of the data transistors Tda, compensation transistors Tc, and reset transistors Tr of multiple sub-pixels Spi independent.

[0142] Optionally, when the gate control signal received by the control end of the data transistor Tda is simultaneously supplied by the first gate driving unit GM1 and the second gate driving unit GM2, in order to keep the third gate control signal Pscan1 and the fourth gate control signal Pscan2 corresponding to the data transistor Tda the same, so as to stabilize the working state of the data transistor Tda, the frequency division control line corresponding to the second frequency division control module of the first gate driving unit GM1 can be electrically connected to the frequency division control line corresponding to the second frequency division control module of the second gate driving unit GM2, so that the second frequency division control module of the first gate driving unit GM1 and the second frequency division control module of the second gate driving unit GM2 apply the same frequency division control signal.

[0143] That is, the control terminals of the data transistors Tda of the plurality of sub-pixels Spi in the same row are electrically connected to the second output terminals O2 of the plurality of first gate drive circuits GA1 and the second output terminals O2 of the plurality of second gate drive circuits GA2. The third frequency-dividing control line FL3 and the fourth frequency-dividing control line FL4 are electrically connected so that the third gate control signal Pscan1 and the fourth gate control signal Pscan2 received by the data transistors Tda in the sub-pixels Spi remain identical. This stabilizes the operating state of the data transistors Tda in the sub-pixels Spi and reduces the number of frequency-dividing control signals used.

[0144] It will be appreciated that when each first gate drive circuit GA1 includes multiple second frequency-division control modules 60, the multiple frequency-division control lines FL may include, in addition to the third frequency-division control line FL3 connected to one second frequency-division control module 60, frequency-division control lines connected to the remaining second frequency-division control modules 60. For example, if each first gate drive circuit GA1 includes two second frequency-division control modules 60, the multiple frequency-division control lines FL may include a fifth frequency-division control line. One second frequency-division control module 60 in each stage of the first gate drive circuit GA1 is electrically connected to the third frequency-division control line FL3, and another second frequency-division control module 60 in each stage of the first gate drive circuit GA1 is electrically connected to the fifth frequency-division control line, so that the operating states of the two second frequency-division control modules 60 in each first gate drive circuit GA1 are independent.

[0145] Similarly, when each second gate driver circuit GA1 includes multiple second frequency-division control modules 60, the multiple frequency-division control lines FL may include, in addition to the fourth frequency-division control line FL4 connected to one second frequency-division control module 60, frequency-division control lines connected to the remaining second frequency-division control modules 60. If each second gate driver circuit GA2 includes two second frequency-division control modules 60, the multiple frequency-division control lines FL may include a sixth frequency-division control line. One second frequency-division control module 60 in each stage of the second gate driver circuit GA2 is electrically connected to the fourth frequency-division control line FL4, and another second frequency-division control module 60 in each stage of the second gate driver circuit GA2 is electrically connected to the sixth frequency-division control line, so that the operating states of the two second frequency-division control modules 60 in each second gate driver circuit GA2 are independent.

[0146] Accordingly, when the gate control signal received by the control terminal of the data transistor Tda is simultaneously supplied by the first gate driving unit GM1 and the second gate driving unit GM2, and both the first gate driving circuit GA1 and the second gate driving circuit GA2 include multiple second frequency-dividing control modules 60, the frequency-dividing control signals applied by the second frequency-dividing control module corresponding to the third gate control signal Pscan1 and the fourth gate control signal Pscan2 received by the control terminal of the data transistor Tda in the plurality of sub-pixels Spi in the same row can still be maintained identical. If the frequency-dividing control signals applied by the second frequency-dividing control module corresponding to the third gate control signal Pscan1 and the fourth gate control signal Pscan2 received by the control terminal of the data transistor Tda in the plurality of sub-pixels Spi in the same row are signals transmitted by the fifth frequency-dividing control line and the sixth frequency-dividing control line, the fifth frequency-dividing control line and the sixth frequency-dividing control line can be electrically connected to ensure that the third gate control signal Pscan1 and the fourth gate control signal Pscan2 received by the data transistor Tda remain identical, thereby stabilizing the operating state of the data transistor Tda.

[0147] Because the first-stage first gate driving circuit GA1(1) included in the first gate driving unit GM1 uses the first start signal stv1 as the start signal STV, and the first-stage second gate driving circuit GA2(1) included in the second gate driving unit GM2 uses the second start signal stv2 as the start signal STV, the phase difference between the first start signal and the second start signal is the same as the phase difference between the first gate driving circuit GA1 of each stage in the first gate driving unit GM1 and the second gate driving circuit GA2 of the same stage in the second gate driving unit GM2. Therefore, when the control end of the data transistor Tda simultaneously receives the third gate control signal Pscan1 and the fourth gate control signal Pscan2, the corresponding transition moments of the first start signal stv1 and the second start signal stv2 from the active level to the inactive level can be controlled to remain the same, so that the third gate control signal Pscan1 and the fourth gate control signal Pscan2 received by the data transistor Tda of a sub-pixel Spi remain the same, thereby stabilizing the working state of the data transistor Tda.

[0148] That is, the start signal STV (such as the aforementioned first start signal stv1) corresponding to the first-stage first gate drive circuit GA1(1) in the multi-stage first gate drive circuit GA1 has a transition from an active level to an inactive level at a first moment, and the start signal STV (such as the aforementioned second start signal stv2) corresponding to the first-stage second gate drive circuit GA2(1) in the multi-stage second gate drive circuit GA2 has a transition from an active level to an inactive level at a first moment. The first moment can be referred to as ta in FIG. 8A below.

[0149] It can be understood that if the transistor is an N-type transistor, then the signal received by the control terminal of the transistor has a valid level, that is, the signal received by the control terminal of the transistor has a high level, and the signal received by the control terminal of the transistor has an invalid level, that is, the signal received by the control terminal of the transistor has a low level. If the transistor is a P-type transistor, then the signal received by the control terminal of the transistor has a valid level, that is, the signal received by the control terminal of the transistor has a low level, and the signal received by the control terminal of the transistor has an invalid level, that is, the signal received by the control terminal of the transistor has a high level.

[0150] Optionally, the pulse widths of the active levels of the first start signal stv1 and the second start signal stv2 may be the same or different.

[0151] Optionally, in some embodiments, in a sub-pixel Spi, after the first gate control signal Nscan1 corresponding to the compensation transistor Tc and the second gate control signal Nscan2 corresponding to the reset transistor Tr are reduced to low frequency, the gate control signal corresponding to the data transistor Tda (i.e., the third gate control signal Pscan1 and / or the fourth gate control signal Pscan2) can maintain a high frequency or be reduced to a low frequency.

[0152] For example, the display panel DP is used to implement a static image display. The high-frequency and low-frequency image display principle diagram provided in the embodiment of the present application in FIG7 is used for explanation. When the display panel DP is displayed at a high frequency (such as 120 Hz), the display panel DP needs to perform 120 display data refresh operations within 1 second, that is, 120 frames are included in 1 second, and each frame display is refreshed. When the display panel DP is displayed at a low frequency (such as 1 Hz), the display panel DP will also contain 120 frames within 1 second, but only the first frame performs the display data refresh operation. The 119 consecutive frames after the first frame all maintain the image data signal of the first frame, and do not perform the display data refresh operation. Among them, the frame for which the display data is refreshed can be recorded as a write frame WF, and the frame for which the display data is not refreshed can be recorded as a hold frame HF. Therefore, during the write frame WF, the first gate control signal Nscan1 corresponding to the compensation transistor Tc, the second gate control signal Nscan2 corresponding to the reset transistor Tr, and the gate control signal corresponding to the data transistor Tda must all have an active level to overwrite the original data signal stored at the control terminal of the drive transistor Tdr with the newly written data signal, so that the sub-pixel Spi can display again according to the newly written data signal during the write frame. During the hold frame HF, the first gate control signal Nscan1 corresponding to the compensation transistor Tc and the second gate control signal Nscan2 corresponding to the reset transistor Tr of some sub-pixels Spi remain at an inactive level, turning off the compensation transistor Tc and the reset transistor Tr, so that no new data signal is stored at the control terminal of the drive transistor Tdr. During the hold frame HF, the gate control signal corresponding to the data transistor Tda can maintain the same frequency as the write frame WF. Alternatively, during the hold frame HF, the gate control signal corresponding to the data transistor Tda can remain at an inactive level so that the frequency of the gate control signal corresponding to the data transistor Tda during the hold frame HF is lower than the frequency during the write frame WF.

[0153] Optionally, in some embodiments, in the hold frame HF, the data transistor Tda is turned on according to the corresponding gate control signal to reset the potential of the input terminal of the driving transistor Tdr using the signal transmitted by the data line DL electrically connected to the data transistor Tda.

[0154] Optionally, in some embodiments, in the holding frame HF, the data transistor Tda remains cut off according to the corresponding gate control signal, and the second initial transistor Ti2 has a conduction period according to the gate control signal transmitted by the corresponding fourth scan line GL4, so as to utilize the second initial signal transmitted by the second initial line VL2 electrically connected to the second initial transistor Ti2 to reset the potential of the input end of the driving transistor Tdr.

[0155] Optionally, please continue to refer to Figures 6A to 6B. At least one gate drive circuit GDC further includes a switch module 70, which is electrically connected between the second frequency division control module 60 and the fourth node K4. The switch module 70 is configured to control the electrical connection between the second frequency division control module 60 and the fourth node K2 according to a corresponding switch control signal SC.

[0156] Optionally, the switch module 70 includes an eleventh transistor T11, the control end of the eleventh transistor T11 is configured to receive a switch control signal SC, the input end of the eleventh transistor T11 is electrically connected to the output end of the fourth frequency-dividing transistor Tf4, and the output end of the eleventh transistor T11 is electrically connected to the fourth node.

[0157] Optionally, the control terminal of the eleventh transistor T11 of the K-th-stage first gate driver circuit GA1(K) is configured to receive the KE-th-stage first gate control signal Nscan1(KE) output by the KE-th-stage first gate driver circuit GA1(KE), so as to use the KE-th-stage first gate control signal Nscan1(KE) output by the KE-th-stage first gate driver circuit GA1(KE) as the switch control signal SC received by the control terminal of the eleventh transistor T11 of the K-th-stage first gate driver circuit GA1(K). Where E≥1.

[0158] Optionally, the switch control signal SC received by the control end of the eleventh transistor T11 of the first-stage first gate drive circuit GA1(1) to the second-stage first gate drive circuit GA1(2) corresponds to the low-level signal VGL, and the control end of the eleventh transistor T11 of each stage of the gate drive circuit after the second-stage first gate drive circuit GA1(2) is configured to receive the first gate control signal Nscan1 output by the first two stages of the first gate drive circuit GA1 (for example, the control end of the eleventh transistor T11 of the third-stage first gate drive circuit GA1(3) as shown in FIG5A to FIG5B is configured to receive the first-stage first gate control signal Nscan1(1) output by the first-stage first gate drive circuit GA1(1). Similarly, the switch control signal SC corresponding to each stage of the second gate drive circuit GA2 in the second gate drive unit GM2 can also be obtained.

[0159] Optionally, the control terminal of the eleventh transistor T11 is electrically connected to the third node K3 of the previous-stage gate driver circuit, so that the potential of the third node K3 of the previous-stage gate driver circuit serves as a switch control signal SC to control the operating state of the eleventh transistor T11 and reduce the load on the first output terminal O1 of the gate driver circuit. For example, the control terminal of the eleventh transistor T11 of the K-th-stage first gate driver circuit GA1(K) is electrically connected to the third node K3 of the KE-th-stage first gate driver circuit GA1(KE), so that the potential of the third node K3 of the KE-th-stage first gate driver circuit GA1(KE) serves as the switch control signal SC received by the control terminal of the eleventh transistor T11 of the K-th-stage first gate driver circuit GA1(K).

[0160] Optionally, referring to Figures 6A and 6B, at least one gate drive circuit further includes a second control module 80. The second control module 80 is electrically connected to the third node K3 of the gate drive circuit GDC at the current stage and the switch module 70. The second control module 80 is configured to control signal transmission between the second power supply terminal PVGH and the switch module 70 based on the corresponding first clock signal XCK and the potential of the third node K3.

[0161] Optionally, the second control module 80 includes a twelfth transistor T12 and a thirteenth transistor T13.

[0162] The first control terminal and the second control terminal of the twelfth transistor T12 are configured to receive the corresponding first clock signal XCK, and the output terminal of the twelfth transistor T12 is electrically connected to the input terminal of the eleventh transistor T11 .

[0163] The control end of the thirteenth transistor T13 is electrically connected to the third node K3 of the current-stage gate driving circuit GDC, the input end of the thirteenth transistor T13 is electrically connected to the second power supply end PVGH, and the output end of the thirteenth transistor T13 is electrically connected to the input end of the twelfth transistor T12.

[0164] Optionally, referring to FIG. 6A to FIG. 6B , at least one gate driving circuit GDC further includes a reset module 90. The reset module 90 is electrically connected to the first node K1 and is configured to control signal transmission between the second power terminal PVGH and the first node K1 according to a reset control signal Ctl.

[0165] Optionally, the reset module 90 includes a reset transistor Tre, a control terminal of the reset transistor Tre is configured to receive a reset control signal Ctl, an input terminal of the reset transistor Tre is electrically connected to the second power terminal PVGH, and an output terminal of the reset transistor Tre is electrically connected to the first node K1.

[0166] Optionally, the reset module 90 is configured to be enabled when the display device is powered on and / or during a blanking interval.

[0167] Optionally, in some embodiments, the voltage corresponding to the first power terminal PVGL is smaller than the voltage corresponding to the second power terminal PVGH, and the voltage corresponding to the third power terminal NVGL is smaller than the voltage corresponding to the fourth power terminal NVGH.

[0168] Optionally, in some embodiments, at least one of the first transistor T1 , the fourth transistor T4 , the sixth transistor T6 , the seventh transistor T7 , the ninth transistor T9 , the twelfth transistor T12 and the first output transistor To1 may have only one control terminal.

[0169] It is understandable that each transistor included in the gate drive circuit GDC may be one of a P-type transistor and an N-type transistor. The semiconductor of each transistor included in the gate drive circuit GDC may be one of a silicon semiconductor and an oxide semiconductor.

[0170] Optionally, clock signals transmitted by multiple clock signal lines may be reused as first clock signals and second clock signals corresponding to multiple cascaded gate driving circuits to reduce power consumption of the display device and reduce the frame size of the display panel DP.

[0171] Optionally, the multiple first gate drive circuits GA1 included in the first gate drive unit GM1 can share clock signals transmitted by F clock lines as corresponding first and second clock signals. F is 2, 4, 6, 8, etc. Continuing with FIG. 5A , taking F equal to 4 as an example, the multiple clock lines include a first clock line CKL1, a second clock line CKL2, a third clock line CKL3, and a fourth clock line CKL4. Among them, when the first gate drive circuit GA1 includes a second output module 50, the first clock signal XCK corresponding to the 4m+1-th level first gate drive circuit GA1 (4m+1) corresponds to the signal transmitted by the second clock line CKL2, and the second clock signal CK corresponding to the 4m+1-th level first gate drive circuit GA1 (4m+1) corresponds to the signal transmitted by the first clock line CKL1; the first clock signal XCK corresponding to the 4m+2-th level first gate drive circuit GA1 (4m+2) corresponds to the signal transmitted by the third clock line CKL3, and the second clock signal CK corresponding to the 4m+2-th level first gate drive circuit GA1 (4m+2) corresponds to the signal transmitted by the third clock line CKL4. The first clock signal XCK corresponding to the first gate driver circuit GA1 (4m+3) of the 4m+3th level corresponds to the signal transmitted by the fourth clock line CKL4, and the second clock signal CK corresponding to the first gate driver circuit GA1 (4m+3) of the 4m+3th level corresponds to the signal transmitted by the third clock line CKL3; the first clock signal XCK corresponding to the first gate driver circuit GA1 (4m+4) of the 4m+4th level corresponds to the signal transmitted by the first clock line CKL1, and the second clock signal CK corresponding to the first gate driver circuit GA1 (4m+4) of the 4m+4th level corresponds to the signal transmitted by the fourth clock line CKL4. m≥0.

[0172] Optionally, when each first gate driving circuit GA1 includes multiple second output modules 50 (X≥2), the multiple first gate driving circuits GA1 included in the first gate driving unit GM1 share clock signals transmitted by F clock lines as corresponding second clock signals CK, where F=2X.

[0173] Continuing with FIG. 5B , each first gate driver circuit GA1 includes two second output modules 50 (X=2), and the first gate driver unit GM1 includes multiple first gate driver circuits GA1 that share four clock lines transmitting clock signals as corresponding second clock signals CK. The multiple clock lines include a first clock line CKL1, a second clock line CKL2, a third clock line CKL3, and a fourth clock line CKL4. Among them, the first clock line CKL1 transmits the corresponding second clock signal CK to a second output module 50 of the 2k+1-level first gate drive circuit GA1(2k+1), and the second clock line CKL2 transmits the corresponding second clock signal CK to another second output module 50 of the 2k+1-level first gate drive circuit GA1(2k+1); the third clock line CKL3 transmits the corresponding second clock signal CK to a second output module of the 2k+2-level first gate drive circuit GA1(2k+2), and the fourth clock line CKL4 transmits the corresponding second clock signal CK to another second output module of the 2k+2-level first gate drive circuit GA1(2k+2), k≥0.

[0174] Similarly, when each first gate driving circuit GA1 includes three second output modules 50 (X=3), the multiple first gate driving circuits GA1 included in the first gate driving unit GM1 can share clock signals transmitted by six clock lines as corresponding second clock signals CK.

[0175] For example, the three second output modules of each first gate driving circuit GA1 include a first sub-output module, a second sub-output module and a third sub-output module, and the multiple clock lines may further include a fifth clock line CKL5 and a sixth clock line CKL6.

[0176] The first clock line CKL1 transmits the corresponding second clock signal CK to the first sub-output module of the first gate drive circuit GA1 (2k+1) of the 2k+1 level, the second clock line CKL2 transmits the corresponding second clock signal CK to the second sub-output module of the first gate drive circuit GA1 (2k+1) of the 2k+1 level, and the third clock line CKL3 transmits the corresponding second clock signal CK to the third sub-output module of the first gate drive circuit GA1 (2k+1) of the 2k+1 level; the fourth clock line CKL4 transmits the corresponding second clock signal CK to the first sub-output module of the first gate drive circuit GA1 (2k+2) of the 2k+2 level, the fifth clock line CKL5 transmits the corresponding second clock signal CK to the second sub-output module of the first gate drive circuit GA1 (2k+2) of the 2k+2 level, and the sixth clock line CKL6 transmits the corresponding second clock signal CK to the third sub-output module of the first gate drive circuit GA1 (2k+2) of the 2k+2 level.

[0177] Alternatively, the fifth clock line CKL5 transmits the corresponding second clock signal CK to the first sub-output module of the 2k+1-level first gate drive circuit GA1(2k+1), the sixth clock line CKL6 transmits the corresponding second clock signal CK to the second sub-output module of the 2k+1-level first gate drive circuit GA1(2k+1), the first clock line CKL1 transmits the corresponding second clock signal CK to the third sub-output module of the 2k+1-level first gate drive circuit GA1(2k+1); the second clock line CKL2 transmits the corresponding second clock signal CK to the first sub-output module of the 2k+2-level first gate drive circuit GA1(2k+2), the third clock line CKL3 transmits the corresponding second clock signal CK to the second sub-output module of the 2k+2-level first gate drive circuit GA1(2k+2), and the fourth clock line CKL4 transmits the corresponding second clock signal CK to the third sub-output module of the 2k+2-level first gate drive circuit GA1(2k+2).

[0178] Alternatively, the sixth clock line CKL6 transmits the corresponding second clock signal CK to the first sub-output module of the 2k+1-level first gate drive circuit GA1(2k+1), the first clock line CKL1 transmits the corresponding second clock signal CK to the second sub-output module of the 2k+1-level first gate drive circuit GA1(2k+1), and the second clock line CKL2 transmits the corresponding second clock signal CK to the third sub-output module of the 2k+1-level first gate drive circuit GA1(2k+1); the third clock line CKL3 transmits the corresponding second clock signal CK to the first sub-output module of the 2k+2-level first gate drive circuit GA1(2k+2), the fourth clock line CKL4 transmits the corresponding second clock signal CK to the second sub-output module of the 2k+2-level first gate drive circuit GA1(2k+2), and the fifth clock line CKL5 transmits the corresponding second clock signal CK to the third sub-output module of the 2k+2-level first gate drive circuit GA1(2k+2).

[0179] It should be noted that the phase difference between the clock signal transmitted by the first clock line CKL1 and the clock signal transmitted by the second clock line CKL2 is φ1, the phase difference between the clock signal transmitted by the second clock line CKL2 and the clock signal transmitted by the third clock line CKL3 is φ2, the phase difference between the clock signal transmitted by the third clock line CKL3 and the clock signal transmitted by the fourth clock line CKL4 is φ3, the phase difference between the clock signal transmitted by the fourth clock line CKL4 and the clock signal transmitted by the fifth clock line CKL5 is φ4, the phase difference between the clock signal transmitted by the fifth clock line CKL5 and the clock signal transmitted by the sixth clock line CKL6 is φ5, and the phase difference between the clock signal transmitted by the sixth clock line CKL6 and the clock signal transmitted by the sixth clock line CKL6 is φ6. Here, φ1=φ2=φ3=φ4=φ5=φ6.

[0180] Optionally, when each first gate driving circuit GA1 includes multiple second output modules 50 (X≥2), the multiple first gate driving circuits GA1 included in the first gate driving unit GM1 share clock signals transmitted by multiple clock lines among F clock lines as corresponding first clock signals XCK.

[0181] Continuing with FIG5B , assuming that each first gate driver circuit GA1 includes two second output modules 50 (X=2), and the first gate driver unit GM1 includes multiple first gate driver circuits GA1 that share four clock lines for clock signal transmission, the third clock line CKL1 transmits the corresponding first clock signal XCK to the 2k+1th stage first gate driver circuit GA1(2k+1), and the first clock line transmits the corresponding first clock signal XCK to the 2k+2th stage first gate driver circuit GA1(2k+2).

[0182] For example, each first gate driver circuit GA1 has three second output modules 50, and the three second output modules 50 include a first sub-output module, a second sub-output module, and a third sub-output module. The fourth clock line CKL4 transmits the corresponding first clock signal XCK to the 2k+1th-stage first gate driver circuit GA1(2k+1), and the first clock line CKL1 transmits the corresponding first clock signal XCK to the 2k+2th-stage first gate driver circuit GA1(2k+2).

[0183] Optionally, when each first gate drive circuit GA1 includes multiple second output modules 50 (X≥2), multiple clock lines can be independently set to provide corresponding first clock signals XCK to the multi-stage first gate drive circuit GA1, so that among the F clock lines, no part of the clock lines simultaneously provide corresponding first clock signals XCK and second clock signals CK to the multi-stage first gate drive circuit GA1, so that the loads corresponding to the multiple clock lines are similar, thereby improving the quality of the third gate control signal Pscan1 output by the multi-stage first gate drive circuit GA1.

[0184] Similarly, based on the similar design principle that the phase difference of the first clock signal XCK corresponding to the two adjacent first gate drive circuits GA1 is XH, the phase difference of the third gate control signal output by the first sub-output module in the two adjacent first gate drive circuits GA1 is XH, and the phase difference of the third gate control signal output by the second sub-output module in the two adjacent first gate drive circuits GA1 is XH, it is obtained that when each first gate drive circuit GA1 includes more second output modules 50, the matching connection relationship between the multi-stage first gate drive circuit GA1 and the multiple clock lines is obtained.

[0185] Optionally, the plurality of first gate driving circuits GA1 included in the second gate driving unit GM2 may share clock signals transmitted by G clock lines as corresponding first clock signals XCK and second clock signals CK, where G is 2, 4, 6, 8, etc.

[0186] Optionally, the number of clock lines corresponding to the first gate driving unit GM1 may be the same as or different from the number of clock lines corresponding to the second gate driving unit GM2 .

[0187] It can be understood that the matching connection relationship between the multi-stage first gate driving circuit GA1 and the multiple clock lines can be referred to to obtain the matching connection relationship between the multi-stage second gate driving circuit GA2 and the multiple clock lines.

[0188] Optionally, the first gate driving unit GM1 and the second gate driving unit GM2 may share multiple clock lines, or may not share multiple clock lines.

[0189] Optionally, the first gate drive unit GM1 and the second gate drive unit GM2 share multiple clock lines to reduce the possibility of mismatching or inconsistent matching timing between the gate control signal generated by the first gate drive unit GM1 and the gate control signal generated by the second gate drive unit GM2 due to factors such as different clock lines used by the first gate drive unit GM1 and the second gate drive unit GM2, or inconsistent changes in the clock signals used by the first gate drive unit GM1 and the second gate drive unit GM2. Sharing multiple clock lines between the first gate drive unit GM1 and the second gate drive unit GM2 can improve the coordination between the first gate drive unit GM1 and the second gate drive unit GM2, and is also beneficial in reducing the number of clock lines used and reducing power consumption.

[0190] In addition, when the gate control signal received by the control end of the data transistor Tda is simultaneously supplied by the first gate driving unit GM1 and the second gate driving unit GM2, the first gate driving unit GM1 and the second gate driving unit GM2 share multiple clock lines, which can also help to keep the third gate control signal Pscan1 and the fourth gate control signal Pscan2 correspondingly received by the data transistor Tda in the sub-pixel Spi the same, thereby improving the operating stability of the data transistor Tda.

[0191] Please continue to refer to Figure 5A, taking the example where the first gate driving circuit GA1 and the second gate driving unit GA2 both include a second output module 50, and the first gate driving unit GM1 and the second gate driving unit GM2 share four clock lines, the connection relationship between the first gate driving unit GM1, the second gate driving unit GM2 and the multiple clock lines is explained. The first clock signal XCK corresponding to the 4m+1-level first gate driver circuit GA1(4m+1) and the 4m+1-level second gate driver circuit GA2(4m+1) corresponds to the signal transmitted by the second clock line CKL2, and the second clock signal CK corresponding to the 4m+1-level first gate driver circuit GA1(4m+1) and the 4m+1-level second gate driver circuit GA2(4m+1) corresponds to the signal transmitted by the first clock line CKL1; the first clock signal XCK corresponding to the 4m+2-level first gate driver circuit GA1(4m+2) and the 4m+2-level second gate driver circuit GA2(4m+2) corresponds to the signal transmitted by the third clock line CKL3, and the second clock signal CK corresponding to the 4m+2-level first gate driver circuit GA1(4m+2) and the 4m+2-level second gate driver circuit GA2(4m+2) corresponds to the signal transmitted by the second clock line CKL2; The first clock signal XCK corresponding to the 4m+3-th level first gate driver circuit GA1 (4m+3) and the 4m+3-th level second gate driver circuit GA2 (4m+3) corresponds to the signal transmitted by the fourth clock line CKL4, and the second clock signal CK corresponding to the 4m+3-th level first gate driver circuit GA1 (4m+3) and the 4m+3-th level second gate driver circuit GA2 (4m+3) corresponds to the signal transmitted by the third clock line CKL3; the first clock signal XCK corresponding to the 4m+4-th level first gate driver circuit GA1 (4m+4) and the 4m+4-th level second gate driver circuit GA2 (4m+4) corresponds to the signal transmitted by the first clock line CKL1, and the second clock signal CK corresponding to the 4m+4-th level first gate driver circuit GA1 (4m+4) and the 4m+4-th level second gate driver circuit GA2 (4m+4) corresponds to the signal transmitted by the fourth clock line CKL4. Where m≥0.

[0192] 5B , taking the example of the first gate driving circuit GA1 and the second gate driving unit GA2 both including two second output modules 50, and the first gate driving unit GM1 and the second gate driving unit GM2 sharing four clock lines, the first clock line CKL1 transmits the corresponding second clock signal CK to a second output module of the 2k+1-stage first gate driving circuit GA1 (2k+1) and a second output module of the 2k+1-stage second gate driving circuit GA2 (2k+1), the second clock line CKL2 transmits the corresponding second clock signal CK to another second output module of the 2k+1-stage first gate driving circuit GA1 (2k+1) and another second output module of the 2k+1-stage second gate driving circuit GA2 (2k+1); the third clock line CKL3 transmits the corresponding second clock signal CK to a second output module of the 2k+2-stage first gate driving circuit GA1 (2k+2) and a second output module of the 2k+2-stage second gate driving circuit GA2 (2k+2). The fourth clock line CKL4 transmits the corresponding second clock signal CK to another second output module of the 2k+2-level first gate driving circuit GA1 (2k+2) and another second output module of the 2k+2-level second gate driving circuit GA2 (2k+2).

[0193] Correspondingly, optionally, the third clock line CKL1 transmits the corresponding first clock signal XCK to the 2k+1-th level first gate drive circuit GA1 (2k+1) and the 2k+1-th level second gate drive circuit GA2 (2k+1), and the first clock line transmits the corresponding first clock signal XCK to the 2k+2-th level first gate drive circuit GA1 (2k+2) and the 2k+2-th level second gate drive circuit GA2 (2k+2).

[0194] Similarly, when the first gate driving unit GM1 and the second gate driving unit GM2 both include more second output modules, the connection relationship between the first gate driving unit GM1, the second gate driving unit GM2 and the multiple clock lines can also be obtained.

[0195] It should be noted that the circuit structures of the first gate drive circuit GA1 and the second gate drive circuit GA2 can be the same or different. For example, in some embodiments, both the first gate drive circuit GA1 and the second gate drive circuit GA2 can adopt the circuit structure shown in Figures 6A and 6B. In other embodiments, one of the first gate drive circuit GA1 and the second gate drive circuit GA2 adopts the circuit structure shown in Figures 6A and 6B, while the other of the first gate drive circuit GA1 and the second gate drive circuit GA2 adopts a circuit structure that can implement frequency division control in related art.

[0196] By controlling the level of the first frequency-dividing control signal NF1, the level of the first gate control signal Nscan1 output by the multi-stage first gate drive circuit GA1 can be controlled. Similarly, by controlling the level of the frequency-dividing control signal corresponding to the second frequency-dividing module of the first gate drive circuit GA1, the level of the third gate control signal Pscan1 output by the multi-stage first gate drive circuit GA1 can be controlled. Similarly, by controlling the level of the second frequency-dividing control signal NF2, the level of the second gate control signal Nscan2 output by the multi-stage second gate drive circuit GA2 can be controlled. Similarly, by controlling the level of the second frequency-dividing module of the second gate drive circuit GA2, the level of the fourth gate control signal Pscan2 output by the multi-stage second gate drive circuit GA2 can be controlled.

[0197] Figures 8A to 8D are timing diagrams of the first gate control signal and the second gate control signal provided in an embodiment of the present application. Figures 8A to 8B correspond to timing diagrams in which each gate drive circuit includes a second output module, and Figures 8C to 8D correspond to timing diagrams in which each gate drive circuit includes two second output modules. Nscan in Figures 8C to 8D can represent either the first or second gate control signal, and Pscan in Figures 8C to 8D can represent either the third or fourth gate control signal.

[0198] The second transistor T2, the third transistor T3, the fifth transistor T5, the eighth transistor T8, the tenth transistor T10, the eleventh transistor T11, the thirteenth transistor T13, the first frequency-dividing transistor Tf1 to the fourth frequency-dividing transistor Tf4, the second output transistor To2 to the fourth output transistor To4 are P-type transistors, the first transistor T1, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the ninth transistor T9, the twelfth transistor T12 and the first output transistor To1 are N-type transistors, the first-stage first gate drive circuit GA1 adopts the first starting signal stv1 as the starting signal, and the first-stage second gate drive circuit GA2 adopts the second starting signal stv2 as the starting signal; the p-th stage first gate drive circuit GA1(p) adopts the first gate outputted from the first output terminal O1 of the p-1-th stage first gate drive circuit GA1(p-1) Taking the p-th level second gate drive circuit GA2(p) as the starting signal STV, the p-th level second gate drive circuit GA2(p) adopts the second gate control signal Nscan2(p-1) outputted from the first output terminal O1 of the p-th level second gate drive circuit GA2(p-1) as the starting signal STV, the switching control signal SC corresponding to the p-th level first gate drive circuit GA1(p) is the p-2-th level first gate control signal Nscan1(p-2) outputted by the p-2-th level first gate drive circuit GA1(p-2), and the switching control signal SC corresponding to the p-th level second gate drive circuit GA2(p) is the p-2-th level second gate control signal Nscan2(p-2) outputted by the p-2-th level second gate drive circuit GA2(p-2) as an example, the working principles of the first gate drive unit GM1 and the second gate drive unit GM2 are explained. Where p>1; corresponding to Figures 8A and 8B , the first clock signal XCK corresponding to the p-th stage first gate driver circuit GA1(p) and the p-th stage second gate driver circuit GA2(p) is provided by the second clock line CKL2, and the corresponding second clock signal CK is provided by the first clock line CKL1. Corresponding to Figures 8C and 8D , the first clock signal XCK corresponding to the p-th stage first gate driver circuit GA1(p) and the p-th stage second gate driver circuit GA2(p) is provided by the first clock line CKL1, and the corresponding second clock signal CK is provided by the third clock line CKL3 and the fourth clock line CKL4, and each gate driver circuit corresponding to Figures 8C and 8D includes a second frequency division control module.

[0199] 5A , 6A , and 8A-8B , the following description will be made by taking the transition from a low level state to a high level state corresponding to the first frequency-division control signal NF1 and the second frequency-division control signal NF2 as an example.

[0200] In the first phase t1, the first clock signal CK1 transmitted by the first clock line CKL1 is at a high level, the second clock signal CK2 transmitted by the second clock line CKL2 is at a low level, the third clock signal CK3 transmitted by the third clock line CKL3 is at a high level, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 is at a high level. The p-1th stage first gate control signal Nscan1(p-1) to the p-2th stage first gate control signal Nscan1(p-2) and the p-1th stage second gate control signal Nscan2(p-1) to the p-2th stage second gate control signal Nscan2(p-2) are at a low level. The first frequency division control signal NF1, the second frequency division control signal NF2, the third frequency division control signal PF1, and the fourth frequency division control signal PF2 are at a low level.

[0201] The first clock signal XCK is correspondingly provided by the second clock line CKL2, and the second clock signal CK is correspondingly provided by the first clock line CKL1. In the first gate drive circuit GA1 and the second gate drive circuit GA2 (such as the p-th stage first gate drive circuit GA1(p) and the p-th stage second gate drive circuit GA2(p), etc.), the second transistor T2, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the eleventh transistor T11, the thirteenth transistor T13, the first frequency-dividing transistor Tf1 to the fourth frequency-dividing transistor Tf4, the first output transistor To1, and the fourth output transistor To4 are turned on, the first transistor T1, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12, the second output transistor To2, and the third output transistor To3 are turned off, the third power supply terminal NVGL is electrically connected to the first output terminal O1, and the second power supply terminal PVGH is electrically connected to the second output terminal O2.

[0202] In the first gate driver circuits GA1 and second gate driver circuits GA2 (such as the p+1th-stage first gate driver circuits GA1(p+1) through p+3th-stage first gate driver circuits GA1(p+3) and the p+1th-stage second gate driver circuits GA2(p+1) through p+3th-stage second gate driver circuits GA2(p+3)) whose first clock signal XCK is not provided by the second clock line CKL2 and whose second clock signal CK is not provided by the first clock line CKL1, the third transistor T3 is turned off. Therefore, the first gate control signal Nscan1 output by the first gate driver circuits GA1 and the second gate control signal Nscan2 output by the second gate driver circuits GA2, whose first clock signal XCK is not provided by the second clock line CKL2 and whose second clock signal CK is not provided by the first clock line CKL1, remain at a low level, while the third gate control signal Pscan1 and the fourth gate control signal Pscan2 remain at a high level.

[0203] In the second phase t2, the first clock signal CK1 is at a high level, the second clock signal CK2 is at a low level, the third clock signal CK3 is at a high level, and the fourth clock signal CK4 is at a high level. The p-1th stage first gate control signal Nscan1(p-1) to the p-2th stage first gate control signal Nscan1(p-2) are at a high level, the p-1th stage second gate control signal Nscan2(p-1) to the p-2th stage second gate control signal Nscan2(p-2) are at a low level, and the first to fourth frequency division control signals NF1 to PF2 are at a low level.

[0204] In the p-th stage first gate drive circuit GA1(p), the first transistor T1, the third transistor T3, the sixth transistor T6, the eighth transistor T8, and the second output transistor To2 are turned on, the second frequency-dividing transistor Tf2 and the fourth frequency-dividing transistor Tf4 remain turned on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the first frequency-dividing transistor Tf1, the third frequency-dividing transistor Tf3, the first output transistor To1, the third output transistor To3, and the fourth output transistor To4 are turned off. The fourth power supply terminal NVGH is electrically connected to the first output terminal O1. The p-th stage first gate control signal Nscan1(p) has a high level, and the p-th stage third gate control signal Pscan1(p) remains high.

[0205] The p-th stage second gate drive circuit GA2(p) performs similar operations in the second phase t2 as in the first phase t1. The p+1-th stage first gate control signal Nscan1(p+1) to the p+11-th stage first gate control signal Nscan1(p+11) and the p-th stage second gate control signal Nscan2(p) to the p+11-th stage second gate control signal Nscan2(p+11) maintain low levels, while the p+1-th stage third gate control signal Pscan1(p+1) to the p+11-th stage third gate control signal Pscan1(p+11) and the p-th stage fourth gate control signal Pscan2(p) to the p+11-th stage fourth gate control signal Pscan2(p+11) maintain high levels.

[0206] In the third phase t3, the first clock signal CK1 is at a high level, the second clock signal CK2 is at a high level, the third clock signal CK3 is at a low level, and the fourth clock signal CK4 is at a high level. The p-1th stage first gate control signal Nscan1(p-1) through the p-2th stage first gate control signal Nscan1(p-2) are at a high level, the p-1th stage second gate control signal Nscan2(p-1) through the p-2th stage second gate control signal Nscan2 are at a low level, and the first through fourth frequency division control signals NF1 through PF2 are at a low level.

[0207] The p-th stage first gate control signal Nscan1 ( p ) and the p-th stage third gate control signal Pscan1 ( p ) maintain a high level.

[0208] In the p-th stage second gate drive circuit GA2(p), the third transistor T3 is turned off. The p-th stage second gate control signal Nscan2(p) through the p+11-th stage second gate control signal Nscan2(p+11) remain low, and the p-th stage fourth gate control signal Pscan2(p) through the p+11-th stage fourth gate control signal Pscan2(p+11) remain high.

[0209] During the third phase t3, the p+1th-level first gate driver circuit GA1(p+1) and the p+1th-level second gate driver circuit GA2(p+1) perform actions similar to those performed by the p-level first gate driver circuit GA1(p) and the p-level second gate driver circuit GA2(p) during the second phase t2. During the third phase t3, the p+2th-level first gate driver circuit GA1(p+2) and the p+2th-level second gate driver circuit GA2(p+2) perform actions similar to those performed by the p+1th-level first gate driver circuit GA1(p+1) and the p+1th-level second gate driver circuit GA2(p+1) during the second phase t2. Similarly, the actions performed by the p+3th-level first gate driver circuit GA1(p+3) through the p+11th-level first gate driver circuit GA1(p+11) and the p+3th-level second gate driver circuit GA2(p+3) through the p+11th-level second gate driver circuit GA2(p+11) during the third phase t3 are obtained.

[0210] Phase 4 t4: The first clock signal CK1 is high, the second clock signal CK2 is low, the third clock signal CK3 is high, and the fourth clock signal CK4 is high. The p-1th stage first gate control signal Nscan1(p-1) to the p-2th stage first gate control signal Nscan1(p-2) are high, the p-1th stage second gate control signal Nscan2(p-1) to the p-2th stage second gate control signal Nscan2 are high, and the first frequency division control signal NF1, the second frequency division control signal NF2, the third frequency division control signal PF1, and the fourth frequency division control signal PF2 are low.

[0211] The p-th stage first gate control signal Nscan1(p) and the p-th stage third gate control signal Pscan1(p) maintain a high level. In addition, the p+1-th stage first gate control signal Nscan1(p+1) to the p+4-th stage first gate control signal Nscan1(p+4) and the p+1-th stage third gate control signal Pscan1(p+1) to the p+11-th stage third gate control signal Pscan1(p+11) maintain a high level, and the p+5-th stage first gate control signal Nscan1(p+5) to the p+11-th stage first gate control signal Nscan1(p+11) maintain a low level.

[0212] The p-th stage second gate driver circuit GA2(p) performs operations similar to those of the p-th stage first gate driver circuit GA1(p) during the second phase t2. The p-th stage second gate control signal Nscan2(p) and the p-th stage fourth gate control signal Pscan2(p) are both high. The p+1-th stage second gate control signal Nscan2(p+1) through the p+11-th stage second gate control signal Nscan2(p+11) remain low, and the p-th stage fourth gate control signal Pscan2(p) through the p+11-th stage fourth gate control signal Pscan2(p+11) remain high.

[0213] Phase 5 t5: The first clock signal CK1 is at a low level, the second clock signal CK2 is at a high level, the third clock signal CK3 is at a high level, and the fourth clock signal CK4 is at a high level. The p-1th stage first gate control signal Nscan1(p-1) to the p-2th stage first gate control signal Nscan1(p-2) and the p-1th stage second gate control signal Nscan2(p-1) to the p-2th stage second gate control signal Nscan2 are at a low level. The first frequency division control signal NF1 to the fourth frequency division control signal PF2 are at a low level.

[0214] In the p-th stage first gate drive circuit GA1(p) and the p-th stage second gate drive circuit GA2(p), the second transistor T2, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11, the twelfth transistor T12, the second frequency-dividing transistor Tf2, the fourth frequency-dividing transistor Tf4, the second output transistor To2, and the third output transistor To3 are turned on, and the first transistor T1, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the thirteenth transistor T13, the first frequency-dividing transistor Tf1, the third frequency-dividing transistor Tf3, the first output transistor To1, and the fourth output transistor To4 are turned off. The p-th stage first gate control signal Nscan1(p) and the p-th stage second gate control signal Nscan2(p) have a high level, and the p-th stage third gate control signal Pscan1(p) and the p-th stage fourth gate control signal Pscan2(p) have a low level.

[0215] The p+1th level first gate control signal Nscan1(p+1) to the p+7th level first gate control signal Nscan1(p+7) and the p+2th level third gate control signal Pscan1(p+2) to the p+11th level third gate control signal Pscan1(p+11) have a high level, and the p+8th level first gate control signal Nscan1(p+8) to the p+11th level first gate control signal Nscan1(p+11) have a low level. The p+1th level second gate control signal Nscan2(p+1) to the p+3th level second gate control signal Nscan2(p+3) and the p+2th level fourth gate control signal Pscan2(p+2) to the p+11th level fourth gate control signal Pscan2(p+11) have a high level, and the p+4th level third gate control signal Nscan2(p+4) to the p+11th level third gate control signal Nscan2(p+11) have a low level.

[0216] Phase 6 t6: The first clock signal CK1 is at a high level, the second clock signal CK2 is at a low level, the third clock signal CK3 is at a high level, and the fourth clock signal CK4 is at a high level. The p-1th stage first gate control signal Nscan1(p-1) to the p-2th stage first gate control signal Nscan1(p-2) and the p-1th stage second gate control signal Nscan2(p-1) to the p-2th stage second gate control signal Nscan2 are at a low level. The first frequency division control signal NF1 to the fourth frequency division control signal PF2 are at a low level.

[0217] In the p-th stage first gate drive circuit GA1(p) and the p-th stage second gate drive circuit GA2(p), the second transistor T2, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the eleventh transistor T11, the thirteenth transistor T13, the first frequency-dividing transistors Tf1 to Tf4, the first output transistor To1, and the fourth output transistor To4 are turned on, and the first transistor T1, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12, the second output transistor To2, and the third output transistor To3 are turned off. The p-th stage first gate control signal Nscan1(p) and the p-th stage second gate control signal Nscan2(p) have a low level, and the p-th stage third gate control signal Pscan1(p) and the p-th stage fourth gate control signal Pscan2(p) have a high level.

[0218] The p+1th-level first gate driver circuit GA1(p+1) and the p+1th-level second gate driver circuit GA2(p+1) perform actions similar to those performed by the p-level first gate driver circuit GA1(p) and the p-level second gate driver circuit GA2(p) at the fifth stage t5 in the sixth stage t6. The p+2th-level first gate driver circuit GA1(p+2) and the p+2th-level second gate driver circuit GA2(p+2) perform actions similar to those performed by the p+1th-level first gate driver circuit GA1(p+1) and the p+2th-level second gate driver circuit GA2(p+2) at the sixth stage t6. By analogy, the actions performed by the p+3-th level first gate driving circuit GA1(p+3) to the p+11-th level first gate driving circuit GA1(p+11) and the p+3-th level second gate driving circuit GA2(p+3) to the p+11-th level second gate driving circuit GA2(p+11) in the sixth stage t6 are obtained.

[0219] Seventh stage t7: the first clock signal CK1 is high, the second clock signal CK2 is high, the third clock signal CK3 is low, the fourth clock signal CK4 is high, and the first to fourth frequency division control signals NF1 to PF2 are low.

[0220] The p-th to p+1-th first gate control signals Nscan1(p) and Nscan1(p+1) and the p+10-th to Nscan1(p+10) to Nscan1(p+11) are low, and the p+2-th to Nscan1(p+2) to Nscan1(p+9) are high. The p+2-th third gate control signal Pscan1(p+2) is low, and the p-th to Pscan1(p+1) and the p+3-th to Pscan1(p+3) are high.

[0221] The p-th level second gate control signal Nscan2(p) to the p+1-th level second gate control signal Nscan2(p+1) and the p+6-th level second gate control signal Nscan2(p+6) to the p+11-th level second gate control signal Nscan2(p+11) are low, and the p+2-th level second gate control signal Nscan2(p+2) to the p+5-th level second gate control signal Nscan2(p+5) are high. The p+2-th level fourth gate control signal Pscan2(p+2) is low, and the p-th level fourth gate control signal Pscan2(p) to the p+1-th level fourth gate control signal Pscan2(p+1) and the p+3-th level fourth gate control signal Pscan2(p+3) to the p+11-th level fourth gate control signal Pscan2(p+11) are high.

[0222] Phase 8: The first clock signal CK1 is high, the second clock signal CK2 is high, the third clock signal CK3 is high, and the fourth clock signal CK4 is low. The first frequency division control signal NF1 is high, and the second to fourth frequency division control signals NF2 to PF2 are low.

[0223] The p-th level first gate driver circuit GA1(p) maintains the same state as the seventh level t7 during the eighth stage t8. The p+1-th level first gate driver circuit GA1(p+1) performs an action similar to the action performed by the p-th level first gate driver circuit GA1(p) during the seventh level t7 during the eighth stage t8. The p+2-th level first gate driver circuit GA1(p+2) performs an action similar to the action performed by the p+1-th level first gate driver circuit GA1(p+1) during the eighth stage t8. This is analogous to the actions performed by the p+4-th level first gate driver circuit GA1(p+4) to the p+9-th level first gate driver circuit GA1(p+9) during the eighth stage t8. The p+10th-level first gate drive circuit GA1(p+10) performs actions similar to those performed by the p-level first gate drive circuit GA1(p) in the second stage t2 in the eighth stage t8, and the p+10th-level first gate control signal Nscan1(p+10) and the p+10th-level third gate control signal Pscan1(p+10) have high levels.

[0224] In the p+11th stage first gate drive circuit GA1(p+11), the first transistor T1, the fourth transistor T4, the ninth transistor T9, the twelfth transistor T12, the first frequency-dividing transistor Tf1, the third frequency-dividing transistor Tf3, and the fourth frequency-dividing transistor Tf4 are turned on, and the second transistor T2, the third transistor T3, the eleventh transistor T11, and the second frequency-dividing transistor Tf2 are turned off. Therefore, the p+11th stage first gate control signal Nscan1(p+11) has a low level, and the p+11th stage third gate control signal Pscan1(p+11) has a high level.

[0225] In the first gate driving circuit GA1 following the p+11th stage first gate driving circuit GA1 (p+11), the first frequency dividing transistor Tf1, the third frequency dividing transistor Tf3 and the fourth frequency dividing transistor Tf4 are turned on, and the second frequency dividing transistor Tf2 is turned off.

[0226] The p-th to p+2-th second gate control signals Nscan2(p+2) and the p+7-th to p+11-th second gate control signals Nscan2(p+7) are low, and the p+3-th to p+6-th second gate control signals Nscan2(p+6) are high. The p+3-th fourth gate control signal Pscan2(p+3) is low, and the p-th to p+2-th fourth gate control signals Pscan2(p+2) and the p+4-th to p+11-th fourth gate control signals Pscan2(p+4) are high.

[0227] Phase 9: The first clock signal CK1 is at a low level, the second clock signal CK2 is at a high level, the third clock signal CK3 is at a high level, and the fourth clock signal CK4 is at a high level. The first frequency division control signal NF1 is at a high level, and the second to fourth frequency division control signals NF2 to PF2 are at a low level.

[0228] The p-th to p+3-th first gate control signals Nscan1(p+3) are low, and the p+4-th to p+10-th first gate control signals Nscan1(p+4) are high. The p+4-th third gate control signal Pscan1(p+4) is low, and the p-th to p+3-th third gate control signals Pscan1(p+3) and the p+5-th to p+11-th third gate control signals Pscan1(p+5) are high.

[0229] In the p+11th level first gate drive circuit GA1(p+11), the first transistor T1, the third transistor T3, the sixth transistor T6, the eighth transistor T8, and the fourth frequency-dividing transistor Tf4 are turned on, and the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the first frequency-dividing transistor Tf1 to the third frequency-dividing transistor Tf3, and the first output transistor To1 to the fourth output transistor To4 are turned off, so that the p+11th level first gate control signal Nscan1(p+11) maintains a low level, and the p+11th level third gate control signal Pscan1(p+11) maintains a high level.

[0230] The p-th to p+3-th second gate control signals Nscan2(p+3) and the p+8-th to p+11-th second gate control signals Nscan2(p+8) are low, and the p+4-th to p+7-th second gate control signals Nscan2(p+7) are high. The p+4-th fourth gate control signal Pscan2(p+4) is low, and the p-th to p+3-th fourth gate control signals Pscan2(p+3) and the p+5-th to p+11-th fourth gate control signals Pscan2(p+5) are high.

[0231] Phase 10 t10: The first clock signal CK1 is high, the second clock signal CK2 is high, the third clock signal CK3 is high, and the fourth clock signal CK4 is low. The first and second frequency division control signals NF1 and NF2 are high, and the third and fourth frequency division control signals PF1 and PF2 are low.

[0232] The p-th to p+6-th first gate control signals Nscan1(p+6), the p+11-th to p+11-th first gate control signals Nscan1(p+11), and subsequent first gate control signals Nscan1 are low, and the p+7-th to p+10-th first gate control signals Nscan1(p+10) are high. The p+7-th third gate control signal Pscan1(p+7) is low, and the p-th to p+6-th third gate control signals Pscan1(p+6), and the p+8-th to p+1-th third gate control signals Pscan1(p+8) are high.

[0233] The p-th to p+6-th second gate control signals Nscan2(p+6), the p+11-th second gate control signal Nscan2(p+11), and subsequent second gate control signals Nscan2 are low, and the p+7-th to p+10-th second gate control signals Nscan2(p+10) are high. The p+7-th fourth gate control signal Pscan2(p+7) is low, and the p-th to p+6-th fourth gate control signals Pscan2(p+6), and the p+8-th to p+11-th fourth gate control signals Pscan2(p+8) are high.

[0234] Phase 11: The first clock signal CK1 is at a low level, the second clock signal CK2 is at a high level, the third clock signal CK3 is at a high level, and the fourth clock signal CK4 is at a high level. The first frequency division control signal NF1 and the second frequency division control signal NF2 are at a high level, and the third frequency division control signal PF1 and the fourth frequency division control signal PF2 are at a low level.

[0235] The p-th to p+7-th first gate control signals Nscan1(p+7), the p+11-th to p+11-th first gate control signals Nscan1(p+11), and subsequent first gate control signals Nscan1 are low, and the p+8-th to p+10-th first gate control signals Nscan1(p+10) are high. The p+8-th third gate control signal Pscan1(p+8) is low, and the p-th to p+7-th third gate control signals Pscan1(p+7), and the p+9-th to p+11-th third gate control signals Pscan1(p+9) are high.

[0236] The p-th level second gate control signal Nscan2(p) to the p+7-th level second gate control signal Nscan2(p+7), the p+11-th level second gate control signal Nscan2(p+11), and the subsequent second gate control signals Nscan2 are low, the p+8-th level second gate control signal Nscan2(p+8) to the p+10-th level second gate control signal Nscan2(p+10) are high. The p+8-th level fourth gate control signal Pscan2(p+8) is low, the p-th level fourth gate control signal Pscan2(p) to the p+7-th level fourth gate control signal Pscan2(p+7), and the p+9-th level fourth gate control signal Pscan2(p+9) to the p+11-th level fourth gate control signal Pscan2(p+11) are high. That is, the p+11th stage second gate driving circuit GA2 (p+11) performs an action in the eleventh stage t11 similar to the action performed by the p+11th stage first gate driving circuit GA1 (p+11) in the ninth stage t9.

[0237] Afterwards, the p+10th level first gate drive circuit GA1(p+10) and the p+10th level second gate drive circuit GA2(p+10) restore the p+10th level first gate control signal Nscan1(p+10) and the p+10th level second gate control signal Nscan2(p+10) to a low level state according to the corresponding first clock signal and the second clock signal, and the p+10th level third gate control signal Pscan1(p+10) and the p+10th level fourth gate control signal Pscan2(p+10) output a low level and then restore to a high level.

[0238] Thus, by controlling the first frequency-dividing control signal NF1, the level of the first gate control signal Nscan1 output by the plurality of first gate drive circuits GA1 can be controlled, and by controlling the second frequency-dividing control signal NF2, the level of the second gate control signal Nscan2 output by the plurality of second gate drive circuits GA2 can be controlled. By controlling the timing at which the first frequency-dividing control signal NF1 and the second frequency-dividing signal transition from an active level to an inactive level, the first gate control signal Nscan1 and the second gate control signal Nscan2 can be output at the same level, that is, at a non-active level.

[0239] Similarly, by controlling the third frequency-dividing control signal PF1, the level of the third gate control signal Pscan1 output by the plurality of first gate drive circuits GA1 can be controlled, and by controlling the fourth frequency-dividing control signal PF2, the level of the fourth gate control signal Pscan2 output by the plurality of second gate drive circuits GA2 can be controlled. By controlling the moments when the third frequency-dividing control signal PF1 and the fourth frequency-dividing signal transition from an active level to an inactive level, the third gate control signal Pscan1 and the fourth gate control signal Pscan2 can be made to correspond to the same level, i.e., outputs that do not have an active level. Therefore, a timing diagram of the first gate drive unit GM1 and the second gate drive unit GM2 corresponding to the transition from an active level to an inactive level of the third frequency-dividing control signal PF1 or the fourth frequency-dividing control signal PF2 is shown in FIG8B . The operating principle of the first gate drive unit GM1 and the second gate drive unit GM2 corresponding to the transition from an active level to an inactive level of the third frequency-dividing control signal PF1 or the fourth frequency-dividing control signal PF2 can be similarly derived from the operating principle of the first frequency-dividing control signal NF1 and the second frequency-dividing signal transitioning from an active level to an inactive level.

[0240] As shown in FIG8B , in the twelfth stage t12 before the moment when the first frequency dividing control signal PF1 jumps from the active level to the inactive level, the p+9th stage first gate control signal Nscan1(p+9) output by the p+9th stage first gate driving circuit GA1(p+9) has a high level, and the p+10th stage first gate control signal Nscan1(p+10) output by the p+10th stage first gate driving circuit GA1(p+10) has a low level. In the thirteenth stage t13 after the moment when the third frequency dividing control signal PF1 or the fourth frequency dividing control signal PF2 jumps from the active level to the inactive level, in the p+11th stage first gate driving circuit GA1(p+11), the first transistor T1, the fourth transistor T4, the ninth transistor T9, the twelfth transistor T12, and the first to third frequency dividing transistors Tf1 to Tf3 are turned on, and the second transistor T2, the third transistor T3, the eleventh transistor T11, and the fourth frequency dividing transistor Tf4 are turned off. The fourth frequency-dividing transistor Tf4 of the p+11th-level first gate driving circuit GA1(p+11) is cut off, causing the p+11th-level third gate control signal Pscan1(p+11) to maintain a high level during the period when the second clock signal corresponding to the p+11th-level first gate driving circuit GA1(p+11) is at a low level.

[0241] Similarly, the working principle of the second gate driving unit GM2 can also be obtained when the fourth frequency-dividing control signal PF2 jumps from the active level to the inactive level.

[0242] Similarly, the working principles of the first gate driving unit GM1 and the second gate driving unit GM2 when they jump from the invalid level to the valid level according to the corresponding frequency-divided control signal can also be obtained, which will not be elaborated here.

[0243] 8A and 8B illustrate the operating principles of the first gate drive unit GM1 or the second gate drive unit GM2 when the first gate drive circuit GA1 or the second gate drive circuit GA2 includes two second output modules 50 and a second frequency division control module 60. This will not be further elaborated here. Accordingly, the timing diagrams of the multiple gate control signals output by the first gate drive unit or the second gate drive unit are shown in FIG8C and FIG8D.

[0244] Continuing to refer to Figures 1A and 1B, in some embodiments, the gate drive module GM further includes a third gate drive unit GM3 and a fourth gate drive unit GM4. The third gate drive unit GM3 includes a plurality of cascaded third gate drive circuits GA3, which are configured to generate a plurality of fifth gate control signals Pscan for output to the control ends of the first initial transistors Ti1 and the second initial transistors Ti2 of the plurality of sub-pixels Spi. The fourth gate drive unit GM4 includes a plurality of cascaded fourth gate drive circuits GA4, which are configured to generate a plurality of emission control signals EM for output to the control ends of the first emission control transistors Te1 and the second emission control transistors Te2 of the plurality of sub-pixels Spi. Optionally, the plurality of third gate drive circuits GA3 are electrically connected to the plurality of fourth scan lines GL4, and the plurality of fourth gate drive circuits GA4 are electrically connected to the plurality of emission control lines EL.

[0245] Optionally, each third gate driving circuit GA3 can drive the first initial transistor Ti1 and the second initial transistor Ti2 of at least one row of sub-pixels Spi, and each fourth gate driving circuit GA4 can drive the first light-emitting control transistor Te1 and the second light-emitting control transistor Te2 of at least one row of sub-pixels Spi.

[0246] Optionally, the third gate drive circuit GA3 and the fourth gate drive circuit GA4 may adopt the same or different circuit structures, and the circuit structures adopted by the third gate drive circuit GA3 and the fourth gate drive circuit GA4 may refer to the designs in related technologies.

[0247] Figure 9 is a timing diagram of the sub-pixel corresponding to the write frame and the hold frame provided by an embodiment of the present application. The operating principle of the pixel drive circuit is described below, taking as an example an example where the compensation transistor Tc and the reset transistor Tr are N-type transistors, and the drive transistor Tdr, the data transistor Tda, the first emission control transistor Te1, the second emission control transistor Te2, the first initial transistor Ti1, and the second initial transistor Ti2 are P-type transistors.

[0248] In the first reset phase Si1, the emission control signal EM transmitted by the emission control line EL and the gate control signal received by the data transistor Tda (i.e., at least one of the third gate control signal Pscan1 and the fourth gate control signal Pscan2) are high. The gate control signal received by the reset transistor Tr (i.e., the first gate control signal Nscan1) and the gate control signal received by the compensation transistor Tc (i.e., the second gate control signal Nscan2) are low. The fifth gate control signal Pscan transmitted by the fourth scan line GL4 is low. The first initial signal transmitted by the first initial line VL1 is transmitted to the anode of the light-emitting device Di to reset the anode potential of the light-emitting device Di. The second initial signal transmitted by the second initial line VL2 is transmitted to the input and output terminals of the driving transistor Tdr to reset the potentials of the input and output terminals of the driving transistor Tdr.

[0249] In the second reset phase Si2, the first gate control signal Nscan1, the emission control signal EM, the third gate control signal Pscan1, the fourth gate control signal Pscan2, and the fifth gate control signal received by the data transistor Tda are at a high level Pscan, and the second gate control signal Nscan2 is at a low level. The reset transistor Tr is turned on, and the reset signal Vr is transmitted to the gate of the drive transistor Tdr to reset the potential of the control terminal of the drive transistor Tdr.

[0250] During the data writing phase Sw, the second gate control signal Nscan2, the emission control signal EM, and the fifth gate control signal Pscan are high, while the first gate control signal Nscan1, the third gate control signal Pscan1 received by the data transistor Tda, and the fourth gate control signal Pscan2 are low. The data transistor Tda and the compensation transistor Tc are turned on, and the data signal is transmitted to the control terminal of the drive transistor Tdr.

[0251] Among them, between the second reset stage Si2 and the data writing stage Sw, it can also include a stage of controlling the reset transistor Tr and the compensation transistor Tc to be turned on at the same time, so that the reset signal Vr can be transmitted to the output end and input end of the driving transistor Tdr, thereby realizing the potential reset of the output end and input end of the driving transistor Tdr.

[0252] In the third reset stage Si3, the light-emitting control signal EM, the third gate control signal Pscan1 and the fourth gate control signal Pscan2 received by the data transistor Tda are high, the first gate control signal Nscan1, the second gate control signal Nscan2, and the fifth gate control signal Pscan are low, the first initial signal is transmitted to the anode of the light-emitting device Di, and the second initial signal is transmitted to the input and output ends of the driving transistor Tdr.

[0253] In the light-emitting stage Sd, the third gate control signal Pscan1, the fourth gate control signal Pscan2, and the fifth gate control signal Pscan received by the data transistor Tda are at a high level, the light-emitting control signal EM, the first gate control signal Nscan1, and the second gate control signal Nscan2 are at a low level, the first light-emitting control transistor Te1 and the second light-emitting control transistor Te2 are turned on, and the driving transistor Tdr generates a driving current to drive the corresponding light-emitting device Di to emit light.

[0254] In the fourth reset stage Si4 and the fifth reset stage Si5, the light-emitting control signal EM, the third gate control signal Pscan1 and the fourth gate control signal Pscan2 received by the data transistor Tda are high levels, the first gate control signal Nscan1, the second gate control signal Nscan2, and the fifth gate control signal are Pscan low levels, the first initial signal is transmitted to the anode of the light-emitting device Di, and the second initial signal is transmitted to the input and output ends of the driving transistor Tdr.

[0255] The write frame WF includes a first reset phase Si1, a second reset phase Si2, a data write phase Sw, a third reset phase Si3, and a light emitting phase Sd. The hold frame HF includes a fourth reset phase Si4, a fifth reset phase Si5, and a light emitting phase Sd.

[0256] Combined with the analysis of Figures 1A, 6A, 8A to 8B and 9, the control end of the compensation transistor Tc of the sub-pixel Spii located in the Lth row is electrically connected to the first output end O1 of the K+1th level first gate driving circuit GA1 (K+1), the control end of the reset transistor Tr of the sub-pixel Spii located in the Lth row is electrically connected to the first output end O1 of the K-3th level second gate driving circuit GA2 (K-3), the control end of the data transistor Tda of the sub-pixel Spii located in the Lth row is electrically connected to the second output end O2 of the K-level first gate driving circuit GA1 (K) and the second output end O2 of the K-level second gate driving circuit GA2 (K), and the K-level gate driving circuit uses the gate control signal output by the first output end O1 of the K-1th level gate driving circuit as the control signal. Taking the example of the K-level gate driving circuit, the principle of using the first gate driving unit GM1 and the second gate driving unit GM2 to enable the display panel DP to achieve frequency division display is explained.

[0257] In the first frame F1 of a display cycle, to ensure that new data signals are written to the control terminals of the drive transistors Tdr of the multiple sub-pixels Spi, the first to fourth frequency-division control signals NF1 to PF2 are controlled to maintain an active level, and the multiple rows of sub-pixels Spi in the display panel DP all undergo the write frame WF phase shown in FIG9 . A display cycle may include one frame or multiple frames. When a display cycle includes one frame, that frame corresponds to the write frame WF for the multiple rows of sub-pixels Spi. When a display cycle includes multiple frames, the first frame F1 corresponds to the write frame WF for the multiple rows of sub-pixels Spi.

[0258] In the second frame F2 of a display cycle, if the 1st to Lth row sub-pixels Spii of the display panel DP display at a high frequency, and the L+1th row sub-pixels Spii and subsequent rows of sub-pixels Spii display at a low frequency, then the first gate control signal Nscan1, the second gate control signal Nscan2, the third gate control signal Pscan1, and the fourth gate control signal Pscan2 applied to the 1st to Lth row sub-pixels Spii must all have valid pulses, causing the 1st to Lth row sub-pixels Spii to all undergo the write frame WF phase shown in FIG9 . However, the first gate control signal Nscan1, the second gate control signal Nscan2, the third gate control signal Pscan1, and the fourth gate control signal Pscan2 applied to the Lth row sub-pixels Spii and subsequent rows of sub-pixels Spi do not need to have valid pulses, causing the Lth row sub-pixels Spii and subsequent rows of sub-pixels Spi to all undergo the hold frame HF phase shown in FIG9 . The second frame F2 is located after the first frame F1.

[0259] Taking the L-1th row of sub-pixels Spi and the nth row of sub-pixels Spi as an example, the first gate control signal Nscan1 applied to the L-1th row of sub-pixels Spi is the K-th level first gate control signal Nscan1(K), the second gate control signal Nscan2 applied to the L-1th row of sub-pixels Spi is the K-4th level second gate control signal Nscan2(K-4), and the third gate control signal Pscan1 and the fourth gate control signal Pscan2 applied to the L-1th row of sub-pixels Spi are the K-1th level third gate control signal Pscan1(K-1) and the K-1th level fourth gate control signal Pscan2(K-1). The timing of the K-th level first gate control signal Nscan1 (K) in the second frame F2 corresponds to the form of the first gate control signal Nscan1 in Figure 9 in the write frame WF, the timing of the K-4 level second gate control signal Nscan2 (K-4) in the second frame F2 corresponds to the form of the second gate control signal Nscan2 in Figure 9 in the write frame WF, and the timing of the K-1 level third gate control signal Pscan1 (K-1) and the K-1 level fourth gate control signal Pscan2 (K-2) in the second frame F2 corresponds to the form of the third gate control signal Pscan1 and the fourth gate control signal Pscan2 in Figure 9 in the write frame WF.

[0260] The first gate control signal Nscan1 applied to the L-th row sub-pixel Spi is the K+1-th level first gate control signal Nscan1(K+1), the second gate control signal Nscan2 applied to the L-th row sub-pixel Spi is the K-3-th level second gate control signal Nscan2(K-3), the third gate control signal Pscan1 and the fourth gate control signal Pscan2 applied to the L-th row sub-pixel Spi are the K-th level third gate control signal Pscan1(K) and the K-th level fourth gate control signal Pscan2(K). The timing of the K+1th-level first gate control signal Nscan1(K+1) in the second frame F2 corresponds to the form of the first gate control signal Nscan1 in the hold frame HF shown in FIG9 . The timing of the K-3th-level second gate control signal Nscan2(K-3) in the second frame F2 corresponds to the form of the second gate control signal Nscan2 in the hold frame HF shown in FIG9 . The timing of the K-level third gate control signal Pscan1(K) and the K-level fourth gate control signal Pscan2(K) in the second frame F2 corresponds to the forms of the third gate control signal Pscan1 and the fourth gate control signal Pscan2 in the hold frame HF shown in FIG9 . Therefore, for the L-1th row of sub-pixels Spi, the second frame F2 is still the write frame WF; while for the Lth row of sub-pixels Spi, the second frame F2 is the hold frame HF. In the second frame F2, the control end of the driving transistor Tdr of the L-1th row sub-pixel Spii has a data signal written therein, while the control end of the driving transistor Tdr of the Lth row sub-pixel Spii does not have a data signal written therein. The refresh frequencies corresponding to the L-1th row sub-pixel Spi and the Lth row sub-pixel Spi in the second frame F2 are different, which enables the display panel DP to achieve a frequency division display function.

[0261] Optionally, in some embodiments, when a sub-pixel Spi corresponds to low-frequency display, the compensation transistor Tc, reset transistor Tr and data transistor Tda are all reduced to low frequency, that is, the compensation transistor Tc, reset transistor Tr and data transistor Tda are controlled to remain in the cut-off state in the holding frame HF. Accordingly, because the L-1th row of sub-pixels Spi apply the K-th level first gate control signal Nscan1(K), and the K-th row of sub-pixels Spi apply the K-th level third gate control signal Pscan1(K) and the K-th level fourth gate control signal Pscan2(K), the first gate control signal Nscan1(K) output by the K-th level first gate driver circuit GA1(K) must meet the high-frequency display requirement of the L-1th row of sub-pixels Spi, the third gate control signal Pscan1(K) output by the K-th level first gate driver circuit GA1(K) must meet the low-frequency display requirement of the L-th row of sub-pixels Spi, and the fourth gate control signal Pscan2(K) output by the K-th level second gate driver circuit GA2(K) must meet the low-frequency display requirement of the L-th row of sub-pixels Spi. Therefore, the K-th level first gate driver circuit GA1(K) must output a first gate control signal Nscan1(K) that meets both the high-frequency requirement and the third gate control signal Pscan1(K) that meets the low-frequency requirement. Therefore, within at least one frame after the first frame HF1 of a display cycle, the frequency of the first gate control signal Nscan1 output by at least one first gate driver circuit GA1 is greater than the frequency of the third gate control signal Pscan1. Similarly, the K-3th-level second gate driver circuit GA2(K-3) through the K-1th-level second gate driver circuit GA2(K-1) are required to output the K-3th-level fourth gate control signal Pscan2(K-3) through the K-1th-level fourth gate control signal Pscan2(K-1) that simultaneously meet high-frequency requirements, and also need to output the K-3th-level second gate control signal Nscan2(K-3) through the K-1th-level second gate control signal Nscan2(K-1) that meet low-frequency requirements. Therefore, within at least one frame after the first frame HF1 of a display cycle, the frequency of the second gate control signal Nscan2 output by at least one second gate driver circuit GA2 is less than the frequency of the fourth gate control signal Pscan2. In other words, the same gate driver circuit needs to output gate control signals with different frequencies. The matching design of the first gate driving unit GM1, the second gate driving unit GM2, the frequency division control signal, and the sub-pixel Spi provided in the present application can meet the above requirements.

[0262] Similarly, when the 1st row of sub-pixels Spi to the Lth row of sub-pixels Spi of the display panel DP are displayed at a low frequency and the L+1th row of sub-pixels Spi and the subsequent multiple rows of sub-pixels Spi are displayed at a high frequency, the Kth-level first gate drive circuit GA1(K) needs to output a first gate control signal Nscan1(K) that meets the low-frequency requirement at the same time, and also needs to output a third gate control signal Pscan1(K) that meets the high-frequency requirement. Therefore, in at least one frame after the first frame HF1 of a display cycle, the frequency of the first gate control signal Nscan1 output by at least one of the first gate drive circuits GA1(K) is less than the frequency of the third gate control signal Pscan1. Similarly, the K-3th-level second gate drive circuit GA2(K-3) to the K-1th-level second gate drive circuit GA2(K-1) need to output the K-3th-level fourth gate control signal Pscan2(K-3) to the K-1th-level fourth gate control signal Pscan2(K-1) that simultaneously meet the low-frequency requirement, and also need to output the K-3th-level second gate control signal Nscan2(K-3) to the K-1th-level second gate control signal Nscan2(n-1) that meet the high-frequency requirement. Therefore, in at least one frame after the first frame HF1 of a display cycle, the frequency of the second gate control signal Nscan2 output by at least one second gate drive circuit GA2 is greater than the frequency of the fourth gate control signal Pscan2. In other words, the same gate drive circuit still needs to output gate control signals with different frequencies.

[0263] Similarly, in a design where a gate driving circuit includes a plurality of second output modules, there is still a need to output gate control signals with different frequencies corresponding to the same gate driving circuit. As analyzed in combination with Figures 1B, 6B, 8C to 8D and 9, the control end of the compensation transistor Tc of the sub-pixel Spii located in the Lth to L+X-1th rows is electrically connected to the first output end O1 of the K-th level first gate driving circuit GA1 (K), the control end of the reset transistor Tr of the sub-pixel Spii located in the Lth to L+X-1th rows is electrically connected to the first output end O1 of the K-2th level second gate driving circuit GA2 (K-2), the control end of the data transistor Tda of the sub-pixel Spii located in the Lth row is electrically connected to a second output end O2 of the K-th level first gate driving circuit GA1 (K) and a second output end O2 of the K-th level second gate driving circuit GA2 (K), and the control end of the data transistor Tda of the sub-pixel Spii located in the L+X-1th row is electrically connected to another second output end O2 of the K-th level first gate driving circuit GA1 (K) and another second output end O2 of the K-th level second gate driving circuit GA2 (K).

[0264] In the second frame F2 of a display cycle, if the 1st row of sub-pixels Spi to the 10th row of sub-pixels Spi of the display panel DP are displayed at a high frequency, and the 11th row of sub-pixels Spi and the subsequent rows of sub-pixels Spi are displayed at a low frequency. Then, the 6th level first gate driving circuit GA1 (6) needs to output the first gate control signal Nscan1 (6) that meets the high frequency requirement, and also needs to output the 11th level third gate control signal Pscan1 (11) to the 12th level third gate control signal Pscan1 (12) that meet the high frequency requirement. The 5th level second gate driving circuit GA2 (5) needs to output the 9th level fourth gate control signal Pscan2 (9) to the 10th level fourth gate control signal Pscan2 (10) that meet the high frequency requirement, and also needs to output the 5th level second gate control signal Nscan2 (5) that meets the low frequency requirement. That is, when the same gate driving circuit includes multiple second output modules, the gate driving circuit is still required to output gate control signals with different frequencies. The matching design of the first gate driving unit GM1, the second gate driving unit GM2, the frequency division control signal, and the sub-pixel Spi provided in the present application can meet the above requirements.

[0265] This document uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for technical personnel in this field, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A display device, wherein: include: A display panel comprising a plurality of sub-pixels, at least one of the sub-pixels comprising a light-emitting device, a driving transistor, a compensation transistor, and a reset transistor, wherein the driving transistor is configured to generate a driving current to drive the light-emitting device to emit light, an output terminal of the reset transistor and an output terminal of the compensation transistor are electrically connected to a control terminal of the driving transistor, an input terminal of the compensation transistor is electrically connected to the output terminal of the driving transistor, and the input terminal of the reset transistor is configured to receive a reset signal; as well as a gate driving module electrically connected to the display panel, comprising a plurality of frequency-division control lines for transmitting frequency-division control signals, a first gate driving unit, and a second gate driving unit; the plurality of frequency-division control signals including a first frequency-division control signal and a second frequency-division control signal; the first gate driving unit including a plurality of cascaded first gate driving circuits; the second gate driving unit including a plurality of cascaded second gate driving circuits; the first gate driving circuit being configured to control a level of a generated first gate control signal according to the first frequency-division control signal; and the second gate driving circuit being configured to control a level of a generated second gate control signal according to the second frequency-division control signal; In which, the first gate driving circuit and the second gate driving circuit both include a first output end, the control ends of the compensation transistors of the multiple sub-pixels are electrically connected to the first output ends of the multi-stage first gate driving circuit to receive multiple first gate control signals, and the control ends of the reset transistors of the multiple sub-pixels are electrically connected to the first output ends of the multi-stage second gate driving circuit to receive multiple second gate control signals; in the same sub-pixel, the frequency of the second gate control signal received by the reset transistor is the same as the frequency of the first gate control signal received by the compensation transistor.

2. The display device according to claim 1, wherein At least one of the sub-pixels includes a data transistor, an input terminal of the data transistor is configured to receive a data signal, and an output terminal of the data transistor is electrically connected to an input terminal of the driving transistor; The first gate driving circuit and the second gate driving circuit both include a second output terminal, the second output terminal of the first gate driving circuit outputs a third gate control signal, and the second output terminal of the second gate driving circuit outputs a fourth gate control signal; The control terminals of the data transistors of the plurality of sub-pixels are electrically connected to the second output terminals of the plurality of first gate driving circuits and / or the second output terminals of the plurality of second gate driving circuits.

3. The display device according to claim 2, wherein: In at least one frame after the first frame in a display cycle, the frequency of the first gate control signal outputted by the corresponding at least one first gate driving circuit is greater than or less than the frequency of the third gate control signal.

4. The display device according to claim 2, wherein In at least one frame after the first frame in a display cycle, the frequency of the second gate control signal outputted by the corresponding at least one second gate driving circuit is smaller than or larger than the frequency of the fourth gate control signal.

5. The display device according to claim 2, wherein The plurality of frequency division control lines include a first frequency division control line for transmitting the first frequency division control signal and a second frequency division control line for transmitting the second frequency division control signal; The first gate driving circuit and the second gate driving circuit both include: a node control module, electrically connected to the first node and configured to control a signal of the first node according to a corresponding start signal and a first clock signal; a first frequency division control module, electrically connected to the first node, the second node, and the third node, and configured to control signal transmission between the first node and the second node according to a signal of the third node and the corresponding frequency division control signal; a first output module, electrically connected to the first node, the second node, and the first output terminal, and configured to control a gate control signal outputted by the first output terminal according to signals of the first node and the second node; The first frequency division control module of the multi-stage first gate driving circuit is electrically connected to the first frequency division control line, and the first frequency division control module of the multi-stage second gate driving circuit is electrically connected to the second frequency division control line. The display device according to claim 5 , wherein: At least one of the first gate driving circuit and the second gate driving circuit includes: a second output module electrically connected to the third node, the fourth node, and the second output terminal, and configured to control a gate control signal outputted by the second output terminal according to signals of the third node and the fourth node and a corresponding second clock signal; and A second frequency division control module is electrically connected to the node control module through the first node and the third node, and is electrically connected to the corresponding second output module through the fourth node, and is configured to control signal transmission between the first node and the fourth node according to the corresponding frequency division control signal.

7. The display device according to claim 6, wherein: The first gate driving circuit and the second gate driving circuit respectively include X second output modules and X second output terminals, and each second output module is electrically connected to one second output terminal; Among them, the phase difference between the first clock signals corresponding to two adjacent levels of the first gate driving circuit is XH, and the phase difference between the first clock signals corresponding to two adjacent levels of the second gate driving circuit is XH; X≥1, H represents the unit time length.

8. The display device according to claim 7, wherein: X>1, the X second output modules of the same first gate drive circuit are configured to output multiple third gate control signals with phase differences, and the X second output modules of the same second gate drive circuit are configured to output multiple fourth gate control signals with phase differences.

9. The display device according to claim 7, wherein: Each of the second output terminals is electrically connected to the control terminals of the data transistors of a plurality of the sub-pixels located in a row; The control end of the data transistor of the sub-pixel located in the Lth row to the L+X-1th row is electrically connected to the X second output ends of the Kth level first gate driving circuit and / or the X second output ends of the Kth level second gate driving circuit; wherein K≥1, L=XK-(X-1).

10. The display device according to claim 7, wherein: X=1； Among them, the control end of the compensation transistor of the sub-pixel located in the Lth row is electrically connected to the first output end of the first gate driving circuit of the K+1th level, and the control end of the reset transistor of the sub-pixel located in the Lth row is electrically connected to the first output end of the second gate driving circuit of the K-3th level.

11. The display device according to claim 10, wherein: Also includes: a plurality of clock lines, including a first clock line, a second clock line, a third clock line, and a fourth clock line; Among them, the first clock signal corresponding to the 4m+1-th level first gate drive circuit and the 4m+1-th level second gate drive circuit corresponds to the signal transmitted by the second clock line, and the second clock signal corresponding to the 4m+1-th level first gate drive circuit and the 4m+1-th level second gate drive circuit corresponds to the signal transmitted by the first clock line; the first clock signal corresponding to the 4m+2-th level first gate drive circuit and the 4m+2-th level second gate drive circuit corresponds to the signal transmitted by the third clock line, and the second clock signal corresponding to the 4m+2-th level first gate drive circuit and the 4m+2-th level second gate drive circuit corresponds to the signal transmitted by the second clock line. Number; the first clock signal corresponding to the first gate drive circuit of the 4m+3th level and the second gate drive circuit of the 4m+3th level corresponds to the signal transmitted by the fourth clock line, and the second clock signal corresponding to the first gate drive circuit of the 4m+3th level and the second gate drive circuit of the 4m+3th level corresponds to the signal transmitted by the third clock line; the first clock signal corresponding to the first gate drive circuit of the 4m+4th level and the second gate drive circuit of the 4m+4th level corresponds to the signal transmitted by the first clock line, and the second clock signal corresponding to the first gate drive circuit of the 4m+4th level and the second gate drive circuit of the 4m+4th level corresponds to the signal transmitted by the fourth clock line.

12. The display device according to claim 7, wherein: X≥2； Among them, the control end of the compensation transistor of the sub-pixel located in the Lth row to the L+X-1th row is electrically connected to the first output end of the first gate driving circuit of the Kth level; the control end of the reset transistor of the sub-pixel located in the Lth row to the L+X-1th row is electrically connected to the first output end of the first gate driving circuit of the K-2th level.

13. The display device according to claim 12, wherein: X=2, the display device further includes a plurality of clock lines, including a first clock line, a second clock line, a third clock line, and a fourth clock line; In which, the first clock line transmits the corresponding second clock signal to the second output module of the first gate drive circuit of the 2k+1th level and the second output module of the second gate drive circuit of the 2k+1th level, and the second clock line transmits the corresponding second clock signal to another second output module of the first gate drive circuit of the 2k+1th level and another second output module of the second gate drive circuit of the 2k+1th level; the third clock line transmits the corresponding second clock signal to the second output module of the first gate drive circuit of the 2k+2th level and the second output module of the second gate drive circuit of the 2k+2th level, and the fourth clock line transmits the corresponding second clock signal to another second output module of the first gate drive circuit of the 2k+2th level and another second output module of the second gate drive circuit of the 2k+2th level, k≥0.

14. The display device according to claim 13, wherein: The third clock line transmits the corresponding first clock signal to the first gate drive circuit of the 2k+1th level and the second gate drive circuit of the 2k+1th level; the first clock line transmits the corresponding first clock signal to the first gate drive circuit of the 2k+2th level and the second gate drive circuit of the 2k+2th level.

15. The display device according to claim 6, wherein The plurality of frequency division control lines include a third frequency division control line and a fourth frequency division control line; the first gate driving circuit and the second gate driving circuit each include a second frequency division control module; The second frequency division control module of the multi-stage first gate driving circuit is electrically connected to the third frequency division control line, and the second frequency division control module of the multi-stage second gate driving circuit is electrically connected to the fourth frequency division control line.

16. The display device according to claim 15, wherein The control terminals of the data transistors of the plurality of sub-pixels in the same row are electrically connected to the second output terminals of the plurality of first gate driving circuits and the second output terminals of the plurality of second gate driving circuits; Wherein, the third frequency-division control line and the fourth frequency-division control line are electrically connected.

17. The display device according to claim 6, wherein: The start signal corresponding to the first-level first gate drive circuit in the multi-level first gate drive circuit has a jump from a valid level to an invalid level at the first moment, and the start signal corresponding to the first-level second gate drive circuit in the multi-level second gate drive circuit has a jump from a valid level to an invalid level at the first moment.

18. The display device according to claim 1, wherein The multi-level first gate driving circuit is electrically connected to the control end of the compensation transistor of the multiple sub-pixels through a unilateral driving method, and the multi-level second gate driving circuit is electrically connected to the control end of the reset transistor of the multiple sub-pixels through a unilateral driving method.

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