Shift register, gate driving circuit, and display device

Abstract

The present disclosure relates to the technical field of display, and provides a shift register, a gate driving circuit, and a display device. The shift register of the present disclosure comprises: an input sub-circuit configured to, in response to an input signal of a signal input end, pre-charge a pull-up node by means of the input signal; an output sub-circuit configured to output a clock signal by means of a signal output end in response to the potential of the pull-up node; a pull-down control sub-circuit configured to respond to a power supply voltage, and control the potential of a pull-down node by means of the power supply voltage; a first pull-down sub-circuit configured to, in response to the potential of the pull-up node and by means of a first non-working level signal, pull down the potential of the pull-down node electrically connected to the first pull-down sub-circuit; and at least one first auxiliary sub-circuit configured to, when a touch phase ends and under the control of a first control signal, discharge the pull-down node electrically connected to the at least one first auxiliary sub-circuit.

Description

Shift register, gate driving circuit and display device TECHNICAL FIELD

[0001] The present disclosure belongs to the technical field of display, and particularly relates to a shift register, a gate driving circuit and a display device. BACKGROUND

[0002] With the continuous development of display technology, the development of display in recent years gradually presents a development trend of high integration and low cost. One of the very important technologies is the realization of mass production of GOA (Gate Driver on Array) technology. The TFT (Thin Film Transistor) gate switch circuit integrated on the array substrate of the display panel by using the GOA technology to form the scanning driving of the display panel, so that the gate driving integrated circuit part can be saved, which not only can reduce the product cost from the aspects of material cost and manufacturing process, but also the display panel can be designed to be symmetrical and narrow frame. At the same time, since the Gate direction bonding process can be saved, the production capacity and yield are also improved. The gate switch circuit integrated on the array substrate by using the GOA technology is also called GOA circuit or shift register circuit. SUMMARY

[0003] The present disclosure aims to at least solve one of the technical problems existing in the prior art, and provides a shift register, a gate driving circuit and a display device.

[0004] The shift register provided by the present disclosure comprises an input sub-circuit, an output sub-circuit, at least one pull-down control sub-circuit and at least one first pull-down sub-circuit.

[0005] The input sub-circuit is configured to pre-charge a pull-up node by an input signal of a signal input end in response to the input signal of the signal input end; the pull-up node is a connection node between the input sub-circuit, the output sub-circuit and the first pull-down sub-circuit.

[0006] The output sub-circuit is configured to output a clock signal through a signal output end in response to a potential of the pull-up node.

[0007] The pull-down control sub-circuit is configured to control a potential of a pull-down node by a power supply voltage in response to the power supply voltage; one pull-down control sub-circuit is connected to one first pull-down sub-circuit, and a connection node between the two is the pull-down node.

[0008] The first pull-down sub-circuit is configured to pull down the potential of the pull-down node electrically connected thereto by a first non-working level signal in response to the potential of the pull-up node; wherein,

[0009] The shift register further comprises at least one first auxiliary sub-circuit, one of the first auxiliary sub-circuit being electrically connected to one of the pull-down nodes; the first auxiliary sub-circuit is configured to discharge the pull-down node electrically connected thereto under the control of the first control signal after the touch phase ends.

[0010] The number of the pull-down control sub-circuit, the first pull-down sub-circuit and the first auxiliary sub-circuit is multiple, and one of the pull-down nodes is electrically connected to one of the pull-down control sub-circuit, one of the first pull-down sub-circuit and one of the first auxiliary sub-circuit.

[0011] Each of the first auxiliary sub-circuit is electrically connected to the same first control signal terminal, and works simultaneously under the first control signal received by the first control signal terminal, and discharges the pull-down node corresponding thereto before the current frame scanning.

[0012] The shift register further comprises a first global reset sub-circuit configured to globally reset the pull-up node by a first non-working level signal under the control of the first global reset signal.

[0013] The global reset signal is multiplexed as the first control signal.

[0014] The global reset sub-circuit comprises a fifteenth transistor.

[0015] The first electrode of the fifteenth transistor is connected to the pull-up node, the second electrode is connected to the first non-working level signal terminal, and the control electrode is connected to the first global reset signal terminal and each of the first auxiliary sub-circuit.

[0016] The first auxiliary sub-circuit comprises a seventeenth transistor.

[0017] The first electrode of the seventeenth transistor is connected to one of the pull-down nodes, the second electrode is connected to the first non-working level signal terminal, and the control electrode is connected to the first global reset signal terminal.

[0018] The frame start signal is multiplexed as the first control signal.

[0019] The first auxiliary sub-circuit comprises a seventeenth transistor.

[0020] The first electrode of the seventeenth transistor is connected to one of the pull-down nodes, the second electrode is connected to the first non-working level signal terminal, and the control electrode is connected to the frame start signal terminal.

[0021] The number of the pull-down control sub-circuits, the first pull-down sub-circuits and the first auxiliary sub-circuits is two, the number of the pull-down nodes is two, the two pull-down nodes are a first pull-down node and a second pull-down node respectively, and the first pull-down node is electrically connected with one pull-down control sub-circuit, one first pull-down sub-circuit and one first auxiliary sub-circuit; the second pull-down node is electrically connected with another pull-down control sub-circuit, another first pull-down sub-circuit and another first auxiliary sub-circuit.

[0022] The potential of the first pull-down node is multiplexed as a first control signal of one first auxiliary sub-circuit, and the second pull-down node is discharged by the first non-working level signal; the potential of the second pull-down node is multiplexed as a first control signal of another first auxiliary sub-circuit, and the first pull-down node is discharged by the first non-working level signal.

[0023] The first auxiliary sub-circuit comprises a seventeenth transistor.

[0024] The first electrode of the seventeenth transistor in one first auxiliary sub-circuit is connected with the first pull-down node, the second electrode is connected with a first non-working level signal end, and the control electrode is connected with the second pull-down node; the first electrode of the seventeenth transistor in another first auxiliary sub-circuit is connected with the first pull-down node, the second electrode is connected with a first non-working level signal end, and the control electrode is connected with the second pull-down node.

[0025] The shift register further comprises a second auxiliary sub-circuit configured to discharge the output of the signal output end by the first non-working level signal in response to a touch enable signal.

[0026] The second auxiliary sub-circuit comprises an eighteenth transistor.

[0027] The first electrode of the eighteenth transistor is connected with the signal output end, the second electrode is connected with a first non-working level signal end, and the control electrode is connected with a touch enable signal end.

[0028] The shift register further comprises at least one second pull-down sub-circuit, and one second pull-down sub-circuit is electrically connected with one pull-down node.

[0029] The second pull-down sub-circuit is configured to pull down the potential of the pull-down node electrically connected therewith by the first non-working level signal in response to an input signal.

[0030] The second pull-down sub-circuit comprises a seventh transistor.

[0031] The first electrode of the seventh transistor is connected with the corresponding pull-down node, the second electrode is connected with a first non-working level signal terminal, and the control electrode is connected with a signal input terminal.

[0032] The shift register further comprises

[0033] The first reset sub-circuit is configured to reset the pull-up node by a first non-working level signal under the control of a reset signal

[0034] The second reset sub-circuit is configured to reset the signal output terminal by a second non-working level signal under the control of the reset signal.

[0035] The first reset sub-circuit comprises a second transistor, and the second reset sub-circuit comprises a fourth transistor.

[0036] The first electrode of the second transistor is connected with the pull-up node, the second electrode is connected with the first non-working level signal terminal, and the control electrode is connected with the reset signal terminal.

[0037] The first electrode of the fourth transistor is connected with the signal output terminal, the second electrode is connected with the second non-working level signal terminal, and the control electrode is connected with the reset signal terminal.

[0038] The shift register further comprises at least one first noise reduction sub-circuit and at least one second noise reduction sub-circuit; one pull-down node is electrically connected with one first noise reduction sub-circuit and one second noise reduction sub-circuit.

[0039] The first noise reduction sub-circuit is configured to reduce noise of the output of the pull-up node by a first non-working level signal under the control of the pull-down node electrically connected therewith;

[0040] The second noise reduction sub-circuit is configured to reduce noise of the output of the signal output terminal by a second non-working level signal under the control of the pull-down node electrically connected therewith.

[0041] The first noise reduction sub-circuit comprises a tenth transistor, and the second noise reduction sub-circuit comprises a thirteenth transistor.

[0042] The first electrode of the tenth transistor is connected with the pull-up node, the second electrode is connected with the first non-working level signal terminal, and the control electrode is connected with the corresponding pull-down node.

[0043] The first electrode of the thirteenth transistor is connected with the signal output terminal, the second electrode is connected with the second non-working level signal terminal, and the control electrode is connected with the corresponding pull-down node.

[0044] The shift register further comprises a cascade sub-circuit configured to output a clock signal through a cascade signal terminal in response to a potential of the pull-up node.

[0045] The cascade sub-circuit comprises an eleventh transistor.

[0046] The first electrode of the eleventh transistor is connected to an always-on signal terminal, the second electrode is connected to the cascade signal terminal, and the control electrode is connected to the pull-up node.

[0047] The shift register further comprises a third noise reduction sub-circuit configured to reduce noise of the output of the cascade signal terminal by a first non-working level signal under the control of the pull-down node electrically connected thereto.

[0048] The third noise reduction sub-circuit comprises a twelfth transistor.

[0049] The first electrode of the twelfth transistor is connected to the cascade signal terminal, the second electrode is connected to a first non-working level signal terminal, and the control electrode is connected to the pull-down node corresponding thereto.

[0050] The shift register further comprises a second global reset sub-circuit configured to discharge a signal output terminal by a first non-working level signal in response to a second global reset signal.

[0051] The second global reset sub-circuit comprises a fourteenth transistor.

[0052] The first electrode of the fourteenth transistor is connected to the signal output terminal, the second electrode is connected to the first non-working level signal terminal, and the control electrode is connected to the second global reset signal terminal.

[0053] The input sub-circuit comprises a first transistor.

[0054] The first electrode and the control electrode of the first transistor are both connected to a signal input terminal, and the second electrode is connected to the pull-up node.

[0055] The output sub-circuit comprises a third transistor and a storage capacitor.

[0056] The first electrode of the third transistor is connected to a clock signal terminal, the second electrode is connected to the signal output terminal and the second terminal of the storage capacitor, and the control electrode is connected to the first terminal of the storage capacitor and the pull-up node.

[0057] The pull-down control sub-circuit comprises a fifth transistor.

[0058] The first electrode of the fifth transistor is connected to the control electrode and a power voltage terminal, and the second electrode is connected to the pull-down node corresponding thereto.

[0059] The first pull-down sub-circuit comprises a sixth transistor.

[0060] The first electrode of the sixth transistor is connected to a corresponding pull-down node, the second electrode is connected to a non-working voltage terminal, and the control electrode is connected to a signal input terminal.

[0061] Each sub-circuit in the shift register comprises at least a thin film transistor, and the thin film transistor is an oxide thin film transistor.

[0062] The shift register comprises an input sub-circuit, an output sub-circuit, at least one pull-down control sub-circuit, and at least one first pull-down sub-circuit.

[0063] The input sub-circuit is configured to pre-charge a pull-up node through an input signal of a signal input terminal in response to the input signal; and a connection node between the input sub-circuit, the output sub-circuit, and the pull-down sub-circuit.

[0064] The output sub-circuit is configured to output a clock signal through a signal output terminal in response to a potential of the pull-up node.

[0065] The pull-down control sub-circuit is configured to control a potential of a pull-down node through a power supply voltage in response to the power supply voltage; one pull-down control sub-circuit is connected to one first pull-down sub-circuit, and a connection node between the two is the pull-down node.

[0066] The first pull-down sub-circuit is configured to pull down the potential of the pull-down node electrically connected thereto through a first non-working level signal in response to the potential of the pull-up node; wherein,

[0067] The shift register further comprises a second auxiliary sub-circuit configured to discharge the output of the signal output terminal through a first non-working level signal in response to a touch enable signal.

[0068] The input sub-circuit comprises a first transistor; the output sub-circuit comprises a third transistor and a storage capacitor; the pull-down control sub-circuit comprises a fifth transistor; the first pull-down sub-circuit comprises a sixth transistor; and the second auxiliary sub-circuit comprises an eighteenth transistor.

[0069] The first electrode and the control electrode of the first transistor are connected to a signal input end, and the second electrode is connected to the pull-up node; the first electrode of the third transistor is connected to a clock signal end, the second electrode is connected to the signal output end and the second end of the storage capacitor, and the control electrode is connected to the first end of the storage capacitor and the pull-up node; the first electrode of the fifth transistor is connected to the control electrode and a power voltage end, and the second electrode is connected to the corresponding pull-down node; the first electrode of the sixth transistor is connected to the corresponding pull-down node, the second electrode is connected to a non-working voltage end, and the control electrode is connected to the signal input end; the first electrode of the eighteenth transistor is connected to the signal output end, the second electrode is connected to a first non-working level signal end, and the control electrode is connected to a touch enable signal end.

[0070] The gate drive circuit according to any one of the above embodiments of the present disclosure is provided.

[0071] The display device according to any one of the above embodiments of the present disclosure is provided. BRIEF DESCRIPTION OF DRAWINGS

[0072] FIG. 1 is a circuit diagram of an exemplary shift register.

[0073] FIG. 2 is a timing diagram corresponding to the shift register shown in FIG. 1.

[0074] FIG. 3 is a simulation diagram of a scan end touch noise defect occurring in a WQXGA product.

[0075] FIG. 4 is a circuit diagram of a first exemplary shift register according to an embodiment of the present disclosure.

[0076] FIG. 5 is a timing diagram corresponding to the shift register shown in FIG. 4.

[0077] FIG. 6 is a circuit diagram of a second exemplary shift register according to an embodiment of the present disclosure.

[0078] FIG. 7 is a timing diagram corresponding to the shift register shown in FIG. 6.

[0079] FIG. 8 is a circuit diagram of a third exemplary shift register according to an embodiment of the present disclosure.

[0080] FIG. 9 is a circuit diagram of a fourth exemplary shift register according to an embodiment of the present disclosure.

[0081] FIG. 10 is a circuit diagram of a fifth exemplary shift register according to an embodiment of the present disclosure.

[0082] FIG. 11 is a timing diagram corresponding to the shift register shown in FIG. 10. DETAILED DESCRIPTION

[0083] In order for those skilled in the art to better understand the technical solutions of the present application, the present application will be further described in detail below in conjunction with the drawings and specific embodiments.

[0084] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. Similarly, the terms "one", "a", or "the" and similar terms do not denote a quantity restriction, but mean that at least one exists. The terms "include", "comprise", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms do not mean a physical or mechanical connection, but can include an electrical connection, whether direct or indirect. The terms "up", "down", "left", "right", and the like are used only to indicate relative positional relationships, and when the absolute positions of the described objects change, the relative positional relationships can also change accordingly.

[0085] It should be noted that the transistors used in the embodiments of the present application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistor used are symmetrical, the source and drain are not distinguished. In the embodiments of the present application, one of the poles is referred to as the first pole, the other pole is referred to as the second pole, and the gate is referred to as the control pole. In addition, the transistors can be divided into N-type and P-type according to their characteristics. In the following embodiments, N-type transistors are used for illustration. When N-type transistors are used, the first pole is the source of the N-type transistor, the second pole is the drain of the N-type transistor, and the gate is inputted with a high level, the source and drain are turned on, and the P-type is the opposite. It is conceivable that P-type transistors can be used to achieve the same result without any creative effort, and therefore are within the scope of protection of the embodiments of the present application.

[0086] In the embodiments of the present application, since the transistors used are N-type transistors, the working level signal in the embodiments of the present application refers to a high level signal, and the first low level signal is a first low level signal. Correspondingly, the working level end is a high level signal end, and the low level end is a first low level signal end.

[0087] Generally, the display panel includes a plurality of gate lines and a plurality of data lines, the gate lines and the data lines are arranged in a cross manner to define a plurality of pixel regions, and each pixel region is provided with a pixel unit. Taking the extension direction of each gate line as the row direction and the extension direction of each data line as the column direction as an example, the structure of the display panel is described. When driving the display panel to display, a gate scanning signal can be written into each gate line row by row according to a to-be-displayed picture, and a data voltage signal is written into each data line at the same time, so that the pixel units in the display panel are lit row by row.

[0088] The gate scanning signal is provided by a gate drive circuit, and the data voltage signal is provided by a source drive circuit. In the related art, the gate drive circuit can be integrated in a gate drive chip, and the source drive circuit can be integrated in a source drive chip. Currently, in order to reduce the number of chips and achieve a narrow frame or no frame, a Gate On Array (GOA) technology is provided. The gate drive circuit includes a plurality of cascaded shift registers integrated on the array substrate. Each shift register is connected to a gate line in one-to-one correspondence, and is configured to provide a gate scanning signal for the gate line connected thereto.

[0089] In order to more clearly describe how the shift register unit implements the output of the gate scanning signal, the following describes a specific example of the shift register unit.

[0090] Figure 1 is a circuit diagram of an exemplary shift register, as shown in Figure 1, the shift register comprises an input sub-circuit 1, an output sub-circuit 3, a cascade sub-circuit 4, a first reset sub-circuit 21 and a second reset sub-circuit 22, two pull-down control sub-circuits 5 / 5', two first pull-down sub-circuits 6 / 6', two second pull-down sub-circuits 7 / 7', two first noise reduction sub-circuits 8 / 8', two second noise reduction sub-circuits 9 / 9', and two third noise reduction sub-circuits 10 / 10', a first global reset sub-circuit 11 and a second global reset sub-circuit 12. Among them, the input sub-circuit 1 is configured to pre-charge the pull-up node PU by the input signal of the signal input end Input in response to the input signal of the signal input end Input; the pull-up node PU is a connection node between the input sub-circuit 1, the output sub-circuit 3, and the two first pull-down sub-circuits 6 / 6'. The output sub-circuit 3 is configured to output the clock signal through the signal output end G_out in response to the potential of the pull-up node PU. The first reset sub-circuit 21 is configured to reset the pull-up node PU by the first low-level signal under the control of the reset signal. The second reset sub-circuit 22 is configured to reset the output of the signal output end G_out by the second low-level signal under the control of the reset signal. The cascade sub-circuit 4 is configured to output the clock signal through the cascade signal end OC in response to the potential of the pull-up node PU. The pull-down control sub-circuit is configured to control the potential of the pull-down node by the power voltage in response to the power voltage; one pull-down control sub-circuit is connected with one first pull-down sub-circuit, and the connection node between them is the pull-down node. The first pull-down sub-circuit is configured to pull down the potential of the pull-down node electrically connected thereto by the first low-level signal in response to the potential of the pull-up node PU. The second pull-down sub-circuit is configured to pull down the potential of the pull-down node electrically connected thereto by the first low-level signal in response to the input signal. The first noise reduction sub-circuit is configured to reduce the output of the pull-up node PU by the first low-level signal under the control of the pull-down node connected thereto. The second noise reduction sub-circuit is configured to reduce the output of the signal output end G_out by the second low-level signal under the control of the pull-down node connected thereto. The third noise reduction sub-circuit is configured to reduce the output of the cascade signal end OC under the control of the pull-down node connected thereto. The first global reset sub-circuit 11 is configured to discharge the pull-up node PU by the first low-level signal in response to the first global reset signal. The second global reset sub-circuit 12 is configured to discharge the output of the signal output end G_out by the second low-level signal in response to the second global reset signal.

[0091] The two pull-down control sub-circuits 5 / 5', the two first pull-down sub-circuits 6 / 6', the two second pull-down sub-circuits 7 / 7', the two first noise reduction sub-circuits 8 / 8', the two second noise reduction sub-circuits 9 / 9', and the two third noise reduction sub-circuits 10 / 10' are connected in series. The pull-down control sub-circuit 5 is connected with a first pull-down sub-circuit 6 and a second pull-down sub-circuit 7, and the connection node of the three is a first pull-down node PD1. The pull-down control sub-circuit 5' is connected with a first pull-down sub-circuit 6' and a second pull-down sub-circuit 7', and the connection node of the three is a first pull-down node PD1PD2. The first pull-down node PD1 is connected with a first noise reduction sub-circuit 8, a second noise reduction sub-circuit 9, and a third noise reduction sub-circuit 10. The second pull-down node PD2 is connected with another first noise reduction sub-circuit 8', another second noise reduction sub-circuit 9', and another third noise reduction sub-circuit 10'. The two pull-down control sub-circuits 5 / 5' in the shift register have the same structure and function, but the two pull-down control sub-circuits 5 / 5' are time-sharing working when the shift register works, that is, the time sequence of the control signals for controlling the two pull-down control sub-circuits 5 / 5' is opposite. Similarly, the two first pull-down sub-circuits 6 / 6' have the same structure and function, and the two first pull-down sub-circuits 6 / 6' are time-sharing working. The two second pull-down sub-circuits 7 / 7' have the same structure and function, and the two second pull-down sub-circuits 7 / 7' are time-sharing working. The two first noise reduction sub-circuits 8 / 8' have the same structure and function, and the two first noise reduction sub-circuits 8 / 8' are time-sharing working. The two second noise reduction sub-circuits 9 / 9' have the same structure and function, and the two second noise reduction sub-circuits 9 / 9' are time-sharing working. The two third noise reduction sub-circuits 10 / 10' have the same structure and function, and the two third noise reduction sub-circuits 10 / 10' are time-sharing working. The first global reset signal can be a frame pre-on signal, and the pull-up node PU is discharged before the current frame scanning.

[0092] Specifically, the input sub-circuit 1 comprises a first transistor M1. The first reset sub-circuit 21 comprises a second transistor M2. The second reset sub-circuit 11 comprises a fourth transistor M4. The output sub-circuit 3 comprises a third transistor M3 and a storage capacitor C1. The cascade sub-circuit 4 comprises an eleventh transistor M11. The first global reset sub-circuit 11 comprises a fifteenth transistor M15. The second global reset sub-circuit 12 comprises a fourteenth transistor M14. Each pull-down control sub-circuit comprises a fifth transistor; the fifth transistors in the two pull-down control sub-circuits 5 / 5' are denoted by M5 and M5', respectively. Each first pull-down sub-circuit comprises a sixth transistor; the sixth transistors in the two first pull-down sub-circuits 6 / 6' are denoted by M6 and M6', respectively. Each second pull-down sub-circuit comprises a seventh transistor; the seventh transistors in the two second pull-down sub-circuits 7 / 7' are denoted by M7 and M7', respectively. Each first noise reduction sub-circuit comprises a tenth transistor; the tenth transistors in the two first noise reduction sub-circuits 8 / 8' are denoted by M10 and M10', respectively. Each second noise reduction sub-circuit comprises a thirteenth transistor; the thirteenth transistors in the two second noise reduction sub-circuits 9 / 9' are denoted by M13 and M13', respectively. Each third noise reduction sub-circuit comprises a twelfth transistor; the twelfth transistors in the two third noise reduction sub-circuits 10 / 10' are denoted by M12 and M12', respectively.

[0093] Further, the gate and source of M1 are connected with a signal input end Input, and the drain of M1 is connected with a pull-up node PU. The gate of M2 is connected with a reset signal end Reset, the source of M2 is connected with the pull-up node PU, and the drain of M2 is connected with a first low voltage signal end LVGL. The gate of M4 is connected with the reset signal end Reset, the source of M4 is connected with a signal output end G_out, and the drain of M4 is connected with a second low voltage signal end VGL. The gate of M3 is connected with the pull-up node PU, the source of M3 is connected with a clock signal end CLK, and the drain of M3 is connected with the signal output end G_out. The gate of M11 is connected with the pull-up node PU, the source of M11 is connected with the clock signal end CLK, and the drain of M11 is connected with a cascade signal end OC. The first end of C1 is connected with the pull-up node PU, and the second end of C1 is connected with the signal output end G_out. The gate and source of M5 are both connected with a first power voltage end VDD1, and the drain of M5 is connected with a first pull-down node PD1. The gate and source of M5' are both connected with a second power voltage end VDD2, and the drain of M5 is connected with a second pull-down node PD2. The gate of M6 is connected with the pull-up node PU, the source of M6 is connected with a first pull-up node PU, and the drain of M6 is connected with the first low voltage signal end LVGL. The gate of M6' is connected with the pull-up node PU, the source of M6' is connected with a second pull-up node PU, and the drain of M6' is connected with the first low voltage signal end LVGL. The gate of M7 is connected with the signal input end Input, the source of M7 is connected with the first pull-up node PU, and the drain of M7 is connected with the first low voltage signal end LVGL. The gate of M7' is connected with the signal input end Input, the source of M7' is connected with the second pull-up node PU, and the drain of M7' is connected with the first low voltage signal end LVGL. The gate of M10 is connected with the first pull-down node PD1, the source of M10 is connected with the pull-up node PU, and the drain of M10 is connected with the first low voltage signal end LVGL. The gate of M10' is connected with the second pull-down node PD2, the source of M10' is connected with the pull-up node PU, and the drain of M10' is connected with the first low voltage signal end LVGL. The gate of M12 is connected with the first pull-down node PD1, the source of M12 is connected with the cascade signal end OC, and the drain of M12 is connected with the first low voltage signal end LVGL. The gate of M12' is connected with the second pull-down node PD2, the source of M12' is connected with the cascade signal end OC, and the drain of M12' is connected with the first low voltage signal end LVGL. The gate of M13 is connected with the first pull-down node PD1, the source of M13 is connected with the signal output end G_out, and the drain of M13 is connected with the second low voltage signal end VGL. The gate of M13' is connected with the second pull-down node PD2, the source of M13' is connected with the signal output end G_out, and the drain of M13' is connected with the first low voltage signal end LVGL. The gate of M14 is connected with a second global reset signal end Total_RST, the source of M14 is connected with the signal output end G_out, and the drain of M14 is connected with the second low voltage signal end VGL.The gate of the M15 is connected with the first global reset signal terminal Total_RST1, the source of the M15 is connected with the signal output terminal G_out, and the drain of the M15 is connected with the first low voltage signal terminal LVGL.

[0094] Fig. 2 is a timing diagram corresponding to the shift register shown in Fig. 1; in combination with Fig. 2, the operation of the shift register can include the following stages:

[0095] The discharge stage, before the frame, that is, before the display, the first global reset signal terminal Total_RST1 and the second global reset signal terminal Total_RST are input with high level signals, the fourteenth transistor and the fifteenth transistor are opened, and the first low level signal input through the first low level signal terminal LVGL is used to discharge the pull-up node PU and the signal output terminal G_out, so as to prevent the residual charge of the pull-up node PU and the signal output terminal G_out from causing display abnormalities.

[0096] The input stage, the signal input terminal Input is input with a high level signal, the M1 is opened, the pull-up node PU is pulled up by the high level signal, and C1 is charged at the same time, and the M6 and M6', M7 and M7' are opened, the first pull-down node PD1 and the second pull-down node PD2 are pulled down to avoid affecting the potential of the pull-up node PU.

[0097] The output stage, since the pull-up node PU is pulled up in the input stage, the M3 and M13 are opened, the high level signal input through the clock signal terminal CLK is output to the gate line connected with the signal output terminal G_out, at the same time, the cascade signal terminal OC outputs the same signal as the signal output terminal G_out, that is, outputs a high level signal to the pull-up reset signal terminal Reset of the previous shift register unit and the signal input terminal Input of the next shift register unit.

[0098] The reset stage, the reset signal terminal Reset is input with a high level signal, the M2 and M4 are opened, the pull-up node PU and the signal output terminal G_out are pulled down by the first low level signal input through the first low level signal terminal LVGL, so as to reset the pull-up node PU and the signal output terminal G_out. At the same time, the pull-down control node and the first pull-down node PD1 are high level signals, the M10, M13 and M12 are opened, respectively, to reduce the noise of the output of the pull-up node PU, the signal output terminal G_out and the cascade signal terminal OC, until the pull-up node PU potential is pulled up at the beginning of the next frame scanning.

[0099] For the shift register of the 19T1C above, the thin film transistors therein can adopt oxide thin film transistors. Since the two pull-down control sub-circuits therein work in time division, the VDD1 and VDD2 signals corresponding to the first power supply voltage terminal VDD1 and the second power supply voltage terminal VDD2 respectively connected to the two pull-down control sub-circuits can be switched in the blanking stage between displaying two frames of pictures, instead of single-path VDD direct current noise reduction. Correspondingly, the first pull-down node PD1 and the second pull-down node PD2 signals follow the VDD1 and VDD2 signals to switch high and low levels. The discharge paths of the first pull-down node PD1 and the second pull-down node PD2 are two: one is discharging through M7 and M7' when the current row signal input terminal Input is written with a high level signal; the other is discharging through M6 and M6' when the current row pull-up node PU is at a high level. Both of the two discharge modes are discharging the pull-down node of the current row when the GOA of the current row is working. However, for the shift register composed of oxide thin film transistors, the Ioff of the thin film transistors is low, and if the above two modes are not adopted, the pull-down node at a high level needs a very long time to be discharged by natural dissipation.

[0100] For a TDDI product, the common way for the IC to collect raw data in the AA area is to collect data by drawing modulation waveforms at fixed rows. Taking a WQXGA product (resolution 2560*1600) as an example, the product has 2560 rows, and the first pass of collecting raw data of the entire surface is performed when the gate driving circuit scans to the X1th row, in which case the shift registers from the 1st to the X1st level work one by one. The second pass of collecting raw data of the entire surface is performed when the gate driving circuit scans to the X2th row, in which case the shift registers from the X1st to the X2th level work one by one. This means that in the first pass of collection, the signal input terminals Input and the pull-up nodes PU of the 1st to X1st rows have been raised, and the charges of the pull-down nodes can be discharged through the above two modes; in the second pass of collection, the signal input terminals Input and the pull-up nodes PU of the X1st to X2nd rows have been raised, and the charges of the pull-down nodes can be discharged through the above two modes; the signal input terminals Input and the pull-up nodes PU of the X2nd to 2560th rows have never been raised, and the charges of the pull-down nodes cannot be discharged.

[0101] It should be noted that, with reference to FIG. 2, the clock signal written to the clock signal terminal CLK in the touch phase is different from the clock signal written in normal display. Since the display panel is invalid in the touch phase, the effective level of the clock signal written to the shift register in the touch phase is lower than the effective level of the clock signal written in normal display.

[0102] For example, the first power voltage is converted from high level to low level, and the second power voltage is converted from low level to high level. After switching, in the first frame, since the Rawdata collection in the touch stage is ended, the gate driving circuit only scans to the X2 row, that is, the first pull-down node PD1 of each shift register corresponding to the X2-2560 row is not discharged. Due to the high Ion characteristic of the oxide thin film transistor product, the second pull-down node PD2 is quickly lifted, and an abnormal state of the first pull-down node PD1 and the second pull-down node PD2 being high at the same time occurs. Thereafter, when the scanning comes to the abnormal row, the signal input end Input and the pull-up node PU normally arrive, and the abnormal first pull-down node PD1 is discharged, and the first pull-down node PD1 and the second pull-down node PD2 return from the abnormal two-high state to the normal one-high and one-low state. Therefore, in the second frame and subsequent frames after switching, the first pull-down node PD1 and the second pull-down node PD2 are in the normal state of one high and one low. Thus, due to the state of the first pull-down node PD1 and the second pull-down node PD2 being high at the same time in the first frame after switching, which is different from the state of the first pull-down node PD1 and the second pull-down node PD2 being one high and one low in the second frame and subsequent frames after switching, the signal output end G_out reflects the VGL Modulation waveform inconsistently, so that the IC collects original data with differences, and a Touch Noise (touch noise) defect is generated.

[0103] Specifically, as shown in (a) of FIG. 3, there is no noise (-100<value<100, uniformly distributed) at the scanning head (near the first row side); and there is noise (value<-200, uniform green) at the scanning tail (near the 2560 row side). As shown in (b) of FIG. 3, the difference between Rawdata is the size of noise, and there is a mutation of Rawdata once in each VDD1 and VDD2 switching period, that is, there is a larger Noise fluctuation once in each VDD1 / 2 switching period; wherein the VDD1 and VDD2 switching period is 240 frames. Wherein, point1, point2, point3, point4 respectively represent four points at the scanning tail (DP side), and the Rawdata values of point1, point2, point3, point4 all have periodic changes consistent with the VDD1 and VDD2 switching period, that is, the noise (difference between Rawdata) is related to the VDD1 and VDD2 switching.

[0104] In view of the above technical problems, the present disclosure provides the following technical solutions.

[0105] It should be noted that the number of the pull-down control sub-circuit, the first pull-down sub-circuit, the first noise reduction sub-circuit, the second noise reduction sub-circuit and the third noise reduction sub-circuit in the embodiments of the present disclosure can be one, two or more. In the embodiments of the present disclosure, the number of the pull-down control sub-circuit, the first pull-down sub-circuit, the first noise reduction sub-circuit, the second noise reduction sub-circuit and the third noise reduction sub-circuit is two. The timing of the first global reset signal and the second global reset signal is the same. The thin film transistor in each sub-circuit is taken as an oxide thin film transistor for illustration.

[0106] The first example: FIG. 4 is a circuit diagram of a shift register according to the first example of the embodiments of the present disclosure. As shown in FIG. 4, the shift register includes an input sub-circuit 1, an output sub-circuit 3, two pull-down control sub-circuits 5 / 5', two first pull-down sub-circuits 6 / 6', and two first auxiliary sub-circuits 13 / 13'. The input sub-circuit 1 is configured to pre-charge a pull-up node PU by an input signal of a signal input end Input in response to the input signal; the pull-up node PU is a connection node between the input sub-circuit 1, the output sub-circuit 3 and the first pull-down sub-circuit 6 / 6'; the output sub-circuit 3 is configured to output a clock signal through a signal output end G_out in response to a potential of the pull-up node PU; the pull-down control sub-circuit is configured to control a potential of a pull-down node by a power supply voltage in response to the power supply voltage; one pull-down control sub-circuit is connected to one first pull-down sub-circuit, and a connection node between the two is the pull-down node; the first pull-down sub-circuit is configured to pull down the potential of the pull-down node electrically connected thereto by a first low-level signal in response to the potential of the pull-up node PU; and the first auxiliary sub-circuit is configured to discharge the pull-down node electrically connected thereto under the control of a first control signal after the end of a touch phase.

[0107] In this example, by adding the first auxiliary sub-circuit, the pull-down node is discharged by the first control signal before the current frame scanning after the end of the touch phase of the display panel, so that the output abnormality caused by the potential difference of the pull-down node of each shift register can be effectively avoided.

[0108] Since the number of the pull-down control sub-circuit and the first pull-down sub-circuit in this example is two, the number of the pull-down node is also two, which are a first pull-down node PD1 and a second pull-down node PD2. The power supply voltage end connected to the pull-down control sub-circuit electrically connected to the first pull-down node PD1 is referred to as a first power supply voltage end VDD1, and the power supply voltage end connected to the pull-down control sub-circuit electrically connected to the second pull-down node PD2 is referred to as a second power supply voltage end VDD2.

[0109] In some examples, the two first auxiliary sub-circuits 13 / 13' can be connected to the same first control signal terminal Total_RST2, i.e. the two first auxiliary sub-circuits 13 / 13' can be controlled simultaneously, for example, before the current frame scanning, the first control signal input through the first control signal terminal Total_RST2 controls the two first auxiliary sub-circuits 13 / 13' to work simultaneously, respectively discharging the first pull-down node PD1 and the second pull-down node PD2.

[0110] In some examples, the shift register can further include the cascade sub-circuit 4, the first reset sub-circuit 21, the second reset sub-circuit 22, the two second pull-down sub-circuits 7 / 7', the two first noise reduction sub-circuits 8 / 8', the two second noise reduction sub-circuits 9 / 9', the two third noise reduction sub-circuits 10 / 10', the first global reset sub-circuit 11 and the second global reset sub-circuit 12.

[0111] The first reset sub-circuit 21 is configured to reset the pull-up node PU through the first low-level signal under the control of the reset signal. The second reset sub-circuit 22 is configured to reset the signal output terminal G_out through the second low-level signal under the control of the reset signal. The cascade sub-circuit 4 is configured to output the clock signal through the cascade signal terminal OC in response to the potential of the pull-up node PU. The second pull-down sub-circuit is configured to pull down the potential of the pull-down node electrically connected thereto through the first low-level signal in response to the input signal. The first noise reduction sub-circuit is configured to reduce the output of the pull-up node PU under the control of the pull-down node connected thereto. The second noise reduction sub-circuit is configured to reduce the output of the signal output terminal G_out under the control of the pull-down node connected thereto. The third noise reduction sub-circuit is configured to reduce the output of the cascade signal terminal OC under the control of the pull-down node connected thereto. The first global reset sub-circuit 11 is configured to discharge the pull-up node PU through the first low-level signal in response to the first global reset signal. The second global reset sub-circuit 12 is configured to discharge the output of the signal output terminal G_out through the second low-level signal in response to the second global reset signal.

[0112] With reference to FIG. 4, two pull-down control sub-circuits 5 / 5', two first pull-down sub-circuits 6 / 6', two second pull-down sub-circuits 7 / 7', two first noise reduction sub-circuits 8 / 8', two second noise reduction sub-circuits 9 / 9', two third noise reduction sub-circuits 10 / 10', the pull-down control sub-circuit corresponds to connect a first pull-down sub-circuit and a second pull-down sub-circuit, and the connection node of the three is a first pull-down node PD1. The pull-down control sub-circuit corresponds to connect a first pull-down sub-circuit and a second pull-down sub-circuit, and the connection node of the three is a first pull-down node PD1. The first pull-down node PD1 is connected with a first noise reduction sub-circuit, a second noise reduction sub-circuit and a third noise reduction sub-circuit, and the second pull-down node PD2 is connected with another first noise reduction sub-circuit, another second noise reduction sub-circuit and another third noise reduction sub-circuit. The structure and function of the two pull-down control sub-circuits 5 / 5' in the shift register are the same, but the two pull-down control sub-circuits 5 / 5' are time-sharing working when the shift register works, that is, the timing of the control signal for controlling the two pull-down control sub-circuits 5 / 5' is opposite. Similarly, the two first pull-down sub-circuits 6 / 6' have the same structure and function, and are time-sharing working; the two second pull-down sub-circuits 7 / 7' have the same structure and function, and are time-sharing working; the two first noise reduction sub-circuits 8 / 8' have the same structure and function, and are time-sharing working; the two second noise reduction sub-circuits 9 / 9' have the same structure and function, and are time-sharing working; the two third noise reduction sub-circuits 10 / 10' have the same structure and function, and are time-sharing working. The first global reset signal can adopt a frame pre-on signal, and the pull-up node PU is discharged before the current frame scanning.

[0113] Specifically, the input sub-circuit 1 comprises a first transistor M1. The first reset sub-circuit 21 comprises a second transistor M2. The second reset sub-circuit 22 comprises a fourth transistor M4. The output sub-circuit 3 comprises a third transistor M3 and a storage capacitor C1. The cascade sub-circuit 4 comprises an eleventh transistor M11. The first global reset sub-circuit 112 comprises a fifteenth transistor M15. The second global reset sub-circuit 122 comprises a fourteenth transistor M14. Each pull-down control sub-circuit comprises a fifth transistor; the fifth transistors in the two pull-down control sub-circuits 5 / 5' 5 / 5' are denoted by M5 and M5', respectively. Each first pull-down sub-circuit comprises a sixth transistor; the sixth transistors in the two first pull-down sub-circuits 6 / 6' 6 / 6' are denoted by M6 and M6', respectively. Each first pull-down sub-circuit comprises a seventh transistor; the seventh transistors in the two second pull-down sub-circuits 7 / 7' are denoted by M7 and M7', respectively. Each first noise reduction sub-circuit comprises a tenth transistor; the tenth transistors in the two first noise reduction sub-circuits 8 / 8' are denoted by M10 and M10', respectively. Each second noise reduction sub-circuit comprises a thirteenth transistor; the thirteenth transistors in the two second noise reduction sub-circuits 9 / 9' are denoted by M13 and M13', respectively. Each third noise reduction sub-circuit comprises a twelfth transistor; the twelfth transistors in the two third noise reduction sub-circuits 10 / 10' are denoted by M12 and M12', respectively. Each first auxiliary sub-circuit comprises a seventeenth transistor; the seventeenth transistors in the two first auxiliary sub-circuits 13 / 13' are denoted by M17 and M17', respectively.

[0114] Further, the gate and source of M1 are connected with a signal input end Input, and the drain of M1 is connected with a pull-up node PU. The gate of M2 is connected with a reset signal end Reset, the source of M2 is connected with the pull-up node PU, and the drain of M2 is connected with a first low voltage signal end LVGL. The gate of M4 is connected with the reset signal end Reset, the source of M4 is connected with a signal output end G_out, and the drain of M4 is connected with a second low voltage signal end VGL. The gate of M3 is connected with the pull-up node PU, the source of M3 is connected with a clock signal end CLK, and the drain of M3 is connected with the signal output end G_out. The gate of M11 is connected with the pull-up node PU, the source of M11 is connected with the clock signal end CLK, and the drain of M11 is connected with a cascade signal end OC. The first end of C1 is connected with the pull-up node PU, and the second end of C1 is connected with the signal output end G_out. The gate and source of M5 are both connected with a first power voltage end VDD1, and the drain of M5 is connected with a first pull-down node PD1. The gate and source of M5' are both connected with a second power voltage end VDD2, and the drain of M5 is connected with a second pull-down node PD2. The gate of M6 is connected with the pull-up node PU, the source of M6 is connected with a first pull-up node PU, and the drain of M6 is connected with the first low voltage signal end LVGL. The gate of M6' is connected with the pull-up node PU, the source of M6' is connected with a second pull-up node PU, and the drain of M6' is connected with the first low voltage signal end LVGL. The gate of M7 is connected with the signal input end Input, the source of M7 is connected with the first pull-up node PU, and the drain of M7 is connected with the first low voltage signal end LVGL. The gate of M7' is connected with the signal input end Input, the source of M7' is connected with the second pull-up node PU, and the drain of M7' is connected with the first low voltage signal end LVGL. The gate of M10 is connected with the first pull-down node PD1, the source of M10 is connected with the pull-up node PU, and the drain of M10 is connected with the first low voltage signal end LVGL. The gate of M10' is connected with the second pull-down node PD2, the source of M10' is connected with the pull-up node PU, and the drain of M10' is connected with the first low voltage signal end LVGL. The gate of M12 is connected with the first pull-down node PD1, the source of M12 is connected with the cascade signal end OC, and the drain of M12 is connected with the first low voltage signal end LVGL. The gate of M12' is connected with the second pull-down node PD2, the source of M12' is connected with the cascade signal end OC, and the drain of M12' is connected with the first low voltage signal end LVGL. The gate of M13 is connected with the first pull-down node PD1, the source of M13 is connected with the signal output end G_out, and the drain of M13 is connected with the second low voltage signal end VGL. The gate of M13' is connected with the second pull-down node PD2, the source of M13' is connected with the signal output end G_out, and the drain of M13' is connected with the first low voltage signal end LVGL. The gate of M14 is connected with a second global reset signal end Total_RST, the source of M14 is connected with the signal output end G_out, and the drain of M14 is connected with the second low voltage signal end VGL.The gate of the M15 is connected with the first global reset signal terminal Total_RST1, the source of the M15 is connected with the signal output terminal G_out, and the drain of the M15 is connected with the first low level signal terminal LVGL. The gate of the M17 is connected with the first control signal terminal Total_RST2, the source of the M17 is connected with the first pull-down node PD1, and the drain of the M17 is connected with the first low level signal terminal LVGL. The gate of the M17' is connected with the first control signal terminal Total_RST2, the source of the M17' is connected with the first pull-down node PD1, and the drain of the M17' is connected with the first low level signal terminal LVGL.

[0115] Fig. 5 is a timing diagram corresponding to the shift register shown in Fig. 4. As shown in Fig. 5, the operation of the shift register can include the following stages:

[0116] The discharge stage, before the frame, that is, before the display, the first global reset signal terminal Total_RST1 and the second global reset signal terminal Total_RST are input with high level signals, the M14 and the M15 are opened, the first low level signal input through the first low level signal terminal LVGL is used to discharge the pull-up node PU and the signal output terminal G_out, so as to prevent the residual charge of the pull-up node PU and the signal output terminal G_out from causing display abnormality. The first control signal terminal Total_RST2 is written with a high level signal, the M17 and the M17' are opened, and the first low level signal input through the first low level signal terminal LVGL is used to discharge the first pull-down node PD1 and the second pull-down node PD2.

[0117] The input stage, the signal input terminal Input is input with a high level signal, the M1 is opened, the pull-up node PU is pulled up through the high level signal, and C1 is charged at the same time, meanwhile, the M6 and the M6', the M7 and the M7' are opened, the first pull-down node PD1 and the second pull-down node PD2 are pulled down, so as to avoid affecting the potential of the pull-up node PU.

[0118] The output stage, since the pull-up node PU is pulled up in the input stage, the M3 and the M13 are opened, the high level signal input through the clock signal terminal CLK is output to the gate line connected therewith through the signal output terminal G_out, at the same time, the cascade signal terminal OC outputs the same signal as the signal output terminal G_out, that is, outputs a high level signal to the pull-up reset signal terminal Reset of the previous shift register unit and the signal input terminal Input of the next shift register unit.

[0119] In the reset stage, a high-level signal is input to the reset signal end Reset, M2 and M4 are turned on, and the potential of the pull-up node PU and the signal output end G_out is pulled low by the first low-level signal input by the first low-level signal end LVGL, so as to reset the pull-up node PU and the signal output end G_out. At the same time, the pull-down control node and the first pull-down node PD1 are high-level signals, M10, M13 and M12 are turned on, and the outputs of the pull-up node PU, the signal output end G_out and the cascade signal end OC are respectively de-noised until the potential of the pull-up node PU is pulled high at the start of the next frame scanning.

[0120] The second example is shown in FIG. 6, which is a circuit diagram of a shift register according to the second example of the embodiment of the present disclosure. As shown in FIG. 6, the structure of this example is substantially the same as that of the first example, and the only difference is that in this example, the first global reset signal input to the first global reset signal end Total_RST1 is multiplexed as the first control signal, that is, both of the two first auxiliary sub-circuits 13 / 13' are connected to the first global reset signal end Total_RST1.

[0121] Specifically, referring to FIG. 6, the input sub-circuit 1 includes a first transistor M1. The first reset sub-circuit 21 includes a second transistor M2. The second reset sub-circuit includes a fourth transistor M4. The output sub-circuit 3 includes a third transistor M3 and a storage capacitor C1. The cascade sub-circuit 4 includes an eleventh transistor M11. The first global reset sub-circuit 11 includes a fifteenth transistor M15. The second global reset sub-circuit 12 includes a fourteenth transistor M14. Each pull-down control sub-circuit includes a fifth transistor; the fifth transistors in the two pull-down control sub-circuits 5 / 5' are denoted by M5 and M5', respectively. Each first pull-down sub-circuit includes a sixth transistor; the sixth transistors in the two first pull-down sub-circuits 6 / 6' are denoted by M6 and M6', respectively. Each first pull-down sub-circuit includes a sixth transistor; the seventh transistors in the two second pull-down sub-circuits 7 / 7' are denoted by M7 and M7', respectively. Each first de-noising sub-circuit includes a tenth transistor; the tenth transistors in the two first de-noising sub-circuits 8 / 8' are denoted by M10 and M10', respectively. Each second de-noising sub-circuit includes a thirteenth transistor; the thirteenth transistors in the two second de-noising sub-circuits 9 / 9' are denoted by M13 and M13', respectively. Each third de-noising sub-circuit includes a tenth transistor; the twelfth transistors in the two third de-noising sub-circuits 10 / 10' are denoted by M12 and M12', respectively. Each first auxiliary sub-circuit includes a seventeenth transistor; the seventeenth transistors in the two first auxiliary sub-circuits 13 / 13' are denoted by M17 and M17', respectively.

[0122] Further, the gate and source of M1 are connected with a signal input end Input, and the drain of M1 is connected with a pull-up node PU. The gate of M2 is connected with a reset signal end Reset, the source of M2 is connected with the pull-up node PU, and the drain of M2 is connected with a first low voltage signal end LVGL. The gate of M4 is connected with the reset signal end Reset, the source of M4 is connected with a signal output end G_out, and the drain of M4 is connected with a second low voltage signal end VGL. The gate of M3 is connected with the pull-up node PU, the source of M3 is connected with a clock signal end CLK, and the drain of M3 is connected with the signal output end G_out. The gate of M11 is connected with the pull-up node PU, the source of M11 is connected with the clock signal end CLK, and the drain of M11 is connected with a cascade signal end OC. The first end of C1 is connected with the pull-up node PU, and the second end of C1 is connected with the signal output end G_out. The gate and source of M5 are both connected with a first power voltage end VDD1, and the drain of M5 is connected with a first pull-down node PD1. The gate and source of M5' are both connected with a second power voltage end VDD2, and the drain of M5 is connected with a second pull-down node PD2. The gate of M6 is connected with the pull-up node PU, the source of M6 is connected with a first pull-up node PU, and the drain of M6 is connected with the first low voltage signal end LVGL. The gate of M6' is connected with the pull-up node PU, the source of M6' is connected with a second pull-up node PU, and the drain of M6' is connected with the first low voltage signal end LVGL. The gate of M7 is connected with the signal input end Input, the source of M7 is connected with the first pull-up node PU, and the drain of M7 is connected with the first low voltage signal end LVGL. The gate of M7' is connected with the signal input end Input, the source of M7' is connected with the second pull-up node PU, and the drain of M7' is connected with the first low voltage signal end LVGL. The gate of M10 is connected with the first pull-down node PD1, the source of M10 is connected with the pull-up node PU, and the drain of M10 is connected with the first low voltage signal end LVGL. The gate of M10' is connected with the second pull-down node PD2, the source of M10' is connected with the pull-up node PU, and the drain of M10' is connected with the first low voltage signal end LVGL. The gate of M12 is connected with the first pull-down node PD1, the source of M12 is connected with the cascade signal end OC, and the drain of M12 is connected with the first low voltage signal end LVGL. The gate of M12' is connected with the second pull-down node PD2, the source of M12' is connected with the cascade signal end OC, and the drain of M12' is connected with the first low voltage signal end LVGL. The gate of M13 is connected with the first pull-down node PD1, the source of M13 is connected with the signal output end G_out, and the drain of M13 is connected with the second low voltage signal end VGL. The gate of M13' is connected with the second pull-down node PD2, the source of M13' is connected with the signal output end G_out, and the drain of M13' is connected with the first low voltage signal end LVGL. The gate of M14 is connected with a second global reset signal end Total_RST, the source of M14 is connected with the signal output end G_out, and the drain of M14 is connected with the second low voltage signal end VGL.The gate of the M15 is connected with the first global reset signal terminal Total_RST1, the source of the M15 is connected with the signal output terminal G_out, and the drain of the M15 is connected with the first low level signal terminal LVGL. The gate of the M17 is connected with the first global reset signal terminal Total_RST1, the source of the M17 is connected with the first pull-down node PD1, and the drain of the M17 is connected with the first low level signal terminal LVGL. The gate of the M17' is connected with the first global reset signal terminal Total_RST1, the source of the M17' is connected with the first pull-down node PD1, and the drain of the M17' is connected with the first low level signal terminal LVGL.

[0123] Fig. 7 is a timing diagram corresponding to the shift register shown in Fig. 6. As shown in Fig. 7, the operation of the shift register can include the following stages:

[0124] The discharging stage: before the frame, i.e. before the display, the high level signal is input to the first global reset signal terminal Total_RST1 and the second global reset signal terminal Total_RST, the M14 and the M15 are opened, the first low level signal input through the first low level signal terminal LVGL is used to discharge the pull-up node PU and the signal output terminal G_out, so as to prevent the residual charge of the pull-up node PU and the signal output terminal G_out from causing the display abnormality. At the same time, since the high level signal is written to the first global reset signal terminal Total_RST1, the M17 and the M17' are opened, and the first low level signal input through the first low level signal terminal LVGL is used to discharge the first pull-down node PD1 and the second pull-down node PD2.

[0125] The input stage: the high level signal is input to the signal input terminal Input, the M1 is opened, the pull-up node PU is pulled up through the high level signal, and C1 is charged, at the same time, the M6 and the M6', the M7 and the M7' are opened, the first pull-down node PD1 and the second pull-down node PD2 are pulled down, so as to avoid affecting the potential of the pull-up node PU.

[0126] The output stage: since the pull-up node PU is pulled up in the input stage, the M3 and the M13 are opened, the high level signal input through the clock signal terminal CLK is output to the gate line connected therewith through the signal output terminal G_out, at the same time, the cascade signal terminal OC outputs the same signal as the signal output terminal G_out, i.e. outputs the high level signal to the pull-up reset signal terminal Reset of the previous shift register unit and the signal input terminal Input of the next shift register unit.

[0127] In the reset stage, a high-level signal is input to the reset signal terminal Reset, M2 and M4 are turned on, a first low-level signal input through the first low-level signal terminal LVGL is used to pull down the potential of the pull-up node PU and the signal output terminal G_out, so as to reset the pull-up node PU and the signal output terminal G_out. At the same time, the pull-down control node and the first pull-down node PD1 are high-level signals, M10, M13 and M12 are turned on, and the output of the pull-up node PU, the signal output terminal G_out and the cascade signal terminal OC is respectively de-noised until the potential of the pull-up node PU is pulled up at the start of the next frame scanning.

[0128] The third example: FIG. 8 is a circuit diagram of a shift register of the third example of the embodiment of the present disclosure; as shown in FIG. 8, the structure of the first example in this example is substantially the same, the difference is only that the frame start signal in the gate driving circuit is used as the first control signal, for example: the input signal of the first to fourth stage shift registers in the gate driving circuit is provided by the frame start signal terminal STV, at this time when the input signal of the first to fourth stage shift registers is written to high level, the first auxiliary sub-circuit in each stage of the shift register will work at this time, and the first pull-down node PD1 and the second pull-down node PD2 are pulled down and discharged. That is, the first auxiliary sub-circuit of the shift register in this example is connected to the frame start signal terminal STV.

[0129] Specifically, referring to FIG. 8, the input sub-circuit 1 includes a first transistor M1. The first reset sub-circuit 21 includes a second transistor M2. The second reset sub-circuit 22 includes a fourth transistor M4. The output sub-circuit 3 includes a third transistor M3 and a storage capacitor C1. The cascade sub-circuit 4 includes an eleventh transistor M11. The first global reset sub-circuit 11 includes a fifteenth transistor M15. The second global reset sub-circuit 12 includes a fourteenth transistor M14. Each pull-down control sub-circuit includes a fifth transistor; the fifth transistors in the two pull-down control sub-circuits 5 / 5' are denoted by M5 and M5', respectively. Each first pull-down sub-circuit includes a sixth transistor; the sixth transistors in the two first pull-down sub-circuits 6 / 6' are denoted by M6 and M6', respectively. Each first pull-down sub-circuit includes a seventh transistor; the seventh transistors in the two second pull-down sub-circuits 7 / 7' are denoted by M7 and M7', respectively. Each first noise reduction sub-circuit includes a tenth transistor; the tenth transistors in the two first noise reduction sub-circuits 8 / 8' are denoted by M10 and M10', respectively. Each second noise reduction sub-circuit includes a thirteenth transistor; the thirteenth transistors in the two second noise reduction sub-circuits 9 / 9' are denoted by M13 and M13', respectively. Each third noise reduction sub-circuit includes a twelfth transistor; the twelfth transistors in the two third noise reduction sub-circuits 10 / 10' are denoted by M12 and M12', respectively. Each first auxiliary sub-circuit includes a seventeenth transistor; the seventeenth transistors in the two first auxiliary sub-circuits 13 / 13' are denoted by M17 and M17', respectively.

[0130] Further, the gate and source of M1 are connected with a signal input end Input, and the drain of M1 is connected with a pull-up node PU. The gate of M2 is connected with a reset signal end Reset, the source of M2 is connected with the pull-up node PU, and the drain of M2 is connected with a first low voltage signal end LVGL. The gate of M4 is connected with the reset signal end Reset, the source of M4 is connected with a signal output end G_out, and the drain of M4 is connected with a second low voltage signal end VGL. The gate of M3 is connected with the pull-up node PU, the source of M3 is connected with a clock signal end CLK, and the drain of M3 is connected with the signal output end G_out. The gate of M11 is connected with the pull-up node PU, the source of M11 is connected with the clock signal end CLK, and the drain of M11 is connected with a cascade signal end OC. The first end of C1 is connected with the pull-up node PU, and the second end of C1 is connected with the signal output end G_out. The gate and source of M5 are both connected with a first power voltage end VDD1, and the drain of M5 is connected with a first pull-down node PD1. The gate and source of M5' are both connected with a second power voltage end VDD2, and the drain of M5 is connected with a second pull-down node PD2. The gate of M6 is connected with the pull-up node PU, the source of M6 is connected with a first pull-up node PU, and the drain of M6 is connected with the first low voltage signal end LVGL. The gate of M6' is connected with the pull-up node PU, the source of M6' is connected with a second pull-up node PU, and the drain of M6' is connected with the first low voltage signal end LVGL. The gate of M7 is connected with the signal input end Input, the source of M7 is connected with the first pull-up node PU, and the drain of M7 is connected with the first low voltage signal end LVGL. The gate of M7' is connected with the signal input end Input, the source of M7' is connected with the second pull-up node PU, and the drain of M7' is connected with the first low voltage signal end LVGL. The gate of M10 is connected with the first pull-down node PD1, the source of M10 is connected with the pull-up node PU, and the drain of M10 is connected with the first low voltage signal end LVGL. The gate of M10' is connected with the second pull-down node PD2, the source of M10' is connected with the pull-up node PU, and the drain of M10' is connected with the first low voltage signal end LVGL. The gate of M12 is connected with the first pull-down node PD1, the source of M12 is connected with the cascade signal end OC, and the drain of M12 is connected with the first low voltage signal end LVGL. The gate of M12' is connected with the second pull-down node PD2, the source of M12' is connected with the cascade signal end OC, and the drain of M12' is connected with the first low voltage signal end LVGL. The gate of M13 is connected with the first pull-down node PD1, the source of M13 is connected with the signal output end G_out, and the drain of M13 is connected with the first low voltage signal end LVGL. The gate of M13' is connected with the second pull-down node PD2, the source of M13' is connected with the signal output end G_out, and the drain of M13' is connected with the second low voltage signal end VGL. The gate of M14 is connected with a second global reset signal end Total_RST, the source of M14 is connected with the signal output end G_out, and the drain of M14 is connected with the second low voltage signal end VGL.The gate of the M15 is connected with the first global reset signal terminal Total_RST1, the source of the M15 is connected with the signal output terminal G_out, and the drain of the M15 is connected with the first low voltage signal terminal LVGL. The gate of the M17 is connected with the frame start signal terminal STV, the source of the M17 is connected with the first pull-down node PD1, and the drain of the M17 is connected with the first low voltage signal terminal LVGL. The gate of the M17' is connected with the frame start signal terminal STV, the source of the M17' is connected with the first pull-down node PD1, and the drain of the M17' is connected with the first low voltage signal terminal LVGL.

[0131] As shown in FIG. 7, the operation of the shift register can include the following stages:

[0132] In the discharging stage, high level signals are input to the first global reset signal terminal Total_RST1 and the second global reset signal terminal Total_RST before a frame, i.e. before display, the M14 and the M15 are opened, and the first low voltage signal input through the first low voltage signal terminal LVGL is used to discharge the pull-up node PU and the signal output terminal G_out, so as to prevent the pull-up node PU and the signal output terminal G_out from causing display abnormality due to residual charge.

[0133] In the input stage, a high level signal is input to the signal input terminal Input, the M1 is opened, the pull-up node PU is pulled up by the high level signal, and C1 is charged at the same time, meanwhile, the M6 and the M6', the M7 and the M7' are opened, the first pull-down node PD1 and the second pull-down node PD2 are pulled down, so as to avoid affecting the potential of the pull-up node PU. At the same time, since the signal input terminal Input (i.e. the frame start signal terminal STV of the first to fourth stage shift register) inputs a high level signal to write a high level signal, the M17 and the M17' are opened, and the first low voltage signal input through the first low voltage signal terminal LVGL is used to discharge the first pull-down node PD1 and the second pull-down node PD2.

[0134] In the output stage, since the pull-up node PU is pulled up in the input stage, the M3 and the M13 are opened, the high level signal input through the clock signal terminal CLK is output to the gate line connected therewith through the signal output terminal G_out, at the same time, the cascade signal terminal OC outputs the same signal as the signal output terminal G_out, i.e. outputs a high level signal to the pull-up reset signal terminal Reset of the previous stage shift register unit and the signal input terminal Input of the next stage shift register unit.

[0135] In the reset stage, a high-level signal is input to the reset signal terminal Reset, M2 and M4 are turned on, and the potential of the pull-up node PU and the signal output terminal G_out is pulled low by the first low-level signal input from the first low-level signal terminal LVGL, so as to reset the pull-up node PU and the signal output terminal G_out. At the same time, the pull-down control node and the first pull-down node PD1 are high-level signals, M10, M13 and M12 are turned on, and the outputs of the pull-up node PU, the signal output terminal G_out and the cascade signal terminal OC are respectively de-noised until the potential of the pull-up node PU is pulled high at the start of the next frame scanning.

[0136] The fourth example: Fig. 9 is a circuit diagram of a shift register of the fourth example of the embodiment of the present disclosure; as shown in Fig. 9, the structure of this example is substantially the same as that of the first example, and the difference is only that in this example, one of the first auxiliary sub-circuits is controlled by the first voltage supply terminal, and the other first auxiliary sub-circuit is controlled by the second power supply voltage terminal VDD2. Specifically, since the two pull-down control sub-circuits 5 / 5' in the embodiment of the present disclosure work alternately, for example, one pull-down control sub-circuit works in an odd frame, and the other pull-down control sub-circuit works in an even frame. When the pull-down control sub-circuit works, the power supply voltage connected thereto is converted from low level to high level. In this example, one of the first auxiliary sub-circuits is controlled by the first pull-down node PD1, and the first low-level signal input from the first low-level signal terminal LVGL is used to discharge the second pull-down node PD2, and the other first auxiliary sub-circuit is controlled by the second pull-down node PD2, and the first low-level signal input from the first low-level signal terminal LVGL is used to discharge the first pull-down node PD1. The pull-up of the first pull-down node PD1 depends on the first power supply voltage, and the pull-up of the second pull-down node PD2 depends on the second power supply voltage. In this way, when the first power supply voltage terminal VDD1 inputs a high level, the second pull-down node PD2 is discharged, and when the second power supply voltage terminal VDD2 inputs a high level, the first pull-down node PD1 is discharged.

[0137] Specifically, with reference to FIG. 10, the input sub-circuit 1 includes a first transistor M1. The first reset sub-circuit 21 includes a second transistor M2. The second reset sub-circuit 22 includes a fourth transistor M4. The output sub-circuit 3 includes a third transistor M3 and a storage capacitor C1. The cascade sub-circuit 4 includes an eleventh transistor M11. The first global reset sub-circuit 11 includes a fifteenth transistor M15. The second global reset sub-circuit 12 includes a fourteenth transistor M14. Each pull-down control sub-circuit includes a fifth transistor; the fifth transistors in the two pull-down control sub-circuits 5 / 5' are denoted by M5 and M5', respectively. Each first pull-down sub-circuit includes a sixth transistor; the sixth transistors in the two first pull-down sub-circuits 6 / 6' are denoted by M6 and M6', respectively. Each first pull-down sub-circuit includes a seventh transistor; the seventh transistors in the two second pull-down sub-circuits 7 / 7' are denoted by M7 and M7', respectively. Each first noise reduction sub-circuit includes a tenth transistor; the tenth transistors in the two first noise reduction sub-circuits 8 / 8' are denoted by M10 and M10', respectively. Each second noise reduction sub-circuit includes a thirteenth transistor; the thirteenth transistors in the two second noise reduction sub-circuits 9 / 9' are denoted by M13 and M13', respectively. Each third noise reduction sub-circuit includes a twelfth transistor; the twelfth transistors in the two third noise reduction sub-circuits 10 / 10' are denoted by M12 and M12', respectively. Each first auxiliary sub-circuit includes a seventeenth transistor; the seventeenth transistors in the two first auxiliary sub-circuits 13 / 13' are denoted by M17 and M17', respectively.

[0138] Further, the gate and source of M1 are connected with a signal input end Input, and the drain of M1 is connected with a pull-up node PU. The gate of M2 is connected with a reset signal end Reset, the source of M2 is connected with the pull-up node PU, and the drain of M2 is connected with a first low voltage signal end LVGL. The gate of M4 is connected with the reset signal end Reset, the source of M4 is connected with a signal output end G_out, and the drain of M4 is connected with a second low voltage signal end VGL. The gate of M3 is connected with the pull-up node PU, the source of M3 is connected with a clock signal end CLK, and the drain of M3 is connected with the signal output end G_out. The gate of M11 is connected with the pull-up node PU, the source of M11 is connected with the clock signal end CLK, and the drain of M11 is connected with a cascade signal end OC. The first end of C1 is connected with the pull-up node PU, and the second end of C1 is connected with the signal output end G_out. The gate and source of M5 are both connected with a first power voltage end VDD1, and the drain of M5 is connected with a first pull-down node PD1. The gate and source of M5' are both connected with a second power voltage end VDD2, and the drain of M5 is connected with a second pull-down node PD2. The gate of M6 is connected with the pull-up node PU, the source of M6 is connected with a first pull-up node PU, and the drain of M6 is connected with the first low voltage signal end LVGL. The gate of M6' is connected with the pull-up node PU, the source of M6' is connected with a second pull-up node PU, and the drain of M6' is connected with the first low voltage signal end LVGL. The gate of M7 is connected with the signal input end Input, the source of M7 is connected with the first pull-up node PU, and the drain of M7 is connected with the first low voltage signal end LVGL. The gate of M7' is connected with the signal input end Input, the source of M7' is connected with the second pull-up node PU, and the drain of M7' is connected with the first low voltage signal end LVGL. The gate of M10 is connected with the first pull-down node PD1, the source of M10 is connected with the pull-up node PU, and the drain of M10 is connected with the first low voltage signal end LVGL. The gate of M10' is connected with the second pull-down node PD2, the source of M10' is connected with the pull-up node PU, and the drain of M10' is connected with the first low voltage signal end LVGL. The gate of M12 is connected with the first pull-down node PD1, the source of M12 is connected with the cascade signal end OC, and the drain of M12 is connected with the first low voltage signal end LVGL. The gate of M12' is connected with the second pull-down node PD2, the source of M12' is connected with the cascade signal end OC, and the drain of M12' is connected with the first low voltage signal end LVGL. The gate of M13 is connected with the first pull-down node PD1, the source of M13 is connected with the signal output end G_out, and the drain of M13 is connected with the first low voltage signal end LVGL. The gate of M13' is connected with the second pull-down node PD2, the source of M13' is connected with the signal output end G_out, and the drain of M13' is connected with the second low voltage signal end VGL. The gate of M14 is connected with a second global reset signal end Total_RST, the source of M14 is connected with the signal output end G_out, and the drain of M14 is connected with the second low voltage signal end VGL.The gate of the M15 is connected with the first global reset signal terminal Total_RST1, the source of the M15 is connected with the signal output terminal G_out, and the drain of the M15 is connected with the first low level signal terminal LVGL. The gate of the M17 is connected with the first pull-down node PD1, the source of the M17 is connected with the first pull-down node PD1, and the drain of the M17 is connected with the first low level signal terminal LVGL. The gate of the M17' is connected with the second pull-down node PD2, the source of the M17' is connected with the first pull-down node PD1, and the drain of the M17' is connected with the first low level signal terminal LVGL.

[0139] When the first power voltage written by the first power voltage terminal VDD1 of the shift register is switched from low level to high level, the M17 is opened, and the second pull-down node PD2 is discharged by the first low level signal. When the second power voltage written by the second power voltage terminal VDD2 of the shift register is switched from low level to high level, the M17' is opened, and the first pull-down node PD1 is discharged by the first low level signal. In this way, the inconsistency of the signal output terminal G_out to the first low level signal after the first power voltage and the second power voltage are switched can be avoided, and the TP Noise caused by the difference of the IC collected different frames of Raw data can be prevented.

[0140] As shown in FIG. 11, the operation of the shift register can include the following stages:

[0141] The discharge stage: before the frame, that is, before the display, a high level signal is input to the first global reset signal terminal Total_RST1 and the second global reset signal terminal Total_RST, the fourteenth transistor and the fifteenth transistor are opened, the pull-up node PU and the signal output terminal G_out are discharged by the first low level signal input by the first low level signal terminal LVGL, and the residual charge of the pull-up node PU and the signal output terminal G_out is prevented from causing display abnormalities.

[0142] The input stage: a high level signal is input to the signal input terminal Input, the M1 is opened, the pull-up node PU is pulled up by the high level signal, and C1 is charged at the same time. At the same time, the M6 and the M6', the M7 and the M7' are opened, the first pull-down node PD1 and the second pull-down node PD2 are pulled down, so as to avoid affecting the potential of the pull-up node PU.

[0143] In the output stage, since the pull-up node PU is pulled high in the input stage, M3 and M13 are opened, and the high level signal input from the clock signal end CLK is output to the gate line connected with the signal output end G_out, at the same time, the cascade signal end OC outputs the same signal as the signal output end G_out, that is, outputs the high level signal to the pull-up reset signal end Reset of the previous stage shift register unit and the signal input end Input of the next stage shift register unit.

[0144] In the reset stage, the high level signal is input to the reset signal end Reset, M2 and M4 are opened, and the first low level signal input from the first low level signal end LVGL pulls down the potential of the pull-up node PU and the signal output end G_out, so as to reset the pull-up node PU and the signal output end G_out. At the same time, the pull-down control node and the first pull-down node PD1 are high level signals, M10, M13 and M12 are opened, and the output of the pull-up node PU, the signal output end G_out and the cascade signal end OC is respectively noise reduced until the potential of the pull-up node PU is pulled high at the beginning of the next frame scanning.

[0145] The fifth example is shown in FIG. 10, which is a circuit diagram of the shift register of the fifth example of the embodiment of the present disclosure. As shown in FIG. 10, the shift register comprises an input sub-circuit 1, an output sub-circuit 3, two pull-down control sub-circuits 5 / 5', two first pull-down sub-circuits 6 / 6', and a second auxiliary sub-circuit 14. The input sub-circuit 1 is configured to pre-charge the pull-up node PU by the input signal of the signal input end Input in response to the input signal; the connection node between the input sub-circuit 1, the output sub-circuit 3 and the pull-down sub-circuit; the output sub-circuit 3 is configured to output the clock signal through the signal output end G_out in response to the potential of the pull-up node PU; the pull-down control sub-circuit is configured to control the potential of the pull-down node by the power voltage in response to the power voltage; one pull-down control sub-circuit is connected with one first pull-down sub-circuit, and the connection node between them is the pull-down node; the first pull-down sub-circuit is configured to pull down the potential of the pull-down node electrically connected therewith by the first low level signal in response to the potential of the pull-up node PU; and the second auxiliary sub-circuit 14 is configured to discharge the output of the signal output end G_out by the first low level signal in response to the touch enable signal.

[0146] In this example, by adding the second auxiliary sub-circuit 14, when the display panel enters the touch stage, the first auxiliary sub-circuit is controlled to work by the touch enable signal, and the pull-down signal output end G_out is discharged, so that the output of the signal output end G_out is consistent with the first low level signal, thereby avoiding the influence of the potential difference of the pull-down node on the output difference of the signal output end G_out of different frames.

[0147] Since the number of pull-down control sub-circuits and the first pull-down sub-circuit is two in this example, the number of pull-down nodes is also two, which are the first pull-down node PD1 and the second pull-down node PD2. The power voltage end connected to the pull-down control sub-circuit connected to the first pull-down node PD1 is referred to as the first power voltage end VDD1, and the power voltage end connected to the pull-down control sub-circuit connected to the second pull-down node PD2 is referred to as the second power voltage end VDD2.

[0148] In some examples, the two first auxiliary sub-circuits 13 / 13' can be connected to the same first control signal end Total_RST2, that is, the two first auxiliary sub-circuits 13 / 13' can be controlled at the same time, for example, before the current frame is scanned, the first control signal input through the first control signal end Total_RST2 controls the two first auxiliary sub-circuits 13 / 13' to work at the same time, and the first pull-down node PD1 and the second pull-down node PD2 are discharged, respectively.

[0149] In some examples, the shift register can further include a cascade sub-circuit 4, a reset sub-circuit 2, two second pull-down sub-circuits 7 / 7', two first noise reduction sub-circuits 8 / 8', two second noise reduction sub-circuits 9 / 9', and two third noise reduction sub-circuits 10 / 10', a first global reset sub-circuit 11, and a second global reset sub-circuit 12.

[0150] The first reset sub-circuit 21 is configured to reset the pull-up node PU through the first low-level signal under the control of the reset signal. The second reset sub-circuit 22 is configured to reset the signal output end G_out through the second low-level signal under the control of the reset signal. The cascade sub-circuit 4 is configured to output the clock signal through the cascade signal end OC in response to the potential of the pull-up node PU. The second pull-down sub-circuit is configured to pull down the potential of the pull-down node electrically connected thereto through the first low-level signal in response to the input signal. The first noise reduction sub-circuit is configured to reduce the output of the pull-up node PU under the control of the pull-down node connected thereto. The second noise reduction sub-circuit is configured to reduce the output of the signal output end G_out under the control of the pull-down node connected thereto. The third noise reduction sub-circuit is configured to reduce the output of the cascade signal end OC under the control of the pull-down node connected thereto. The first global reset sub-circuit 11 is configured to discharge the pull-up node PU through the first low-level signal in response to the first global reset signal. The second global reset sub-circuit 12 is configured to discharge the output of the signal output end G_out through the second low-level signal in response to the second global reset signal.

[0151] With reference to FIG. 10, two pull-down control sub-circuits 5 / 5', two first pull-down sub-circuits 6 / 6', two second pull-down sub-circuits 7 / 7', two first noise reduction sub-circuits 8 / 8', two second noise reduction sub-circuits 9 / 9', two third noise reduction sub-circuits 10 / 10', the pull-down control sub-circuit corresponds to connect a first pull-down sub-circuit and a second pull-down sub-circuit, and the connection node of the three is a first pull-down node PD1. The pull-down control sub-circuit corresponds to connect a first pull-down sub-circuit and a second pull-down sub-circuit, and the connection node of the three is a first pull-down node PD1PD2. The first pull-down node PD1 connects a first noise reduction sub-circuit, a second noise reduction sub-circuit and a third noise reduction sub-circuit 9, and the second pull-down node PD2 connects another first noise reduction sub-circuit, another second noise reduction sub-circuit and another third noise reduction sub-circuit. The structure and function of the two pull-down control sub-circuits 5 / 5' in the shift register are the same, but the two pull-down control sub-circuits 5 / 5' are time-sharing working when the shift register works, that is, the timing of the control signal for controlling the two pull-down control sub-circuits 5 / 5' is opposite. Similarly, the two first pull-down sub-circuits 6 / 6' have the same structure and function and are time-sharing working; the two second pull-down sub-circuits 7 / 7' have the same structure and function and are time-sharing working; the two first noise reduction sub-circuits 8 / 8' have the same structure and function and are time-sharing working; the two second noise reduction sub-circuits 9 / 9' have the same structure and function and are time-sharing working; and the two third noise reduction sub-circuits 10 / 10' have the same structure and function and are time-sharing working. The first global reset signal can adopt a frame pre-on signal to discharge the pull-up node PU before the current frame scanning.

[0152] Specifically, the input sub-circuit 1 comprises a first transistor M1. The reset sub-circuit 2 comprises a second transistor M2 and a fourth transistor M4. The output sub-circuit 3 comprises a third transistor M3 and a storage capacitor C1. The cascade sub-circuit 4 comprises an eleventh transistor M11. The first global reset sub-circuit 11 comprises a fifteenth transistor M15. The second global reset sub-circuit 12 comprises a fourteenth transistor M14. Each pull-down control sub-circuit comprises a fifth transistor; the fifth transistors in the two pull-down control sub-circuits 5 / 5' are denoted by M5 and M5', respectively. Each first pull-down sub-circuit comprises a sixth transistor; the sixth transistors in the two first pull-down sub-circuits 6 / 6' are denoted by M6 and M6', respectively. Each first pull-down sub-circuit comprises a seventh transistor; the seventh transistors in the two second pull-down sub-circuits 7 / 7' are denoted by M7 and M7', respectively. Each first noise reduction sub-circuit comprises a tenth transistor; the tenth transistors in the two first noise reduction sub-circuits 8 / 8' are denoted by M10 and M10', respectively. Each second noise reduction sub-circuit comprises a thirteenth transistor; the thirteenth transistors in the two second noise reduction sub-circuits 9 / 9' are denoted by M13 and M13', respectively. Each third noise reduction sub-circuit comprises a twelfth transistor; the twelfth transistors in the two third noise reduction sub-circuits 10 / 10' are denoted by M12 and M12', respectively. Each second auxiliary sub-circuit 14 comprises an eighteenth transistor M18.

[0153] Further, the gate and source of M1 are connected with a signal input end Input, and the drain of M1 is connected with a pull-up node PU. The gate of M2 is connected with a reset signal end Reset, the source of M2 is connected with the pull-up node PU, and the drain of M2 is connected with a first low voltage signal end LVGL. The gate of M4 is connected with the reset signal end Reset, the source of M4 is connected with a signal output end G_out, and the drain of M4 is connected with a second low voltage signal end VGL. The gate of M3 is connected with the pull-up node PU, the source of M3 is connected with a clock signal end CLK, and the drain of M3 is connected with the signal output end G_out. The gate of M11 is connected with the pull-up node PU, the source of M11 is connected with the clock signal end CLK, and the drain of M11 is connected with a cascade signal end OC. The first end of C1 is connected with the pull-up node PU, and the second end of C1 is connected with the signal output end G_out. The gate and source of M5 are both connected with a first power voltage end VDD1, and the drain of M5 is connected with a first pull-down node PD1. The gate and source of M5' are both connected with a second power voltage end VDD2, and the drain of M5 is connected with a second pull-down node PD2. The gate of M6 is connected with the pull-up node PU, the source of M6 is connected with a first pull-up node PU, and the drain of M6 is connected with the first low voltage signal end LVGL. The gate of M6' is connected with the pull-up node PU, the source of M6' is connected with a second pull-up node PU, and the drain of M6' is connected with the first low voltage signal end LVGL. The gate of M7 is connected with the signal input end Input, the source of M7 is connected with the first pull-up node PU, and the drain of M7 is connected with the first low voltage signal end LVGL. The gate of M7' is connected with the signal input end Input, the source of M7' is connected with the second pull-up node PU, and the drain of M7' is connected with the first low voltage signal end LVGL. The gate of M10 is connected with the first pull-down node PD1, the source of M10 is connected with the pull-up node PU, and the drain of M10 is connected with the first low voltage signal end LVGL. The gate of M10' is connected with the second pull-down node PD2, the source of M10' is connected with the pull-up node PU, and the drain of M10' is connected with the first low voltage signal end LVGL. The gate of M12 is connected with the first pull-down node PD1, the source of M12 is connected with the cascade signal end OC, and the drain of M12 is connected with the first low voltage signal end LVGL. The gate of M12' is connected with the second pull-down node PD2, the source of M12' is connected with the cascade signal end OC, and the drain of M12' is connected with the first low voltage signal end LVGL. The gate of M13 is connected with the first pull-down node PD1, the source of M13 is connected with the signal output end G_out, and the drain of M13 is connected with the first low voltage signal end LVGL. The gate of M13' is connected with the second pull-down node PD2, the source of M13' is connected with the signal output end G_out, and the drain of M13' is connected with the second low voltage signal end VGL. The gate of M14 is connected with a second global reset signal end Total_RST, the source of M14 is connected with the signal output end G_out, and the drain of M14 is connected with the second low voltage signal end VGL.The gate of the M15 is connected with the first global reset signal terminal Total_RST1, the source of the M15 is connected with the signal output terminal G_out, and the drain of the M15 is connected with the first low level signal terminal LVGL. The gate of the M18 is connected with the touch enable signal terminal, the source of the M18 is connected with the signal output terminal G_out, and the drain of the M18 is connected with the first low level signal terminal LVGL.

[0154] When the display panel enters the touch stage, the eighteenth transistor is controlled to be turned on by the touch enable signal, and the pull-down signal output terminal G_out is outputted, so that the output of the signal output terminal G_out is consistent with the first low level signal, thereby avoiding the influence of the potential difference of the pull-down node on the output difference of the signal output terminal G_out of different frames.

[0155] FIG. 11 is a timing diagram corresponding to the shift register shown in FIG. 10; as shown in FIG. 11, the operation of the shift register can include the following stages:

[0156] The discharge stage, before the frame, that is, before the display, the first global reset signal terminal Total_RST1 and the second global reset signal terminal Total_RST are inputted with high level signals, the fourteenth transistor and the fifteenth transistor are turned on, and the first low level signal inputted through the first low level signal terminal LVGL is used to discharge the pull-up node PU and the signal output terminal G_out, so as to prevent the residual charge of the pull-up node PU and the signal output terminal G_out from causing display abnormalities.

[0157] The input stage, the signal input terminal Input is inputted with a high level signal, the M1 is turned on, the pull-up node PU is pulled up through the high level signal, and C1 is charged at the same time, and the M6 and M6', the M7 and M7' are all turned on, so as to pull down the first pull-down node PD1 and the second pull-down node PD2, thereby avoiding affecting the potential of the pull-up node PU.

[0158] The output stage, since the pull-up node PU is pulled up in the input stage, the M3 and the M13 are turned on, the high level signal inputted through the clock signal terminal CLK is outputted to the gate line connected therewith through the signal output terminal G_out, at the same time, the cascade signal terminal OC outputs the same signal as the signal output terminal G_out, that is, outputs the high level signal to the pull-up reset signal terminal Reset of the previous shift register unit and the signal input terminal Input of the next shift register unit.

[0159] In the reset stage, a high-level signal is input to the reset signal terminal Reset, M2 and M4 are turned on, and the potential of the pull-up node PU and the signal output terminal G_out is pulled low by the first low-level signal input from the first low-level signal terminal LVGL, so as to reset the pull-up node PU and the signal output terminal G_out. At the same time, the pull-down control node and the first pull-down node PD1 are high-level signals, M10, M13 and M12 are turned on, and the output of the pull-up node PU, the signal output terminal G_out and the cascade signal terminal OC is respectively noise-reduced until the potential of the pull-up node PU is pulled high at the start of the next frame scanning.

[0160] Of course, for the first to fourth examples described above, a second auxiliary sub-circuit 14 can be added on the basis of any of the above-mentioned circuits. In the touch stage of the display panel, the eighteenth transistor is turned on by the touch enable signal to output a pull-down signal to the signal output terminal G_out, so that the output of the signal output terminal G_out is consistent with the first low-level signal, thereby avoiding the influence of the potential difference of the pull-down node on the output difference of the signal output terminal G_out of different frames. Referring to FIG. 11, in the touch stage, that is, the touch enable signal is a high-level signal, the signal output terminal G_out of the first row and the signal output terminal G_out of the tail row are both consistent with the first low-level signal.

[0161] The embodiments of the present disclosure provide a gate drive circuit, which can include any of the above-mentioned shift registers.

[0162] The embodiments of the present disclosure provide a display panel, which can include any of the above-mentioned gate drive circuits.

[0163] It can be understood that the above embodiments are only exemplary embodiments adopted for illustrating the principles of the present application, and the present application is not limited thereto. Various modifications and improvements can be made by those skilled in the art without departing from the spirit and essence of the present application, and these modifications and improvements are also considered to be within the protection scope of the present application.

Claims

1. A shift register, comprising an input sub-circuit, an output sub-circuit, at least one pull-down control sub-circuit, and at least one first pull-down sub-circuit; the input sub-circuit is configured to pre-charge a pull-up node by an input signal of a signal input terminal in response to the input signal; the pull-up node is a connection node between the input sub-circuit, the output sub-circuit and the first pull-down sub-circuit; the output sub-circuit is configured to output a clock signal through a signal output terminal in response to a potential of the pull-up node; the pull-down control sub-circuit is configured to control a potential of a pull-down node by a power supply voltage in response to the power supply voltage; one pull-down control sub-circuit is connected to one first pull-down sub-circuit, and a connection node therebetween is the pull-down node; the first pull-down sub-circuit is configured to pull down the potential of the pull-down node electrically connected thereto by a first non-working level signal in response to the potential of the pull-up node; wherein the shift register further comprises at least one first auxiliary sub-circuit, one first auxiliary sub-circuit is electrically connected to one pull-down node; the first auxiliary sub-circuit is configured to discharge the pull-down node electrically connected thereto under the control of a first control signal after the end of a touch phase.

2. The shift register of claim 1, wherein, the number of the pull-down control sub-circuit, the first pull-down sub-circuit and the first auxiliary sub-circuit is plural, and one pull-down node is electrically connected to one pull-down control sub-circuit, one first pull-down sub-circuit and one first auxiliary sub-circuit; each first auxiliary sub-circuit is electrically connected to the same first control signal terminal, and works simultaneously under the first control signal received by the first control signal terminal, and discharges the pull-down node corresponding thereto before the current frame scanning.

3. The shift register of claim 1, wherein, a first global reset sub-circuit is further included, and is configured to globally reset the pull-up node by a first non-working level signal under the control of a first global reset signal; the global reset signal is multiplexed as the first control signal.

4. The shift register of claim 3, wherein, the global reset sub-circuit comprises a fifteenth transistor; the first electrode of the fifteenth transistor is connected to the pull-up node, the second electrode is connected to the first non-working level signal terminal, and the control electrode is connected to the first global reset signal terminal and each first auxiliary sub-circuit.

5. The shift register of claim 4, wherein, the first auxiliary sub-circuit comprises a seventeenth transistor; the first electrode of the seventeenth transistor is connected to one pull-down node, the second electrode is connected to the first non-working level signal terminal, and the control electrode is connected to the first global reset signal terminal.

6. The shift register of claim 1, wherein, the frame start signal is multiplexed as the first control signal.

7. The shift register of claim 6, wherein, the first auxiliary sub-circuit comprises a seventeenth transistor; the first electrode of the seventeenth transistor is connected to one pull-down node, the second electrode is connected to the first non-working level signal terminal, and the control electrode is connected to the frame start signal terminal.

8. The shift register of claim 1, wherein, The number of the pull-down control sub-circuits, the first pull-down sub-circuits and the first auxiliary sub-circuits is two, the number of the pull-down nodes is two, the two pull-down nodes are a first pull-down node and a second pull-down node respectively, and the first pull-down node is electrically connected with one pull-down control sub-circuit, one first pull-down sub-circuit and one first auxiliary sub-circuit; the second pull-down node is electrically connected with another pull-down control sub-circuit, another first pull-down sub-circuit and another first auxiliary sub-circuit. The potential of the first pull-down node is multiplexed as a first control signal of a first auxiliary sub-circuit, and the second pull-down node is discharged by the first non-working level signal; the potential of the second pull-down node is multiplexed as a first control signal of another first auxiliary sub-circuit, and the first pull-down node is discharged by the first non-working level signal.

9. The shift register of any one of claim 8, wherein, The first auxiliary sub-circuit comprises a seventeenth transistor. The first electrode of the seventeenth transistor in one of the first auxiliary sub-circuits is connected with the first pull-down node, the second electrode is connected with a first non-working level signal terminal, and the control electrode is connected with the second pull-down node; the first electrode of the seventeenth transistor in another of the first auxiliary sub-circuits is connected with the first pull-down node, the second electrode is connected with a first non-working level signal terminal, and the control electrode is connected with the second pull-down node.

10. The shift register of claim 1, wherein, Further comprising a second auxiliary sub-circuit configured to discharge the output of the signal output terminal by the first non-working level signal in response to a touch enable signal.

11. The shift register of claim 10, wherein, The second auxiliary sub-circuit comprises an eighteenth transistor. The first electrode of the eighteenth transistor is connected with the signal output terminal, the second electrode is connected with a first non-working level signal terminal, and the control electrode is connected with a touch enable signal terminal.

12. The shift register of any one of claims 1-11, wherein, Further comprising at least one second pull-down sub-circuit, one of the second pull-down sub-circuits is electrically connected with one of the pull-down nodes; The second pull-down sub-circuit is configured to pull down the potential of the pull-down node electrically connected therewith by the first non-working level signal in response to an input signal.

13. The shift register of claim 12, wherein, The second pull-down sub-circuit comprises a seventh transistor; The first electrode of the seventh transistor is connected with the pull-down node corresponding thereto, the second electrode is connected with a first non-working level signal terminal, and the control electrode is connected with a signal input terminal.

14. The shift register of any one of claims 1-11, wherein, Further comprising: A first reset sub-circuit configured to reset the pull-up node by the first non-working level signal under the control of a reset signal A second reset sub-circuit configured to reset the signal output terminal by the second non-working level signal under the control of the reset signal.

15. The shift register of claim 14, wherein, The first reset sub-circuit comprises a second transistor; the second reset sub-circuit comprises a fourth transistor; The first electrode of the second transistor is connected with the pull-up node, the second electrode is connected with a first non-working level signal terminal, and the control electrode is connected with a reset signal terminal; The first electrode of the fourth transistor is connected with the signal output terminal, the second electrode is connected with a second non-working level signal terminal, and the control electrode is connected with a reset signal terminal.

16. The shift register of any one of claims 1-11, wherein, The shift register further comprises at least one first noise reduction sub-circuit and at least one second noise reduction sub-circuit; one of the pull-down nodes is electrically connected to one of the first noise reduction sub-circuit and one of the second noise reduction sub-circuit; The first noise reduction sub-circuit is configured to reduce noise of an output of the pull-up node by a first non-working level signal under control of the pull-down node electrically connected thereto; The second noise reduction sub-circuit is configured to reduce noise of an output of the signal output terminal by a second non-working level signal under control of the pull-down node electrically connected thereto.

17. The shift register of claim 16, wherein, The first noise reduction sub-circuit comprises a tenth transistor; the second noise reduction sub-circuit comprises a thirteenth transistor; The first electrode of the tenth transistor is connected to the pull-up node, the second electrode is connected to a first non-working level signal terminal, and the control electrode is connected to the pull-down node corresponding thereto; The first electrode of the thirteenth transistor is connected to the signal output terminal, the second electrode is connected to a second non-working level signal terminal, and the control electrode is connected to the pull-down node corresponding thereto.

18. The shift register of any one of claims 1-11, wherein, The shift register further comprises a cascade sub-circuit configured to output a clock signal through a cascade signal terminal in response to the potential of the pull-up node.

19. The shift register of claim 18, wherein, The cascade sub-circuit comprises an eleventh transistor; The first electrode of the eleventh transistor is connected to an always-on signal terminal, the second electrode is connected to the cascade signal terminal, and the control electrode is connected to the pull-up node.

20. The shift register of claim 18, wherein, The shift register further comprises a third noise reduction sub-circuit configured to reduce noise of an output of the cascade signal terminal by a first non-working level signal under control of the pull-down node electrically connected thereto.

21. The shift register of claim 20, wherein, The third noise reduction sub-circuit comprises a twelfth transistor; The first electrode of the twelfth transistor is connected to the cascade signal terminal, the second electrode is connected to a first non-working level signal terminal, and the control electrode is connected to the pull-down node corresponding thereto.

22. The shift register of any one of claims 1-11, wherein, The shift register further comprises a second global reset sub-circuit configured to discharge the signal output terminal by a second non-working level signal in response to a second global reset signal.

23. The shift register of claim 22, wherein, The second global reset sub-circuit comprises a fourteenth transistor; The first electrode of the fourteenth transistor is connected to the signal output terminal, the second electrode is connected to a second non-working level signal terminal, and the control electrode is connected to a second global reset signal terminal.

24. The shift register of any one of claims 1-11, wherein, The input sub-circuit comprises a first transistor; The first electrode and the control electrode of the first transistor are both connected to a signal input terminal, and the second electrode is connected to the pull-up node.

25. The shift register of any one of claims 1-11, wherein, The output sub-circuit comprises a third transistor and a storage capacitor; The first electrode of the third transistor is connected to a clock signal terminal, the second electrode is connected to the signal output terminal and the second end of the storage capacitor, and the control electrode is connected to the first end of the storage capacitor and the pull-up node.

26. The shift register of any one of claims 1-11, wherein, The pull-down control sub-circuit comprises a fifth transistor; The first electrode of the fifth transistor is connected to the control electrode and a power voltage terminal, and the second electrode is connected to the pull-down node corresponding thereto.

27. The shift register of any one of claims 1-11, wherein, The first pull-down sub-circuit comprises a sixth transistor; The first electrode of the sixth transistor is connected to the pull-down node corresponding thereto, the second electrode is connected to a non-working voltage terminal, and the control electrode is connected to the signal input terminal.

28. The shift register of any one of claims 1-11, wherein, Each sub-circuit in the shift register comprises at least a thin film transistor, and the thin film transistor is an oxide thin film transistor.

29. A shift register comprising an input sub-circuit, an output sub-circuit, at least one pull-down control sub-circuit, at least one first pull-down sub-circuit; the input sub-circuit is configured to pre-charge a pull-up node by an input signal of a signal input end in response to the input signal; a connection node between the input sub-circuit, the output sub-circuit and the pull-down sub-circuit; the output sub-circuit is configured to output a clock signal through a signal output end in response to a potential of the pull-up node; the pull-down control sub-circuit is configured to control a potential of a pull-down node by a power voltage in response to the power voltage; one of the pull-down control sub-circuit connects one of the first pull-down sub-circuit, and a connection node therebetween is the pull-down node; the first pull-down sub-circuit is configured to pull down the potential of the pull-down node electrically connected thereto by a first non-working level signal in response to the potential of the pull-up node; wherein, the shift register further comprises a second auxiliary sub-circuit configured to discharge the output of the signal output end by the first non-working level signal in response to a touch enable signal.

30. The shift register of claim 29, wherein, the input sub-circuit comprises a first transistor; the output sub-circuit comprises a third transistor and a storage capacitor; the pull-down control sub-circuit comprises a fifth transistor; the first pull-down sub-circuit comprises a sixth transistor; the second auxiliary sub-circuit comprises an eighteenth transistor; a first pole and a control pole of the first transistor are both connected to the signal input end, and a second pole is connected to the pull-up node; a first pole of the third transistor is connected to a clock signal end, a second pole is connected to the signal output end and a second end of the storage capacitor, and a control pole is connected to a first end of the storage capacitor and the pull-up node; a first pole of the fifth transistor is connected to its control pole and a power voltage end, and a second pole is connected to the pull-down node corresponding thereto; a first pole of the sixth transistor is connected to the pull-down node corresponding thereto, a second pole is connected to a non-working voltage end, and a control pole is connected to the signal input end; a first pole of the eighteenth transistor is connected to the signal output end, a second pole is connected to a first non-working level signal end, and a control pole is connected to a touch enable signal end.

31. A gate drive circuit comprising the shift register of any one of claims 1-30.

32. A display device comprising the gate drive circuit of claim 31.

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