Polar code decoding method and communication apparatus

Abstract

Provided in the present application are a polar code decoding method and a communication apparatus. The method comprises: obtaining a symbol sequence to be decoded; determining a first decoding result, the first decoding result being obtained by decoding the symbol sequence to be decoded; and, if the first decoding result does not pass verification, determining a second decoding result, wherein the second decoding result is obtained by decoding a first sequence, the first sequence is generated from the symbol sequence to be decoded and a perturbation sequence, and the perturbation sequence is related to the first decoding result. When the first decoding result of the symbol sequence to be decoded does not pass the verification, specific perturbation is applied to the symbol sequence to be decoded and re-decoding is performed, thus improving the polar code decoding performance.

Description

Polar code decoding method and communication device

[0001] This application claims priority to Chinese patent application No. 202410396267.0 filed with the State Intellectual Property Office of China on March 30, 2024, and priority to Chinese patent application entitled “Decoding method and communication device for polarization code”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present application relates to the field of communications, and more specifically, to a polar code decoding method and a communication device. Background Art

[0003] Polar code is the first channel coding method that can be rigorously proven to "reach" the channel capacity. In addition, polar code has a lower computational complexity in encoding and decoding. These advantages make polar code popular in the fifth generation (5 th generation, and has been widely used in 5G) communication systems.

[0004] For industrial applications, polar code decoding algorithms are particularly important. Professor Arikan demonstrated that polar codes can achieve high capacity at infinite code lengths using the successive cancellation decoding (SC) algorithm. However, with finite code lengths, the performance of the SC algorithm is unsatisfactory. To address this issue, the industry has proposed decoding algorithms such as the Successive Cancellation List (SCL) algorithm, the Successive Cancellation List (CA-SC List, CA-SCL) algorithm assisted by a cyclic redundancy check (CRC), and Successive Cancellation Flip (SC Flip or SCF) decoding. By perturbing the received symbols and re-decoding them when SCL decoding fails, performance gains can be achieved that do not decrease with increasing code length. This method can achieve performance twice or four times that of List with a smaller List decoder.

[0005] Therefore, how to further reduce the decoding complexity of polar codes and improve the decoding performance of polar codes is a problem that needs to be solved. Summary of the Invention

[0006] The present application provides a polar code decoding method and a communication device, which can improve decoding performance.

[0007] In a first aspect, a polar code decoding method is provided. The method includes: obtaining a symbol sequence to be decoded; determining a first decoding result, where the first decoding result is obtained by decoding the symbol sequence to be decoded; and if the first decoding result fails verification, determining a second decoding result, where the second decoding result is obtained by decoding a first sequence, where the first sequence is generated by the symbol sequence to be decoded and a perturbation sequence, and the perturbation sequence is related to the first decoding result.

[0008] Based on the above solution, when a first decoding result of a to-be-decoded symbol sequence fails verification, a specific perturbation is applied to the to-be-decoded symbol sequence and re-decoded. That is, a first sequence is determined based on the to-be-decoded symbol sequence and a perturbation sequence, and the first sequence is decoded to generate a second decoding result. The perturbation sequence is related to the first decoding result. This can improve the decoding performance of polar codes.

[0009] In combination with the first aspect, in certain implementations of the first aspect, the first decoding result includes L candidate decoding results, where L is a positive integer. Before obtaining the second decoding result, the method further includes: generating the perturbation sequence based on at least one candidate decoding result among the L candidate decoding results.

[0010] In combination with the first aspect, in certain implementations of the first aspect, generating the perturbation sequence based on at least one candidate decoding result among the L candidate decoding results includes: generating the perturbation sequence based on an lth candidate decoding result among the L candidate decoding results, the path metric value corresponding to the lth candidate decoding result being less than the path metric values ​​corresponding to candidate decoding results other than the lth candidate decoding result among the L candidate decoding results; or, generating the perturbation sequence based on the L candidate decoding results; or, generating the perturbation sequence based on any one or more candidate decoding results among the L candidate decoding results.

[0011] Based on the above solution, by generating the perturbation sequence based on the lth candidate decoding result, decoding performance can be improved. At the same time, selecting the lth candidate decoding result from the L candidate decoding results to generate the perturbation sequence can reduce implementation complexity. Generating the perturbation sequence based on the L candidate decoding results can make the perturbation sequence more targeted, thereby improving decoding performance.

[0012] In combination with the first aspect, in certain implementations of the first aspect, the first decoding result is obtained by performing a k-th decoding of the to-be-decoded symbol sequence, where k is an integer greater than or equal to 1, and the generating the perturbation sequence based on at least one candidate decoding result among the L candidate decoding results includes: generating the perturbation sequence based on the first decoding result and candidate decoding results obtained by performing the 1st to k-1th decoding of the to-be-decoded symbol sequence.

[0013] Based on the above solution, by generating the perturbation sequence according to the first decoding result and the candidate decoding results obtained by decoding the symbol sequence to be decoded from the 1st to the k-1th times, the perturbation sequence can be made more targeted and the decoding performance can be improved.

[0014] In combination with the first aspect, in certain implementations of the first aspect, each candidate decoding result of the L candidate decoding results includes a first result obtained by decoding the i-th coded bit, i takes any value between 1 and M, M is a positive integer, and M represents the length of the coded bit sequence in the to-be-decoded symbol sequence, and generating the perturbation sequence based on at least one candidate decoding result of the L candidate decoding results includes: generating a first perturbation value based on the first result when the first result included in each candidate decoding result is consistent; or generating a first perturbation value based on the first result when the first result included in each candidate decoding result is consistent and the direction of the likelihood ratio corresponding to the first result and the i-th code bit is different; wherein the first perturbation value is a perturbation value in the perturbation sequence, and the first perturbation value is used to apply perturbation to the to-be-decoded symbol sequence corresponding to the i-th coded bit.

[0015] Based on the above solution, by generating the perturbation sequence when the first result included in each candidate decoding result is consistent, or when the first result included in each candidate decoding result is consistent and the directions of the likelihood ratios corresponding to the first result and the i-th coded bit are different, the perturbation sequence can be made more targeted and the decoding performance can be improved.

[0016] In combination with the first aspect, in certain implementations of the first aspect, before obtaining the second decoding result, the method further includes: verifying the first decoding result based on a cyclic redundancy check bit, wherein the to-be-decoded symbol sequence is obtained by the encoding device by modulating a polar code, and the polar code is obtained by the encoding device by polar encoding information bits and the cyclic shift bits; or verifying the first decoding result based on a relationship between a path metric value corresponding to the first decoding result and a preset threshold.

[0017] In a second aspect, a communication device is provided, comprising a transceiver unit and a processing unit, wherein the transceiver unit is configured to obtain a symbol sequence to be decoded; the processing unit is configured to determine a first decoding result, where the first decoding result is obtained by decoding the symbol sequence to be decoded; if the first decoding result fails verification, the processing unit is further configured to determine a second decoding result, where the second decoding result is obtained by decoding a first sequence, wherein the first sequence is generated by the symbol sequence to be decoded and a perturbation sequence, and the perturbation sequence is related to the first decoding result.

[0018] In combination with the second aspect, in certain implementations of the second aspect, the first decoding result includes L candidate decoding results, where L is a positive integer. Before obtaining the second decoding result, the processing unit is further configured to generate the perturbation sequence based on at least one candidate decoding result among the L candidate decoding results.

[0019] In combination with the second aspect, in certain implementations of the second aspect, the processing unit is specifically configured to: generate the perturbation sequence based on the lth candidate decoding result among the L candidate decoding results, the path metric value corresponding to the lth candidate decoding result being less than the path metric values ​​corresponding to the candidate decoding results other than the lth candidate decoding result among the L candidate decoding results; or, generate the perturbation sequence based on the L candidate decoding results; or, generate the perturbation sequence based on any one or more candidate decoding results of the L candidate decoding results.

[0020] In combination with the second aspect, in certain implementations of the second aspect, the first decoding result is obtained by performing a k-th decoding of the to-be-decoded symbol sequence, where k is an integer greater than or equal to 1, and the processing unit is specifically configured to generate the perturbation sequence based on the first decoding result and candidate decoding results obtained by performing the 1st to k-1th decoding of the to-be-decoded symbol sequence.

[0021] In combination with the second aspect, in certain implementations of the second aspect, each candidate decoding result of the L candidate decoding results includes a first result obtained by decoding the i-th coded bit, i takes any value between 1 and M, M is a positive integer, and M represents the length of the coded bit sequence in the to-be-decoded symbol sequence, and the processing unit is specifically configured to: when the first result included in each candidate decoding result is consistent, generate a first disturbance value based on the first result; or, when the first result included in each candidate decoding result is consistent and the direction of the likelihood ratio corresponding to the first result and the i-th coded bit is different, generate a first disturbance value based on the first result; wherein the first disturbance value is a disturbance value in the disturbance sequence, and the first disturbance value is used to apply disturbance to the to-be-decoded symbol sequence corresponding to the i-th coded bit.

[0022] With reference to the second aspect, in certain implementations of the second aspect, before obtaining the second decoding result, the processing unit is further configured to verify the first decoding result based on a cyclic redundancy check (CRC) bit, wherein the to-be-decoded symbol sequence is obtained by the encoding device by modulating a polar code, and the polar code is obtained by the encoding device by polar encoding information bits and the cyclic shift bits; or, verify the first decoding result based on a relationship between a path metric value corresponding to the first decoding result and a preset threshold.

[0023] In a third aspect, the present application provides a communication device having the function of implementing the method of the first aspect or any possible implementation thereof. The function can be implemented by hardware or by hardware executing corresponding software implementation. The hardware or software includes one or more units corresponding to the above-mentioned functions.

[0024] In a fourth aspect, the present application provides a communication device comprising a communication interface and a processing circuit, wherein the communication interface is used to receive a signal and transmit the received signal to the processing circuit, and the processing circuit processes the signal so that the method in the first aspect or any possible implementation thereof is executed.

[0025] In the present application, the communication interface is specifically used to receive a sequence of symbols to be decoded and transmit the sequence of symbols to be decoded to the processing circuit. The processing circuit uses the decoding method provided in the present application to decode the sequence of symbols to be decoded to obtain a decoding result. The communication interface is also used to output the decoding result.

[0026] In a fifth aspect, the present application provides a communication device, comprising at least one processor, wherein the at least one processor is coupled to at least one memory, wherein the at least one memory is used to store a computer program or instruction, and the at least one processor is used to call and run the computer program or instruction from the at least one memory, so that the communication device executes the method in the first aspect or any possible implementation thereof.

[0027] Optionally, the communication device may further include one or more transceivers, and the one or more transceivers may transmit and receive signals under the control of the one or more processors to implement corresponding functions of the communication device.

[0028] In one example, the communication device may be a decoder.

[0029] In a sixth aspect, the present application provides a decoding device, wherein the decoding device implements the functions of the receiving end in the first aspect or any possible implementation of the first aspect. The functions can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more functionally corresponding modules.

[0030] In one possible implementation, when part or all of the functions are implemented by hardware, the decoding device includes: an input interface circuit, used to obtain a sequence of symbols to be decoded; a logic circuit or a processing circuit, used to execute the decoding method of the first aspect or any possible implementation thereof, and decode the sequence of symbols to be decoded; and an output interface circuit, used to output a decoding result obtained by decoding.

[0031] Optionally, the decoding device may be a chip or an integrated circuit.

[0032] In another possible implementation, when part or all of the functions are implemented by software, the decoding device includes: one or more memories for storing computer programs; and one or more processors for executing the computer programs stored in the one or more memories. When the computer programs are executed, the decoding device can implement the decoding method described in the first aspect or any possible implementation of the first aspect.

[0033] In another possible implementation, when part or all of the functions are implemented by software, the decoding device includes one or more processors. A memory for storing a computer program is located outside the decoding device, and the one or more processors are connected to the memory via circuits / wires and configured to read and execute the computer program stored in the memory, thereby implementing the decoding method of the first aspect or any possible implementation thereof.

[0034] Optionally, in each of the above implementations, the memory may be a physically independent unit or may be integrated with the processor.

[0035] In a seventh aspect, the present application provides a computer-readable storage medium, in which computer instructions are stored. When the computer instructions are executed on a computer, the method in the first aspect or any possible implementation thereof is implemented.

[0036] In an eighth aspect, the present application provides a computer program product, comprising computer program code. When the computer program code runs on a computer, the method in the first aspect or any possible implementation thereof is implemented.

[0037] In a ninth aspect, the present application provides a wireless communication system, comprising the communication device as described in the fourth aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] FIG1 is a schematic diagram of a communication system suitable for use in the present application.

[0039] FIG2 is a schematic diagram of the basic flow of wireless communication.

[0040] FIG3 is a schematic diagram of polar code encoding.

[0041] FIG4 is a schematic diagram of polar code decoding.

[0042] FIG5 is a schematic diagram of a polar code decoding method provided in the present application.

[0043] FIG6 is a schematic diagram of another polar code decoding method provided in the present application.

[0044] FIG7 is a schematic block diagram of a communication device 700 provided in this application.

[0045] FIG8 is a schematic block diagram of a communication device 800 provided in this application.

[0046] FIG9 is a schematic block diagram of a chip system 900 provided in this application. DETAILED DESCRIPTION

[0047] The technical solution in this application will be described below with reference to the accompanying drawings.

[0048] The embodiments of the present application can be applied to various communication systems, including but not limited to: fifth generation (5G) th The present invention relates to a 5G network or a NR system, an LTE system, a LTE system, a LTE-A system, an LTE frequency division duplex (FDD) system, an LTE time division duplex (TDD) system, and the like. The present invention can also be applied to future communication systems, such as the sixth generation mobile communication system. In addition, the present invention can also be applied to device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine type communication (MTC), Internet of Things (IoT) communication system, narrowband Internet of Things (NB-IoT) system, or other communication systems. In addition, the present invention can also be extended to similar wireless communication systems, such as wireless-fidelity (Wi-Fi), worldwide interoperability for microwave access (WIMAX), and communication systems related to the 3rd Generation Partnership Project (3GPP), without limitation.

[0049] Figure 1 is a schematic diagram of a communication system applicable to an embodiment of the present application. As shown in Figure 1, the communication system 10 includes at least one radio access network (RAN) node (such as 110a and 110b in Figure 1, collectively referred to as 110) and at least one terminal device (such as 120a-120j in Figure 1, collectively referred to as 120). RAN 100 may also include other RAN nodes, such as wireless relay devices and / or wireless backhaul devices (not shown in Figure 1). Terminal device 120 is connected to RAN node 110 via a wireless connection.

[0050] The terminal device of the present application may also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, drone, wireless communication device, user agent or user device, etc. The terminal device in the embodiments of the present application may refer to a device that provides voice and / or data connectivity to a user, and can be used to connect people, objects and machines, such as a handheld device with wireless connection function, a vehicle-mounted device, etc. The terminal device in the embodiments of the present application can be a mobile phone, a tablet computer, a laptop computer, a PDA, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, a wireless terminal in a smart home, etc.

[0051] The RAN node 110, sometimes also referred to as access network equipment, RAN entity, access node, or network equipment, facilitates wireless access for terminals. The multiple RAN nodes 110 in the communication system 10 can be of the same type or different types. In some scenarios, the roles of the RAN node 110 and the terminal device 120 are relative. For example, the network element 120i in Figure 1 can be a helicopter or a drone, which can be configured as a mobile base station. For terminal devices 120j accessing the RAN 100 through the network element 120i, the network element 120i is a base station; however, for the base station 110a, the network element 120i is a terminal device.

[0052] In one possible scenario, a RAN node may be a base station, an evolved NodeB (eNodeB), an access point (AP), a transmission reception point (TRP), a next generation NodeB (gNB), a base station in a future mobile communication system, or an access node in a WiFi system. A RAN node may be a macro base station (such as 110a in FIG1 ), a micro base station or an indoor station (such as 110b in FIG1 ), a relay node or a donor node, or a wireless controller in a CRAN scenario. Optionally, a RAN node may also be a server, a wearable device, a vehicle or an onboard device, etc. For example, the access network device in the vehicle to everything (V2X) technology may be a road side unit (RSU). All or part of the functions of the RAN node in this application may also be implemented by software functions running on hardware, or by virtualized functions instantiated on a platform (such as a cloud platform). The RAN node may also be provided with a communication module, circuit or chip that performs the corresponding communication functions. The RAN node may also be configured with program instructions for executing corresponding communication functions and corresponding program instructions. The RAN node in this application may also be a logical node, logical module or software that can implement all or part of the RAN node functions.

[0053] In another possible scenario, multiple RAN nodes collaborate to assist the terminal in achieving wireless access, and different RAN nodes respectively implement part of the functions of the base station. For example, the RAN node can be a centralized unit (CU), a distributed unit (DU), a CU-control plane (CP), a CU-user plane (UP), or a radio unit (RU). The CU and DU can be set separately, or they can be included in the same network element, such as a baseband unit (BBU). The RU can be included in a radio frequency device or radio frequency unit, such as a remote radio unit (RRU), an active antenna unit (AAU), or a remote radio head (RRH).

[0054] In different systems, CU (or CU-CP and CU-UP), DU or RU may also have different names, but those skilled in the art can understand their meanings. For example, in the ORAN system, CU may also be called O-CU (Open CU), DU may also be called O-DU, CU-CP may also be called O-CU-CP, CU-UP may also be called O-CU-UP, and RU may also be called O-RU. For the convenience of description, this application uses CU, CU-CP, CU-UP, DU and RU as examples for description. Any unit of CU (or CU-CP, CU-UP), DU and RU in this application can be implemented by a software module, a hardware module, or a combination of a software module and a hardware module.

[0055] Terminal device 120 can be a device or module that accesses the aforementioned communication system and has corresponding communication functions. A terminal can also be referred to as a terminal device, user equipment (UE), mobile station, mobile terminal, etc. Terminals can be widely used in various scenarios, such as device-to-device (D2D), vehicle-to-everything (V2X) communication, machine-type communication (MTC), the Internet of Things (IoT), virtual reality, augmented reality, industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearables, smart transportation, smart cities, etc. A terminal can be a mobile phone, tablet computer, computer with wireless transceiver functions, wearable device, vehicle, drone, helicopter, airplane, ship, robot, robotic arm, smart home appliance, transport vehicle with wireless communication functions, communication module, etc. The embodiments of this application do not limit the device form of the terminal. The terminal is typically provided with a communication module, circuit, or chip that performs the corresponding communication functions. The terminal is also configured with program instructions for performing the corresponding communication functions.

[0056] It is understood that Figure 1 is only an example and does not limit the scope of protection of this application. The communication method provided in the embodiment of this application may also involve network elements not shown in Figure 1. Of course, the communication method provided in the embodiment of this application may also include only some of the network elements shown in Figure 1.

[0057] In the wireless communication system shown in FIG1 , original information is encoded by an encoder, transmitted through a channel, received by a decoder, and decoded by the decoder to restore the original information.

[0058] The encoding end may also be referred to as a transmitting end (or a transmitting device), and the decoding end may also be referred to as a receiving end (or a receiving device) of information or data. The transmitting device may be a network device, and the receiving device may be a terminal device. Alternatively, the transmitting device may be a terminal device, and the receiving device may be a network device. Alternatively, the transmitting device may be a terminal device, and the receiving device may be a terminal device. Alternatively, the transmitting device may be a network device, and the receiving device may be a network device.

[0059] It should be understood that the embodiments of this application use the 5G system as an example to describe specific solution details. It is understood that when this solution is applied to other communication systems, such as the LTE system or future communication systems, the various messages, channels, or information in the solution can be replaced with messages, channels, or information that can achieve corresponding functions in other communication systems, and this application does not limit this.

[0060] In addition, the embodiments of the present application can be applied to various application scenarios, such as high throughput scenarios, high reliability scenarios, low latency scenarios, high reliability and low latency scenarios, or low power consumption scenarios. For example, the three most typical communication scenarios in 5G communication systems include:

[0061] 1) eMBB scenario: requires support for higher transmission rates (peak rate: uplink reaches 10 Gbit / s, downlink reaches 20 Gbit / s), higher spectrum efficiency (peak spectrum efficiency: uplink reaches 12 bit / (s·Hz), downlink reaches 30 bit / (s·Hz)), etc.

[0062] 2) mMTC scenario: requires support for higher connection density (1×106 connections / km2) and lower energy consumption (terminal battery life reaches 15 years);

[0063] 3) uRLLC scenario: requires support for lower latency (uplink and downlink latency of 0.5ms, i.e., end-to-end latency less than 1ms), higher reliability (up to 99.9999%), and lower error floor.

[0064] Channel coding and decoding, as fundamental wireless access technologies, are key research areas for meeting 5G communication requirements. Figure 2 illustrates a communication process within a communication system. The signal from the transmitter undergoes source coding, channel coding, rate matching, and modulation before being transmitted over the channel. The receiver receives the signal through demodulation, rate matching, channel decoding, and source decoding to obtain the information.

[0065] Channel coding and decoding is a core technology in wireless communications. Improvements in its performance directly enhance network coverage and user transmission rates. Since the Shannon limit was proposed, researchers worldwide have been dedicated to finding coding and decoding methods that achieve the Shannon limit while maintaining relatively low complexity. While turbo codes and low-density parity-check (LDPC) codes, which have become mainstream research areas and have been successfully applied in LTE and WiMAX, these codes are not sufficient to address some key challenges in 5G communications.

[0066] In the future, channel coding will need to support a wider range of code rates with lower complexity and better performance. For example, a key feature that distinguishes eMBB and mMTC from LTE is the transmission of short to medium packets, requiring channel coding to better support communications with these code lengths. uRLLC further demands reliability in data transmission. Regarding code rates, turbo codes currently cannot support very low or very high code rates. Due to their inherent coding characteristics, turbo and LDPC codes struggle to achieve ideal performance within limited code lengths for short to medium packet transmission. For long packets, while turbo and LDPC codes can approach the Shannon limit as code length increases, their theoretical performance remains below the target. Furthermore, turbo and LDPC codes exhibit high implementation complexity during coding. Therefore, 5G communication systems require a new coding technology to address the challenges of existing technologies with regard to short packets, code rates, reliability, and complexity.

[0067] Polar codes are the first channel coding method rigorously proven to achieve channel capacity. Across various code lengths, polar codes significantly outperform turbo and LDPC codes. Furthermore, polar codes offer lower computational complexity in encoding and decoding. These advantages have led to their widespread adoption in 5G.

[0068] The following describes the encoding process of polar code and the decoding process of polar code.

[0069] In the polar code encoding process, the generator matrix is ​​G N , the encoding process is in is a binary row vector with a length of N (i.e., code length); G N is an N×N matrix, and Also called polarized nucleus; represents the n-th Kronecker product, n=log2(N).

[0070] FIG3 shows a schematic diagram of a polar code encoding process. As shown in FIG3 (a), the polar code encoding process can be represented by a fence diagram. Place it on the far left of the fence diagram, and perform n-order butterfly operations from left to right to get the encoding result in, A portion of the bits in the datagram are used to carry information, which are called information bits; the other portion of the bits are set to fixed values ​​pre-agreed by the sender and receiver, which are called fixed bits or frozen bits.

[0071] A key issue in polar code construction is determining the information bit sequence set. For example, the polar code construction can be obtained by offline construction through reliability sequence or based on methods such as Gaussian analysis. For example, the reliability of each subchannel can be sorted, and the K positions with the highest reliability are set as information bits, and the remaining NK positions are set as frozen bits. As shown in Figure 3 (b), a polar code with N = 8 and k = 4 is constructed, where u3, u5, u6, and u7 are information bits and the remaining positions are frozen bits.

[0072] Polar code decoding can use a successive cancellation (SC) decoding algorithm. In the SC decoding algorithm, the log likelihood ratio (LLR) of the information bit is calculated step by step. For an information bit, if the LLR is greater than 0, the bit is judged as 0; if the LLR is less than 0, the bit is judged as 1. For frozen bits, the bit is set to 0 regardless of the LLR. This decision condition is also called LLR hard decision.

[0073] Figure 4 shows a schematic diagram of an SC decoding algorithm. Figure 4 shows eight computational nodes: four f-nodes and four g-nodes. The f-nodes can be understood as nodes that perform the f operation; the g-nodes can be understood as nodes that perform the g operation. The f-operation and the g-operation are two types of operations in the polar code decoding process. For details, please refer to existing related descriptions. The calculation of the f-node requires the two LLRs to the right as input, while the calculation of the g-node requires the two LLRs to the right and a "partial sum" above as input. Based on the above rules, as shown in Figure 4, SC decoding begins with the right-side received signal and sequentially calculates the eight nodes, resulting in a decoding sequence of ①-②-③-④.

[0074] It can be understood that since each information bit has only two possible values, 0 and 1, SC decoding of polar codes can be abstracted as a binary tree search problem with a height of n = log2(N), where N is the code length. Furthermore, since each hard decision step is based only on local information, SC can be regarded as a greedy search algorithm.

[0075] Decoding algorithms are particularly important for industrial applications. Professor Arikan demonstrated that polar codes can achieve high capacity at infinite lengths using the SC algorithm. However, at finite lengths, SC's performance is unsatisfactory. To address this issue, the industry has proposed methods such as the Successive Elimination List (SCL) algorithm, the Successive Elimination List (CA-SC) algorithm assisted by a cyclic redundancy check (CRC), and Successive Cancellation Flip (SC Flip or SCF) decoding.

[0076] Among them, the SCL algorithm is an extension of the SC decoding algorithm. Different from the SC decoding algorithm, the SCL algorithm decodes information bits u t When saving u t =0 and u t =1. Thus, one decoding path becomes two, and the total number of decoding paths becomes twice the current number of paths. To avoid exponential growth of decoding paths, when the total number of decoding paths reaches 2L, it is necessary to retain L paths with better path metrics and eliminate the remaining L paths with poorer path metrics. The path metric calculation formula for the lth path is as follows:

[0077] in, Polarized channel LLRs:

[0078] Where W represents the channel conditional transition probability.

[0079] At the end of SCL decoding, the CA-SCL algorithm generates a set of candidate paths that can be combined with CRC for low-complexity detection and decoding. Candidate sequences that pass the CRC check are selected as the decoder's output sequence, thereby improving the decoding algorithm's error correction capability. The CA-SCL algorithm adds a CRC check bit sequence to the information bit sequence and uses the SCL decoding algorithm to obtain L search paths. Using the prior knowledge that the correct information bits pass the CRC check, the algorithm then selects these L search paths to output the optimal decoding path.

[0080] By perturbing the received symbols and re-decoding them when SCL decoding fails, performance gains can be achieved that persist with increasing code length. This approach can achieve double or quadruple the performance of a decoder with a smaller list size.

[0081] For example, when receiving the symbol sequence y = [y1, y2, ..., y i ,…,y N-1 ,y N]When the decoding fails, a random Gaussian perturbation is applied to it to generate the perturbation sequence y', y' = [y1', y2', ..., y i ',…,y N-1 ',y N '], where y i '=y i +N(0,σ 2 ), re-decode y' to obtain the decoding result.

[0082] In view of this, the present application provides a polar code decoding method and communication device, which can more specifically apply perturbations to the received symbol sequence, thereby improving the decoding performance of the polar code and reducing the implementation complexity of the decoding.

[0083] Figure 5 shows a schematic flow chart of a polar code decoding method 500. This method can be performed by a first communication device, a component within the first communication device (e.g., a chip, chip system, or circuit), or a logic module or software capable of implementing all or part of the functionality of the first communication device. As an example, the first communication device can be a receiving end in the aforementioned communication system, which can include a decoding device. The following description uses the decoding device as an example. This method can include the following steps.

[0084] S510: Obtain a sequence of symbols to be decoded.

[0085] Exemplarily, a decoding device receives the to-be-decoded symbol sequence from a transmitter (encoding device). For example, the to-be-decoded symbol sequence is a symbol sequence sent by the encoding device after modulating a polar code, where the polar code may be obtained by polar encoding information bits and frozen bits. Optionally, a CRC check bit sequence is added to the information bit sequence before polar encoding.

[0086] S520: Determine a first decoding result.

[0087] The first decoding result is obtained by decoding a symbol sequence to be decoded. Exemplarily, a decoding device receives the symbol sequence to be decoded, demodulates the symbol sequence to be decoded, and obtains an LLR sequence corresponding to the coded bits; the decoding device inputs the LLR sequence into a decoder for decoding to obtain the first decoding result; or the first decoding result is obtained by directly inputting the symbol sequence to be decoded into a decoder.

[0088] The decoder may be an SC decoder, an SCL decoder, a belief propagation (BP) decoder, or any other decoder for polar code decoding, without limitation. The decoder may be understood as a decoding algorithm, or a corresponding decoding algorithm may be pre-installed in the decoder.

[0089] The first decoding result includes L candidate decoding results, where L is a positive integer. It can be understood that each decoding result in the L candidate decoding results is a result obtained by decoding the to-be-decoded symbol sequence.

[0090] For example, if the decoder is an SCL decoder, the L candidate decoding results can be the decoding results output by executing the SCL algorithm once; or, if the decoder is an SC decoder, the value of L can be 1, that is, the one candidate decoding result is the decoding result output by executing the SC algorithm once.

[0091] The “candidate decoding results” mentioned above may also be referred to as “candidate decoding sequences”, “decoding paths”, “candidate decoding codeword sequences”, etc., without limitation.

[0092] Optionally, the method further includes: verifying the first decoding result.

[0093] It should be understood that by checking the first decoding result, it can be determined whether to use one of the L candidate decoding results as the final decoding result of the to-be-decoded symbol sequence.

[0094] In one example, the L candidate decoding results are checked based on CRC bits. If a CRC check bit sequence is added to the information bit sequence before polar coding, the L candidate decoding results are checked based on the CRC bits. Specifically, if at least one of the L candidate decoding results passes the CRC check, the first decoding result passes the CRC check; otherwise, the first decoding result fails the check.

[0095] In another example, the first decoding result is verified based on a relationship between a path metric value corresponding to each of the L candidate decoding results and a preset threshold. Specifically, if at least one decoding result among the L candidate decoding results has a path metric value less than or equal to the preset threshold, the first decoding result passes verification (this verification method may also be referred to as path metric value verification); otherwise, the first decoding result fails verification.

[0096] Optionally, when the first decoding result passes the verification, the decoding result with the smallest corresponding path metric value among at least one decoding result that passes the verification can be used as the final decoding result of the symbol sequence to be decoded.

[0097] The specific method of determining the path metric value corresponding to the candidate decoding result may refer to the existing related description.

[0098] If the first decoding result fails the verification, the method further includes:

[0099] S530: Determine a second decoding result.

[0100] The second decoding result is obtained by decoding the first sequence. The first sequence is generated by the to-be-decoded symbol sequence and a perturbation sequence, that is, the to-be-decoded symbol sequence is perturbed to obtain the first sequence. The perturbation sequence may include perturbation values ​​corresponding to the coded bits included in the to-be-decoded symbol sequence.

[0101] Specifically, the first sequence may be obtained by applying a perturbation to the LLR sequence corresponding to the to-be-decoded symbol sequence, wherein the perturbation sequence is related to the first decoding result, or in other words, the perturbation sequence is determined according to the first decoding result.

[0102] In this application, the "disturbance sequence" may also be referred to as a soft value sequence, an external information sequence, a soft information sequence, etc., without limitation.

[0103] The method may further include: generating a perturbation sequence (denoted as perturbation sequence #1) based on at least one candidate decoding result in the first decoding result. The specific process may refer to the following example:

[0104] Example 1: The perturbation sequence is generated according to any one or more candidate decoding results among L candidate decoding results.

[0105] For example, any two candidate decoding results among the L candidate decoding results include the encoding bit x i The decoding results are Then generating the disturbance sequence according to the L candidate decoding results includes: Generate coded bits x i The corresponding perturbation value. The perturbation sequence includes the coded bits x i The corresponding disturbance value.

[0106] In Example 2, the perturbation sequence is generated based on the lth candidate decoding result in the first decoding result. The path metric value corresponding to the lth candidate decoding result is smaller than the path metric values ​​corresponding to the other candidate decoding results in the L candidate decoding results included in the first decoding result, i.e., the path metric value corresponding to the lth candidate decoding result is the lowest.

[0107] For example, the lth candidate decoding result includes the coded bit x i The decoding result of Then generating the disturbance sequence according to the lth candidate decoding result includes: Generate coded bits x i The corresponding perturbation value. The perturbation sequence includes the coded bits x i The disturbance sequence also includes the disturbance values ​​corresponding to other coded bits in the symbol sequence to be decoded, which are determined in the same way as the generated coded bit x. iThe corresponding perturbation values are similar.

[0108] In this example, the perturbation value can be generated based on only one candidate decoding result, and the implementation is relatively simple.

[0109] Example 3: Generate the perturbation sequence according to L candidate decoding results in the first decoding result.

[0110] For example, each of the L candidate decoding results includes the decoding result of the coded bit x i and they are respectively Then generating the perturbation sequence according to the L candidate decoding results includes: according to generate the perturbation value corresponding to the coded bit x i The perturbation sequence includes the perturbation value corresponding to the coded bit x i The perturbation sequence also includes the perturbation values corresponding to other coded bits in the candidate decoding results.

[0111] In this example, only L candidate decoding results need to be stored, which can reduce the implementation complexity of the decoder.

[0112] Example 4: Generate the perturbation sequence according to K decoding results obtained by performing K decodings on the symbol sequence to be decoded. The K decoding results can include the first decoding result, and K is an integer greater than or equal to 2.

[0113] Among them, the decoding for obtaining the first decoding result can be understood as the last decoding in the K decodings. Before obtaining the first decoding result, the decoding device obtains the K - 1 decoding results before the first decoding result, that is, performs K - 1 decodings on the symbol sequence to be decoded to obtain K - 1 decoding results. The process of performing K - 1 decodings on the symbol sequence to be decoded can refer to the process of determining the first decoding result.

[0114] Exemplarily, in the first decoding, the symbol sequence to be decoded (denoted as the initial decoding symbol sequence) input can be the received symbol sequence, or the symbol sequence obtained by demodulating the received symbol sequence; in the kth decoding, the symbol sequence to be decoded input can be generated according to the initial decoding symbol sequence and the perturbation sequence, where 1 < k < K. The generation method of the symbol sequence to be decoded input in the kth decoding can refer to the generation method of the first sequence.

[0115] For example, assume K is 2, L = 1, the initial symbol sequence to be decoded is denoted as y0, and after the first decoding of the initial symbol sequence to be decoded, the candidate decoding result If does not pass the check, then perform the second decoding: decode the sequence (denoted as y1) after applying perturbation (the corresponding perturbation sequence is denoted as r0) to y0 to obtain the candidate decoding result (i.e. the first decoding result). The perturbation sequence generated by performing K decoding on the symbol sequence to be decoded can be: and candidate decoding results Generate the perturbation sequence.

[0116] Based on the above solution, by generating the perturbation sequence #1 according to K decoding results obtained by performing K decoding on the candidate decoding results, the existing decoding paths can be utilized as much as possible, thereby improving the error correction performance.

[0117] Optionally, in Examples 3 and 4, each candidate decoding result includes the coded bit x i When the decoding results are consistent, or when each candidate decoding result includes the coded bit x i The decoding results are consistent, and each candidate decoding result includes the coded bits x i The decoding result and the coded bit x i When the hard decision of the LLR value is different, the coded bit x is generated according to the L candidate decoding results. i The corresponding perturbation value (Example 3), or the coded bit x generated based on K decoding results i The corresponding perturbation value (Example 4). The perturbation sequence includes the coded bits x i The corresponding disturbance value is i=0, ..., N-1, where N is the length of the symbol sequence to be decoded.

[0118] For example, each candidate decoding result in the L candidate decoding results includes a decoding result for the coded bit x i The decoding results (an example of the first result) are like Equal and According to Generate coded bits x i The corresponding disturbance value δ (an example of the first disturbance value).

[0119] In one possible implementation, the encoding bit x i The corresponding disturbance value It can be understood that if the perturbation sequence is generated according to the lth candidate decoding result, then Indicates the coded bits x included in the lth candidate decoding result i The decoding result of . Among them, σ is a natural number; λ1 is used to adjust the power of the disturbance value.

[0120] Exemplarily, the value of λ1 can be configured based on parameters such as the signal-to-noise ratio and power of the received symbol sequence to be decoded. For example, λ1 is determined based on reducing the equivalent signal-to-noise ratio by λdB. The value of λ1 can also be determined based on the code rate of the channel coding. For example, based on the relationship between the code rate and the signal-to-noise ratio, the equivalent signal-to-noise ratio is determined, and λ1 is determined based on the equivalent signal-to-noise ratio. λ1 can be configured by the decoder. For example, to improve error correction performance, the value of λ1 can be between 0.1 and 0.3.

[0121] In another possible implementation, PM1, PM2,…, PM L , and LLR i Input the neural network and determine the encoding bit x based on the output value of the neural network i The corresponding disturbance value. Among them, PM1, PM2,…, PM L Respectively represent the path metrics corresponding to the L candidate decoding results; LLR i Represents the coded bit x i The neural network can be trained using historical data. For example, the historical data may include candidate decoding results, path metrics corresponding to the candidate decoding results, LLRs of the bits to be decoded, and perturbation values ​​corresponding to the bits to be decoded.

[0122] Optionally, in Example 3 and Example 4, if each candidate decoding result includes a pair of coded bits x i There is inconsistency in the decoding results, or each candidate decoding result includes the coded bits x i The decoding result and the coded bit x i The hard decision of the LLR value of i Generate random disturbance. For example, the random disturbance Among them, λ2 can represent the power of the disturbance value, 0<λ2<1; σ represents the standard deviation of the random disturbance.

[0123] It can be understood that if the decoding device performs at least one decoding on the symbol sequence to be decoded before obtaining the first decoding result, the decoding result obtained each time is obtained by decoding the sequence obtained by applying a perturbation to the symbol sequence to be decoded, and the perturbation sequence is related to the decoding result obtained by the previous decoding. The way of applying perturbation to the decoding result obtained by the at least one decoding may be the same as or different from the way of applying perturbation to the first decoding result. That is, in the present application, the process of decoding the symbol sequence to be decoded can be understood as an iterative process (decoding the symbol sequence to be decoded to obtain a decoding result. If the decoding result fails to pass the verification, the symbol sequence to be decoded is perturbed and re-decoded until the decoding result passes the verification or reaches the preset maximum number of decoding times). In this iterative process, the method shown in any of the examples described above can be used to apply perturbation to each decoding result.

[0124] For example, if the decoding device decodes the symbol sequence to be decoded K times, and the Kth time is the decoding process for obtaining the first decoding result, then in the first K-1 rounds of iterations, the decoding result can be disturbed in the manner described in Example 3; the first decoding result can be disturbed in the manner described in Example 2.

[0125] For another example, in the iterative decoding process, the methods shown in Examples 2 to 4 are alternately used to treat the time disturbance of the decoding symbol sequence.

[0126] Based on the decoding method provided in the embodiment of the present application, by generating a disturbance value according to the decoding result, the disturbance addition can be made more accurate and the error correction performance can be improved.

[0127] Figure 6 shows a schematic flow chart of a polar code decoding method 600. This method can be performed by a first communication device, a component within the first communication device (e.g., a chip, chip system, or circuit), or a logic module or software capable of implementing all or part of the functionality of the first communication device. As an example, the first communication device can be a receiving end in the aforementioned communication system, which can include a decoding device. The following description uses the decoding device as an example. This method can include the following steps.

[0128] S610: Obtain a symbol sequence to be decoded.

[0129] For this step, please refer to the description in S510.

[0130] S620, determining a decoding result #i obtained by decoding the i-th coded bit in the to-be-decoded symbol sequence, and judging whether the decoding result #i passes verification, where i=1, 2, ..., N, and N represents the length of the to-be-decoded symbol sequence.

[0131] This step may refer to the description of S520. Different from the verification of the first decoding result in S520, this step verifies the decoding result of each coded bit in the to-be-decoded symbol sequence. That is, compared to S420, the decoding result of each coded bit is verified in the process of obtaining the first decoding result.

[0132] The specific verification process can be found in the description of S520. For example, if a CRC check bit sequence is added to the information bit sequence before polar coding, verification is performed based on the CRC bits. Alternatively, verification is performed based on the relationship between the path metric value corresponding to decoding result #i and a preset threshold.

[0133] S630: If the decoding result #i fails the verification, determine a decoding result #i1 for the i-th coded bit according to the second sequence and the perturbation sequence.

[0134] The second sequence is an intermediate sequence obtained by decoding the i-th coded bit. That is, the second sequence is a sequence generated during the process of decoding the i-th coded bit to produce decoding result #i. In other words, the second sequence is used to determine decoding result #i for the i-th coded bit during a single decoding process.

[0135] For example, as shown in FIG3(a), during verification of the decoding results of the coded bits, if the decoding result of the i-th coded bit (i=8) fails verification, the decoding result of the i-th coded bit is generated based on the intermediate sequence (such as the sequence in the dashed box in FIG3(a), an example of the second sequence) used to generate the decoding result of the i-th coded bit and the perturbation sequence. It should be understood that the second sequence in FIG3(a) is merely an example, and the second sequence can be a sequence in any layer of the intermediate layer.

[0136] The perturbation sequence may be described in S530. For example, the perturbation sequence is a random perturbation sequence, or the perturbation sequence is generated according to the second sequence. This step may refer to the process of generating a perturbation sequence according to the first decoding result.

[0137] Based on the decoding method provided in the embodiment of the present application, by applying perturbations to the intermediate layers in the decoding process of the coded bits, when an error occurs in the middle of the decoding process, the decoding can be stopped and re-decoding can be started by adding perturbations, thereby saving computational complexity.

[0138] The decoding method provided in the embodiments of the present application is described in detail above in conjunction with Figures 5 and 6. It should be understood that in the embodiments of the present application, the various numerical numbers are only used for the convenience of description and are not intended to limit the scope of the embodiments of the present application. The order of the sequence numbers of the above-mentioned processes does not imply the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0139] In the embodiments of the present application, “first”, “second” and various numerical numbers are used to distinguish for the convenience of description and are not used to limit the scope of the embodiments of the present application. For example, different indication information is distinguished.

[0140] In the embodiments of the present application, descriptions such as "when...", "under...", and "if" all mean that the device will perform corresponding processing under certain objective circumstances. They do not limit the time, nor do they require the device to perform judgment actions when implemented, nor do they mean that there are other limitations.

[0141] The communication device provided in the embodiment of the present application is described in detail below with reference to Figures 7 to 9. It should be understood that the description of the device embodiment corresponds to the description of the method embodiment. Therefore, for matters not described in detail, reference can be made to the method embodiment above. For the sake of brevity, they will not be repeated here.

[0142] FIG7 shows a schematic diagram of a communication device 700 provided in an embodiment of the present application.

[0143] The device 700 includes a transceiver unit 710 , which can be used to implement corresponding communication functions. The transceiver unit 710 can also be called a communication interface or a communication unit.

[0144] Optionally, the apparatus 700 may further include a processing unit 720 , which may be configured to perform data processing.

[0145] Optionally, the device 700 also includes a storage unit, which can be used to store instructions and / or data. The processing unit 720 can read the instructions and / or data in the storage unit so that the device can implement the actions of different devices in the aforementioned method embodiments.

[0146] In one possible design, the device 700 may be the decoding device described in the aforementioned embodiment, or may be a component of the decoding device (e.g., a chip). The device 700 may implement steps or processes corresponding to those performed by the decoding device in the aforementioned method embodiment. Specifically, the transceiver unit 710 may be configured to perform the transceiver-related operations of the decoding device described in the aforementioned method embodiment, such as the transceiver-related operations of the decoding device described in the embodiments shown in Figures 5 and 6 ; and the processing unit 720 may be configured to perform the processing-related operations of the decoding device described in the aforementioned method embodiment, such as the processing-related operations of the decoding device described in the embodiments shown in Figures 5 and 6 .

[0147] FIG8 is a schematic block diagram of a communication device 800 provided in an embodiment of the present application.

[0148] The apparatus 800 includes a processor 810 coupled to a memory 820. Optionally, the apparatus 800 further includes the memory 820. The memory 820 is configured to store computer programs or instructions and / or data. The processor 810 is configured to execute the computer programs or instructions stored in the memory 820, or read data stored in the memory 820, to perform the methods in the above method embodiments.

[0149] Optionally, there are one or more processors 810 .

[0150] Optionally, there are one or more memories 820 .

[0151] Optionally, the memory 820 is integrated with the processor 810 or provided separately.

[0152] Optionally, as shown in Figure 8, the apparatus 800 further includes a transceiver 830, which is configured to receive and / or transmit signals. For example, the processor 810 is configured to control the transceiver 830 to receive and / or transmit signals.

[0153] As a solution, the device 800 is used to implement the operations performed by the decoding device in each of the above method embodiments.

[0154] For example, the processor 810 is configured to execute computer programs or instructions stored in the memory 820 to implement the relevant operations of the terminal device in the above various method embodiments. For example, the methods executed by the terminal device in the embodiments shown in Figures 5 and 6.

[0155] During implementation, each step of the above method can be completed by an integrated logic circuit of the hardware in the processor 810 or by instructions in the form of software. The method disclosed in conjunction with the embodiments of the present application can be directly embodied as being executed by a hardware processor, or can be executed by a combination of hardware and software modules in the processor. The software module can be located in a storage medium mature in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory 820, and the processor 810 reads the information in the memory 820 and completes the steps of the above method in combination with its hardware. To avoid repetition, it will not be described in detail here.

[0156] It should be understood that in the embodiments of the present application, the processor may be one or more integrated circuits for executing relevant programs to execute the method embodiments of the present application.

[0157] A processor (e.g., processor 810) may include one or more processors and be implemented as a combination of computing devices. The processor may include one or more of the following: a microprocessor, a microcontroller, a digital signal processor (DSP), a digital signal processing device (DSPD), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a programmable logic device (PLD), gating logic, transistor logic, discrete hardware circuits, processing circuits, or other suitable hardware, firmware, and / or a combination of hardware and software to perform the various functions described in this disclosure. The processor may be a general-purpose processor or a special-purpose processor. For example, processor 810 may be a baseband processor or a central processing unit. A baseband processor may be used to process communication protocols and communication data. A central processing unit may be used to enable the device to execute software programs and process data in the software programs. In addition, a portion of the processor may also include non-volatile random access memory. For example, the processor may also store information about the device type.

[0158] In this application, the term "program" is used broadly to refer to software. Non-limiting examples of software include program code, program, subroutine, instruction, instruction set, code, code segment, software module, application, or software application. The program can be executed in a processor and / or computer to cause the device to perform the various functions and / or processes described in this application.

[0159] The memory (e.g., memory 820) can store data required by the processor (e.g., processor 810) when executing software. The memory can be implemented using any suitable storage technology. For example, the memory can be any available storage medium that can be accessed by the processor and / or computer. Non-limiting examples of storage media include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM), static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM), removable media, optical disk storage, magnetic disk storage media, magnetic storage devices, flash memory, registers, state memory, remotely mounted storage, local or remote memory components, or any other medium capable of carrying or storing software, data, or information and accessible by a processor / computer. It should be noted that the memory described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0160] The memory (e.g., memory 820) and the processor (e.g., processor 810) may be provided separately or integrated together. The memory may be used to connect to the processor so that the processor can read information from the memory and store and / or write information in the memory. The memory may be integrated into the processor. The memory and the processor may be provided in an integrated circuit (e.g., the integrated circuit may be provided in a UE or other network node).

[0161] FIG9 is a schematic block diagram of a chip system 900 provided in an embodiment of the present application.

[0162] The chip system 900 (or also referred to as a processing system) includes a logic circuit 910 and an input / output interface 920 .

[0163] The logic circuit 910 may be a processing circuit in the chip system 900. The logic circuit 910 may be coupled to a storage unit and call instructions in the storage unit so that the chip system 900 can implement the methods and functions of the various embodiments of the present application. The input / output interface 920 may be an input / output circuit in the chip system 900, outputting information processed by the chip system 900 or inputting data or signaling information to be processed into the chip system 900 for processing.

[0164] As a solution, the chip system 900 is used to implement the operations performed by the decoding device in each of the above method embodiments.

[0165] For example, the logic circuit 910 is used to implement the processing-related operations performed by the decoding device in the above method embodiments, such as the processing-related operations performed by the decoding device in the embodiments shown in Figures 5 and 6; the input / output interface 920 is used to implement the sending and / or receiving-related operations performed by the decoding device in the above method embodiments, such as the sending and / or receiving-related operations performed by the decoding device in the embodiments shown in Figures 5 and 6.

[0166] An embodiment of the present application further provides a computer-readable storage medium storing computer instructions for implementing the methods executed by the decoding device in the above-mentioned method embodiments.

[0167] An embodiment of the present application further provides a computer program product comprising instructions, which, when executed by a computer, implement the methods performed by the decoding device in the above-mentioned method embodiments.

[0168] The explanation of the relevant contents and beneficial effects of any of the above-mentioned devices can be referred to the corresponding method embodiments provided above, which will not be repeated here.

[0169] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the above-mentioned units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0170] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected according to actual needs to implement the solutions provided in this application.

[0171] In addition, each functional unit in each embodiment of the present application may be integrated into one unit, each unit may exist physically separately, or two or more units may be integrated into one unit.

[0172] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0173] When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable devices. For example, the computer can be a personal computer, a server, or a network device, etc. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center to another website, computer, server or data center by wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.). About computer-readable storage media, reference can be made to the above description.

[0174] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A polar code decoding method, characterized in that: include: Obtaining a sequence of symbols to be decoded; Determining a first decoding result, where the first decoding result is obtained by decoding the sequence of symbols to be decoded; If the first decoding result fails the verification, a second decoding result is determined, where the second decoding result is obtained by decoding a first sequence, where the first sequence is generated by the to-be-decoded symbol sequence and a perturbation sequence, and the perturbation sequence is related to the first decoding result.

2. The method according to claim 1, characterized in that The first decoding result includes L candidate decoding results, where L is a positive integer. Before determining the second decoding result, the method further includes: The perturbation sequence is generated according to at least one candidate decoding result among the L candidate decoding results.

3. The method according to claim 2, characterized in that Generating the perturbation sequence according to at least one candidate decoding result among the L candidate decoding results includes: generating the perturbation sequence according to a lth candidate decoding result among the L candidate decoding results, wherein the path metric value corresponding to the lth candidate decoding result is smaller than the path metric values ​​corresponding to the candidate decoding results other than the lth candidate decoding result among the L candidate decoding results; or generating the perturbation sequence according to the L candidate decoding results; or, The perturbation sequence is generated according to any one or more candidate decoding results of the L candidate decoding results.

4. The method according to claim 2, characterized in that The first decoding result is obtained by performing a k-th decoding on the to-be-decoded symbol sequence, where k is an integer greater than or equal to 1, and the generating the perturbation sequence according to at least one candidate decoding result among the L candidate decoding results includes: The perturbation sequence is generated according to the first decoding result and candidate decoding results obtained by performing the 1st to k-1th decoding on the to-be-decoded symbol sequence.

5. The method according to claim 2, characterized in that Each candidate decoding result of the L candidate decoding results includes a first result obtained by decoding the i-th coded bit, where i takes any value from 1 to M, M is a positive integer, and M represents the length of the coded bit sequence in the to-be-decoded symbol sequence. Generating the perturbation sequence according to at least one candidate decoding result of the L candidate decoding results includes: If the first result included in each candidate decoding result is consistent, generating a first disturbance value according to the first result; or In a case where the first result included in each candidate decoding result is consistent, and the directions of the likelihood ratios corresponding to the first result and the i-th coded bit are different, generating a first disturbance value according to the first result; The first disturbance value is a disturbance value in the disturbance sequence, and the first disturbance value is used to apply disturbance to the to-be-decoded symbol sequence corresponding to the i-th coded bit.

6. The method according to any one of claims 1 to 5, characterized in that Before determining the second decoding result, the method further includes: verifying the first decoding result according to cyclic redundancy check (CRC) bits, wherein the to-be-decoded symbol sequence is obtained by modulating a polar code by an encoding device, and the polar code is obtained by the encoding device by polar encoding information bits and the CRC bits; or The first decoding result is verified according to a relationship between a path metric value corresponding to the first decoding result and a preset threshold.

7. A communication device, characterized in that: Including transceiver unit and processing unit, The transceiver unit is used to obtain a sequence of symbols to be decoded; The processing unit is further configured to determine a first decoding result, where the first decoding result is obtained by decoding the sequence of symbols to be decoded; If the first decoding result fails the verification, the processing unit is further configured to determine a second decoding result, where the second decoding result is obtained by decoding a first sequence, wherein the first sequence is generated by the to-be-decoded symbol sequence and a perturbation sequence, and the perturbation sequence is related to the first decoding result.

8. The device according to claim 7, characterized in that The first decoding result includes L candidate decoding results, where L is a positive integer. Before determining the second decoding result, the processing unit is further configured to: The perturbation sequence is generated according to at least one candidate decoding result among the L candidate decoding results.

9. The device according to claim 8, characterized in that The processing unit is specifically configured to: generating the perturbation sequence according to a lth candidate decoding result among the L candidate decoding results, wherein a path metric value corresponding to the lth candidate decoding result is smaller than a path metric value corresponding to a candidate decoding result other than the lth candidate decoding result among the L candidate decoding results; or, generating the perturbation sequence according to the L candidate decoding results; or, The perturbation sequence is generated according to any one or more candidate decoding results of the L candidate decoding results.

10. The device according to claim 8, characterized in that The first decoding result is obtained by performing the k-th decoding on the to-be-decoded symbol sequence, where k is an integer greater than or equal to 1. The processing unit is specifically configured to: The perturbation sequence is generated according to the first decoding result and candidate decoding results obtained by performing the 1st to k-1th decoding on the to-be-decoded symbol sequence.

11. The device according to claim 8, characterized in that Each candidate decoding result of the L candidate decoding results includes a first result obtained by decoding the i-th coded bit, where i takes any value from 1 to M, M is a positive integer, and M represents the length of the coded bit sequence in the to-be-decoded symbol sequence, and the processing unit is specifically configured to: If the first result included in each candidate decoding result is consistent, generating a first disturbance value according to the first result; or In a case where the first result included in each candidate decoding result is consistent, and the directions of the likelihood ratios corresponding to the first result and the i-th coded bit are different, generating a first disturbance value according to the first result; The first disturbance value is a disturbance value in the disturbance sequence, and the first disturbance value is used to apply disturbance to the to-be-decoded symbol sequence corresponding to the i-th coded bit.

12. The device according to any one of claims 7 to 11, characterized in that The processing unit is further configured to: verifying the first decoding result according to cyclic redundancy check (CRC) bits, wherein the to-be-decoded symbol sequence is obtained by modulating a polar code by an encoding device, and the polar code is obtained by the encoding device by polar encoding information bits and the CRC bits; or The first decoding result is verified according to a relationship between a path metric value corresponding to the first decoding result and a preset threshold.

13. A communication device, characterized in that: The device comprises at least one processor coupled to at least one memory, and the at least one processor is configured to execute a computer program or instruction stored in the at least one memory, so that the device performs the method according to any one of claims 1 to 6.

14. The communication device according to claim 13, wherein: The at least one processor is integrated with the at least one memory.

15. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program or instructions, and when the computer program or instructions are executed on a computer, the computer is caused to perform the method according to any one of claims 1 to 6.

16. A computer program product, characterized in that The computer program product comprises a computer program or instructions, which, when executed on a computer, cause the computer to perform the method according to any one of claims 1 to 6.

17. A communication device comprising a communication interface and a processing circuit, wherein the communication interface is configured to receive a signal and transmit the received signal to the processing circuit, wherein the processing circuit processes the signal so that the communication device executes the method according to any one of claims 1 to 6.

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