Squaring circuit and root mean square detector

Abstract

A calibratable squaring circuit and a root mean square detector. A squaring circuit (10) comprises: a squaring unit (41) for outputting a first signal; a mirror squaring unit (42) for outputting a second signal, wherein the second signal is a static current (IB); a first current mirror structure, for mirroring and replicating the first signal to output a third signal; a second current mirror structure for mirroring and replicating the second signal to output a fourth signal; and a trimming unit (15), configured to adjust the mirror replication ratio of the first current mirror structure or the second current mirror structure, so that the difference between a direct-current component at an output end of a first output unit (13) and a direct-current component at an output end of a second output unit (14) falls within a first range. The present invention can achieve calibration of mismatches between the two squaring units in the root mean square detector, involves a simple structure, and can also achieve calibration of temperature-induced mismatch variations.

Description

A squaring circuit and root mean square detector

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to a Chinese patent application filed with the Patent Office of China on April 1, 2024, with application number 202410389926.8 and application name “A Squaring Circuit and Root Mean Square Detector,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application relates to the field of integrated circuits, and in particular to a squaring circuit and a root mean square detector. Background Art

[0004] Detectors, typically used to measure the amplitude or power of a signal, are widely used in wireless systems. They can be roughly divided into two categories: logarithmic amplifier detectors (or envelope detectors) and root mean square (RMS) detectors. For an RMS detector, three operations are required on the signal: root (Root), average (Mean), and square (Square). Since the squaring unit itself has a DC operating current / voltage, this current / voltage needs to be subtracted. Therefore, an additional mirror squaring unit is used to provide the same bias for accurate subtraction of the corresponding DC voltage / current. However, there may be a mismatch between the transistors in the squaring unit and the mirror squaring unit, and this mismatch varies with temperature, resulting in an inability to accurately subtract the corresponding DC voltage / current, resulting in inaccurate output results. Summary of the Invention

[0005] The present application provides a squaring circuit and a root mean square detector.

[0006] The technical solution of this application is achieved as follows:

[0007] In a first aspect, an embodiment of the present application provides a calibrable and adaptable square circuit, comprising:

[0008] a squaring unit, configured to square a received AC signal, the squaring unit receiving a bias voltage and the AC signal, and an output terminal of the squaring unit outputting a first signal;

[0009] a mirror square unit, configured to receive the bias voltage, wherein the structure of the mirror square unit is consistent with that of the square unit, and an output end of the mirror square unit outputs a second signal, wherein the second signal is a static current;

[0010] a first current mirror structure comprising a first input unit and a first output unit, wherein the first input unit receives the first signal; and the first output unit is connected to the first input unit and is configured to mirror the first signal and output a third signal;

[0011] a second current mirror structure comprising a second input unit and a second output unit, wherein the second input unit receives the second signal; and the second output unit is connected to the second input unit and is configured to mirror the second signal and output a fourth signal;

[0012] The trimming unit is configured to receive a control signal and adjust the mirror copy ratio of the first current mirror structure or the second current mirror structure based on the control signal.

[0013] In a second aspect, an embodiment of the present application provides a root mean square detector, which includes the squaring circuit as described in the first aspect.

[0014] The present invention provides a calibrable and adaptable squaring circuit and root mean square detector, which introduces a first current mirror structure, a second current mirror structure, and a trimming unit to calibrate the mismatch between the squaring unit and the mirrored squaring unit, wherein the first current mirror structure generates a third signal based on a first signal output from the output end of the squaring unit; the second current mirror structure generates a fourth signal based on a second signal output from the output end of the squaring unit; and the trimming unit adjusts the mirror copy ratio of the first current mirror structure or the second current mirror structure based on a control signal. When there is a mismatch between the transistors in the squaring unit and the mirrored squaring unit, there is a mismatch between the first signal and the second signal, and the DC portion in the first signal and the DC portion in the second signal are different. The first current mirror structure and the second current mirror structure respectively mirror the first signal and the second signal in proportion, so that the DC portion in the third signal and the DC portion in the fourth signal are different. The trimming unit is configured to receive a control signal and adjust the mirror copy ratio of the first current mirror structure or the second current mirror structure based on the control signal. By adjusting the mirror copy ratio of the first current mirror structure or the second current mirror structure through the adjustment unit, the third signal and the fourth signal are compensated, so that the DC part in the output end of the first output unit and the DC part in the output end of the second output unit can be made as identical as possible, thereby ultimately obtaining a better detection result. In addition, the square circuit design is simple, the power consumption is extremely low, and it does not affect the characteristics of the RF input port.

[0015] At the same time, by adjusting the mirror copy ratio of the first current mirror structure or the second current mirror structure through the trimming unit, the DC portion of the output terminal of the first output unit and the DC portion of the output terminal of the second output unit can be made as identical as possible. Any mismatch between the current mirror structure of the squaring circuit and the trimming unit itself can also be eliminated through calibration. Furthermore, during calibration, the trimming unit does not require RF signal input, which reduces the requirements for calibration equipment and site.

[0016] Furthermore, any mismatch between the first and second signals is mirrored by the first and second current mirror structures. The trimming unit adjusts the mirrored copy ratio of the first and second current mirror structures. Therefore, when the mismatch between the first and second signals varies with temperature, the compensation provided by the trimming unit also varies proportionally with temperature. The trimming unit can reuse the temperature characteristics of the squaring unit's output current, dynamically compensating for mismatches in the squaring unit as temperature changes. Consequently, the squaring circuit only requires calibration at a single temperature point, ensuring that mismatch calibration requirements are met at multiple temperature points, saving cost and calibration time. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] FIG1 is a schematic diagram of the results of an envelope detector and an RMS detector;

[0018] FIG2 is a schematic diagram of the structure of an RMS detector;

[0019] FIG3 is a schematic diagram of the structure of another RMS detector;

[0020] FIG4 is a schematic structural diagram of another mirror image square unit;

[0021] FIG5 is a schematic structural diagram of another square unit;

[0022] FIG6 is a structural diagram 1 of a squaring circuit provided in an embodiment of the present application;

[0023] FIG. 7A is a structural diagram of a square circuit provided in an embodiment of the present application.

[0024] FIG7B is a third structural diagram of a squaring circuit provided in an embodiment of the present application;

[0025] FIG8 is a schematic structural diagram of a single-pole double-throw switch provided in an embodiment of the present application;

[0026] FIG9 is a schematic diagram of the structure of a current mirror provided in an embodiment of the present application;

[0027] FIG10 is a fourth structural diagram of a squaring circuit provided in an embodiment of the present application;

[0028] FIG11 is a fifth structural diagram of a squaring circuit provided in an embodiment of the present application;

[0029] FIG12 is a first structural diagram of an RMS detector provided in an embodiment of the present application;

[0030] FIG13 is a schematic diagram showing how the output voltage of the detection logarithmic amplifier changes with the trimming code according to an embodiment of the present application. DETAILED DESCRIPTION

[0031] The following, in conjunction with the accompanying drawings, provides a clear and complete description of the technical solutions in the embodiments of the present application. It should be understood that the specific embodiments described herein are intended solely to illustrate the related applications and are not intended to limit those applications. It should also be noted that, for ease of description, only portions relevant to the related applications are shown in the drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meanings as commonly understood by those skilled in the art to which this application relates. The terms used herein are for the purpose of describing the embodiments of the present application only and are not intended to limit this application. In the following description, references to "some embodiments" describe a subset of all possible embodiments. However, it should be understood that "some embodiments" may refer to the same or different subsets of all possible embodiments and may be combined with each other without conflict. It should be noted that the terms "first," "second," and "third" in the embodiments of the present application are used solely to distinguish similar objects and do not represent a specific ordering of the objects. It should be understood that "first," "second," and "third" may be interchanged in a specific order or sequential order, where permitted, to enable the embodiments of the present application described herein to be implemented in an order other than that illustrated or described. In the description of this application, connections may include direct and indirect connections.

[0032] MOS (Metal-Oxide-Semiconductor Field-Effect Transistor): Metal-Oxide Semiconductor Field-Effect Transistor;

[0033] NMOS: N-type doped metal-oxide semiconductor field-effect transistor;

[0034] PMOS: P-type doped metal-oxide semiconductor field-effect transistor;

[0035] CMOS (Complementary Metal Oxide Semiconductor): complementary metal oxide semiconductor;

[0036] BJT (Bipolar Junction Transistor): Bipolar junction transistor;

[0037] DC (Direct Current): direct current;

[0038] LDO (Low Dropout Regulaor): low voltage dropout linear regulator;

[0039] dB (decibel): decibel;

[0040] dBm (decibel relative to one milliwatt): decibel milliwatt;

[0041] nA (Nanoampere): nanoampere;

[0042] mA (milliampere): milliampere;

[0043] uV (microvolt): microvolt;

[0044] mV (millivolt): millivolt;

[0045] Ω(ohm): Ohm;

[0046] kΩ: kiloohm.

[0047] Detectors can be categorized as envelope detectors and RMS detectors. See Figure 1, which shows the detection results of envelope and RMS detectors for the same RF signal. As shown in Figure 1, the RF signal is a high-frequency sine wave whose amplitude and phase vary with time. Envelope detection detects the envelope of the input signal, typically its logarithmic value, as shown in Output 1. An RMS detector detects the root mean square (RMS) value (or power) of the input signal, as shown in Output 2. Its output voltage does not vary with the signal's shape or peak-to-average power ratio (PAPR). The PAPR refers to the Peak to Average Power Ratio (PAPR). As shown in Figure 1, the amplitude of the high-frequency sine wave oscillation varies with the RF input signal value. The PAPR is the ratio of the power corresponding to its peak value to the power corresponding to its average value.

[0048] Please refer to Figure 2, which shows the common structure of an RMS detector. As shown in Figure 2, an RMS detector includes a squaring unit, a mirror squaring unit, an arithmetic module, an averaging capacitor, a logarithmic converter, and a driver. The squaring unit and the mirror squaring unit have identical structures. The squaring unit receives a mixed signal consisting of a bias voltage (DC Bias) (used to drive the squaring unit) and an RF input signal (RF Input). The mirror squaring unit receives a bias voltage (DC Bias) or a bias voltage (DC Bias) plus a feedback voltage (Feedback). The feedback voltage can be generated by the arithmetic module or the driver. The output signals of the squaring unit and the mirror squaring unit are subtracted after passing through the arithmetic module, then averaged by an averaging capacitor and logarithmically converted by a logarithmic converter. The resulting detection result signal is equivalent to the logarithmic RMS value (or power value) output in Figure 1. As shown in Figure 3, the averaging capacitor can also be placed at the output of the squaring unit.

[0049] Combined with Figure 2 or Figure 3, for the RMS detector, its working process includes performing three operations on the signal: Root, Mean, and Square. That is, the output voltage or current is:

[0050] Where Y is the output current or voltage, X is the input current or voltage, and s is the slope.

[0051] Since the absolute value of the input signal X can be relatively small, usually in dBm units, the absolute value of the output signal Y is also small for equation (1). For example, when the input power changes from -40dBm to -20dBm and s = 1, the voltage corresponding to Y only changes from 2.24mV to 22.4mV. The absolute value and dynamic range are extremely small, making it difficult for subsequent detection. Therefore, the RMS detector usually processes the result Y into a logarithmic value before outputting it:

[0052] Where Z is the actual output current or voltage of the RMS detector, k is the logarithmic slope, b is the logarithmic intercept, k' is the logarithmic slope after incorporating the square root operation, and b' is the logarithmic intercept after incorporating the linear slope s. The logarithms in this formula can also have other bases, as long as a logarithmic relationship exists.

[0053] When the subsequent stage adds logarithmic conversion, the square root operation in the RMS detector can be moved directly outside the logarithm and become part of the slope, eliminating the need for hardware implementation. The slope s mentioned above is added to the logarithmic intercept here to form a new logarithmic intercept, which no longer affects the slope of the output signal Z. The following description is based on this principle.

[0054] Since the RMS detector performs an averaging operation on the input signal, no matter how high the frequency of the input signal is, after averaging over a certain time window, the output signal will be close to DC and will only change slowly with changes in the mean value of the input signal.

[0055] Figure 4 shows a transistor-based square circuit. As shown in Figure 4, the square circuit includes four transistors Q1, Q2, Q3 and Q4, four resistors R connected to the four transistors respectively. E , capacitor C L , resistor R L1 and resistor R L2 , where: The bases of transistors Q3 and Q4 receive bias voltage V CM (i.e. the aforementioned bias voltage DC Bias), the bases of transistors Q1 and Q2 receive the bias voltage V CM (Square circuit has no input, see Figure 4,) or input signal (Square circuit has input, see Figure 5), where the input signal is differential input, respectively and (Wherein, V CM is the bias voltage, and are the negative phase signal and positive phase signal of the AC signal RF Input respectively), capacitor C L One end of the resistor R L1 One end of the transistor Q1, the collector of the transistor Q2 are connected as the positive phase output end of the square circuit, and the positive phase output voltage V OUT+ ; Among them, I OUT is the positive phase output current, the resistor R L1 Convert it into a positive output voltage V OUT+ .Resistor R L2 One end of the transistor Q3, the collector of the transistor Q4 are connected as the inverting output end of the square circuit, and the inverted output voltage V OUT- The resulting squared current is based on the assumption that the two transistors are completely aligned. However, in practice, due to process variations and other factors, the transistors Q1 / Q2 and Q3 / Q4 on the two paths are unlikely to be completely aligned, and a certain degree of mismatch is inevitable.

[0056] As shown in Figure 4, when there is no input to the square circuit, the bases of the four transistors all receive the bias voltage V CM , the output current of the square unit formed by transistors Q1 and Q2 is I B +I OS , the output current of the mirror square unit formed by transistors Q3 and Q4 is I B , there is already an I between the two currents in the square circuit OSAs an example, the offset circuit is equivalent to the positive phase output terminal. As shown in Figure 5, when the square circuit has an input, the output current of the square unit formed by transistors Q1 and Q2 is I B +I SQ +I OS , the output current of the mirror square unit formed by transistors Q3 and Q4 is I B The difference between the two currents contains not only the useful square current I SQ , also includes the offset current I OS Because of the existence of offset current, the sensitivity of the square circuit will be limited. For example, if the offset current is equivalent to the input offset voltage, this value will usually reach several millivolts (mV) or even tens of mV. Therefore, for signals with amplitudes less than 10mV or at the level of 10mV, the square current value obtained will be very inaccurate. B is the inverting output current, is the quiescent current, and the resistor R L2 Convert it into an inverting output voltage V OUT- According to the three-stage tube formula, I OUT with I B Subtracting the input voltage signal, we can get the current I SQ .

[0057] From the above, it can be seen that since the square unit and the mirror square unit include transistors, due to process deviation of the transistors, the difference between the output currents of the square unit and the mirror square unit is not only the square current I SQ , and the offset current I OS Because the offset current I OS The presence of , the sensitivity of the square circuit will be limited. In addition, the offset current I OS It will also change with temperature, and the changing offset current cannot be well suppressed.

[0058] In summary, due to the limitations of the square cell principle, its output signal dynamic range is strongly correlated with the input signal dynamic range. To detect an input signal in the 60dBm range, the output voltage / current will also vary by 120dB, or a factor of one million. If the upper limit of the output dynamic range is set to 1V, the lower limit of the output voltage will reach 1µV. Without additional mismatch treatment, the mismatch voltage may reach several millivolts, far exceeding the lower limit of the output voltage. If the lower limit voltage is increased to significantly exceed the square cell mismatch, for example, increasing the lower limit voltage to 10mV, the upper limit voltage will correspondingly increase to 10,000V, which is obviously unachievable.

[0059] It should be understood that the mismatch voltage or mismatch current is at DC, and the useful signal It is also at DC or very low frequency, so the mismatch voltage / current cannot be suppressed by traditional DC offset elimination circuit DCOC feedback, capacitor isolation and other methods, because these methods will also suppress the useful signal. inhibition.

[0060] Therefore, there are the following solutions to the mismatch problem between the two branches of the square circuit:

[0061] One solution involves measuring the output voltage with no input or with a known input signal amplitude, then manually adding an offset voltage to the input, adjusting the voltage to cancel the offset current. This method has several drawbacks: First, it requires measuring the output and manually adjusting the input offset voltage after the chip is manufactured. This process is relatively complex and, in mass-produced chips, incurs significant testing costs. Second, the offset current varies with the chip's operating temperature. This one-time calibration method can only cancel the offset current at a single temperature; once the temperature changes, the shifting offset current cannot be effectively suppressed. Therefore, it is desirable to achieve automatic offset current suppression at the circuit level, while also ensuring that the offset current can be effectively suppressed at different temperatures.

[0062] Another solution involves introducing a pre-positioned variable gain amplifier (VGA). By feeding the output of the squaring unit back to the control terminal of the VGA, the VGA converts the output to logarithmically while compressing the input power range of the squaring unit, thereby reducing the dynamic range requirement for the squaring unit. However, this solution does not reduce the mismatch; it simply adjusts the input range of the squaring unit to within the linear range of the squaring unit. However, due to the need for an RF signal amplifier, power consumption is extremely high, and the overall linear range of the system will be limited by the VGA.

[0063] Another solution is to introduce a chopper, which uses switches before and after the squaring unit to chop the mismatch voltage or current to a high frequency. When the subsequent stage performs averaging, the mismatch at the high frequency is filtered out, thereby achieving automatic mismatch suppression. However, since choppers usually use MOS or BJT switches, the parasitic capacitance of the switches may cause input RF leakage, affecting input matching. On the other hand, it may cause the drive clock of the chopper switch to feed through to the RF path, forming a noise floor, which in turn limits the dynamic range of the squaring unit. The drive clock of the chopper also requires additional power consumption.

[0064] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0065] In one embodiment of the present application, please refer to FIG6 , which is a schematic diagram of the structure of a calibrated and adaptable square circuit 10 provided in an embodiment of the present application. Referring to FIG6 , the square circuit 10 includes:

[0066] The square unit 41 is used to square the received AC signal. The square unit 41 receives the bias voltage DC Bias and the AC signal RF Input. The output end of the square unit 41 outputs a first signal. The first signal includes at least the aforementioned quiescent current I B and square current I SQ Mirror square unit 42 is used to receive the bias voltage DC Bias, the structure of the mirror square unit 42 is consistent with the structure of the square unit 41, the output end of the mirror square unit 42 outputs a second signal, the second signal is the static current I B (i.e., DC signal). The structure of the square unit 41 may include transistors Q1 to Q4 shown in FIG4 , and the structure of the mirror square unit 42 may include transistors Q1 to Q4 shown in FIG5 . At the same time, the first signal or the second signal also includes a mismatch current I OS .

[0067] The first current mirror structure is used to generate a third signal proportional to the first signal (current signal). The first current mirror structure includes a first input unit 11 and a first output unit 13. The first input unit 11 receives the first signal; the first output unit 13 is connected to the first input unit 11 and is used to mirror the first signal and output the third signal. The second current mirror structure is used to generate a fourth signal proportional to the second signal (current signal). The second current mirror structure includes a second input unit 12 and a second output unit 14. The second input unit 12 receives the second signal; the second output unit 14 is connected to the second input unit 12 and is used to mirror the second signal and output the fourth signal.

[0068] In the embodiment shown in FIG6 , the trimming unit 15 is configured to receive a control signal and, based on the control signal, adjust the mirror copy ratio of the second current mirror structure so that the difference between the DC component at the output of the first output unit 13 and the DC component at the output of the second output unit 14 is within a first range. The first range is a preset range, and when the difference is within the first range, the mismatch between the squaring unit and the mirrored squaring unit is negligible. The first range can be close to zero, and when the difference is zero, the mismatch between the squaring unit and the mirrored squaring unit is fully calibrated.

[0069] It should be noted that the squaring circuit 10 provided in the embodiment of the present application is calibrable, specifically for resolving the mismatch problem between the squaring unit and the mirror squaring unit in the RMS detector. Specifically, since the first input unit 11 and the first output unit 13 form a mirror transmission channel, the first signal is mirror-copied proportionally to generate a third signal, and the second input unit 12 and the second output unit 14 form a mirror transmission channel, the second signal is mirror-copied proportionally to generate a fourth signal, and the trimming unit 15 can adjust the mirror copy ratio of the fourth signal relative to the second signal. In this way, even if there is a mismatch between the DC voltage / current of the first signal and the second signal, the trimming unit 15 can make the DC voltage / current between the third signal and the fourth signal as similar as possible, so that the DC voltage at the two differential terminals of the operation module in the RMS detector can be accurately subtracted, ultimately obtaining a better detection result. At the same time, since the current mirror copies the first and second signals, these two signals are the output signals of the squaring unit 41 / mirror squaring unit 42, that is, the first and second signals contain the temperature characteristics of the squaring unit / mirror squaring unit 42. If the trimming unit 15 has the same device doping type as the second input unit 12 and the second output unit 14, then because the current of the second input unit 12 copied by the second output unit 14 includes the temperature characteristics of the mirror image square unit 42, the current copied by the second output unit 14 has the temperature characteristics of the mirror image square unit 42; if the trimming unit 15 and the second output unit 14 have the same device doping type, then the trimming unit 15 also copies the current of the second input unit 12, so the current output by the second input unit 12 includes the temperature characteristics of the square unit. Therefore, even if calibration is performed at a single temperature point, the calibration effect is still good after the operating temperature changes. Alternatively, if the device doping type of the trimming unit 15 and the second output unit 14 is different, an additional temperature control signal is required to perform multi-temperature point calibration. Alternatively, a current with temperature characteristics can be designed to achieve single-point calibration.

[0070] Furthermore, the equivalent size of the first input unit 11 (i.e., the width-to-length ratio of the transistor therein) is the same as the equivalent size of the second input unit 12, and the equivalent size of the first output unit 13 is the same as the equivalent size of the second output unit 14, that is, the basic replication ratio of the first output unit 13 and the basic replication ratio of the second output unit 14 are always the same, and the adjustment unit 15 can calculate the compensated DC voltage / current according to a one-to-one ratio to facilitate the calculation of the mirror ratio that the adjustment unit 15 needs to adjust.

[0071] Furthermore, referring to FIG6 , squaring circuit 10 further includes a first voltage conversion unit 16 and a second voltage conversion unit 17 . The first voltage conversion unit 16 is configured to convert the current signal output by the first output unit 13 into a voltage signal, and the second voltage conversion unit 17 is configured to convert the current signal output by the second output unit 14 into a voltage signal. The first voltage conversion unit 16 is connected to the output terminal of the first output unit 13, and the second voltage conversion unit 17 is connected to the output terminal of the second output unit 14. Specifically, the first voltage conversion unit 16 and the second voltage conversion unit 17 may be resistors. Referring to FIG6 , the first voltage conversion unit 16 includes a first resistor R1, and the second voltage conversion unit 17 includes a second resistor R2. The output terminal of the first output unit 13 is connected to the ground terminal via the first resistor R1, and the output terminal of the second output unit 14 is connected to the ground terminal via the second resistor R2. The resistance values ​​of the first resistor R1 and the second resistor R2 are both greater than or equal to 1 kilo-ohm.

[0072] In addition, the first voltage conversion unit 16 and the second voltage conversion unit 17 may also be diodes or bipolar junction transistors (BJTs) connected to diodes.

[0073] In the comparative scheme, the squaring circuit does not include the first current mirror structure, the second current mirror structure and the trimming unit. The squaring unit and the mirror squaring unit are directly connected to the load resistor (the function is similar to the first resistor R1 and the second resistor R2). Taking the output voltage range of the RMS detector as 1V~1μV as an example, if the direct output current of the squaring unit and the mirror squaring unit is 10mA~10nA, in order to achieve the corresponding voltage range, the load resistor connected to the squaring unit and the mirror squaring unit is about 100Ω, which is relatively small. If there is a certain deviation in the resistance of the load resistor, it will cause a greater impact. In this scheme, the above-mentioned current mirror (the first current mirror structure and the second current mirror structure) can be connected to the load resistor. The mirror ratio of the current mirror structure is set to 5:1 to 20:1 (for example, the current ratio of the first signal to the third signal, and the current ratio of the second signal to the fourth signal), for example, 10:1. If the current directly output by the square unit and the mirror square unit is 10mA to 10nA, the current range of the third signal and the fourth signal is stable at 1mA to 1nA. When the output voltage range of the RMS detector is set to 1V to 1μV, the resistance of the load resistor (the first resistor R1 and the second resistor R2) can be greater than or equal to 1kΩ. If there is a certain deviation in the resistance value of the load resistor, it will not cause a significant impact. In this case, the first resistor R1 and the second resistor R2 are easier to design and implement. For example, if several types of resistors with higher precision provided by the process are used, considering their block resistance, resistors of this resistance value can achieve acceptable matching accuracy within a relatively reasonable area. At the same time, even if there is a small amount of mismatch, the overall resistance value will not be greatly affected, and the impact of resistor mismatch on the result is reduced.

[0074] In some embodiments, referring to FIG6 , the first input unit 11 , the second input unit 12 , the first output unit 13 , and the second output unit 14 include a control terminal, a first terminal, and a second terminal, and selectively connect the first terminal and the second terminal based on a control terminal signal. The second terminal of the first input unit 11 receives the first signal, the second terminal of the first output unit 13 outputs the third signal, the second terminal of the second input unit 12 receives the second signal, and the second terminal of the second output unit 14 outputs the fourth signal. The control terminals of the first input unit 11 and the first output unit 13 are both connected to the second terminal of the first input unit 11, the control terminals of the second input unit 12 and the second output unit 14 are both connected to the second terminal of the second input unit 12, and the first terminals of the first input unit 11, the second input unit 12, the first output unit 13, and the second output unit 14 are all connected to a power supply voltage VDD. Thus, the first input unit 11 and the first output unit 13 simultaneously connect their first terminals and the second terminal, replicating the first signal into the third signal. The second input unit 12 and the second output unit 14 simultaneously connect their first terminals and the second terminal, replicating the second signal into the fourth signal. 7A , the first input unit 11 , the second input unit 12 , the first output unit 13 , and the second output unit 14 all include transistors.

[0075] In other embodiments, the mirror square unit 42 can also receive a bias voltage DC Bias + feedback voltage Feedback, where the feedback voltage refers to a voltage generated by other circuit modules of the square circuit that also affects the signal. Thus, the mirror square unit 42 can replicate the influencing factors caused by the feedback voltage, so that an accurate square result of the AC signal can be obtained after subtracting the third signal from the fourth signal.

[0076] Please refer to Figures 7A and 7B. In some embodiments, the first input unit 11, the second input unit 12, the first output unit 13 and the second output unit 14 each include a P-type transistor, and the control end, the first end and the second end of the first input unit 11 refer to the gate, source and drain of the included P-type transistor, respectively. Other units are similar.

[0077] In some embodiments, referring to FIG. 7B , the trimming unit 15 includes a plurality of first transistors ( FIG. 7B shows four as an example, numbered 21 a to 21 d ), each of which is connected to the second input unit 12 or the second output unit 14 . The trimming unit 15 is specifically configured to control the corresponding first transistor to be in an off state or an on state based on a control signal (not shown in FIG. 7B ). In the on state, the first transistor is used to increase the equivalent size of the transistor in the second output unit 14 . Specifically, in the on state, the control terminal of the first transistor is connected to the second current mirror structure, and the voltage level at the first node can adjust whether the first transistor is off or on, thereby changing the current magnitude of the fourth signal. In the off state, the control terminal of the first transistor is not connected to the second current mirror structure, and the current magnitude of the fourth signal is not changed.

[0078] Thus, when the first transistor is turned on, the second output unit 14 is connected in parallel with the first transistor in the working state, which is equivalent to increasing the equivalent size of the second output unit 14 of the second current mirror structure (i.e., the aspect ratio of the transistor gate). Simply put, the more first transistors in the working state, the higher the mirror copy ratio of the output signal of the current mirror relative to the input signal. For example, if all first transistors are in the off state, the DC voltage / DC current of the fourth signal = the DC voltage / DC current of the second signal × 100%; if one of the first transistors is in the working state and the remaining first transistors are in the on state, the DC voltage / DC current of the fourth signal = the DC voltage / DC current of the second signal × 120%. The above is only an example, and the specific ratio value also needs to consider the specific aspect ratio of the first transistors in the working state.

[0079] In the embodiment shown in FIG7B , the adjustment unit 15 further includes a plurality of first switches ( FIG7B shows four as an example, numbered 24 a to 24 d ). The number of the first switches is the same as the number of the first transistors. The first switches 24 a to 24 d may correspond one-to-one to the first transistors 21 a to 21 d . Each first switch is used to control the gate connection state of a first transistor. The first switches 24 a to 24 d connect the control terminal of the corresponding first transistor and the power supply voltage VDD, or connect the control terminal of the corresponding first transistor and the first node based on the control signal. The first node is a connection node between the second input unit and the second output unit, specifically the control terminal of the transistor in the second input unit 12 / second output unit 14.

[0080] In some embodiments, each of the first switches 24a-24d is a first single-pole double-throw (SPDT) switch, which can conveniently control the gate connection state of the first transistor. The first SPDT switch has a control terminal (not shown in FIG. 7B ), a fixed terminal s, a first gate terminal c1, and a second gate terminal c2. Based on a control terminal signal, the fixed terminal s and the second gate terminal c2 are connected to set the corresponding first transistor of the first SPDT switch to an active state, or based on a control terminal signal, the fixed terminal s and the first gate terminal c1 are connected to set the corresponding first transistor of the first SPDT switch to an off state. The control terminal of the first SPDT switch receives a control signal. The first gate terminal c1 of each of the first SPDT switches is connected to the power supply voltage VDD. The second gate terminal c2 of each first SPDT switch is connected to the first node and can be considered to receive the second signal. The fixed terminal s of each first SPDT switch is connected to the gate of a first transistor. If the first transistor is a PMOS transistor, the first terminal of the first transistor is connected to the power supply voltage VDD. The second terminal of the first transistor is connected to the output terminal of the second output unit 14.

[0081] Here, the number of first transistors is the same as the number of control signal Trim Code, for example, if there are 4 first transistors, the control signal is 4 bits. It should be understood that if the number of first transistors is more or less, the number of bits of the control signal can also be more or less.

[0082] In this way, if a control signal is in the first state (for example, a low level), the fixed end s of the first single-pole double-throw switch corresponding to the control signal is connected to the power supply voltage VDD, and the corresponding first transistor is turned off; if a control signal is in the second state (for example, a high level), the fixed end s of the first single-pole double-throw switch corresponding to the control signal is connected to the first node (that is, receives the second signal), that is, the second signal controls the current flowing through the first transistor, which is equivalent to the first transistor being connected in parallel with the P-type transistor in the second output unit 14, thereby increasing the width-to-length ratio of the P-type transistor in the second output unit 14.

[0083] In the embodiment shown in FIG. 7B , the square unit 41 outputs a first signal I1 , and the mirror square unit 42 outputs a second signal I2 . The first signal I1 = I B +I SQ +I OS , for I B is the quiescent current, I SQ is the square current, I OS is the offset current I OS , the second signal I2 = I B Assuming that the mirror ratios of the first current mirror structure and the second current mirror structure are both one to one, the current I30 output by the first output unit 13 is I1 = I B +ISQ +I OS , the current output by the second output unit 14 is I40=I2=I B .

[0084] The currents I41 to I44 output by the first transistors 21a to 21d are used to compensate for the offset current I OS , such as the offset current I OS A current I41 is needed for compensation. The control signal only needs to connect the fixed terminal s and the second gate terminal c2 of the first switch 24a, and connect the fixed terminal s and the first gate terminal c1 of the first switches 24b-24d. Then the current I4 after the second signal I2 and the currents I41-I44 are combined = I40 + I41. Therefore, I30-I4=(I B +I SQ +I OS )-(I B +I41)=I SQ It can be seen that the offset current I in the first signal I1 and the second signal I2 OS are canceled. When I OS As the temperature changes, I41 as a mirror current also changes with the temperature, so I41 can dynamically compensate for the mismatch problem.

[0085] Please refer to Figure 8, which provides a feasible structure for a single-pole double-throw switch. As shown in Figure 8, the single-pole double-throw switch includes an inverter, a P-type transistor M11, and a P-type transistor M12. The control terminal of the single-pole double-throw switch is connected to the control terminal of the P-type transistor M11, and the control terminal of the single-pole double-throw switch is connected to the control terminal of the P-type transistor M12 via the inverter. The P-type transistor M11 is connected in series between the first gate terminal c1 and the fixed terminal s, and the P-type transistor M12 is connected in series between the second gate terminal c2 and the fixed terminal s. At this time, if the control terminal signal is low, the P-type transistor M11 is turned on and the P-type transistor M12 is turned off, connecting the first gate terminal c1 to the fixed terminal s. If the control terminal signal is high, the P-type transistor M11 is turned off and the P-type transistor M12 is turned on, connecting the second gate terminal c2 to the fixed terminal s. The above is only an example. The single-pole double-throw switch can also be implemented using a CMOS transmission gate.

[0086] However, if only the first transistor is provided, the mirror copy ratio of the second output unit 14 can only be adjusted unidirectionally in the direction of increasing (or decreasing). In order to enable the mirror copy ratio of the second output unit 14 to be adjusted bidirectionally in the directions of increasing and decreasing, the following multiple optional methods are provided:

[0087] Therefore, as shown in Figure 7B, squaring circuit 10 also includes a dummy unit for increasing the equivalent size of the transistors in first input unit 11 or first output unit 13 to achieve bidirectional adjustment. The dummy unit includes at least one second transistor 22. When the first transistor is connected to second input unit 12, the first transistor is used to increase the equivalent size of the transistors in second input unit 12, and the second transistor 22 is used to increase the equivalent size of the transistors in first input unit 11, thereby achieving bidirectional adjustment. When the first transistor is connected to second output unit 14, the first transistor is used to increase the equivalent size of the transistors in second output unit 14, and the second transistor 22 is used to increase the equivalent size of the transistors in first output unit 13, thereby achieving bidirectional adjustment.

[0088] Please refer to Figure 7B. In some embodiments, the second transistor 22 is connected in parallel with the first output unit 13, the control end of the second transistor 22 is connected to the control end of the transistor in the first output unit 13, the first end (drain) of the second transistor 22 is connected to the first end of the transistor in the first output unit 13, and the second end (source) of the second transistor 22 is connected to the second end of the transistor in the first output unit 13. The second transistor 22 is used to increase the equivalent size of the transistor in the first output unit 13 for bidirectional adjustment of the mirror replication ratio for more precise adjustment; wherein, the transistor type of the second transistor 22 is the same as the transistor type of the first transistor.

[0089] Thus, the mirror copy ratio of the first current mirror structure is denoted as A1. Since the second transistor is connected in parallel with the first output unit 13, A1>100%. By controlling the operating state of the first transistor through the control signal, the mirror copy ratio of the second current mirror structure can be adjusted between 100% and A2, with A2>A1. Therefore, the mirror copy ratio of the second current mirror structure can be adjusted in both directions, either toward a direction greater than or less than the mirror copy ratio of the first current mirror structure, to achieve bidirectional calibration.

[0090] In an optional embodiment, referring to FIG7B , the width-to-length ratio of the first first transistor 21 a: the width-to-length ratio of the second first transistor 21 b: the width-to-length ratio of the third first transistor 21 c: the width-to-length ratio of the fourth first transistor 21 d = 1:2:4:8, and the width-to-length ratio of the second transistor 22 = the width-to-length ratio of the fourth first transistor 21 d.

[0091] It should be understood that, in the default state, the control signal Trim Code = 1000, i.e., the fourth first transistor is in an operating state and the other three first transistors are in an off state. Since the second transistor 22 is always in an operating state, i.e., the operating second transistor 22 and the fourth first transistor cancel each other out, without considering manufacturing process deviations, the mirror copy ratio of the third signal relative to the first signal is equal to the mirror copy ratio of the fourth signal relative to the second signal.

[0092] If the control signal Trim Code is less than 1000, the width-to-length ratio of the first transistor in the working state is smaller than the width-to-length ratio of the second transistor 22, so that the mirror copy ratio of the third signal relative to the first signal is greater than the mirror copy ratio of the fourth signal relative to the second signal;

[0093] If the control signal Trim Code>1000, the width-to-length ratio of the working first transistor is greater than that of the second transistor 22, so that the mirror copy ratio of the third signal to the first signal is less than the mirror copy ratio of the fourth signal to the second signal.

[0094] At the same time, since the width-to-length ratio of the four first transistors is multiplied by 2 times, the control signal Trim Code can provide 2 4 The ratio of the mirror copy is adjustable, but this does not constitute a relevant limitation. The width-to-length ratio of the four first transistors can also be other ratios.

[0095] Thus, the mirror copy ratio of the second output unit 14 can be adjusted in both directions, that is, toward increasing and decreasing.

[0096] It should be understood that due to device non-idealities, leakage current may exist even when the first transistor is in the off state, thereby affecting the trimming effect. In some embodiments, referring to FIG. 7B , the squaring circuit 10 further includes a third transistor 23, which is connected to the first output unit 13. The first and second terminals of the third transistor 23 are respectively connected to the power supply voltage and the output terminal of the first output unit 13. The control terminal of the third transistor is connected to the power supply voltage, and the third transistor 23 is in the off state. Exemplarily, the third transistor 23 is a P-type transistor, so its control terminal can be connected to the power supply voltage VDD, thereby keeping it in a normally off state.

[0097] In this way, the third transistor 23 is always in the off state, so as to offset the leakage current when the first transistor is in the off state.

[0098] In an optional embodiment, the width-to-length ratio of the third transistor 23 = the sum of the width-to-length ratios of all the first transistors - the width-to-length ratio of the second transistor 22 .

[0099] As previously mentioned, the width-to-length ratio of the second transistor 22 equals the width-to-length ratio of the first transistor 21d, so the width-to-length ratio of the third transistor 23 equals the sum of the width-to-length ratios of the first transistors 21a through 21c. Thus, in the default state, the control signal Trim Code = 1000. For the first current mirror structure, the second transistor 22 is turned off, and for the second current mirror structure, the first transistors 21a through 20c are turned off. The third transistor 23 can offset the leakage current of the first transistors 20a through 20c that are in the off state.

[0100] In the above description, the structure of the squaring circuit of Figures 7A and 7B adopts the current mirror structure shown in Figure 9(a). In the first variant, the following current mirror structures can also be used: Please refer to Figure 9(b), the first input unit 11, the second input unit 12, the first output unit 13, and the second output unit 14 each include a P-type transistor and a resistor, the control end and the second end of the first input unit 11 respectively refer to the gate and drain of the included P-type transistor, and the first end of the first input unit 11 refers to the end of the included resistor away from the P-type transistor. The other units are similar. Referring to FIG9(c), each of the first input unit 11, the second input unit 12, the first output unit 13, and the second output unit 14 includes two P-type transistors. The first input unit 11 has two control terminals, specifically the gates of the two P-type transistors. The first terminal of the first input unit 11 refers to the source of the first P-type transistor (the P-type transistor closer to the power supply VDD), and the second terminal of the first input unit 11 refers to the drain of the second P-type transistor (the P-type transistor farther from the power supply VDD). The other units are similar. Referring to FIG9(d), each of the first input unit 11, the second input unit 12, the first output unit 13, and the second output unit 14 includes two P-type transistors and a resistor. The control terminal of the first input unit 11 refers to the gate of the second P-type transistor, the first terminal of the first input unit 11 refers to the source of the first P-type transistor (the P-type transistor closer to the power supply VDD), and the second terminal of the first input unit 11 refers to the end of the resistor farther from the P-type transistor. The other units are similar.

[0101] In the preceding and following content of this application, P-type transistors can be MOS or BJT. In addition, the above are all current mirrors composed mainly of P-type transistors, and current mirrors composed mainly of N-type transistors can also be used. It should be noted that the structure of the adjustment unit 15 can refer to the structure adopted by the current mirror.

[0102] In the square circuit 10 shown in FIG7B , a plurality of first transistors 21a to 21d are connected in parallel with the second output unit 14. In a second variant, such as the case of FIG10 , the plurality of first transistors 21a to 21d can also be connected in series with the plurality of second output units 14, and the switching states of the first transistors 21a to 21d depend on the corresponding trimming signals Trim[0]-Trim[3], where Trim[0]-Trim[3] are the trimming signals Trim Code on the gates of the first transistors 21a to 21d, respectively, and the mirror ratio can also be adjusted. There can be a second output unit 14 without a first transistor connected in series, or at least one of the first transistors 21a to 21d can be in an on state.

[0103] In the squaring circuit 10 shown in FIG7B , a dummy unit is additionally provided to achieve bidirectional current regulation. In a third variation, the dummy unit may be omitted, so that the size of the transistor in the first output unit 13 is larger than the size of the transistor in the second output unit 14, which can also achieve bidirectional current regulation.

[0104] In the square circuit 10 shown in FIG7B , the plurality of first transistors 21 a to 21 d in the trimming unit 15 are respectively connected to the second output unit 14. In the fourth variant, the plurality of first transistors in the trimming unit 15 are respectively connected to the second input unit 12. Specifically, there are two possibilities: (1) the plurality of first transistors are respectively connected in parallel to the second input unit 12, the control end of the first transistor is selectively connected (based on the control of the control signal) to the control end of the second input unit 12 or the power supply voltage VDD via the first switch, the first end and the second end of the first transistor are respectively connected to the power supply voltage VDD and the output end of the second input unit 12 (i.e., the second end of the second input unit 12), and the control end of the third transistor is connected to the power supply voltage VDD, and the first end and the second end of the third transistor 23 are respectively connected to the power supply voltage and the output end of the first input unit 11 (i.e., the second end of the first input unit 11); (2) the plurality of first transistors are respectively connected in series to the second input unit 12. In this case, the second input unit 12 is provided with a plurality of first transistors, each of which is connected in series between one second input unit 12 and the power supply voltage, and the on / off state of the first transistor depends on the control signal.

[0105] Furthermore, the adjustment unit 15 is specifically configured to control the corresponding first transistor to be in an off state or an operating state based on the control signal; wherein, in the operating state, the first transistor is used to increase the equivalent size of the transistor in the second input unit 12.

[0106] Furthermore, in the dummy unit, a second transistor 22 is connected in parallel with the first input unit 11, and the second transistor is used to increase the equivalent size of the transistor in the first input unit 11. A third transistor 23 is connected in parallel with the first input unit 11, and the third transistor 23 is in the off state. Alternatively, in the absence of a dummy unit, the size of the transistor in the first input unit 11 is larger than the size of the transistor in the second input unit 12.

[0107] In the square circuit 10 shown in FIG7B , the multiple first transistors in the trimming unit 15 are P-type transistors. In a fifth variant, see FIG11 , the trimming unit 15 can be constructed using N-type transistors. The trimming unit 15 constructed using N-type transistors is described in detail below. Referring to FIG11 , the trimming unit 15 includes multiple first transistors (N-type) ( FIG11 shows four as an example, numbered 31 a to 31 d). The first end of each first transistor (N-type) is connected to the output end of the second output unit 14 (or the input end of the second input unit 12), and the second end of each first transistor (N-type) is connected to the ground end. The trimming unit 15 is specifically configured to control the corresponding first transistor (N-type) to be in an off state or an operating state based on multiple control signals. When the first transistor (N-type) is in the operating state, the gate of the first transistor (N-type) receives a bias signal Ibias.

[0108] In some embodiments, referring to FIG11 , the trimming unit 15 further includes a plurality of second switches ( FIG11 shows four as an example, numbered 34 a through 34 d) and a bias transistor 35. The second switches 34 a through 34 d may correspond one-to-one with a first transistor (N-type, numbered 31 a through 31 d), with the number of second switches being the same as the number of first transistors. Each second switch is configured to control the gate connection state of a first transistor. Based on a control signal, the second switches 34 a through 34 d connect the control terminal of the corresponding first transistor to the control terminal of the bias transistor (which receives the bias signal I bias ), or connect the control terminal of the bias transistor to ground.

[0109] Exemplarily, each of the second switches 34a-34d is a second single-pole double-throw (SPDT) switch, which can conveniently control the control terminal of the bias transistor 35 to be connected to the control terminal of the first transistor or to ground. The gate and drain of the bias transistor 35, as well as the fixed terminal s of each second SPDT switch, receive a bias signal Ibias. The source of the bias transistor 35 is connected to ground. The first select terminal c1 of a second SPDT switch is connected to the gate of a first transistor (N-type), and the second select terminal c2 of the second SPDT switch is connected to ground. Here, the bias transistor 35 is N-type doped.

[0110] In some embodiments, referring to FIG11 , the trimming unit 15 further includes a second transistor (N-type) 32, the drain of the second transistor (N-type) 32 being connected to the output end of the first output unit 13, the source of the second transistor (N-type) 32 being connected to the ground end, and the gate of the second transistor (N-type) 32 receiving a bias signal Ibias for achieving bidirectional adjustment; the trimming unit 15 further includes a third transistor (N-type) 33, the drain of the third transistor (N-type) 33 being connected to the output end of the first output unit 13, the source of the third transistor (N-type) 33 being connected to the ground end, and the gate of the third transistor (N-type) 33 being connected to the ground end for offsetting the leakage current in the off state.

[0111] The embodiment of the present application provides a square circuit 10, which introduces two sets of current mirrors, a first input unit 11 / first output unit 13 and a second input unit 12 / second output unit 14, to adjust the current of the output final load resistor, thereby making the resistance design of the load resistor (i.e., the first resistor R1 and the second resistor R2) more flexible. At the same time, the dynamic range of the output port can be reduced by cooperating with the segmentation technology, thereby reducing the design difficulty; the introduction of the adjustment unit adjusts the mirror copy ratio of the second input unit / second output unit current mirror set, thereby solving the mismatch problem of the front square unit, with a simple design, extremely low power consumption, and no impact on the characteristics of the RF input port; at the same time, due to the introduction of the adjustment unit, the current mirror structure, The mismatch between the trimming unit itself, the first resistor R1 and the second resistor R2 can be calibrated and eliminated at the same time by this structure; when a P-type transistor is used, the trimming unit 15 can reuse the temperature compensation temperature characteristics of the square unit to dynamically compensate for the mismatch problem of the square unit during temperature changes. Therefore, only single-temperature reading point calibration is required during testing, saving cost and calibration time; mismatch calibration only requires detecting the output of the post-stage logarithmic amplifier, and does not require additional pads to monitor internal nodes. The test method is simple and saves chip area. In addition, the post-stage logarithmic amplifier is used to convert the originally small and difficult-to-measure voltage into a voltage with a reasonable variation range, reducing the requirements for the accuracy of the test instrument; calibration does not require RF signal input, and the requirements for test equipment and site are relaxed.

[0112] In yet another embodiment of the present application, please refer to FIG12 , which is a schematic diagram of the structure of an RMS detector 40 provided in an embodiment of the present application. Referring to FIG12 , RMS detector 40 includes the aforementioned squaring circuit 10, as well as an operation module 44 and a logarithmic converter 45 . Operation module 44 is configured to perform a subtraction operation on the third signal and the fourth signal to generate a fifth signal. Logarithmic converter 45 is connected to operation module 44 and configured to perform a logarithmic conversion on the fifth signal to generate a detection result signal, Iout.

[0113] It should be noted that the fourth signal is a static current signal (i.e., a DC signal), the third signal is square information and also contains a DC bias component, and the subtraction operation specifically refers to: using the fourth signal to offset the DC component in the third signal to generate the fifth signal, that is, the fifth signal = third signal - fourth signal.

[0114] 7B , 10 , and 11 , the RMS detector 40 further includes an averaging capacitor 204 connected in series between the input terminal of the first input unit 11 and the ground terminal. It should be understood that the averaging capacitor 204 is used to implement an averaging operation. Thus, the averaging operation and the squaring operation are performed together, making the overall current more stable and subsequent processing more accurate.

[0115] In some other embodiments, the averaging capacitor 204 may also be connected in series between the output terminal of the operation module 44 and the ground terminal. Please refer to FIG. 3 for further understanding.

[0116] It should be noted that the third signal and the fourth signal respectively enter the two differential terminals of the operation module 44, and the DC voltage / current in the third signal and the fourth signal can be considered to be the same, so they cancel each other out to generate the fifth signal. That is, the fifth signal can be regarded as the signal generated by the RMS detector performing square and averaging operations on the RF input signal. The fifth signal is logarithmically transformed to generate the detection result signal Iout, thereby representing the root mean square value (or power value) output of the RF input signal.

[0117] In related art, the calibration method employed may route the output signal voltage VOUT = (Vout+) - (Vout-) off-chip via a pad. Calibration is then performed by directly measuring the output signal voltage VOUT. To achieve a lower square unit dynamic range lower limit, the calibration step size is typically small, enabling more precise calibration. This results in a small change in the voltage at VOUT per unit step size of the control signal. Direct measurement requires high instrument precision, making accurate detection difficult.

[0118] In the embodiment of the present application, considering that in the actual circuit, the square circuit 10 is usually connected to the detection logarithmic amplifier to realize the logarithmic to linear function, when the square circuit 10 is trimmed, the external tester inputs the control signal TRIM Code directly or through an interface such as a serial peripheral interface (SPI), and scans the control signal TRIM Code from 0000 to the upper limit. If the range and step size of the designed control signal are reasonable, the output voltage change of the post-stage detection logarithmic amplifier will be as shown in Figure 13. The part parallel to the X-axis is the area where the VOUT voltage input to the logarithmic amplifier is less than the lower limit of the logarithmic amplifier input range, that is, the area where VOUT is smaller. This area will move left and right with the mismatch of the square unit, and the Y-axis coordinate will also be different from the characteristics of the post-stage logarithmic amplifier, that is, the curves obtained by scanning different chips will be different, but the feature of being parallel to the X-axis always exists. The tester detects the logarithmic amplifier output, draws this curve, and selects the X-axis coordinate value corresponding to the midpoint of the area parallel to the X-axis as the optimal TRIM Code under the current design. Using this TRIM code to control the conduction state of the single-pole double-throw switch can achieve the optimal lower limit of the dynamic range. This TRIM code is then fixed in the chip by writing it into the anti-fuse (E-FUSE), completing the calibration during the test and verification phase.

[0119] An embodiment of the present application provides a root mean square detector 40. To address the mismatch problem between a squaring unit 41 and a mirror squaring unit 42, a squaring circuit 10 is used to calibrate the first signal and the second signal. The squaring circuit 10 includes two sets of current mirrors, namely a first input unit 11 / first output unit 13 and a second input unit 12 / second output unit 14, which adjust the current outputted to the final load resistor, thereby making the resistance design of the load resistor (i.e., the first resistor and the second resistor) more flexible and reducing the design difficulty. A trimming unit 15 is introduced to adjust the mirror copy ratio of the current mirror set of the second input unit / second output unit, thereby addressing the mismatch problem of the preceding squaring unit. The design is simple, power consumption is extremely low, and the characteristics of the RF input port are not affected. At the same time, due to the introduction of the trimming unit, the mismatch between the current mirror structure of the squaring circuit itself, the trimming unit itself, the first resistor, and the second resistor itself can be simultaneously calibrated and eliminated by this structure. The structure is simple, the effect is good, and the requirements for test equipment and site are relaxed.

[0120] In yet another embodiment of the present application, the first current mirror structure may receive the second signal, and the second current mirror structure may receive the first signal, thereby also achieving the purpose of accurate measurement.

[0121] The above are only preferred embodiments of the present application and are not intended to limit the scope of protection of the present application. It should be noted that, in the present application, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element. The above serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined to obtain new method embodiments if there is no conflict. The features disclosed in the several product embodiments provided in this application can be arbitrarily combined to obtain new product embodiments if there is no conflict. The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined to obtain new method embodiments or device embodiments if there is no conflict. The above is only a specific implementation method of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this application, which should be covered by the protection scope of the present application.

Claims

1. A calibrable and adaptable square circuit, characterized in that: include: a squaring unit, configured to square a received AC signal, the squaring unit receiving a bias voltage and the AC signal, and an output terminal of the squaring unit outputting a first signal; a mirror square unit, configured to receive the bias voltage, wherein the structure of the mirror square unit is consistent with that of the square unit, and an output end of the mirror square unit outputs a second signal, wherein the second signal is a static current; a first current mirror structure and a second current mirror structure, wherein the first current mirror structure includes a first input unit and a first output unit connected to each other, and the second current mirror structure includes a second input unit and a second output unit connected to each other; wherein the first input unit receives the first signal, and the first output unit is used to mirror the first signal and output a third signal, and the second input unit receives the second signal, and the second output unit is used to mirror the second signal and output a fourth signal; or, the first input unit receives the second signal, and the first output unit is used to mirror the second signal and output a third signal, and the second input unit receives the first signal, and the second output unit is used to mirror the first signal and output a fourth signal; The trimming unit is configured to receive a control signal and adjust the mirror copy ratio of the first current mirror structure or the second current mirror structure based on the control signal.

2. The squaring circuit according to claim 1, wherein: The trimming unit includes a plurality of first transistors, and the plurality of first transistors are respectively connected to the second input unit or the second output unit; The first transistor is configured to be in an off state or an operating state based on a received control signal; in the operating state, the control end of the first transistor is connected to a first node, the first node is a connection node between the second input unit and the second output unit, and the first transistor is used to increase the equivalent size of the transistor in the second input unit or the second output unit.

3. The squaring circuit according to claim 2, wherein: A plurality of first transistors are respectively connected in parallel to the second input unit or the second output unit.

4. The squaring circuit according to claim 3, wherein: The first transistor is a PMOS transistor, and a first end of the first transistor is connected to a power supply voltage; when a plurality of the first transistors are respectively connected in parallel with the second input unit, a second end of the first transistor is connected to an output end of the second input unit; when a plurality of the first transistors are respectively connected in parallel with the second output unit, a second end of the first transistor is connected to an output end of the second output unit; The adjustment unit also includes multiple first switches, which, based on the control signal, connect the control end of the corresponding first transistor to the power supply voltage, or connect the control end of the corresponding first transistor to the first node, where the first node is the connection node between the second input unit and the second output unit.

5. The squaring circuit according to claim 4, characterized in that The first switch is a first single-pole double-throw switch.

6. The squaring circuit according to claim 3, wherein: The first transistor is an NMOS transistor, a first terminal of the first transistor is grounded, and when a plurality of the first transistors are respectively connected in parallel with the second input unit, a second terminal of the first transistor is connected to an output terminal of the second input unit; when a plurality of the first transistors are respectively connected in parallel with the second output unit, a second terminal of the first transistor is connected to an output terminal of the second output unit; The trimming unit further includes a second switch and a bias transistor, wherein a first terminal of the bias transistor receives a bias signal, and a second terminal of the bias transistor is connected to a ground terminal; The second switch connects the control terminal of the bias transistor and the control terminal of the first transistor, or connects the control terminal of the bias transistor and ground based on the control signal.

7. The squaring circuit according to claim 6, wherein: The second switch is a second single-pole double-throw switch.

8. The squaring circuit according to claim 2, wherein: Also included is a dummy unit, configured to increase the equivalent size of a transistor in the first input unit or the first output unit; The dummy unit includes at least one second transistor; When the first transistor is connected to the second input unit, the second transistor is used to increase the equivalent size of the transistor in the first input unit; When the first transistor is connected to the second output unit, the second transistor is used to increase the equivalent size of the transistor in the first output unit.

9. The squaring circuit according to claim 8, wherein: The first transistor is connected to the second input unit, the second transistor is connected to the first input unit, and the second transistor is connected in parallel with the first input unit; or the first transistor is connected to the second output unit, the second transistor is connected to the first output unit, and the second transistor is connected in parallel with the first output unit; The transistor type of the second transistor is the same as the transistor type of the first transistor.

10. The squaring circuit according to claim 8, wherein: Also including a third transistor; The first transistor is connected to the second input unit, the first end and the second end of the third transistor are respectively connected to the power supply voltage and the output end of the first input unit, and the control end of the third transistor is connected to the power supply voltage; alternatively, the first transistor is connected to the second output unit, the first end and the second end of the third transistor are respectively connected to the power supply voltage and the output end connected to the first output unit, and the control end of the third transistor is connected to the power supply voltage.

11. The squaring circuit according to claim 2, wherein: The first transistor is connected to the second input unit, and the size of the transistor in the first input unit is larger than the size of the transistor in the second input unit; or, The first transistor is connected to the second output unit, and the size of the transistor in the first output unit is larger than the size of the transistor in the second output unit.

12. The squaring circuit according to claim 1, wherein: The square circuit further includes a first voltage conversion unit and a second voltage conversion unit; the first voltage conversion unit is connected to the output end of the first output unit, and the second voltage conversion unit is connected to the output end of the second output unit.

13. The squaring circuit according to claim 12, wherein: The first voltage conversion unit includes a first resistor, and the second voltage conversion unit includes a second resistor; the output terminal of the first output unit is connected to the ground terminal through the first resistor, and the output terminal of the second output unit is connected to the ground terminal through the second resistor; The resistance of the first resistor and the second resistor are both greater than or equal to 1 kilo-ohm.

14. The squaring circuit according to claim 1, wherein: The first input unit, the second input unit, the first output unit and the second output unit each include a control terminal, a first terminal and a second terminal, and selectively conduct the first terminal and the second terminal based on a signal from the control terminal; The second end of the first input unit receives the first signal, the second end of the first output unit outputs the third signal, the control end of the second input unit receives the second signal, the second end of the second output unit outputs the fourth signal, the control end of the first input unit and the control end of the first output unit are both connected to the second end of the first input unit, the control end of the second input unit and the control end of the second output unit are both connected to the second end of the second input unit, and the first end of the first input unit, the first end of the second input unit, the first end of the first input unit and the first end of the second input unit are all connected to the power supply voltage.

15. A root mean square detector, characterized in that: The root mean square detector comprises a squaring circuit as claimed in any one of claims 1 to 14.

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