Display device including demultiplexer having different numbers of output channels

Abstract

A display device including different demultiplexers configured to have different numbers of output channels is disclosed. A time constant of a data line connected to a demultiplexer having a smaller number of output channels is greater than a time constant of a data line connected to a demultiplexer having a larger number of output channels.

Description

A display device comprising demultiplexers having different numbers of output channels

[0001] The present invention relates to a display device that supplies a data voltage through a signal control technique utilizing a demultiplexer, and more particularly, to a technique for utilizing a plurality of different demultiplexers having different numbers of output channels.

[0002] A display panel system consists of several components that convert image data received from an external image processor to a display panel's type and characteristics, forming the desired image. Key components include a timing controller (TCON), a source driver, and a pixel unit. The timing controller generates digital data and transmits it to the source driver, which then converts the data into an analog signal and supplies it to the pixel unit. Additionally, a power supply and gate driver may be included.

[0003] OLED displays are a display technology based on organic light-emitting diodes (OLEDs). Their self-luminous nature allows them to deliver vivid image quality without a backlight. These displays are affected by factors such as power consumption, brightness uniformity, and color expression, depending on the pixel configuration and operating method. Some OLED displays utilize signal control techniques utilizing demultiplexers to efficiently supply data voltage and optimize timing signals to improve operating performance.

[0004] For small and medium-sized panels, a single source driver is typically used. However, for large panels, multiple source drivers are deployed to drive a wide area of ​​the panel evenly, with data transmitted from the timing controller to each source driver. As the panel size increases, the connection distance between the panel and the driver increases, becoming shorter in the center and longer towards the edges. This results in increased wiring resistance and parasitic capacitance near the panel edges.

[0005] In high-resolution displays, the number of source channels that must be driven simultaneously increases, so a method of applying time-division driving is used by placing a demultiplexer between the source driver and the panel. In other words, a single source driver sequentially controls multiple panel drive lines over time. However, the wiring from the panel driver to the pixel unit has an RC time constant (τ) composed of resistors and capacitors, which is a critical factor in determining the data charging rate. If the RC time constant is large, charging may be incomplete, which can cause problems such as screen smudges or vertical lines.

[0006] Conventional methods have employed digital algorithms to compensate for screen noise caused by charging rate variations, or physical methods such as increasing wiring width to reduce resistance. However, digital algorithms require individual compensation for each panel's characteristics, which complicates the circuitry. Furthermore, increasing wiring width reduces the effective screen area.

[0007] The present invention provides a technology for optimizing the configuration and operation of a demultiplexer so that a sufficient data voltage application time is secured for a group of data lines having a large time constant, and so that there is no waste of data voltage application time for a group of data lines having a small time constant, by taking into account different time constants of data lines having different lengths.

[0008] <Structure of the display device>

[0009] The T-CON (Timing Controller) is a control device that drives the display panel. It analyzes the image signal and converts it so that it can be displayed on the panel. It can be viewed as the central control unit responsible for signal coordination of the display system. The role of the T-CON is to convert the input image data (RGB or LVDS, eDP signal) to suit the display and provide appropriate timing signals to the source driver and gate driver. It also generates clock signals and synchronization signals for pixel driving and performs resolution and frame scanning control. The input data of the T-CON are digital image signals and control signals provided by the CPU or GPU. These are generally provided in formats such as LVDS (Low-Voltage Differential Signaling), eDP (Embedded DisplayPort), and HDMI, and include not only pixel data but also clock signals and synchronization signals. The output data of the T-CON are pixel data and timing signals transmitted to the source driver and gate driver. The source driver provides RGB data, clock signals, and control signals, while the gate driver provides scan signals and gate drive signals for row selection. The input data of the T-CON is provided from the CPU or GPU, and the output data is transmitted to the source driver and gate driver.

[0010] The source driver is a circuit that supplies voltage to the data lines of the display panel to drive individual pixels. It converts digital pixel data received from the T-CON into a voltage signal and then supplies it to the data lines in each column direction of the panel. The role of the source driver is to convert the image data provided from the T-CON into a voltage signal to determine the color of the pixel. It can also perform a signal compensation function to control the data transmission speed and maintain consistent image quality. The input data of the source driver is RGB pixel data, clock signal, and control signal provided by the T-CON. The output data of the source driver is the pixel voltage output to the data lines of each column, which determines the color of each pixel. The input data of the source driver is provided by the T-CON, and the output data is transmitted to the data lines of the panel.

[0011] Data lines are arranged in the column direction within the display panel and are electrical paths that transmit pixel data (RGB voltage) provided by the source driver to each pixel. Typically, data lines extend vertically across the panel, and the number of data lines increases as the resolution increases. The role of the data lines is to supply pixel data output from the source driver to the pixels. Through this, individual pixels receive voltage to express a specific color. The input data of the data lines is the pixel voltage (RGB signal) provided by the source driver, and this is transmitted to the subpixel (R, G, B) electrodes of each pixel. The output data of the data lines is a voltage signal supplied to the subpixel transistor (TFT) of the pixel. Through this, each pixel emits light or adjusts its transmittance according to the given voltage. The input data of the data lines is provided by the source driver, and the output data is transmitted to each pixel (pixel) of the panel.

[0012] A demultiplexer (Demux) is a circuit that time-divides and distributes data output from a single source driver into multiple data lines. This allows for a smaller number of source drivers to drive more data lines. The role of the demultiplexer is to temporally divide the pixel data provided by the source driver and output it to multiple data lines. This allows for reducing the number of source drivers while maintaining high resolution. The input data of the demultiplexer is the pixel voltage (RGB signal) provided by the source driver. The output data of the demultiplexer is the time-divided pixel signal distributed to each data line. The input data of the demultiplexer is provided by the source driver, and the output data is transmitted to the data lines of the panel.

[0013] The gate driver is a circuit that controls the gate lines in units of rows of the panel. Based on the synchronization signal provided by the T-CON, the gate line of a specific row is activated so that the pixels of the corresponding row can receive data provided by the source driver. The role of the gate driver is to sequentially send row path selection signals based on the control signal received from the T-CON. The input data of the gate driver is the timing signal and gate drive signal provided by the T-CON. The output data of the gate driver is the row path selection signal that activates the gate line. The input data of the gate driver is provided by the T-CON, and the output data is transmitted to the gate lines of the panel.

[0014] Gate lines are electrical paths arranged in the row direction within the display panel and serve to select pixels in a specific row using signals provided by the gate driver. Gate lines generally extend in the horizontal direction of the panel. The role of the gate lines is to activate a specific row using signals provided by the gate driver, so that the pixels in the corresponding row can receive voltage from the data line. The input data of the gate line is a scan signal (row path selection signal) provided by the gate driver. The output data of the gate line is a signal that activates the TFT of the corresponding row. The input data of the gate line is provided by the gate driver, and the output data is transmitted to individual pixels (TFTs) of the panel.

[0015] The panel consists of pixels (TFT, OLED, LCD cells, etc.) located at the intersection of data lines and gate lines. The data lines supply voltage across the pixels' columns, while the gate lines transmit switching signals across the pixels' rows. This allows individual pixels to be controlled to display the desired color.

[0016] <Data line wiring>

[0017] In OLED display panels, the data lines extending from the source driver to each pixel are directly connected to the wiring section, a crucial path for transmitting electrical signals within the panel. These data lines transmit pixel data output from the source driver to individual subpixels (R, G, B), and their lengths vary depending on the panel's resolution and size. In particular, the wiring structure of the data lines in OLED panels is considered a crucial factor in determining display performance and signal quality.

[0018] The physical length of the wiring section of an OLED panel varies depending on the panel size and design. Typically, the source driver is located at the top or side of the panel, and the data lines extend in the column direction (vertical direction) of the panel. Therefore, as the panel height increases, the length of the data lines also increases. For example, in a 6-inch smartphone OLED panel, the data lines are only a few centimeters long, but in a 65-inch TV OLED panel, they can extend to tens of centimeters or more.

[0019] In large OLED displays, longer data lines can lead to degraded signal transmission speed and quality. To address this, low-resistance wiring capable of high-speed signal transmission is used, or data lines are split to accommodate multiple source drivers. Furthermore, longer data lines can lead to signal delay and voltage drop issues, so compensation circuits and multi-layer interconnect technologies are often employed to minimize these issues.

[0020] Typically, OLED panels utilize Chip-On-Film (COF) or Chip-On-Glass (COG) technology to optimize wiring length, placing the source driver near the panel edge. This reduces data line length and maintains signal quality. For high-resolution panels in particular, structures that place the source driver at the top, bottom, or both sides of the panel are also considered to minimize wiring length and increase signal transmission speed.

[0021] According to one aspect of the present invention, a display device is provided that optimizes charging time in a demultiplexer-based time-division driving method, thereby eliminating charging rate deviations depending on panel position. To this end, a structure is applied that reduces the number of demultiplexer output channels in areas where parasitic components between the driving unit and the panel unit are large, and increases the number of demultiplexer output channels in areas where parasitic components are small.

[0022] At this time, a method of securing a uniform charging rate is used by applying different numbers of output channels of a demultiplexer connected to pixels arranged in the center of the panel and output channels of another demultiplexer connected to pixels arranged at an edge forming the outside of the center. According to the prior art, one amplifier drives the entire panel uniformly, but according to one embodiment of the present invention, a 1:4 demultiplexer is used in the center of the panel, and a 1:2 demultiplexer is used in the edge to control the charging time.

[0023] This addresses the issue of insufficient charging caused by long wiring lengths at the edges, while simultaneously driving more channels in the center, maximizing data transmission efficiency. Furthermore, if the panel drive unit is located at the center of the panel, charging time at the edges is likely to be insufficient. Therefore, reducing the number of demultiplexer output channels at the edges is beneficial.

[0024] The structure of the present invention is designed so that the sum of the reduced number of output channels and the increased number of output channels of the demultiplexers remains constant, thereby enabling uniform driving of the charging data lines of the entire panel. The control signals of the demultiplexers can be supplied independently to each group.

[0025] According to one aspect of the present invention, a pixel unit (15) including a plurality of pixel columns each including a plurality of sub-pixels; a source driver (12) including a first output buffer (1201) and a second output buffer (1202); a demultiplexer unit (13) including a first demultiplexer (1301) and a second demultiplexer (1302); an input data line unit including a first input data line (DL1) connecting an input terminal of the first demultiplexer and an output terminal of the first output buffer, and a second input data line (DL2) connecting an input terminal of the second demultiplexer and an output terminal of the second output buffer; N1 data lines (D) corresponding to a first group of pixel columns among the plurality of pixel columns A,1 , D B,1 ), and N2 data lines (D) corresponding to the second group of pixel columns among the plurality of pixel columns A,2 , D B,2 , D C,2 , D D,2 ), and the first demultiplexer includes N1 output channels connected to the N1 data lines, and the second demultiplexer includes N2 output channels connected to the N2 data lines, and N1 and N2 are different values. A display device (10) can be provided.

[0026] At this time, the first output buffer may be configured to alternately output a total of N1 independent data voltages in a time-division manner during one horizontal period, and the second output buffer may be configured to alternately output a total of N2 independent data voltages in a time-division manner during one horizontal period.

[0027] At this time, the display device may further include a timing control unit (11), and the timing control unit may be configured to connect the first input data line to the p-th data line among the N1 data lines during the p-th sub-section among the N1 sub-sections that do not overlap each other in the one horizontal period (p=1, ..., N1), and to connect the second input data line to the q-th data line among the N2 data lines during the q-th sub-section among the N2 sub-sections that do not overlap each other in the one horizontal period (q=1, ..., N2).

[0028] At this time, N2 is a value greater than N1, and the maximum value of the time constant of the N2 data lines may be smaller than the maximum value of the time constant of the N1 data lines.

[0029] At this time, N2 is a value greater than N1, and the maximum length of the N2 data lines may be less than the maximum length of the N1 data lines.

[0030] At this time, N2 is a value greater than N1, the lengths of each sub-interval of the N1 sub-intervals are equal to each other, the lengths of each sub-interval of the N2 sub-intervals are equal to each other, and the length of each sub-interval of the N1 sub-intervals can be longer than the length of each sub-interval of the N2 sub-intervals.

[0031] At this time, N2 is a value greater than N1, the maximum value of the time constants of the N2 data lines is smaller than the maximum value of the time constants of the N1 data lines, the lengths of each sub-section of the N1 sub-sections are equal to each other, the lengths of each sub-section of the N2 sub-sections are equal to each other, the lengths of each sub-section of the N1 sub-sections are greater than the maximum value of the time constants of the N1 data lines, and the lengths of each sub-section of the N2 sub-sections may be greater than the maximum value of the time constants of the N2 data lines.

[0032] At this time, the selection signal of the first demultiplexer and the selection signal of the second demultiplexer may be different signals.

[0033] According to another aspect of the present invention, a timing control unit (11); a source driver (12) including a first output buffer (1201) and a second output buffer (1202); and a demultiplexer unit (13) including a first demultiplexer (1301) and a second demultiplexer (1302); an input data line unit including a first input data line (DL1) connecting an input terminal of the first demultiplexer and an output terminal of the first output buffer, and a second input data line (DL2) connecting an input terminal of the second demultiplexer and an output terminal of the second output buffer; wherein the first demultiplexer includes N1 data lines (D) corresponding to a first group of pixel columns among a plurality of pixel columns included in a predetermined pixel section (15). A,1 , D B,1 ) and the second demultiplexer comprises N1 output channels, wherein the second demultiplexer comprises N2 data lines (D) corresponding to pixel columns of a second group among the plurality of pixel columns. A,2 , D B,2 , D C,2 , D D,2), wherein the timing control unit is configured to connect the first input data line to the p-th output channel of the N1 output channels during the p-th sub-interval among the N1 sub-intervals that do not overlap each other in the one horizontal period (p=1, ..., N1), and to connect the second input data line to the q-th output channel of the N2 output channels during the q-th sub-interval among the N2 sub-intervals that do not overlap each other in the one horizontal period (q=1, ..., N2), and a control device may be provided where N1 and N2 are different values.

[0034] At this time, N2 is a value greater than N1, and the maximum value of the time constant of the N2 data lines may be smaller than the maximum value of the time constant of the N1 data lines.

[0035] At this time, N2 is a value greater than N1, and the maximum length of the N2 data lines may be less than the maximum length of the N1 data lines.

[0036] At this time, N2 is a value greater than N1, the lengths of each sub-interval of the N1 sub-intervals are equal to each other, the lengths of each sub-interval of the N2 sub-intervals are equal to each other, and the length of each sub-interval of the N1 sub-intervals can be longer than the length of each sub-interval of the N2 sub-intervals.

[0037] At this time, N2 is a value greater than N1, the maximum value of the time constants of the N2 data lines is smaller than the maximum value of the time constants of the N1 data lines, the lengths of each sub-section of the N1 sub-sections are equal to each other, the lengths of each sub-section of the N2 sub-sections are equal to each other, the lengths of each sub-section of the N1 sub-sections are greater than the maximum value of the time constants of the N1 data lines, and the lengths of each sub-section of the N2 sub-sections may be greater than the maximum value of the time constants of the N2 data lines.

[0038] At this time, the selection signal of the first demultiplexer and the selection signal of the second demultiplexer may be different signals.

[0039] According to another aspect of the present invention, a first demultiplexer having N1 output channels and a second demultiplexer having N2 output channels (N1 <N2); 및 상기 N1개의 출력 채널에 연결된 N1개의 데이터 라인 및 상기 N2개의 출력 채널에 연결된 N2개의 데이터 라인;을 포함하며, 상기 N1개의 데이터 라인 각각의 시정수의 최대값은 상기 N2개의 데이터 라인 각각의 시정수의 최대값보다 큰 것을 특징으로 하는, 표시 장치가 제공될 수 있다.

[0040] At this time, the maximum length of the N2 data lines may be less than the maximum length of the N1 data lines.

[0041] At this time, the selection signal of the first demultiplexer and the selection signal of the second demultiplexer may be different signals.

[0042] According to the present invention, by considering different time constants of data lines having different lengths, a technology can be provided for optimizing the configuration and operation of a demultiplexer so that sufficient data voltage application time is secured for a group of data lines having a large time constant and there is no waste of data voltage application time for a group of data lines having a small time constant.

[0043] Figure 1 is a block diagram of a display device provided according to a comparative example.

[0044] FIG. 2 is a drawing for specifically explaining the data voltage output from the source driver to each pixel by the demultiplexer unit provided according to one embodiment.

[0045] FIG. 3 illustrates the configuration of a data drive network part of a display device provided according to one embodiment of the present invention.

[0046] Fig. 4 is a simplified diagram showing the configuration of a data drive network section of a display device presented according to Fig. 3.

[0047] FIG. 5 illustrates an example of the internal configuration of demultiplexers belonging to different groups provided according to one embodiment of the present invention.

[0048] FIG. 6 illustrates a timing diagram of a gate drive signal provided to a demultiplexer belonging to a first group and a voltage applied to a plurality of data lines connected to the demultiplexer according to one embodiment of the present invention.

[0049] Figure 7 is a diagram explaining the operation of a demultiplexer belonging to the second group.

[0050] Figure 8 is a diagram constructed to illustrate how the control methods of a 1:2 demultiplexer and a 1:4 demultiplexer differ and can be compared within one horizontal cycle.

[0051] Hereinafter, embodiments of the present invention will be described with reference to the attached drawings. However, the present invention is not limited to the embodiments described herein and may be implemented in various other forms. The terminology used herein is intended to aid understanding of the embodiments and is not intended to limit the scope of the present invention. Furthermore, the singular forms used below also include the plural forms, unless the context clearly indicates otherwise.

[0052] Fig. 1 is a block diagram of a display device provided according to a comparative example. The display device (10) may include a timing control unit (11), a source driver (12), a demultiplexer unit (13), a gate driver (14), a pixel unit (15), and a power supply unit (16).

[0053] This display device (10) can be implemented in various forms such as a flat display, a flexible display, a curved display, a foldable display, a bendable display, etc. In addition, it can be utilized in various application environments such as a transparent display, a head-mounted display, and a wearable display. It can be applied to electronic devices such as smartphones, tablets, smart pads, TVs, and monitors, and can also be implemented as, for example, an OLED (organic light-emitting display), an LCD (liquid crystal display), a self-luminous display including an inorganic light-emitting element, etc.

[0054] The pixel unit (15) is an input data line (DL1~DL m , where m is a natural number) and gate selection lines (GSL1~GSL n , where n is a natural number) and the connected pixel (P ij ) can be composed of pixels (P). Also, ij ) can receive voltages of the first power supply (ELVDD) and the second power supply (ELVSS) from the power supply unit (16).

[0055] A number of pixels (P ij) are respectively corresponding gate selection lines (GSL1~GSL n ) are connected to form a pixel row, and several of these pixel rows can be included. n gate selection lines (GSL1 to GSL) as illustrated in Fig. 1 n ) is only a specific implementation case and may be configured in other ways. Also, pixels (P ij ) Depending on the circuit structure, the pixel unit (15) may additionally include a control line, a gate selection line, a light emission control line, a sensing line, etc.

[0056] In addition, multiple pixels (P ij ) is the data line (D A,1 ~D A,m , D B,1 ~D B,m ) and can form corresponding pixel rows respectively. These pixel rows can also include multiple ones, and the PENTILE™ pixel structure can be applied. In this case, individual pixels (P ij ) can be composed of sub-pixels. In the pentile pixel structure, red (R) and blue (B) sub-pixels are connected to data lines (D A,1 ~D A,m ) can be cross-arranged along the extension direction of the data line (D), and the green (G) sub-pixels can be cross-arranged along the data line (D). B,1 ~D B,m ) can be arranged sequentially.

[0057] In one embodiment, a pixel (P ij ) may be a P-type oxide thin film transistor. For example, a low-temperature polyoxide (LTPO) thin film transistor may be applied. However, this is only a specific example, and only P-type transistors are not necessarily applied. The semiconductor layer (active pattern) of the transistor may include an inorganic semiconductor (e.g., amorphous silicon, polysilicon) or an organic semiconductor, and may be replaced with an N-type transistor under certain conditions.

[0058] The gate driver (14) receives the horizontal scan control signal (HSS) provided by the timing control unit (11) and controls the gate selection lines (GSL1 to GSL n ) can supply injection signals. Gate select lines (GSL1~GSL n ) are sequentially supplied with injection signals, the pixels (P ij ) are selected in horizontal line units. For this purpose, the scanning signal is a pixel (P ij ) can be set to a gate-on voltage (e.g., logic low level) so that the transistor included in the transistor can be turned on.

[0059] The source driver (12) can receive a pixel data control signal (PDCS) and image data (RGB) from the timing control unit (11) and provide a data voltage to the pixel unit (15). The image data (RGB) received from the timing control unit (11) for each horizontal period is converted into a data voltage and then transmitted to each input data line (DL1 to DL) through a plurality of output buffers. m ) is transmitted. The image data (RGB) received from the outside may be a digital signal, and the converted data voltage may be an analog signal.

[0060] For example, the source driver (12) can provide data voltages to the sub-pixels of the first pixel row in synchronization with the scan signal supplied to the gate selection line (GSL1) for a specific horizontal period. In the same way, the source driver (12) can provide data voltages to the sub-pixels of the first pixel row in synchronization with the scan signal supplied to the gate selection line (GSL2, GSL3, ..., GSL) for each horizontal period. n ) can supply data voltage to the sub-pixels of each pixel row in synchronization.

[0061] In one embodiment, the source driver (12) may alternately output two color data voltages through a specific input data line during one horizontal period. For example, during a specific horizontal period, a first output buffer may alternately output red (R) and green (G) data voltages and supply them to a first input data line (DL1), and a second output buffer may alternately output blue (B) and green (G) data voltages and supply them to a second input data line (DL2).

[0062] The timing control unit (11) can generate a pixel data control signal (PDCS), a horizontal scan control signal (HSS), a voltage level control signal (VLCS, Voltage Level Control Signal), and a demultiplexer control signal (MHSS) according to a synchronization signal input from an external source. At this time, the external input signal can include a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), and input image data (RGB).

[0063] The vertical synchronization signal (Vsync) can contain multiple pulses, each of which indicates the end of the previous frame and the beginning of a new one. Furthermore, the interval between adjacent pulses can correspond to one frame period. Meanwhile, the horizontal synchronization signal (Hsync) also contains multiple pulses, each of which indicates the end of the previous horizontal period and the beginning of a new horizontal period. The input image data (RGB) corresponding to one frame can be viewed as one input image.

[0064] The pixel data control signal (PDCS) generated in the timing control unit (11) is transmitted to the source driver (12), and the horizontal scan control signal (HSS) is supplied to the gate driver (14). In addition, the demultiplexer control signal (MHSS) can be transmitted to the demultiplexer unit (13), and the voltage level control signal (VLCS) can be transmitted to the power supply unit (16).

[0065] The pixel data control signal (PDCS) may include a source start signal and a clock signal. Here, the source start signal serves to control when data sampling begins, and the clock signal is used to coordinate the sampling operation.

[0066] The horizontal scan control signal (HSS) may include a scan start signal, a control start signal, and a clock signal. The scan start signal adjusts the timing of the scan signal, and the control start signal determines the timing of the control signal. Additionally, the clock signal may be used to shift the scan start signal and / or the control start signal.

[0067] The demultiplexer control signal (MHSS) may include a first path selection signal (GC1) and a second path selection signal (GC2). The first path selection signal may control the on / off states of a plurality of first selection transistors (M1, M3, M5) included in the demultiplexer unit (13), and the second path selection signal may control the on / off states of a plurality of second selection transistors (M2, M4).

[0068] The voltage level control signal (VLCS) serves to regulate the supply and voltage levels of the first power supply (ELVDD) and the second power supply (ELVSS).

[0069] The demultiplexer unit (13) has multiple input data lines (DL1 to DL m ) and multiple data lines (D A,1 ~D A,m , D B,1 ~D B,m) can be connected between the demultiplexer control signal (MHSS) for each horizontal cycle. Through this, the data voltage provided from the source driver (12) is transmitted to multiple input data lines (DL1 to DL m ), then multiple data lines (D A,1 ~D A,m , D B,1 ~D B,m ) can be transmitted to the sub-pixels included in the pixel unit (15).

[0070] For example, during a specific horizontal cycle, the demultiplexer unit (13) transmits the red data voltage transmitted to the first input data line (DL1) to the A1 data line (D A,1 ), the green data voltage transmitted through the same input data line (DL1) is transmitted to the B1 data line (D B,1 ) can be transmitted. Similarly, during the first horizontal cycle, the demultiplexer unit (13) transmits the blue data voltage transmitted to the second input data line (DL2) to the A2 data line (D A,2 ), and then the green data voltage transmitted through the same input data line (DL2) is transmitted to the B2 data line (D B,2 ) can be supplied. Furthermore, during the first horizontal cycle, the demultiplexer unit (13) supplies the jth input data line (DL j ) is supplied to the red (or blue) data line (D A,j ) and then transmits the green data voltage to the Bj data line (D B,j ) can operate in a way that transmits it.

[0071] In Fig. 1, the demultiplexer unit (13) is shown as being separate from the source driver (12), but in other embodiments, the demultiplexer unit (13) may be included within the source driver (12).

[0072] The power supply unit (16) can supply the voltage of the first power supply (ELVDD) and the second power supply (ELVSS) to the pixel unit (15) according to the voltage level control signal (VLCS). For example, the first power supply (ELVDD) serves to determine the voltage of the first electrode (e.g., source voltage) of the driving transistor, and the second power supply (ELVSS) can be used to adjust the cathode voltage of the light-emitting element.

[0073] FIG. 2 is a drawing for specifically explaining the data voltage output from the source driver to each pixel by the demultiplexer unit provided according to one embodiment.

[0074] Hereinafter, the description will be made with reference to FIG. 1 and FIG. 2 together.

[0075] The demultiplexer unit (13) may include a plurality of selection transistors (M1, M2, M3, M4, M5…) that perform on / off operations according to a demultiplexer control signal (MHSS), and this signal may include a first path selection signal (GC1) and a second path selection signal (GC2).

[0076] Referring to FIGS. 1 and 2, the source driver (12) may include a plurality of output buffers, each of which may alternately output a blue (B) or red (R) data voltage and a green (G) data voltage during one horizontal period corresponding to a specific gate selection line. For example, the j-th output buffer may alternately output blue (B) and green (G) data voltages during a horizontal period to the j-th input data line (DL). j ) can be transmitted. Similarly, the j+1 output buffer alternately outputs red (R) and green (G) data voltages to the j+1 input data line (DL j+1 ) can be transmitted to the j+2 output buffer, and the j+2 input data line (DL) alternates between blue (B) and green (G) data voltages. j+2 ) can also be printed.

[0077] The demultiplexer unit (13) may include a plurality of selection transistors (M1 to M5) connected between a plurality of input data lines (DLs) and data lines (DAs or DBs). For example, the first selection transistor (M1) may be connected to the jth input data line (DL j ) and the Aj data line (D A,j ) can be connected between the second selection transistor (M2) and the j input data line (DL j ) and the Bj data line (D B,j ) can be connected between the j+1 input data line (DL). In the same way, the third selection transistor (M3) can be connected between the j+1 input data line (DL j+1 ) and the Aj+1 data line (D A,j+1 ), the fourth selection transistor (M4) is connected to the j+1 input data line (DL j+1 ) and the Bj+1 data line (D B,j+1 ), and the fifth selection transistor (M5) is connected to the j+2 input data line (DL j+2 ) and the Aj+2 data line (D A,j+2 ) can be connected to each other.

[0078] During one horizontal period, a first path selection signal (GC1) may be applied to the gate electrodes of the first, third, and fifth selection transistors (M1, M3, M5), whereas a second path selection signal (GC2) may be provided to the gate electrodes of the second and fourth selection transistors (M2, M4). These selection transistors (M1 to M5) may be PMOS transistors, and in the case of PMOS transistors, the gate-on voltage may be at a low level and the gate-off voltage may be at a high level. However, this is not limited thereto, and some of the selection transistors (M1 to M5) may be replaced with NMOS transistors. In the case of NMOS transistors, the gate-on voltage may be at a high level and the gate-off voltage may be at a low level.

[0079] The demultiplexer unit (13) can selectively transmit the red (R) or blue (B) data voltage and the green (G) data voltage output from each output buffer to two data lines during each horizontal period.

[0080] For example, during the first horizontal period, the jth input data line (DL) outputs the blue (B) data voltage from the jth output buffer. j ) and the Aj data line (D A,j ) can be connected. At this time, a first path selection signal (GC1) is provided to the gate of the first selection transistor (M1) so that the transistor can be turned on. Thereafter, while the green (G) data voltage is output from the jth output buffer during the same horizontal period, the jth input data line (DL j ) and the Bj data line (D B,j ) can be connected, and at this time, the first selection transistor (M1) is turned off, and a second path selection signal (GC2) is supplied to the gate of the second selection transistor (M2) so that the transistor can be turned on.

[0081] In a similar manner, the j+1 input data line (DL) outputs the red (R) data voltage from the j+1 output buffer during the first horizontal period. j+1 ) and the Aj+1 data line (D A,j+1 ) can be connected, and at this time, a first path selection signal (GC1) can be provided to the gate of the third selection transistor (M3). When the green (G) data voltage is output from the j+1th output buffer during the same horizontal period, the j+1th input data line (DL j+1 ) and the Bj+1 data line (D B,j+1 ) is connected, and at this time, the third selection transistor (M3) is turned off, and the second path selection signal (GC2) is provided to the gate of the fourth selection transistor (M4) so ​​that the transistor can be turned on.

[0082] Additionally, when the blue (B) data voltage is output from the j+2th output buffer during the first horizontal period, the j+2th input data line (DL j+2 ) and the Aj+2 data line (D A,j+2 ) can be connected, and at this time, a first path selection signal (GC1) is provided to the gate of the fifth selection transistor (M5) so that the transistor can be turned on.

[0083] Even in the second horizontal period, the demultiplexer unit (13) operates in a manner that selectively transfers the red (R) or blue (B) data voltage and the green (G) data voltage output from each output buffer to two data lines for each horizontal period. This is the same as the operating method in the first horizontal period.

[0084] FIG. 3 illustrates the configuration of a data drive network unit of a display device provided according to one embodiment of the present invention.

[0085] The data-driven network unit (20) may be composed of a source driver (12), input data lines (DL) connecting the source driver (12) to the demultiplexer unit (13), the demultiplexer unit (13), and data lines (D) extending from the demultiplexer unit (13) to individual pixels of the pixel unit (15). The data lines (D) may be made of a conductive material and may be referred to as wiring. The pixel unit (15) may be a panel that ultimately receives a data signal and displays an image.

[0086] The source driver (12) includes a plurality of output buffers (120), and the demultiplexer unit (13) includes a plurality of demultiplexers (130). In one embodiment, the number of output buffers (120) and demultiplexers (130) may be N, and FIG. 3 illustrates an example where N=4.

[0087] In order to distinguish between different output buffers (120), a delimiter is provided as a subscript to the right of the reference number '120'. Each output buffer is indicated by the reference numbers 1201, 1202, 1203, and 1204.

[0088] The demultiplexer unit (13) includes a plurality of demultiplexers (130) and provides a function of distributing an input data signal to a plurality of pixels. The demultiplexers (130) are divided into different groups, and the number of output channels may vary for each group. In the example of Fig. 3, each demultiplexer (130) has an output channel structure of 1:2 or 1:4.

[0089] In order to distinguish between different demultiplexers (130), a distinguishing symbol is provided as a subscript to the right of the reference number '130'. In Fig. 3, this is illustrated by distinguishing them with reference numbers 1301, 1302, 1303, and 1304.

[0090] In order to distinguish different input data lines, a delimiter is provided as a subscript to the right of the reference letter 'DL', and in order to distinguish different data lines, a delimiter is provided as a subscript to the right of the reference letter 'D'. In Fig. 3, reference symbol D A,1 , D B,1 , D A,2 , D C,2 Examples are provided by dividing them into the following categories.

[0091] The reference character 'L.D' indicates the wiring length of the corresponding data line 'D'.

[0092] The wiring lengths of different data lines may be the same, but typically differ. Furthermore, the longer the distance between the demultiplexer from which each data line originates and the pixel to which that data line is to be connected, the longer the wiring length of that data line may be. Multiple pixels may be connected to a single data line.

[0093] Although there may be various inflection points in the routing path of each data line crossing the pixel unit (15), in Fig. 3, the routing path of each data line is symbolized by a vertical line, and the fact that the wiring length of each data line may be different is indicated by expressing the length of the vertical line differently. Therefore, the shape of the data line presented in Fig. 3 may be different from the actual implementation example. In Fig. 3, only the connection of the data line is represented, and the illustration of the individual configuration of each pixel is omitted.

[0094] Additionally, the lengths of different input data lines (DL) may also be different. The input data lines (DL) are paths that transmit data signals output from the source driver (12) to the demultiplexer unit (13), and are illustrated in FIG. 3 by distinguishing them with reference numerals DL1, DL2, DL3, and DL4.

[0095] If a resistor (R) and a capacitor (C) exist in the wiring extending from the output of the display panel driver, for example, from the output terminal of a specific output buffer (120) to the pixel connected thereto, an RC time constant (τ) exists due to this. The charging rate up to the driving voltage for each pixel according to the image is determined by this time constant (τ). If the time constant (τ) is large, the charging is less than the desired driving voltage, and if the time constants are different for each position, the charging rate for each driving line is different. This may cause unwanted spots or vertical lines to appear on the screen.

[0096] In one embodiment of the present invention, a plurality of demultiplexers (130) included in a demultiplexer unit (13) may be divided into a plurality of groups. Any one demultiplexer (130) may belong to any one group. In addition, the number of output channels of all demultiplexers (130) belonging to a specific group among the plurality of groups is the same.

[0097] The first number of output channels of a demultiplexer (130) belonging to a first group among a plurality of groups is different from the second number of output channels of a demultiplexer (130) belonging to a second group. In addition, the numbers of output channels of two demultiplexers (130) belonging to different groups among a plurality of groups are different from each other. That is, the demultiplexers belonging to one group have the same number of output channels, and the demultiplexers belonging to different groups have different numbers of output channels.

[0098] Fig. 4 is a simplified diagram showing the configuration of a data drive network section of a display device presented according to Fig. 3.

[0099] In Fig. 3, the data lines extended from the demultiplexer are designed to have different lengths, but in Fig. 4, it is assumed that all data lines output from each demultiplexer have the same length. Fig. 4 may be closer to an actual implementation example than Fig. 3. However, Fig. 4 is presented to suggest that the structure of Fig. 3 can be simplified and considered as in Fig. 4 in order to help understand the timing diagram of the data voltage in each data line described later.

[0100] FIG. 5 illustrates an example of the internal configuration of demultiplexers belonging to different groups provided according to one embodiment of the present invention.

[0101] Figure 5 includes four demultiplexers (130₁, 130₂, 130₃, 130₄), which are classified into two groups (G1, G2). The first demultiplexer (130₁) and the fourth demultiplexer (130₄) belong to the first group (G1), and provide 1:2 output channels, respectively. On the other hand, the second demultiplexer (130₂) and the third demultiplexer (130₃) belong to the second group (G2), and provide 1:4 output channels, respectively.

[0102] The reference symbol 'GC' represents the gate drive signal (GC) that drives the switches included in each demultiplexer. To distinguish between different gate drive signals, a subscript is provided to the right of the reference symbol 'GC'.

[0103] A demultiplexer providing 1:N output channels has N switches inside it. One end of each of the N switches is connected to a specific input data line connected to a specific output buffer, and the other ends of each of the N switches are connected to different data lines. A demultiplexer providing 1:N output channels can receive N gate drive signals, and each of the N gate drive signals can be connected to a corresponding gate of the N switches.

[0104] That is, the number of internal switches is determined by the number of output channels of the demultiplexer. The 1:2 demultiplexers 130₁ and 130₄ contain two switches, the inputs of each switch are connected to the same data line (DL), and the outputs are distributed to two different data lines (D). On the other hand, the 1:4 demultiplexers 130₂ and 130₃ contain four switches, and transmit signals from one input data line (DL) to four separate data lines (D).

[0105] Each demultiplexer is controlled by a gate drive signal (GC). Different sets of gate drive signals are used for different groups, and demultiplexers within the same group share the same set of drive signals. In the G1 group, which contains 1:2 demultiplexers, `{GC Ax . GC Bx}` is used as a gate drive signal, and in the G2 group including a 1:4 demultiplexer, `{GC Ay . GC By , GC Cy , GC Dy}` is used. There are no identical signals in the sets of gate drive signals of different groups.

[0106] Gate signals operate in a specific manner. When a specific gate drive signal in a demultiplexer is on, the other signals in the corresponding gate signal set remain off. In addition, the on-state duration of all gate signals belonging to a specific gate drive signal set can be adjusted to be the same. The on-state duration of each gate drive signal is determined according to the number of output channels of the demultiplexer, and has an on / off pattern that repeats within a given horizontal period (T1). In the case of a 1:2 demultiplexer, the on-state duration of the gate drive signal is less than the time T1 divided by 2, and in the case of a 1:4 demultiplexer, the on-state duration is less than the time T1 divided by 4.

[0107] For example, the gate drive signal (GC Ax ), and gate drive signal (GC Bx ) has two output channels, so the gate drive signal (GC) Ax ) or gate drive signal (GC Bx ) may be less than a time interval obtained by dividing the above horizontal period (T1) by 2.

[0108] For example, the gate drive signal (GC Ay ), gate drive signal (GC By ), gate drive signal (GC Cy ), and gate drive signal (GC Dy ) has four output channels, so the gate drive signal (GC) Ay ), gate drive signal (GC By ), gate drive signal (GC Cy ), and gate drive signal (GC Dy ) may be less than a time interval obtained by dividing the above horizontal period (T1) by 4.

[0109] Figures (a) to (d) of Fig. 5 individually show the internal configuration of each demultiplexer. Figures (a) and (d) of Fig. 5 show the structure of a 1:2 demultiplexer (130₁, 130₄), respectively, and belong to the G1 group. Figures (b) and (c) of Fig. 5 show the structure of a 1:4 demultiplexer (130₂, 130₃), respectively, and belong to the G2 group. The gate signal set of each demultiplexer is set differently, and the number of output channels differs depending on the group.

[0110] Figure 5 is a diagram illustrating the grouping of demultiplexers, the number of output channels, and the control method of the gate drive signal. It shows the difference between 1:2 and 1:4 demultiplexers, and indicates that the demultiplexer configuration method varies depending on the group (G1, G2). The gate drive signal has a specific pattern, and the duration of the ON state is adjusted according to the number of output channels. This design enables uniform data distribution on the display panel and optimization of the drive signal timing.

[0111] FIG. 6 illustrates a timing diagram of a gate drive signal provided to a demultiplexer belonging to a first group and a voltage applied to a plurality of data lines connected to the demultiplexer according to one embodiment of the present invention.

[0112] Figure 6 (a) shows the structure of a demultiplexer belonging to the first group (G1), and has the same configuration as the circuit presented in Figure 5 (a). Figure 6 (b) provides a timing diagram for voltage changes of data lines connected to the demultiplexer, and includes information necessary for analyzing the selection signal of the demultiplexer and the charging characteristics of each data line.

[0113] In Fig. 6, reference symbol 'GC' represents a gate drive signal that controls the switch of the demultiplexer. In addition, 'V.D' means the voltage of a specific data line, and represents the process in which the voltage of the data line increases when the gate drive signal is turned on. 'τ.D' is a time constant determined by the capacitance and resistance of the data line, and represents the time it takes for the voltage of the data line to reach a set value. In Fig. 6, 'T1' is used as a time unit representing one horizontal period to explain the periodic change of the gate drive signal.

[0114] In Fig. 6, the first group is assumed to have a 1:2 output channel structure.

[0115] Reference symbols 'D', 'V.D', 'τ.D' with the same subscript are corresponding values.

[0116] In the example presented in Fig. 6, the gate drive signal (GC Ax ) is switched on immediately after the data line (D) A,1 ) is designed to increase the voltage of the data line (D). A,1 ) the time taken for the voltage to rise is the time constant (τ.D) of the corresponding data line. A,1 ) is determined by the data line (D). At this time, the data line (D A,1 ) until the voltage of the gate drive signal (GC) rises sufficiently. Ax ) must be maintained in the on state. Therefore, the gate drive signal (GC Ax ) on the data line (D A,1 ) time constant (τ.D A,1 ) is determined by the time constant (τ.D A,1 ) is longer, the gate drive signal (GC) Ax ) must be set to a sufficiently long time to maintain the on state. If the time constant (τ.D A,1) is large, the on-state duration of the gate drive signal must be set longer, and conversely, if the time constant is small, the on-state duration can be set shorter.

[0117] Data line (D A,1 ) wiring length (LD) A,1 ) increases, the time constant (τ.D A,1 ) increases. Therefore, the data line (D A,1 ) wiring length (LD) A,1 ) is longer, the gate drive signal (GC) Ax ) needs to be set to a longer on-state retention time.

[0118] In other words, in a preferred embodiment of the present invention, the longer the wiring length of a given data line, the longer the on-state maintenance period of the gate drive signal (i.e., the selection signal of the demultiplexer) for connecting the data line to the output buffer must be set. Since the on-state maintenance period of each gate drive signal is limited by the time-division driving method of the demultiplexer, in order to set the on-state maintenance period of each gate drive signal to be maintained long, it is preferable to connect data lines having relatively longer wiring to a demultiplexer having a relatively smaller number of output channels.

[0119] Fig. 7 is a diagram illustrating the operation of a demultiplexer belonging to the second group (G2). It has a similar structure to Fig. 6, but unlike Fig. 6, which deals with a first group (G1) demultiplexer having 1:2 output channels, Fig. 7 illustrates a second group (G2) demultiplexer having 1:4 output channels.

[0120] Fig. 7 (a) shows the circuit structure of a demultiplexer belonging to the second group (G2). It has the same structure as the 1:4 demultiplexer circuit presented in Fig. 5 (b) and (c). Fig. 7 (b) shows a timing diagram of voltages applied to four data lines connected to the demultiplexer. Compared to Fig. 6, the 1:4 demultiplexer has the characteristic of controlling more data lines, and thus the on-state duration of each gate drive signal (GC) is shortened.

[0121] The switches of the demultiplexer are controlled by gate drive signals (GC). The set of gate drive signals used in Fig. 7 is `{GC Ay , GC By , GC Cy , GC Dy}`, the first group (G1) `{GC Ax , GC Bx}`. When a specific gate drive signal (GC) is turned on, the voltage of the data line (VD) corresponding to the gate signal increases. The time it takes for the voltage of the data line to sufficiently increase is determined by the time constant (τ.D) of the data line.

[0122] Since the 1:4 demultiplexer has four output channels, the on-state duration of each gate drive signal is less than the total horizontal period (T1) divided by 4. This means that the signal is maintained for a shorter time compared to the time shorter than T1 divided by 2 in the 1:2 demultiplexer. As the wiring length of the data line increases, the time constant (τ.D) increases, and accordingly, the time until the driving voltage is sufficiently charged increases. Therefore, it is appropriate to connect data lines with long wiring to a demultiplexer with a relatively smaller number of output channels.

[0123] Figure 7 illustrates the operation of a 1:4 demultiplexer and the difference in charging speed depending on the length of the data line. This allows for appropriately setting the gate drive signal of the demultiplexer, maximizing uniform data transmission and charging efficiency of the display panel.

[0124] Figure 8 is a diagram constructed to explain how the control methods of a 1:2 demultiplexer and a 1:4 demultiplexer differ and can be compared within one horizontal cycle (T1).

[0125] The timing diagram of the 1:2 demultiplexer presented in (b) of Fig. 6 is placed at the top of Fig. 8, and the timing diagram of the 1:4 demultiplexer presented in (b) of Fig. 7 is placed at the bottom of Fig. 8. This allows for a direct comparison of the control schemes of the two demultiplexers and the charging characteristics of the data lines.

[0126] A 1:2 demultiplexer has two output channels, and the ON-state duration of each gate drive signal (GC) is less than the horizontal period (T1) divided by 2. In contrast, a 1:4 demultiplexer has four output channels, and therefore the ON-state duration of each gate drive signal (GC) is less than the time T1 divided by 4. Figure 8 clearly shows this time difference, and you can see a pattern in which the gate signals are sequentially activated at regular time intervals.

[0127] In addition, the voltage change of the data line can also be compared. In Fig. 8, the reference symbol 'V.D' means the voltage of a specific data line, and it shows that the voltage of the data line increases (level changes) when a specific gate signal is turned on. The time it takes for the voltage of the data line to sufficiently increase is determined by the time constant (τ.D) of the data line. In a 1:2 demultiplexer, a specific data line can be selected for a relatively longer time, so the data voltage is likely to be sufficiently charged. On the other hand, in a 1:4 demultiplexer, the time allocated to each data line is shorter, so the voltage charging may not be sufficient, and an appropriate gate signal duration can be set to compensate for this.

[0128] By utilizing the embodiments of the present invention described above, those skilled in the art will be able to easily implement various changes and modifications without departing from the essential characteristics of the present invention. The content of each claim may be combined with other claims that are not in a citation relationship within the scope of this specification, as long as it is understood.

Claims

1. A pixel unit (15) including a plurality of pixel columns each including a plurality of sub-pixels; A source driver (12) including a first output buffer (1201) and a second output buffer (1202); A demultiplexer unit (13) including a first demultiplexer (1301) and a second demultiplexer (1302); An input data line section including a first input data line (DL1) connecting an input terminal of the first demultiplexer and an output terminal of the first output buffer, and a second input data line (DL2) connecting an input terminal of the second demultiplexer and an output terminal of the second output buffer; N1 data lines (D) corresponding to the first group of pixel columns among the above plurality of pixel columns A,1 , D B,1 ), and N2 data lines (D) corresponding to the second group of pixel columns among the plurality of pixel columns A,2 , D B,2 , D C,2 , D D,2 ) including data line section; Includes, The above first demultiplexer includes N1 output channels connected to the N1 data lines, The second demultiplexer includes N2 output channels connected to the N2 data lines, N1 and N2 are different values, Display device (10).

2. In paragraph 1, The above first output buffer is configured to alternately output a total of N1 independent data voltages in a time-division manner during one horizontal period, The second output buffer is configured to alternately output a total of N2 independent data voltages in a time-division manner during the one horizontal period. Display device.

3. In paragraph 2, It further includes a timing control unit (11), The above timing control unit, Connecting the first input data line to the p-th data line among the N1 data lines during the p-th sub-interval among the N1 sub-intervals that do not overlap each other in the above one horizontal period (p=1, ..., N1), and The second input data line is configured to be connected to the q-th data line among the N2 data lines during the q-th sub-interval among the N2 sub-intervals that do not overlap each other in the above one horizontal period (q=1, ..., N2), Display device.

4. In paragraph 3, N2 is a value greater than N1, The maximum value of the time constant of the above N2 data lines is smaller than the maximum value of the time constant of the above N1 data lines. Display device.

5. In paragraph 3, N2 is a value greater than N1, The maximum length of the above N2 data lines is less than the maximum length of the above N1 data lines. Display device.

6. In paragraph 3, N2 is a value greater than N1, The length of each sub-interval of the above N1 sub-intervals is equal to each other, The length of each sub-interval of the above N2 sub-intervals is equal to each other, The length of each sub-interval of the N1 sub-intervals is characterized by being longer than the length of each sub-interval of the N2 sub-intervals. Display device.

7. In paragraph 3, N2 is a value greater than N1, The maximum value of the time constant of the above N2 data lines is less than the maximum value of the time constant of the above N1 data lines, The length of each sub-interval of the above N1 sub-intervals is equal to each other, The length of each sub-interval of the above N2 sub-intervals is equal to each other, The length of each sub-interval of the above N1 sub-intervals is greater than the maximum value of the time constant of the above N1 data lines, The length of each sub-interval of the above N2 sub-intervals is greater than the maximum value of the time constant of the above N2 data lines. Display device.

8. In paragraph 1, The selection signal of the first demultiplexer and the selection signal of the second demultiplexer are characterized in that they are different signals. Display device.

9. Timing control unit (11); A source driver (12) including a first output buffer (1201) and a second output buffer (1202); and A demultiplexer unit (13) including a first demultiplexer (1301) and a second demultiplexer (1302); An input data line section including a first input data line (DL1) connecting an input terminal of the first demultiplexer and an output terminal of the first output buffer, and a second input data line (DL2) connecting an input terminal of the second demultiplexer and an output terminal of the second output buffer; Includes, The above first demultiplexer has N1 data lines (D) corresponding to the first group of pixel columns among the plurality of pixel columns included in a given pixel section (15). A,1 , D B,1 ) contains N1 output channels that are intended to be connected to The second demultiplexer has N2 data lines (D) corresponding to the second group of pixel columns among the plurality of pixel columns. A,2 , D B,2 , D C,2 , D D,2 ) contains N2 output channels that are intended to be connected to The above timing control unit, Connecting the first input data line to the pth output channel among the N1 output channels during the pth sub-interval among the N1 sub-intervals that do not overlap each other in the above one horizontal period (p=1, ..., N1), and The second input data line is connected to the qth output channel among the N2 output channels during the qth sub-interval among the N2 sub-intervals that do not overlap each other in the above one horizontal period (q=1, ..., N2), N1 and N2 are different values, controller.

10. In paragraph 9, N2 is a value greater than N1, The maximum value of the time constant of the N2 data lines is characterized in that it is smaller than the maximum value of the time constant of the N1 data lines. controller.

11. In paragraph 9, N2 is a value greater than N1, The maximum length of the N2 data lines is characterized in that it is smaller than the maximum length of the N1 data lines. controller.

12. In paragraph 9, N2 is a value greater than N1, The length of each sub-interval of the above N1 sub-intervals is equal to each other, The length of each sub-interval of the above N2 sub-intervals is equal to each other, The length of each sub-interval of the N1 sub-intervals is characterized by being longer than the length of each sub-interval of the N2 sub-intervals. controller.

13. A first demultiplexer having N1 output channels and a second demultiplexer having N2 output channels (N1 <N2); 및 N1 data lines connected to the N1 output channels and N2 data lines connected to the N2 output channels; Includes, The maximum value of the time constant of each of the N1 data lines is characterized in that it is greater than the maximum value of the time constant of each of the N2 data lines. Display device.

14. In paragraph 13, The maximum length of the above N2 data lines is less than the maximum length of the above N1 data lines. Display device.

15. In paragraph 13, The selection signal of the first demultiplexer and the selection signal of the second demultiplexer are characterized in that they are different signals. Display device.

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