Dynamic bias buffer

Abstract

Embodiments of a dynamic bias buffer are disclosed. The dynamic bias buffer includes a dynamic current source, an output node, a common gate amplifier, and a constant current source. A power source voltage is generated at the output node. The constant current source is configured to generate a constant current with a constant current level. The dynamic current source is coupled to the common gate amplifier so as to receive a feedback signal indicative of a common gate amplifier current level of a common gate amplifier current through the common gate amplifier. The dynamic current source is responsive to adjust the variable current level in accordance with the feedback signal so as to drive the power source voltage at the output node to a predetermined voltage level.

Description

2867-3431 -WO / P241474-WO-UTL 1DYNAMIC BIAS BUFFERRelated

[0001] This application claims the benefit of provisional patent application serial number 63 / 574,019, filed April 3, 2024, the disclosure of which is hereby incorporated herein by reference in its entirety.Field of the Disclosure

[0002] This disclosure relates to circuitry for generating power source voltage from a battery voltage and methods of operating the same.Background

[0003] WiFi circuitry should respond quickly to mode changes where load currents are very dynamic. Accommodation of wide input voltage ranges is another feature that is often required for products powered by a battery. Often, these circuits are formed with silicon on insulator (SOI) technology and reside on the same die as associated with radio frequency (RF) circuits. These circuits are often idle for long periods of time and become suddenly active. Thus, low battery consumption during idle phases and a quick response to active phases are needed in order to power this WiFi circuitry.

[0004] In some embodiments, a dynamic bias buffer includes: a dynamic current source configured to generate a variable current having a variable current level set in accordance with a feedback signal; an output node for coupling to a load; a common gate amplifier configured to generate a power source voltage at the output node, wherein the output node is between the dynamic current source and the common gate amplifier so that a common gate amplifier current having a common gate amplifier current level is received from the dynamic current source; and a constant current source configured to generate a constant current with a constant current level, wherein the dynamic current source is coupled to the2867-3431 -WO / P241474-WO-UTL 2 common gate amplifier so as to receive the feedback signal indicative of the common gate amplifier current level and wherein the dynamic current source is responsive to adjust the variable current level in accordance with the feedback signal so as to drive a power source voltage level of the power source voltage at the output node to a predetermined voltage level.

[0005] In some embodiments, the predetermined voltage level is 2.5 Volts.

[0006] In some embodiments, the common gate amplifier includes a P- channel field effect transistor (PFET) having a gate configured to receive a reference voltage.

[0007] In some embodiments, the reference voltage has a positive polarity and a non-zero magnitude.

[0008] In some embodiments, the dynamic current source is configured to receive a battery voltage, the dynamic current source includes: a first PFET having a first source, a first gate, and a first drain, wherein the first source is coupled to receive the battery voltage; and a second PFET having a second source, a second gate, and a second drain, wherein the second PFET is cascaded with the first PFET such that the first drain is coupled to the first source and the second drain is coupled to the output node.

[0009] In some embodiments, the common gate amplifier includes a third PFET having a third source, a third drain, and a third gate, wherein: the third gate is configured to receive a reference voltage; the third source is coupled to the second drain; and the third drain is coupled to the constant current source.

[0010] In some embodiments, the third drain is coupled to the constant current source at a feedback node, wherein the dynamic current source is configured to receive the feedback signal from the feedback node.

[0011] In some embodiments, the dynamic bias buffer further includes: a first resistive device coupled between the first gate and the second gate; and a second resistive device coupled between the second gate and the feedback node.

[0012] In some embodiments, the dynamic bias buffer further includes: a first proportional to battery voltage current source (PBVCS) coupled between the first2867-3431 -WO / P241474-WO-UTL 3 source and the first gate; and a second PBVCS coupled between the feedback node and ground.

[0013] In some embodiments, the dynamic bias buffer further includes: a first capacitive device coupled between the first gate and the second gate; and a second capacitive device coupled between the second gate and the feedback node.

[0014] In some embodiments, the first PBVCS includes a PFET mirror circuit and the second PBVCS is an N-channel field effect transistor (NFET) mirror, wherein the PFET mirror circuit is coupled to the NFET mirror.

[0015] In some embodiments, the constant current source includes an NFET mirror.

[0016] In some embodiments, the dynamic bias buffer further includes: a voltage clamp coupled to the output node.

[0017] In some embodiments, a method of generating a power source voltage from a battery voltage includes: generating a variable current having a variable current level set in accordance with a feedback signal; generating a common gate amplifier current having a common gate amplifier current level from at least a portion of the variable current; generating a power source voltage at an output node; generating a constant current with a constant current level; receiving the feedback signal indicative of the common gate amplifier current level; and adjusting the variable current level in accordance with the feedback signal so that a dynamic current level and the constant current level are set to a predetermined proportion.

[0018] In some embodiments, a user element includes a dynamic bias buffer, the dynamic bias buffer includes: a dynamic current source configured to generate a variable current having a variable current level set in accordance with a feedback signal; an output node for coupling to a load; a common gate amplifier configured to generate a power source voltage at the output node, wherein the output node is between the dynamic current source and the common gate amplifier so that a common gate amplifier current having a common gate amplifier current level is received from the dynamic current source; and a2867-3431 -WO / P241474-WO-UTL 4 constant current source configured to generate a constant current with a constant current level, wherein the dynamic current source is coupled to the common gate amplifier so as to receive the feedback signal indicative of the common gate amplifier current level and wherein the dynamic current source is responsive to adjust the variable current level in accordance with the feedback signal so as to drive a power source voltage level of the power source voltage at the output node to a predetermined voltage level.

[0019] In some embodiments, the predetermined voltage level is 2.5 Volts.

[0020] In some embodiments, the common gate amplifier includes a PFET having a gate configured to receive a reference voltage.

[0021] In some embodiments, the reference voltage has a positive polarity and a non-zero magnitude.

[0022] In some embodiments, the dynamic current source is configured to receive a battery voltage, the dynamic current source includes: a first PFET having a first source, a first gate, and a first drain, wherein the first source is coupled to receive the battery voltage; and a second PFET having a second source, a second gate, and a second drain, wherein the second PFET is cascaded with the first PFET such that the first drain is coupled to the first source and the second drain is coupled to the output node.

[0023] In some embodiments, the common gate amplifier includes a third PFET having a third source, a third drain, and a third gate, wherein: the third gate is configured to receive the reference voltage; the third source is coupled to the second drain; and the third drain is coupled to the constant current source.

[0024] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.2867-3431 -WO / P241474-WO-UTL 5Brief Description of the Drawing Figures

[0025] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0026] FIG. 1 illustrates a dynamic bias buffer, in accordance with some embodiments;

[0027] FIG. 2 illustrates another dynamic bias buffer, in accordance with some embodiments;

[0028] FIG. 3 is a graph that illustrates a power source voltage and an output current versus time with regards to operation of the dynamic bias buffer shown in FIG. 2, in accordance with some embodiments;

[0029] FIG. 4 is a graph that illustrates a power source voltage versus a battery voltage with regards to operation of the dynamic bias buffer shown in FIG. 2, in accordance with some embodiments;

[0030] FIG. 5 is a flow chart that illustrates a method of generating a power source voltage from a battery voltage; and

[0031] FIG. 6 illustrates a user element, in accordance with some embodiments.Detailed Description

[0032] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0033] It should be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element2867-3431 -WO / P241474-WO-UTL 6 from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0034] It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0035] It should be understood that, although the terms “upper,” “lower,” “bottom,” “intermediate,” “middle,” “top,” and the like may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed an “upper” element and, similarly, a second element could be termed an “upper” element depending on the relative orientations of these elements, without departing from the scope of the present disclosure.

[0036] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including" when used herein specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0037] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having meanings2867-3431 -WO / P241474-WO-UTL 7 that are consistent with their meanings in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0038] A dynamic bias buffer is disclosed. The dynamic bias buffer provides a voltage source of sufficient accuracy that idles at a low standby current and responds quickly to load currents by dynamically changing its bias while a load is activated. This feature is valuable in circuits that are battery powered and held in standby operating modes for much of the time. The standby current is low, which saves battery life, but responds quickly to the activation of the circuitry. The dynamic bias buffers disclosed herein may be used to power digital circuitry or supply radio frequency (RF) switch drivers with a power source voltage.

[0039] FIG. 1 illustrates a dynamic bias buffer 100, in accordance with some embodiments.

[0040] The dynamic bias buffer 100 is configured to receive a battery voltage VBAT at a battery node 102 and generate a power source voltage VOUT at an output node 104. In some embodiments, the output node 104 is used for coupling to a load, such as digital or analog RF circuitry (not explicitly). For example, the power source voltage VOUT may power to Complementary Metal on Oxide (CMOS) logic in digital circuitry in a user element (e.g., a tablet, a smart phone, etc.). CMOS logic is often idle and does not require much current until an operation is to be implemented in the CMOS logic. The dynamic bias buffer 100 provides a voltage source for a load that idles at a low standby current and responds quickly to load currents by dynamically changing the bias current and, thereby, preventing excessive swings in the power source voltage VOUT when the CMOS logic is active. Thus, the dynamic bias buffer 100 responds quickly to changes in the load impedance during operation of the CMOS logic while providing a low bias current level while the CMOS logic is inactive. The dynamic bias buffer 100, thus, is advantageous when operating with circuitry that is held in standby operating modes for long periods of time and then is suddenly requiring large increases in current during operation. In some embodiments, the dynamic bias buffer 100 is used with CMOS logic to supply RF switch drivers.2867-3431 -WO / P241474-WO-UTL 8

[0041] The dynamic bias buffer 100 includes a dynamic current source 106, a common gate amplifier 108, and a constant current source 110. The dynamic current source 106 is configured to generate a variable current Iv having a variable current level set in accordance with a feedback signal Vf. In other words, the dynamic current source 106 is configured to adjust the variable current level of the variable current Iv in accordance with a signal level of the feedback signal Vf. In this embodiment, the feedback signal Vf is a feedback voltage and the signal level is a voltage level. In other embodiments, the feedback signal Vf is a feedback current and the signal level is a current level.

[0042] The common gate amplifier 108 is configured to generate the power source voltage VOIIT at the output node 104. The output node 104 is between the dynamic current source 106 and the common gate amplifier 108 so that a common gate amplifier current Ic, having a common gate amplifier current level, is received from the dynamic current source 106. In this embodiment, the variable current Iv is split between the common gate amplifier current Ic and an output current Io that is provided through the output node 104. While the load is idle, very little current is provided through the output node 104 so that the current level of the output current Io is very low. However, when the load is active, the current level of the output current Io increases rapidly.

[0043] The constant current source 110 is configured to generate a constant current Ik with a constant current level. Thus, the dynamic current source 106 is coupled to the common gate amplifier 108 to receive the feedback signal Vf indicative of the common gate amplifier current level. The dynamic current source 106 is responsive to adjust the variable current level in accordance with the feedback signal Vf so as to drive the power source voltage VOIIT at the output node 104 to a predetermined voltage level (e.g., 2.5 Volts).

[0044] In FIG. 1 , by maintaining the dynamic current level and the constant current level, the output voltage level of the power source voltage VOIIT is maintained within an acceptable error range, despite large increases in the current level of the output current Io.2867-3431 -WO / P241474-WO-UTL 9

[0045] In FIG. 1 , the common gate amplifier 108 is a P-channel field effect transistor (PFET) having a gate configured to receive a reference voltage VREF. In some embodiments, the reference voltage VREF is a direct current (DC) voltage having a positive polarity and a non-zero magnitude. A source of the common gate amplifier 108 is coupled to the output node 104 and a drain of the common gate amplifier 108 is coupled to a feedback node 112. The feedback signal Vf is generated at the feedback node 1 12.

[0046] The dynamic current source 106 is configured to receive the battery voltage VBAT from the battery node 102. In FIG. 1 , the dynamic current source 106 includes a PFET 1 14, having a source connected to the battery node 102, in order to receive the battery voltage VBAT. The dynamic current source 106 further includes another PFET 116, which is cascoded with the PFET 1 14. Accordingly, the source of the PFET 116 is connected to the drain of the PFET 1 14. The drain of the PFET 116 is coupled to the output node 104. Furthermore, a capacitor 118 is coupled between the source of the PFET 116 and the gate of the PFET 1 14.

[0047] A resistive device 120 is coupled between the gate of the PFET 1 14 and the gate of the PFET 116. The resistive device 120 includes at least one resistor. In this embodiment, the resistive device 120 includes more than one resistor, which are coupled in series.

[0048] A resistive device 122 is coupled between the gate of the PFET 1 16 and the feedback node 112. The resistive device 122 includes at least one resistor. In this embodiment, the resistive device 122 includes more than one resistor, which are coupled in series.

[0049] A capacitor 124 is coupled between the gate of the PFET 1 14 and the gate of the PFET 1 16. Also, a capacitor 126 is coupled between the gate of the PFET 1 16 and the feedback node 112. A proportional to battery voltage current source (PBVCS) 128 is coupled between the battery node 102 and the gate of the PFET 1 14. A PBVCS 130 is coupled between the feedback node 112 and ground.2867-3431 -WO / P241474-WO-UTL 10

[0050] In FIG. 1 , in response to the output current Io having an output current level of 0 Amps, the dynamic current source 106 is configured to generate the variable current Iv with a current level that is equal to the constant current level of the constant current Ik that is generated by the constant current source 110. In response to the output current level of the output current Io increasing, the constant current source 110 pulls the feedback voltage level of the feedback voltage Vf at the feedback node 112 down. In response, the voltage level at the gate of the PFET 1 14 is pulled down and the PFET 114 thereby increases the variable current level of the variable current Iv. As a result, the dynamic current source 106 responds by delivering the needed increase in the output current level of the output current Io and the voltage level of the power source voltage VOUT is driven to a predetermined voltage level (i.e., the voltage level of the power source voltage VOUT dropped and then is increased to the predetermined voltage level when the dynamic current source 106 responds by delivering the needed increase in the output current level of the output current Io).

[0051] In response to the output current level of the output current Io decreasing, available current from the variable current Iv returns to the common gate amplifier 108, supplying the constant current Ik. The constant current Ik no longer pulls down the resistive devices 120, 122. This allows the feedback signal Vf to return upward to its static level. In response, the voltage level at the gate of the PFET 1 14 is pulled up and the PFET 1 14 thereby decreases the variable current level of the variable current Iv. As a result, the dynamic current source 106 responds by delivering the needed decrease in the output current level of the output current Io and the voltage level of the power source voltage VOUT is driven to a predetermined voltage level.

[0052] The PBVCS 128 is configured to generate a current having a current level. The current level is directly proportional to the voltage level of the battery voltage VBAT. The PBVCS 130 is also configured to generate a current having a current level. The current level is directly proportional to the voltage level of the battery voltage VBAT. The currents generated by the PBVCSs 128, 130, the resultant drop across the resistive devices 120, 122, and the charge stored by2867-3431 -WO / P241474-WO-UTL 1 1 the capacitors 124, 126 ensure that there is a sufficient voltage difference between the gates of the PFETs 1 14, 1 16 in order to generate an adequate voltage difference from the drain to the source of both of the PFETs 114, 116 in order to maintain the PFETs 114, 116 in the saturation region. Furthermore, the currents generated by the PBVCSs 128, 130 and the charge stored by the capacitors 124, 126 ensure that there is a sufficient voltage difference between the source and the drain of the common gate amplifier 108 in order to maintain the common gate amplifier 108 in the saturation region. If the voltage level of the battery voltage VBAT increases, the voltage differences between the PFETs 114, 1 16 and the common gate amplifier 108 (which is a PFET in this embodiment) are increased, thereby distributing the increased battery voltage VBAT across these devices to prevent over-voltage and Safe Operating Area (SOA) stress and to allow the PFETs 114, 116 and the common gate amplifier 108 to remain operational.

[0053] More specifically, the PFETs 1 14, 1 16 and the common gate amplifier 108 each have drain source voltages Vds of the PFETs 1 14, 1 16 and the common gate amplifier 108. The saturation mode of a PFET (like the PFETs 1 14, 1 16, and the common gate amplifier 108) is usually defined as the region for which Vds > (Vgs - Kt) (where Vgs is the gate-to-source voltage and Vt is the threshold voltage of the PFET). The voltage difference between the voltage level of the battery voltage VBAT and the power source voltage VOUT is shared between the drain source voltage Vd of the PFET 114 and the drain source voltage Vd of the PFET 116. The voltage drop across the resistive device 120 sets the gate voltage of the cascode PFET 1 16 so that the voltage difference is shared appropriately. The voltage level of the feedback signal Vf at the feedback node 112 is below the voltage level of the battery voltage VBAT by the sum of the gate source voltage of the PFET 114 and the voltage level drop across the resistive devices 120, 122. This maintains the drain source voltage Vd high enough across the common gate amplifier 108 to maintain the common gate amplifier 108 in saturation. Further, as the voltage level of the battery voltage VBAT changes, the voltage level of the gate voltage of the PFET 116 changes2867-3431 -WO / P241474-WO-UTL 12 proportionately. This prevents voltage stress on the PFETs 114, 116 at high voltage levels of the battery voltage VBAT.

[0054] The dynamic bias buffer 100 is configured to maintain the voltage level of the power source voltage VOIIT relatively steady, despite rapid changes in the current level of the output current Io while consuming low power while the load is idle. While the load connected to the output node 104 is idle, the current level of the output current Io is very low and, thus, the feedback signal Vf is set so that the variable current level is set to a specific current level relative to the constant current level. In some embodiments, the variable current level and the constant current level are both set to equal about 0.5 Microamps while the load is idle since almost all of the variable current Iv will be transmitted through the common gate amplifier 108 as the common gate amplifier current Ic. The current level of the common gate amplifier current Ic is approximately equal to the constant current level of the constant current Ik generated by the constant current source 1 10. In other embodiments, circuitry may be connected to the output node 104 such that the dynamic current level and the constant current level are not approximately equal while the load is idle. For example, a clamping circuit may be connected to the output node 104. In this case, the variable current level and the constant current level are both set to equal about 0.5 Microamps.

[0055] In response to the load becoming active, the current level of the output current Io will suddenly increase. This tends to result in the power source voltage VOIIT drooping, which will, thereby, result in the voltage at the source and the drain of the common gate amplifier 108 decreasing. In response, with the common gate amplifier current Ic decreasing, the constant current Ik is diverted to the resistive device 122 , resulting in the voltage level of the feedback signal Vf decreasing. As a result, the voltage levels of the voltages at the gates of the PFETs 114, 116 will decrease. In response, the PFETs 1 14, 1 16 will increase their current levels and pull up the voltage at their drains. Accordingly, this pulls up the voltage level of the power source voltage VOIIT.

[0056] In response to the load becoming idle again, the current level of the output current Io will suddenly decrease. This tends to result in the power source2867-3431 -WO / P241474-WO-UTL 13 voltage VOUT increasing, which will, thereby, result in the voltage at the source and the drain of the common gate amplifier 108 increasing. In response, with the common gate amplifier current Ic restored, the constant current Ik returns to the common gate amplifier 108 and the voltage level of the feedback signal Vf will increase. As a result, the voltage levels of the voltages at the gates of the PFETs 114, 116 will increase. In response, the PFETs 114, 116 will decrease their current levels, allowing the constant current Ik of the constant current source 110 to absorb the restored common gate amplifier current Ic from the common gate amplifier 108. Accordingly, this pulls down the voltage level of the power source voltage VOUT. In this manner, the voltage level of the power source voltage VOUT is maintained relatively steady by the dynamic bias buffer 100.

[0057] FIG. 2 illustrates a dynamic bias buffer 200, in accordance with some embodiments.

[0058] The dynamic bias buffer 200 is an embodiment of the dynamic bias buffer 100 shown in FIG. 1 . More specifically, the dynamic bias buffer 200 includes the battery node 102, the output node 104, the dynamic current source 106, the common gate amplifier 108, the constant current source 110, the feedback node 112, the PFETs 1 14, 116, the resistive devices 120, 122, the capacitors 124, 126, and the PBVCSs 128, 130, as described above with respect to FIG. 1.

[0059] In FIG. 2, the reference voltage VREF is generated by a reference voltage generator 202. The reference voltage generator 202 includes a resistive device 204 and a resistive device 206. The resistive device 204 is coupled between the gate of the common gate amplifier 108 and the gate of a PFET 207. The resistive device 206 is coupled between the gate of the PFET 207 and a ground node 210. The ground node 210 is configured to receive a ground voltage. A reference current pin 212 is configured to receive a reference current IREF1 . The reference current IREF1 has a non-zero magnitude and a positive polarity from the gate of the common gate amplifier 108. The reference voltage VREF is generated by the reference current IREF1 and is transmitted through the2867-3431 -WO / P241474-WO-UTL 14 resistive devices 204, 206. The reference current IREF1 is constant with respect to temperature, as such currents are available incidentally from certain bandgap reference architectures.

[0060] In FIG. 2, the constant current source 110 is formed by an N-channel field effect transistor (NFET) mirror. The constant current source 110 includes cascoded input NFETs, 214, 216. The source of the NFET 214 is coupled to a reference node 218 that is configured to receive a reference current IREF2. The reference current IREF2 has a non-zero magnitude and a positive polarity from the gate of the common gate amplifier 108. The drain of the NFET 214 is coupled to the reference node 218 in order to receive the reference current IREF2. The drain of the NFET 214 is coupled to the gate of the NFET 214. The source of the NFET 214 is coupled to the drain of the NFET 216. The drain of the NFET 216 is coupled to the gate of the NFET 216. The source of the NFET 216 is coupled to the ground node 210.

[0061] The constant current source 110 includes an output current source NFET 220 cascoded by an output NFET 219. The drain of the NFET 219 is coupled to the drain of the common gate amplifier 108. The source of the NFET 219 is coupled to the drain of the NFET 220. The source of the NFET 220 is coupled to the ground node 210. The gate of the NFET 219 is coupled to the gate of the NFET 214. The gate of the NFET 220 is coupled to the gate of the NFET 216. Thus, in response to the reference current IREF2 being received at the drain of the NFET 214, the constant current Ik is generated through the NFETs 219, 220.

[0062] In FIG. 2, the PBVCS 128 is formed by a PFET current mirror. The PBVCS 128 includes input PFETs 222, 224 and output PFETs 226, 228. The PFET 222 has a source coupled to the battery node 102. A drain of the PFET 222 is coupled to the source of the PFET 224. A drain of the PFET 224 is coupled to the source of the PFET 207. A gate of the PFET 222 is coupled to the drain of the PFET 224.

[0063] The PFET 226 has a source coupled to the battery node 102. A drain of the PFET 226 is coupled to the source of the PFET 228. A drain of the PFET2867-3431 -WO / P241474-WO-UTL 15228 is coupled to the gate of the PFET 1 14. A gate of the PFET 222 is coupled to the gate of the PFET 226. A gate of the PFET 224 is coupled to the gate of the PFET 228. The gate of the PFET 207 is set at a fixed voltage level at a tap on a resistive divider formed by the resistive devices 204, 206. Since the reference current IREF1 is a constant current, a voltage level of a tap voltage Vtap at the tap of the resistive divider is also constant. A resistor 205 (having a resistance R) is connected between the source of the PFET 207 and the gate of the PFET 222. Current flows in the circuit branch with the PFET 207 so that the source of the PFET 207 is pinned to a voltage equal to one gate source voltage above the tap voltage Vtap of the resistive divider formed by the resistive devices 204, 206 while the source of the PFET 222 is at the battery voltage VBAT voltage. As a result, current in this the circuit branch with the PFET 207 is equal to VBAT - (2Vgs - Vtap) / R. Therefore, the circuit branch with the PFET 207 carries essentially zero current at the low battery voltage VBAT and produces a current proportional to the battery voltage VBAT when the battery voltage VBAT is two gate source voltage drops above the tap voltage Vtap. This allows the full battery voltage VBAT to be available to the circuit (i.e., the dynamic bias buffer 200) at low voltages and protects the circuit at high voltages. Further, the current produced in the PBVCS 128 is passed to the PBVCS 130 through the PFET 207, which also acts as a cascode to deliver this current to the PBVCS 130. This means that the same current delivered to the resistive devices 120, 122 by the PBVCS 128 is absorbed by the PBVCS 130. In this manner, the resistive devices 120, 122 behave as floating voltage sources. The resistive devices 120, 122 both protect devices from over-voltage and are able to be driven quickly by the feedback signal Vf in response to output current level changes. This allows the current sourcing PFET 114 and the cascode PFET 116 to move very quickly together and deliver fast transient currents that are demanded by the current drawn from the output node 104.

[0064] In FIG. 2, the PBVCS 130 is formed by an NFET current mirror. The PBVCS 130 includes input NFETs 230, 232 and output NFETs 234, 236. The NFET 230 has a source coupled to the ground node 210. A drain of the NFET2867-3431 -WO / P241474-WO-UTL 16230 is coupled to the source of the NFET 232. A drain of the NFET 232 is coupled to the drain of the PFET 207. A gate of the NFET 230 is coupled to the drain of the NFET 230. A gate of the NFET 232 is coupled to the drain of the NFET 232.

[0065] The NFET 234 has a source coupled to the ground node 210. A drain of the NFET 234 is coupled to the source of the NFET 236. A drain of the NFET 236 is coupled to the feedback node 112. A gate of the NFET 230 is coupled to the gate of the NFET 234. A gate of the NFET 232 is coupled to the gate of the NFET 236. In this manner, a current based on a voltage level of the battery voltage VBAT is generated through the output NFETs 234, 236.

[0066] The dynamic bias buffer 200 includes a cascode circuit 240 that is configured to bias cascode field effect transistors. The cascode circuit 240 includes a PFET 242. The PFET 242 has a source coupled to the battery node 102 and a gate connected to its drain. The drain of the PFET 242 is connected to the gates of the PFETs 224, 228. The drain of the PFET 242 is coupled to a drain of an NFET 244.

[0067] The gate of the NFET 244 is connected to the source of the PFET 207. The source of the NFET 244 is coupled to the drain of an NFET 246. The source of the NFET 246 is coupled to the drain of an NFET 248. The source of the NFET 248 is coupled to the ground node 210. The gate of the NFET 246 is coupled to the gates of the NFETs 232, 236. The gate of the NFET 248 is coupled to the gates of the NFETs 230, 234. In this manner, once the PFET 207 is turned on, the PFET 242 generates a cascode voltage for the PFETs 224, 228. Furthermore, the current through the NFETs 230, 232 generates a current through the NFETs 246, 248.

[0068] FIG. 3 is a graph that illustrates the power source voltage VOIIT and the output current Io versus time with regards to the operation of the dynamic bias buffer 200 as shown in FIG. 2, in accordance with some embodiments.

[0069] As shown in FIG. 3, from 0 microseconds to 1 microsecond, the load is idle. The power source voltage VOUT is set to the predetermined voltage level of 2.5 Volts. At 1 microsecond, the load becomes active and the power source2867-3431 -WO / P241474-WO-UTL 17 voltage VOUT briefly drops. At this point, the dynamic current source 106 increases the variable current Iv to drive the power source voltage VOUT back to the predetermined voltage level of 2.5 Volts. The load again becomes idle at 2 microseconds, where the dynamic current source 106 decreases the current to maintain the power source voltage VOUT at 2.5 Volts. The output current Io (not shown in FIG. 3), in a simulation related to the behavior shown in FIG. 3, changes from idle current levels to full current levels in 1 nanosecond and from full current levels back to idle current levels in 1 nanosecond. The spike in the voltage level of the power source voltage VOUT has a duration proportional to the feedback loop delay which, even under these strenuous test conditions, drives the voltage level of the power source voltage VOUT to the predetermined voltage level without overshoot in a few nanoseconds.

[0070] FIG. 4 is a graph 400 that illustrates the power source voltage VOUT versus the battery voltage VBAT with regards to the operation of the dynamic bias buffer 200 as shown in FIG. 2, in accordance with some embodiments.

[0071] As shown in FIG. 4, the voltage level of the battery voltage VBAT can vary between 2.5 Volts to 6 Volts. Nevertheless, the power source voltage VOUT only varies between 2.33 Volts to 2.44 Volts. Change in the voltage level of the output voltage is 32 Millivolts for each change in the battery voltage VBAT level of 1 .0 Volt. A standard approach to increase accuracy is to apply the reference voltage VREF to an operational amplifier, have the output of this operational amplifier drive the gate of the common gate amplifier 108, and return the source of the common gate amplifier 108 to the inverting input of the common gate amplifier 108 as the feedback signal Vf. In some embodiments, this would reduce the change in the power source voltage VOUT to the Millivolt level, but this may cause slewing and small-signal settling times for the common gate amplifier 108. In some embodiments, dynamic bias techniques are applied to the common gate amplifier 108 if idle current levels of the output current Io are to remain nearly as low as those delivered by the dynamic bias buffer 200. In some embodiments, the dynamic bias buffers 100, 200 disclosed are advantageous in2867-3431 -WO / P241474-WO-UTL 18 applications where very low idle current, very fast response time, and moderate output voltage accuracy are required.

[0072] FIG. 5 is a flow chart 500 that illustrates a method of generating a power source voltage from a battery voltage.

[0073] An example of the power source voltage is the power source voltage VOIIT as discussed above with respect to FIGs. 1 and 2. An example of the battery voltage is the battery voltage VBAT as discussed above with respect to FIGs. 1 and 2. The flow chart 500 may be implemented by the dynamic bias buffer 100 shown in FIG. 1 or the dynamic bias buffer 200 shown in FIG. 2. The flow chart includes blocks 502-510. Flow begins at block 502.

[0074] At block 502, a variable current is generated having a variable current level set in accordance with a feedback signal. In some embodiments, block 502 is performed by the dynamic current source 106 as described above with respect to FIGs. 1 and 2. An example of the variable current is the variable current Iv described above with respect to FIGs. 1 and 2. An example of the feedback signal is the feedback signal Vf as shown in FIGs. 1 and 2. Flow then proceeds to block 504.

[0075] At block 504, a common gate amplifier current is generated having a common gate amplifier current level from at least a portion of the variable current. In some embodiments, the common gate amplifier 108 performs block 504. An example of the common gate amplifier current is the common gate amplifier current Ic. Flow then proceeds to block 505.

[0076] At block 505, a power source voltage is generated at an output node. An example of the power source voltage is the power source voltage VOUT. An example of the output node is the output node 104. In some embodiments, block 505 is performed by the common gate amplifier 108 in FIGs. 1 and 2. In some embodiments, the output node is between the dynamic current source and the common gate amplifier. Flow then proceeds to block 506.

[0077] At block 506, a constant current is generated with a constant current level. In some embodiments, the constant current is generated by the constant2867-3431 -WO / P241474-WO-UTL 19 current source 110. An example of the constant current is the constant current Ik as shown in FIGs. 1 and 2. Flow then proceeds to block 508.

[0078] At block 508, a feedback signal indicative of the common gate amplifier current level is generated. In some embodiments, the feedback signal is the feedback signal Vf as shown in FIGs. 1 and 2. Flow then proceeds to block 510.

[0079] At block 510, the variable current level is adjusted in accordance to the feedback signal so as to drive the power source voltage at the output node to a predetermined voltage level. In some embodiments, the dynamic current source 106 is configured to perform block 510.

[0080] With reference to FIG. 6, the concepts described above may be implemented in various types of user elements 600, such as mobile terminals, smart watches, tablets, computers, navigation devices, access points, and like wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, and near field communications.

[0081] The user element 600 will generally include a control system 602, a baseband processor 604, transmit circuitry 606, receive circuitry 608, antenna switching circuitry 610, multiple antennas 612, and user interface circuitry 614. In a non-limiting example, the control system 602 may be a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). In this regard, the control system 602 may include at least microprocessor(s), embedded memory circuit(s), and communication bus interface(s). The receive circuitry 608 receives radio frequency signals via the antennas 612 and through the antenna switching circuitry 610 from one or more base stations. A low noise amplifier and a filter cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using analog-to-digital converter(s) (ADC).

[0082] The baseband processor 604 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This2867-3431 -WO / P241474-WO-UTL 20 processing typically comprises demodulation, decoding, and error correction operations, as will be discussed in greater detail below. The baseband processor 604 is generally implemented in one or more digital signal processors (DSPs) and ASICs.

[0083] For transmission, the baseband processor 604 receives digitized data, which may represent voice, data, or control information, from the control system 602, which it encodes for transmission. The encoded data is output to the transmit circuitry 606, where digital-to-analog converter(s) (DAC) convert the digitally encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission and deliver the modulated carrier signal to the antennas 612 through the antenna switching circuitry 610. The multiple antennas 612 and the replicated transmit and receive circuitries 606, 608 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0084] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims

2867-3431 -WO / P241474-WO-UTL 21ClaimsWhat is claimed is:1 . A dynamic bias buffer, comprising: a dynamic current source configured to generate a variable current having a variable current level set in accordance with a feedback signal; an output node for coupling to a load; a common gate amplifier configured to generate a power source voltage at the output node, wherein the output node is between the dynamic current source and the common gate amplifier so that a common gate amplifier current having a common gate amplifier current level is received from the dynamic current source; and a constant current source configured to generate a constant current with a constant current level, wherein the dynamic current source is coupled to the common gate amplifier so as to receive the feedback signal indicative of the common gate amplifier current level and wherein the dynamic current source is responsive to adjust the variable current level in accordance with the feedback signal so as to drive a power source voltage level of the power source voltage at the output node to a predetermined voltage level.

2. The dynamic bias buffer of claim 1 , wherein the predetermined voltage level is 2.5 Volts.

3. The dynamic bias buffer of claim 1 , wherein the common gate amplifier comprises a P-channel field effect transistor (PFET) having a gate configured to receive a reference voltage.

4. The dynamic bias buffer of claim 3, wherein the reference voltage has a positive polarity and a non-zero magnitude.2867-3431 -WO / P241474-WO-UTL 225. The dynamic bias buffer of claim 1 , wherein the dynamic current source is configured to receive a battery voltage, the dynamic current source comprising: a first P-channel field effect transistor (PFET) having a first source, a first gate, and a first drain, wherein the first source is coupled to receive the battery voltage; and a second PFET having a second source, a second gate, and a second drain, wherein the second PFET is cascaded with the first PFET such that the first drain is coupled to the first source and the second drain is coupled to the output node.

6. The dynamic bias buffer of claim 5, wherein the common gate amplifier comprises a third PFET having a third source, a third drain, and a third gate, wherein: the third gate is configured to receive a reference voltage; the third source is coupled to the second drain; and the third drain is coupled to the constant current source.

7. The dynamic bias buffer of claim 6, wherein the third drain is coupled to the constant current source at a feedback node, wherein the dynamic current source is configured to receive the feedback signal from the feedback node.

8. The dynamic bias buffer of claim 7, further comprising: a first resistive device coupled between the first gate and the second gate; and a second resistive device coupled between the second gate and the feedback node.

9. The dynamic bias buffer of claim 8, further comprising: a first proportional to battery voltage current source (PBVCS) coupled between the first source and the first gate; and a second PBVCS coupled between the feedback node and ground.2867-3431 -WO / P241474-WO-UTL 2310. The dynamic bias buffer of claim 9, further comprising: a first capacitive device coupled between the first gate and the second gate; and a second capacitive device coupled between the second gate and the feedback node.1 1 . The dynamic bias buffer of claim 9, wherein the first PBVCS comprises a PFET mirror circuit and the second PBVCS is an N-channel field effect transistor (NFET) mirror, wherein the PFET mirror circuit is coupled to the NFET mirror.

12. The dynamic bias buffer of claim 1 , wherein the constant current source comprises an N-channel field effect transistor (NFET) mirror.

13. The dynamic bias buffer of claim 1 , further comprising: a voltage clamp coupled to the output node.

14. A method of generating a power source voltage from a battery voltage, comprising: generating a variable current having a variable current level set in accordance with a feedback signal; generating a common gate amplifier current having a common gate amplifier current level from at least a portion of the variable current; generating a power source voltage at an output node; generating a constant current with a constant current level; receiving the feedback signal indicative of the common gate amplifier current level; and adjusting the variable current level in accordance with the feedback signal so that a dynamic current level and the constant current level are set to a predetermined proportion.2867-3431 -WO / P241474-WO-UTL 2415. A user element comprising a dynamic bias buffer, the dynamic bias buffer comprising: a dynamic current source configured to generate a variable current having a variable current level set in accordance with a feedback signal; an output node for coupling to a load; a common gate amplifier configured to generate a power source voltage at the output node, wherein the output node is between the dynamic current source and the common gate amplifier so that a common gate amplifier current having a common gate amplifier current level is received from the dynamic current source; and a constant current source configured to generate a constant current with a constant current level, wherein the dynamic current source is coupled to the common gate amplifier so as to receive the feedback signal indicative of the common gate amplifier current level and wherein the dynamic current source is responsive to adjust the variable current level in accordance with the feedback signal so as to drive a power source voltage level of the power source voltage at the output node to a predetermined voltage level.

16. The user element of claim 15, wherein the predetermined voltage level is 2.5 Volts.

17. The user element of claim 15, wherein the common gate amplifier comprises a P-channel field effect transistor (PFET) having a gate configured to receive a reference voltage.

18. The user element of claim 17, wherein the reference voltage has a positive polarity and a non-zero magnitude.

19. The user element of claim 18, wherein the dynamic current source is configured to receive a battery voltage, the dynamic current source comprising:2867-3431 -WO / P241474-WO-UTL 25 a first PFET having a first source, a first gate, and a first drain, wherein the first source is coupled to receive the battery voltage; and a second PFET having a second source, a second gate, and a second drain, wherein the second PFET is cascaded with the first PFET such that the first drain is coupled to the first source and the second drain is coupled to the output node.

20. The user element of claim 19, wherein the common gate amplifier comprises a third PFET having a third source, a third drain, and a third gate, wherein: the third gate is configured to receive the reference voltage; the third source is coupled to the second drain; and the third drain is coupled to the constant current source.

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