Shift register unit, driving method, gate driving circuit, and display device

Abstract

A shift register unit, a driving method, a gate driving circuit, and a display device. The shift register unit comprises: a first input circuit (10) configured to provide a signal of a first reference voltage signal end (VREF1) to a first node (N1) in response to a signal of an input signal end (IPT); a second input circuit (20) configured to provide a signal of a second reference voltage signal end (VREF2) to the first node (N1) in response to a signal of a reset signal end (RST); a first control circuit (30) configured to control the level of a signal of the first node (N1) to be opposite to that of a second node (N2); a second control circuit (40) coupled to the second node (N2) and configured to provide a signal of a third reference voltage signal end (VREF3) to the second node (N2) in response to the signal of the input signal end (IPT) and a signal of an output signal end (OPT); and an output circuit (50) coupled to the first node (N1) and the second node (N2), and configured to provide a signal of a clock signal end (CLK) to the output signal end (OPT) in response to the signal of the first node (N1), and provide the signal of the third reference voltage signal end (VREF3) to the output signal end (OPT) in response to the signal of the second node (N2).

Description

Shift register unit, driving method, gate driving circuit and display device TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a shift register unit, a driving method, a gate driving circuit and a display device. BACKGROUND

[0002] With the rapid development of display technology, display presents the development trend of high integration and low cost. Among them, the array substrate row driving (Gate Driver on Array, GOA) technology integrates the thin film transistor (Thin Film Transistor, TFT) gate switch circuit on the array substrate of the display panel to form the scanning driving of the display panel, so as to save the bonding area and the fan-out area of the gate integrated circuit (Integrated Circuit, IC) wiring space, which can not only reduce the product cost in terms of material cost and manufacturing process, but also make the display panel symmetrical and narrow frame design. Moreover, this integrated process can also save the bonding process in the gate scanning line direction, thereby improving the production capacity and yield.

[0003] SUMMARY

[0004] Some embodiments of the present disclosure provide a shift register unit, comprising:

[0005] A first input circuit is coupled to the first node and is configured to provide a signal of a first reference voltage signal terminal to the first node in response to a signal of an input signal terminal;

[0006] A second input circuit is coupled to the first node and is configured to provide a signal of a second reference voltage signal terminal to the first node in response to a signal of a reset signal terminal;

[0007] A first control circuit is coupled to the first node and a second node and is configured to control the signal level of the first node and the second node to be opposite;

[0008] A second control circuit is coupled to the second node and is configured to provide a signal of a third reference voltage signal terminal to the second node in response to signals of the input signal terminal and an output signal terminal;

[0009] The output circuit is coupled to the first node and the second node and is configured to provide a signal of a clock signal terminal to the output signal terminal in response to the signal of the first node, and provide a signal of the third reference voltage signal terminal to the output signal terminal in response to the signal of the second node.

[0010] In some possible implementation provided by the present disclosure, the second control circuit comprises: a first transistor and a second transistor;

[0011] a gate of the first transistor is coupled with the input signal terminal, a first pole of the first transistor is coupled with the second node, and a second pole of the first transistor is coupled with the third reference voltage signal terminal;

[0012] a gate of the second transistor is coupled with the output signal terminal, a first pole of the second transistor is coupled with the second node, and a second pole of the second transistor is coupled with the third reference voltage signal terminal.

[0013] In some possible implementation provided by the present disclosure, the first control circuit comprises: a third transistor and a fourth transistor;

[0014] a gate of the third transistor is coupled with the second node, a first pole of the third transistor is coupled with the first node, and a second pole of the third transistor is coupled with the third reference voltage signal terminal;

[0015] a gate of the fourth transistor is coupled with a fourth reference voltage signal terminal, a first pole of the fourth transistor is coupled with the fourth reference voltage signal terminal, and a second pole of the fourth transistor is coupled with the second node.

[0016] In some possible implementation provided by the present disclosure, the first control circuit, coupled with the first node, the second node and the third node, is configured to: in response to a signal of the fourth reference voltage signal terminal and the third node, provide a signal of the fourth reference voltage signal terminal to the second node and the third node; in response to signals of the input signal terminal and the output signal terminal, provide a signal of the third reference voltage signal terminal to the second node; and in response to a signal of the second node, provide a signal of the third reference voltage signal terminal to the first node.

[0017] In some possible implementation provided by the present disclosure, the first control circuit comprises: a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a ninth transistor;

[0018] a gate of the fifth transistor is coupled with the second node, a first pole of the fifth transistor is coupled with the first node, and a second pole of the fifth transistor is coupled with the third reference voltage signal terminal;

[0019] a gate of the sixth transistor is coupled with the third node, a first pole of the sixth transistor is coupled with the fourth reference voltage signal terminal, and a second pole of the sixth transistor is coupled with the second node.

[0020] a gate of the seventh transistor is coupled with the fourth reference voltage signal terminal, a first electrode of the seventh transistor is coupled with the fourth reference voltage signal terminal, and a second electrode of the seventh transistor is coupled with the third node;

[0021] a gate of the eighth transistor is coupled with the input signal terminal, a first electrode of the eighth transistor is coupled with the third node, and a second electrode of the eighth transistor is coupled with the third reference voltage signal terminal;

[0022] a gate of the ninth transistor is coupled with the output signal terminal, a first electrode of the ninth transistor is coupled with the third node, and a second electrode of the ninth transistor is coupled with the third reference voltage signal terminal.

[0023] In some possible implementation provided by the present disclosure, the second node comprises a plurality of second sub-nodes; the first control circuit comprises a plurality of first control sub-circuits; and the second control circuit comprises a plurality of second control sub-circuits.

[0024] The plurality of first control sub-circuits correspond to the plurality of second sub-nodes one by one; and the plurality of second control sub-circuits correspond to the plurality of second sub-nodes one by one.

[0025] Each of the first control sub-circuits is configured to control the signal level of the first node to be opposite to that of the corresponding second sub-node.

[0026] Each of the second control sub-circuits is configured to provide the signal of the third reference voltage signal terminal to the corresponding second sub-node in response to the signals of the output signal terminal and the input signal terminal.

[0027] In some possible implementation provided by the present disclosure, the second control sub-circuit comprises a tenth transistor and an eleventh transistor.

[0028] a gate of the tenth transistor is coupled with the output signal terminal, a first electrode of the tenth transistor is coupled with the corresponding second sub-node, and a second electrode of the tenth transistor is coupled with the third reference voltage signal terminal;

[0029] a gate of the eleventh transistor is coupled with the input signal terminal, a first electrode of the eleventh transistor is coupled with the corresponding second sub-node, and a second electrode of the eleventh transistor is coupled with the third reference voltage signal terminal.

[0030] In some possible implementation provided by the present disclosure, the first control sub-circuit comprises a twelfth transistor and a thirteenth transistor.

[0031] A gate of the twelfth transistor is coupled with the corresponding second sub-node, a first pole of the twelfth transistor is coupled with the first node, and a second pole of the twelfth transistor is coupled with the third reference voltage signal end;

[0032] A gate of the thirteenth transistor is coupled with the fifth reference voltage signal end, a first pole of the thirteenth transistor is coupled with the fifth reference voltage signal end, and a second pole of the thirteenth transistor is coupled with the corresponding second sub-node.

[0033] In some possible implementation modes provided by the present disclosure, the first control sub-circuit, coupled with the first node, the corresponding second sub-node and the third node, is configured to provide the signal of the third reference voltage signal end to the third node in response to the signal of the output signal end and the signal of the input signal end, provide the signal of the fifth reference voltage signal end to the third node and the corresponding second sub-node in response to the signal of the fifth reference voltage signal end and the signal of the third node, and provide the signal of the third reference voltage signal end to the first node in response to the signal of the corresponding second sub-node.

[0034] In some possible implementation modes provided by the present disclosure, the first control sub-circuit includes a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor and an eighteenth transistor.

[0035] A gate of the fourteenth transistor is coupled with the corresponding second sub-node, a first pole of the fourteenth transistor is coupled with the first node, and a second pole of the fourteenth transistor is coupled with the third reference voltage signal end;

[0036] A gate of the fifteenth transistor is coupled with the third node, a first pole of the fifteenth transistor is coupled with the fifth reference voltage signal end, and a second pole of the fifteenth transistor is coupled with the corresponding second sub-node.

[0037] A gate of the sixteenth transistor is coupled with the fifth reference voltage signal end, a first pole of the sixteenth transistor is coupled with the fifth reference voltage signal end, and a second pole of the sixteenth transistor is coupled with the third node.

[0038] A gate of the seventeenth transistor is coupled with the output signal end, a first pole of the seventeenth transistor is coupled with the third node, and a second pole of the seventeenth transistor is coupled with the third reference voltage signal end.

[0039] A gate of the eighteenth transistor is coupled with the input signal end, a first pole of the eighteenth transistor is coupled with the third node, and a second pole of the eighteenth transistor is coupled with the third reference voltage signal end.

[0040] In some possible implementation provided by the present disclosure, the signal of the output signal terminal is the same as the signal of the first reference voltage signal terminal.

[0041] The signal of the second reference voltage signal terminal is the same as the signal of the third reference voltage signal terminal.

[0042] In some possible implementation provided by the present disclosure, further comprising a cascade circuit coupled with the first node and the second node, configured to provide the signal of the clock signal terminal to a cascade signal terminal in response to the signal of the first node, and provide the signal of the third reference voltage signal terminal to the cascade signal terminal in response to the signal of the second node.

[0043] In some possible implementation provided by the present disclosure, the cascade circuit comprises a first cascade transistor, a second cascade transistor and a third cascade transistor.

[0044] The gate of the first cascade transistor is coupled with the first node, the first pole of the first cascade transistor is coupled with the clock signal terminal, and the second pole of the first cascade transistor is coupled with the cascade signal terminal.

[0045] The gate of the second cascade transistor is coupled with the second node, the first pole of the second cascade transistor is coupled with the cascade signal terminal, and the second pole of the second cascade transistor is coupled with the third reference voltage signal terminal.

[0046] The gate of the third cascade transistor is coupled with the second node, the first pole of the third cascade transistor is coupled with the cascade signal terminal, and the second pole of the third cascade transistor is coupled with the third reference voltage signal terminal.

[0047] The gate drive circuit provided by some embodiments of the present disclosure comprises a cascade of the above-mentioned shift register units, the input signal terminal of the first stage shift register unit is connected with a frame start signal terminal, the input signal terminal of each shift register unit is connected with the output signal terminal of the previous stage shift register unit except the first stage shift register unit, and the reset signal terminal of each shift register unit is connected with the output signal terminal of the next stage shift register unit except the last stage shift register unit.

[0048] Some embodiments of the present disclosure provide a gate drive circuit, which comprises a plurality of cascaded shift register units as described above. An input signal terminal of a first shift register unit is connected to a frame start signal terminal. An input signal terminal of each shift register unit, except the first shift register unit, is connected to a cascade signal terminal of a previous shift register unit. A reset signal terminal of each shift register unit, except the last shift register unit, is connected to a cascade signal terminal of a next shift register unit. An output signal terminal of each shift register unit is connected to a corresponding gate line.

[0049] Some embodiments of the present disclosure provide a display device, which comprises a gate drive circuit as described above.

[0050] Some embodiments of the present disclosure provide a driving method of a shift register unit as described above, which comprises:

[0051] In the input stage, the first input circuit provides a signal of the first reference voltage signal terminal to the first node in response to a signal of the input signal terminal; and the second control circuit provides a signal of the third reference voltage signal terminal to the second node in response to the signal of the input signal terminal.

[0052] In the output stage, the second control circuit provides a signal of the third reference voltage signal terminal to the second node in response to a signal of the output signal terminal; and the output circuit provides a signal of the clock signal terminal to the output signal terminal in response to a signal of the first node.

[0053] In the reset stage, the second input circuit provides a signal of the second reference voltage signal terminal to the first node in response to a signal of the reset signal terminal; the first control circuit controls the signal of the first node to be opposite to that of the second node; and the output circuit provides a signal of the third reference voltage signal terminal to the output signal terminal in response to a signal of the second node. BRIEF DESCRIPTION OF DRAWINGS

[0054] FIG. 1 is a schematic diagram of some structures of a shift register unit according to some embodiments of the present disclosure;

[0055] FIG. 2 is a schematic diagram of other structures of a shift register unit according to some embodiments of the present disclosure;

[0056] FIG. 3 is a flow chart of a driving method of a shift register unit according to some embodiments of the present disclosure;

[0057] FIG. 4 is a timing diagram of some signals according to some embodiments of the present disclosure;

[0058] FIG. 5 is a schematic diagram of further structures of a shift register unit according to some embodiments of the present disclosure;

[0059] Fig. 6 is another structural schematic diagram of a shift register unit provided by an embodiment of the present disclosure;

[0060] Fig. 7 is another structural schematic diagram of a shift register unit provided by an embodiment of the present disclosure;

[0061] Fig. 8 is another structural schematic diagram of a shift register unit provided by an embodiment of the present disclosure;

[0062] Fig. 9 is another signal timing diagram provided by an embodiment of the present disclosure;

[0063] Fig. 10 is another structural schematic diagram of a shift register unit provided by an embodiment of the present disclosure;

[0064] Fig. 11 is another structural schematic diagram of a shift register unit provided by an embodiment of the present disclosure;

[0065] Fig. 12 is another structural schematic diagram of a shift register unit provided by an embodiment of the present disclosure;

[0066] Fig. 13 is a structural schematic diagram of a gate drive circuit provided by an embodiment of the present disclosure;

[0067] Fig. 14 is another structural schematic diagram of a shift register unit provided by an embodiment of the present disclosure;

[0068] Fig. 15 is another structural schematic diagram of a shift register unit provided by an embodiment of the present disclosure;

[0069] Fig. 16 is a structural schematic diagram of a gate drive circuit provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0070] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. And the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present disclosure.

[0071] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the same meaning as commonly understood by one of ordinary skill in the art to which this present disclosure belongs. Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the same meaning as commonly understood by one of ordinary skill in the art to which this present disclosure belongs. The terms "first", "second", and similar terms do not denote any order, quantity, or importance, but are used to distinguish different components. The terms "include" or "contain" and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connected" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0072] It should be noted that the size and shape of the figures in the drawings do not reflect the true proportions, but only serve to illustrate the present disclosure. The same or similar reference numerals represent the same or similar elements or elements having the same or similar functions throughout.

[0073] The shift register unit provided by the embodiments of the present disclosure, as shown in FIG. 1, comprises:

[0074] The first input circuit 10 is coupled to the first node N1 and is configured to provide the signal of the first reference voltage signal end VREF1 to the first node N1 in response to the signal of the input signal end IPT;

[0075] The second input circuit 20 is coupled to the first node N1 and is configured to provide the signal of the second reference voltage signal end VREF2 to the first node N1 in response to the signal of the reset signal end RST;

[0076] The first control circuit 30 is coupled to the first node N1 and the second node N2 and is configured to control the signal level of the first node N1 and the second node N2 to be opposite;

[0077] The second control circuit 40 is coupled to the second node N2 and is configured to provide the signal of the third reference voltage signal end VREF3 to the second node N2 in response to the signals of the input signal end IPT and the output signal end OPT;

[0078] The output circuit 50 is coupled to the first node N1 and the second node N2 and is configured to provide the signal of the clock signal end CLK to the output signal end OPT in response to the signal of the first node N1, and provide the signal of the third reference voltage signal end VREF3 to the output signal end OPT in response to the signal of the second node N2.

[0079] The shift register unit provided by the embodiments of the present disclosure can ensure that the signal of the second node is low when the signal of the first node is high, thereby stabilizing the signal of the first node, improving the charging capability of the first node, avoiding the competitive relationship between the first node and the second node, improving the reliability of the shift register unit, and improving the output stability of the shift register unit. In addition, through the mutual cooperation of the first input circuit, the second input circuit, the first control circuit, the second control circuit, and the output circuit, the shift register unit can also realize the forward and reverse scanning function.

[0080] In some embodiments of the present disclosure, as shown in FIG. 2, the second control circuit 40 includes a first transistor M1 and a second transistor M2; wherein the gate of the first transistor M1 is coupled with the input signal terminal IPT, the first pole of the first transistor M1 is coupled with the second node N2, and the second pole of the first transistor M1 is coupled with the third reference voltage signal terminal VREF3; the gate of the second transistor M2 is coupled with the output signal terminal OPT, the first pole of the second transistor M2 is coupled with the second node N2, and the second pole of the second transistor M2 is coupled with the third reference voltage signal terminal VREF3.

[0081] In some embodiments of the present disclosure, as shown in FIG. 2, the first control circuit 30 includes a third transistor M3 and a fourth transistor M4; wherein the gate of the third transistor M3 is coupled with the second node N2, the first pole of the third transistor M3 is coupled with the first node N1, and the second pole of the third transistor M3 is coupled with the third reference voltage signal terminal VREF3; the gate of the fourth transistor M4 is coupled with the fourth reference voltage signal terminal VREF4, the first pole of the fourth transistor M4 is coupled with the fourth reference voltage signal terminal VREF4, and the second pole of the fourth transistor M4 is coupled with the second node N2.

[0082] In some embodiments of the present disclosure, as shown in FIG. 2, the first input circuit 10 comprises: a first input transistor MR1; wherein the gate of the first input transistor MR1 is coupled with the input signal end IPT, the first pole of the first input transistor MR1 is coupled with the first reference voltage signal end VREF1, and the second pole of the first input transistor MR1 is coupled with the first node N1.

[0083] In some embodiments of the present disclosure, as shown in FIG. 2, the second input circuit 20 comprises: a second input transistor MR2; wherein the gate of the second input transistor MR2 is coupled with the reset signal end RST, the first pole of the second input transistor MR2 is coupled with the first node N1, and the second pole of the second input transistor MR2 is coupled with the second reference voltage signal end VREF2.

[0084] In some embodiments of the present disclosure, as shown in FIG. 2, the output circuit 50 comprises: a first output transistor MC1, a second output transistor MC2, and a first capacitor C1; wherein the gate of the first output transistor MC1 is coupled with the first node N1, the first pole of the first output transistor MC1 is coupled with the clock signal end CLK, and the second pole of the first output transistor MC1 is coupled with the output signal end OPT; the gate of the second output transistor MC2 is coupled with the second node N2, the first pole of the second output transistor MC2 is coupled with the output signal end OPT, and the second pole of the second output transistor MC2 is coupled with the third reference voltage signal end VREF3; the first electrode of the first capacitor C1 is coupled with the first node N1, and the second electrode of the first capacitor C1 is coupled with the output signal end OPT.

[0085] In some embodiments of the present disclosure, as shown in FIG. 2, the shift register unit further comprises: a frame reset circuit 60, coupled with the first node N1 and the output signal end OPT, configured to provide the signal of the third reference voltage signal end VREF3 to the first node N1 and the output signal end OPT in response to the signal of the frame reset signal end TRST.

[0086] In some embodiments of the present disclosure, as shown in FIG. 2, the frame reset circuit 60 comprises: a first reset transistor MF1 and a second reset transistor MF2; wherein the gate of the first reset transistor MF1 is coupled with the frame reset signal end TRST, the first pole of the first reset transistor MF1 is coupled with the first node N1, and the second pole of the first reset transistor MF1 is coupled with the third reference voltage signal end VREF3; the gate of the second reset transistor MF2 is coupled with the frame reset signal end TRST, the first pole of the second reset transistor MF2 is coupled with the first node N1, and the second pole of the second reset transistor MF2 is coupled with the third reference voltage signal end VREF3.

[0087] The embodiment of the present disclosure provides a driving method of a shift register unit, as shown in FIG. 3, comprising the following steps:

[0088] In the input stage, the first input circuit provides the signal of the first reference voltage signal end to the first node in response to the signal of the input signal end; and the second control circuit provides the signal of the third reference voltage signal end to the second node in response to the input signal end.

[0089] In the output stage, the second control circuit provides the signal of the third reference voltage signal end to the second node in response to the signal of the output signal end; and the output circuit provides the signal of the clock signal end to the output signal end in response to the signal of the first node.

[0090] In the reset stage, the second input circuit provides the signal of the second reference voltage signal end to the first node in response to the signal of the reset signal end; the first control circuit controls the signal level of the first node to be opposite to that of the second node; and the output circuit provides the signal of the third reference voltage signal end to the output signal end in response to the signal of the second node.

[0091] For example, in order to reduce the preparation process, all the transistors can be P-type transistors, or all the transistors can be N-type transistors, which are not limited herein. Further, the N-type transistor is turned on under the action of a high-level signal and is turned off under the action of a low-level signal; and the P-type transistor is turned off under the action of a high-level signal and is turned on under the action of a low-level signal.

[0092] It should be noted that the transistors mentioned in the above embodiments of the present disclosure can be thin film transistors (TFT) or metal oxide semiconductor field effect transistors (MOS), which are not limited herein. In the specific implementation, the first pole of the transistor can be used as the source pole and the second pole can be used as the drain pole, or the first pole can be used as the drain pole and the second pole can be used as the source pole according to the type of the transistor and the input signal, which are not distinguished herein.

[0093] Further, in the shift register unit provided in the embodiment of the present disclosure, the first input circuit and the second input circuit are symmetrically designed, and the function interchange can be realized, so that the shift register unit provided in the embodiment of the present disclosure can realize bidirectional scanning. When the reverse scanning is performed, the functions of the first input circuit and the second input circuit of the shift register unit are interchanged, that is, with respect to the forward scanning, the second input circuit is used as the first input circuit, the reset signal end is used as the input signal end, the first input circuit is used as the second input circuit, and the input signal end is used as the reset signal end.

[0094] For example, the above-mentioned transistors are all configured as N-type transistors, and in the forward scanning, the first reference voltage signal terminal VREF1 can be configured to load a constant first reference voltage signal, and the first reference voltage signal is positive, and the first reference voltage signal is a high level signal. And, the second reference voltage signal terminal VREF2 can be configured to load a constant second reference voltage signal, and the second reference voltage signal is negative, and the second reference voltage signal is a low level signal. In the reverse scanning, the first reference voltage signal terminal VREF1 can be configured to load a constant first reference voltage signal, and the first reference voltage signal is positive, and the first reference voltage signal is a high level signal. And, the second reference voltage signal terminal VREF2 can be configured to load a constant second reference voltage signal, and the second reference voltage signal is negative, and the second reference voltage signal is a low level signal.

[0095] For example, the third reference voltage signal terminal VREF3 can be configured to load a constant third reference voltage signal, and the third reference voltage signal is generally negative, and the third reference voltage signal is a low level signal. The fourth reference voltage signal terminal VREF4 can be configured to load a constant fourth reference voltage signal, and the fourth reference voltage signal is generally positive, and the third reference voltage signal is a high level signal.

[0096] Next, taking the shift register unit structure shown in FIG. 2 as an example, and combining the signal timing diagram shown in FIG. 4, the working process of the above-mentioned shift register unit provided by the embodiment of the present disclosure is described taking the forward scanning as an example.

[0097] As shown in FIG. 4, ipt represents the signal of the input signal terminal IPT, n1 represents the signal of the first node N1, n2 represents the signal of the second node N2, opt represents the signal of the output signal terminal OPT, rst represents the signal of the reset signal terminal RST, and trst represents the signal of the frame reset signal terminal TRST.

[0098] In the input stage F1, the signal ipt of the input signal terminal IPT is a high-level signal, the signal opt of the output signal terminal OPT is a low-level signal, the signal rst of the reset signal terminal RST is a low-level signal, and the signal trst of the frame reset signal terminal TRST is a low-level signal; the first transistor M1 and the first input transistor MR1 are turned on under the control of the high level of the signal ipt, the turned-on first input transistor MR1 provides the high-level first reference voltage signal to the first node N1, thereby charging the first node N1, and the signal n1 of the first node N1 rises from a low-level signal to a high-level signal; the turned-on first transistor M1 provides the low-level third reference voltage signal to the second node N2, and thus the signal n2 of the second node N2 is a low-level signal, thereby preventing the signal n2 of the second node N2 from being unstable and further avoiding affecting the charging of the first node N1; the second input transistor MR2 is turned off under the control of the low level of the signal rst; the second transistor M2 is turned off under the control of the low level of the signal opt; the third transistor M3 is turned off under the control of the low level of the signal n2; the fourth transistor M4 is turned on under the control of the high level of the fourth reference voltage signal, and the turned-on fourth transistor M4 provides the fourth reference voltage signal to the second node N2; the first reset transistor MF1 and the second reset transistor MF2 are turned off under the control of the low level of the signal trst; the first output transistor MC1 is turned on under the control of the high level of the signal n1, and the turned-on first output transistor MC1 provides the signal of the clock signal terminal CLK to the output signal terminal OPT; and the second output transistor MC2 is turned off under the control of the low level of the signal n2.

[0099] In the output stage F2, the signal ipt of the input signal terminal IPT is a low-level signal, the signal opt of the output signal terminal OPT is a high-level signal, the signal rst of the reset signal terminal RST is a low-level signal, and the signal trst of the frame reset signal terminal TRST is a low-level signal; the first transistor M1 and the first input transistor MR1 are turned off under the control of the low level of the signal ipt; the second transistor M2 is turned on under the control of the high level of the signal opt, and the turned-on second transistor M2 provides the third reference voltage signal to the second node N2, so that the signal n2 of the second node N2 is a low-level signal, thereby preventing the signal n2 of the second node N2 from being unstable and further avoiding affecting the charging of the first node N1 by the first capacitor C1; the second input transistor MR2 is turned off under the control of the low level of the signal rst; the third transistor M3 is turned off under the control of the low level of the signal n2; the fourth transistor M4 is turned on under the control of the high level of the fourth reference voltage signal, and the turned-on fourth transistor M4 provides the fourth reference voltage signal to the second node N2; the first reset transistor MF1 and the second reset transistor MF2 are turned off under the control of the low level of the signal trst; the first output transistor MC1 is turned on under the control of the high level of the signal n1, and the turned-on first output transistor MC1 provides the signal of the clock signal terminal CLK to the output signal terminal OPT; and the second output transistor MC2 is turned off under the control of the low level of the signal n2.

[0100] In the reset stage F3, the signal ipt of the input signal terminal IPT is a low-level signal, the signal opt of the output signal terminal OPT is a low-level signal, the signal rst of the reset signal terminal RST is a high-level signal, and the signal trst of the frame reset signal terminal TRST is a high-level signal; the first transistor M1 and the first input transistor MR1 are turned off under the control of the low level of the signal ipt; the second transistor M2 is turned off under the control of the low level of the signal opt; the second input transistor MR2 is turned on under the control of the high level of the signal rst, and the turned-on second input transistor MR2 provides the second reference voltage signal to the first node N1, so that the signal n1 of the first node N1 is a low-level signal; the third transistor M3 is turned on under the control of the high level of the signal n2, and the turned-on third transistor M3 provides the third reference voltage signal to the first node N1, so that the signal n1 of the first node N1 is a low-level signal; the fourth transistor M4 is turned on under the control of the high level of the fourth reference voltage signal, and the turned-on fourth transistor M4 provides the fourth reference voltage signal to the second node N2, so that the signal n2 of the second node N2 is a high-level signal; the first reset transistor MF1 and the second reset transistor MF2 are turned on under the control of the high level of the signal trst, the turned-on first reset transistor MF1 provides the third reference voltage signal to the first node N1, so that the signal n1 of the first node N1 is a low-level signal, and the turned-on second reset transistor MF2 provides the third reference voltage signal to the output signal terminal OPT, so that the signal opt of the output signal terminal OPT is a low-level signal; the first output transistor MC1 is turned off under the control of the low level of the signal n1; and the second output transistor MC2 is turned on under the control of the high level of the signal n2, and the turned-on second output transistor MC2 provides the third reference voltage signal to the output signal terminal OPT, so that the signal opt of the output signal terminal OPT is a low-level signal.

[0101] The embodiment of the present disclosure further provides another structural diagram of a shift register unit, as shown in FIG. 5, which is a transformation of the implementation manner in the above embodiment. The following only describes the difference between the present embodiment and the above embodiment, and the substantially same parts are not described herein.

[0102] In some other embodiments of the present disclosure, as shown in FIG. 5, the signal of the output signal terminal IPT is the same as the signal of the first reference voltage signal terminal VREF1; the gate and the first electrode of the first input transistor MR1 are both coupled with the output signal terminal IPT; the signal of the second reference voltage signal terminal VREF2 is the same as the signal of the third reference voltage signal terminal VREF3, and the second electrode of the second input transistor MR2 is coupled with the third reference voltage signal terminal VREF3. In this way, the number of signal lines can be reduced, the wiring difficulty can be reduced, and the circuit can be simplified.

[0103] It should be noted that, since the shift register unit provided in the above-mentioned other embodiments of the present disclosure is not symmetrically designed in the first input circuit and the second input circuit, the function cannot be interchanged, and therefore the shift register unit provided in the embodiments of the present disclosure cannot realize bidirectional scanning, but only forward scanning.

[0104] The signal timing diagram corresponding to the shift register unit shown in FIG. 5 can be as shown in FIG. 4. The working process of the forward scanning of this embodiment is similar to the working process of the forward scanning of the aforementioned shift register unit, and therefore the working process of the forward scanning of this embodiment can be implemented by referring to the working process of the forward scanning of the aforementioned shift register unit, and the repeated parts will not be described herein.

[0105] The embodiments of the present disclosure also provide another structure diagram of a shift register unit, as shown in FIG. 6, which is a transformation of the implementation manner in the above-mentioned embodiments. Only the differences between this embodiment and the above-mentioned embodiments will be described below, and the substantially same parts will not be described herein.

[0106] In still other embodiments of the present disclosure, as shown in FIG. 6, the first control circuit 30 is coupled with the first node N1, the second node N2 and the third node N3, and is configured to provide the signal of the fourth reference voltage signal terminal VREF4 to the second node N2 and the third node N3 in response to the signal of the fourth reference voltage signal terminal VREF4 and the third node N3, provide the signal of the third reference voltage signal terminal VREF3 to the second node N2 in response to the signal of the input signal terminal IPT and the output signal terminal OPT, and provide the signal of the third reference voltage signal terminal VREF3 to the first node N1 in response to the signal of the second node N2.

[0107] In some embodiments of the present disclosure, as shown in FIG. 6, the first control circuit 30 comprises a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8 and a ninth transistor M9; a gate of the fifth transistor M5 is coupled with the second node N2, a first electrode of the fifth transistor M5 is coupled with the first node N1, and a second electrode of the fifth transistor M5 is coupled with the third reference voltage signal terminal; a gate of the sixth transistor M6 is coupled with the third node N3, a first electrode of the sixth transistor M6 is coupled with the fourth reference voltage signal terminal VREF4, and a second electrode of the sixth transistor M6 is coupled with the second node N2; a gate of the seventh transistor M7 is coupled with the fourth reference voltage signal terminal VREF4, a first electrode of the seventh transistor M7 is coupled with the fourth reference voltage signal terminal VREF4, and a second electrode of the seventh transistor M7 is coupled with the third node N3; a gate of the eighth transistor M8 is coupled with the input signal terminal IPT, a first electrode of the eighth transistor M8 is coupled with the third node N3, and a second electrode of the eighth transistor M8 is coupled with the third reference voltage signal terminal VREF3; a gate of the ninth transistor M9 is coupled with the output signal terminal OPT, a first electrode of the ninth transistor M9 is coupled with the third node N3, and a second electrode of the ninth transistor M9 is coupled with the third reference voltage signal terminal VREF3.

[0108] Further, since the first input circuit and the second input circuit in the shift register unit provided in some embodiments of the present disclosure are symmetrically designed and can realize function interchanging, the shift register unit provided in the embodiments of the present disclosure can realize bidirectional scanning. When reverse scanning, the functions of the first input circuit and the second input circuit of the shift register unit are interchanged, i.e., with respect to forward scanning, the second input circuit serves as the first input circuit, the reset signal terminal serves as the input signal terminal, the first input circuit serves as the second input circuit, and the input signal terminal serves as the reset signal terminal.

[0109] For example, when the above transistors are all N-type transistors, in forward scanning, the first reference voltage signal terminal VREF1 can be configured to load a constant first reference voltage signal, and the first reference voltage signal is positive, i.e., the first reference voltage signal is a high-level signal. In addition, the second reference voltage signal terminal VREF2 can be configured to load a constant second reference voltage signal, and the second reference voltage signal is negative, i.e., the second reference voltage signal is a low-level signal. In reverse scanning, the first reference voltage signal terminal VREF1 can be configured to load a constant first reference voltage signal, and the first reference voltage signal is positive, i.e., the first reference voltage signal is a high-level signal. In addition, the second reference voltage signal terminal VREF2 can be configured to load a constant second reference voltage signal, and the second reference voltage signal is negative, i.e., the second reference voltage signal is a low-level signal.

[0110] For example, the third reference voltage signal terminal VREF3 can be configured to load a constant third reference voltage signal, and the third reference voltage signal is generally negative, and the third reference voltage signal is a low-level signal. The fourth reference voltage signal terminal VREF4 can be configured to load a constant fourth reference voltage signal, and the fourth reference voltage signal is generally positive, and the third reference voltage signal is a high-level signal.

[0111] Next, taking the shift register unit structure shown in FIG. 6 as an example, and combining the signal timing diagram shown in FIG. 4, the working process of the above-mentioned shift register unit provided by the embodiment of the present disclosure is described taking the forward scanning as an example.

[0112] As shown in FIG. 4, ipt represents the signal of the input signal terminal IPT, n1 represents the signal of the first node N1, n2 represents the signal of the second node N2, opt represents the signal of the output signal terminal OPT, rst represents the signal of the reset signal terminal RST, and trst represents the signal of the frame reset signal terminal TRST.

[0113] In the input stage F1, the signal ipt of the input signal terminal IPT is a high-level signal, the signal opt of the output signal terminal OPT is a low-level signal, the signal rst of the reset signal terminal RST is a low-level signal, and the signal trst of the frame reset signal terminal TRST is a low-level signal; the first transistor M1, the eighth transistor M8, and the first input transistor MR1 are turned on under the control of the high level of the signal ipt, the turned-on first input transistor MR1 provides the first reference voltage signal of the high level to the first node N1, thereby charging the first node N1, and the signal n1 of the first node N1 rises from a low-level signal to a high-level signal; the turned-on first transistor M1 provides the third reference voltage signal of the low level to the second node N2, so that the signal n2 of the second node N2 is a low-level signal, thereby preventing the signal n2 of the second node N2 from being unstable and further avoiding affecting the charging of the first node N1; the turned-on eighth transistor M8 provides the third reference voltage signal to the third node N3; the second input transistor MR2 is turned off under the control of the low level of the signal rst; the second transistor M2 and the ninth transistor M9 are turned off under the control of the low level of the signal opt; the fifth transistor M5 is turned off under the control of the low level of the signal n2; the sixth transistor M6 is turned off under the control of the low level of the signal of the third node N3; the seventh transistor M7 is turned on under the control of the high level of the fourth reference voltage signal, the turned-on seventh transistor M7 provides the fourth reference voltage signal to the third node N3; the first reset transistor MF1 and the second reset transistor MF2 are turned off under the control of the low level of the signal trst; the first output transistor MC1 is turned on under the control of the high level of the signal n1, the turned-on first output transistor MC1 provides the signal of the clock signal terminal CLK to the output signal terminal OPT; and the second output transistor MC2 is turned off under the control of the low level of the signal n2.

[0114] In the output stage F2, the signal ipt of the input signal terminal IPT is a low-level signal, the signal opt of the output signal terminal OPT is a high-level signal, the signal rst of the reset signal terminal RST is a low-level signal, and the signal trst of the frame reset signal terminal TRST is a low-level signal; the first transistor M1, the eighth transistor M8, and the first input transistor MR1 are turned off under the control of the low level of the signal ipt; the second transistor M2 and the ninth transistor M9 are turned on under the control of the high level of the signal opt, the turned-on second transistor M2 provides the third reference voltage signal to the second node N2, so that the signal n2 of the second node N2 is a low-level signal, thereby preventing the signal n2 of the second node N2 from being unstable and further avoiding affecting the charging of the first node N1 by the first capacitor C1; the turned-on ninth transistor M9 provides the third reference voltage signal to the third node N3; the sixth transistor M6 is turned off under the control of the low level of the signal of the third node N3; the seventh transistor M7 is turned on under the control of the high level of the fourth reference voltage signal, the turned-on seventh transistor M7 provides the fourth reference voltage signal to the third node N3; the first reset transistor MF1 and the second reset transistor MF2 are turned off under the control of the low level of the signal trst; the first output transistor MC1 is turned on under the control of the high level of the signal n1, the turned-on first output transistor MC1 provides the signal of the clock signal terminal CLK to the output signal terminal OPT; and the second output transistor MC2 is turned off under the control of the low level of the signal n2.

[0115] In the reset stage F3, the signal ipt of the input signal terminal IPT is a low-level signal, the signal opt of the output signal terminal OPT is a low-level signal, the signal rst of the reset signal terminal RST is a high-level signal, and the signal trst of the frame reset signal terminal TRST is a high-level signal; the first transistor M1, the eighth transistor M8, and the first input transistor MR1 are turned off under the control of the low level of the signal ipt; the second input transistor MR2 is turned on under the control of the high level of the signal rst, and the turned-on second input transistor MR2 provides the second reference voltage signal to the first node N1, so that the signal n1 of the first node N1 is a low-level signal; the second transistor M2 and the ninth transistor M9 are turned off under the control of the low level of the signal opt; the fifth transistor M5 is turned on under the control of the high level of the signal n2, and the turned-on fifth transistor M5 provides the third reference voltage signal to the first node N1, so that the signal n1 of the first node N1 is a low-level signal; the sixth transistor M6 is turned on under the control of the high level of the signal of the third node N3, and the turned-on sixth transistor M6 provides the fourth reference voltage signal to the second node N2, so that the signal n2 of the second node N2 is a high-level signal; the seventh transistor M7 is turned on under the control of the high level of the fourth reference voltage signal, and the turned-on seventh transistor M7 provides the fourth reference voltage signal to the third node N3; the first reset transistor MF1 and the second reset transistor MF2 are turned on under the control of the high level of the signal trst, the turned-on first reset transistor MF1 provides the third reference voltage signal to the first node N1, so that the signal n1 of the first node N1 is a low-level signal, and the turned-on second reset transistor MF2 provides the third reference voltage signal to the output signal terminal OPT, so that the signal opt of the output signal terminal OPT is a low-level signal; the first output transistor MC1 is turned off under the control of the low level of the signal n1; and the second output transistor MC2 is turned on under the control of the high level of the signal n2, and the turned-on second output transistor MC2 provides the third reference voltage signal to the output signal terminal OPT, so that the signal opt of the output signal terminal OPT is a low-level signal.

[0116] The embodiment of the present disclosure further provides another structure diagram of a shift register unit, as shown in Figure 7, which is a variation of the implementation in the above embodiment. The differences between the present embodiment and the above embodiment will be described below, and the same parts will not be described herein.

[0117] In some other embodiments of the present disclosure, as shown in FIG. 7, the signal of the output signal terminal IPT is the same as the signal of the first reference voltage signal terminal VREF1; the gate and the first electrode of the first input transistor MR1 are both coupled with the output signal terminal IPT; the signal of the second reference voltage signal terminal VREF2 is the same as the signal of the third reference voltage signal terminal VREF3, and the second electrode of the second input transistor MR2 is coupled with the third reference voltage signal terminal VREF3. In this way, the number of signal lines can be reduced, the wiring difficulty can be reduced, and the circuit can be simplified.

[0118] It should be noted that, in the above shift register unit provided in some other embodiments of the present disclosure, the first input circuit and the second input circuit are not symmetrically designed, and therefore the function cannot be interchanged, and therefore the above shift register unit provided in the embodiments of the present disclosure cannot realize bidirectional scanning, but only forward scanning.

[0119] The signal timing diagram corresponding to the shift register unit shown in FIG. 7 can be as shown in FIG. 4. The working process of the forward scanning of this embodiment is similar to the working process of the forward scanning of the above shift register unit, and therefore the working process of the forward scanning of this embodiment can be implemented by referring to the working process of the forward scanning of the above shift register unit, and the repeated parts will not be described herein.

[0120] The embodiments of the present disclosure also provide another structure diagram of a shift register unit, as shown in FIG. 8, which is a transformation of the implementation manner in the above embodiments. Only the differences between this embodiment and the above embodiments will be described below, and the substantially same parts will not be described herein.

[0121] In some other embodiments of the present disclosure, as shown in FIG. 8, the second node N2 includes a plurality of second sub-nodes (for example, N2-1 and N2-2 in FIG. 8); the first control circuit 30 includes a plurality of first control sub-circuits (for example, 30-1 and 30-2 in FIG. 8); and the second control circuit 40 includes a plurality of second control sub-circuits (for example, 40-1 and 40-2 in FIG. 8);

[0122] The plurality of first control sub-circuits (for example, 30-1 and 30-2 in FIG. 8) correspond to the plurality of second sub-nodes (for example, N2-1 and N2-2 in FIG. 8) one by one; and the plurality of second control sub-circuits (for example, 40-1 and 40-2 in FIG. 8) correspond to the plurality of second sub-nodes (for example, N2-1 and N2-2 in FIG. 8) one by one.

[0123] Each first control sub-circuit (for example, 30-1 and 30-2 in FIG. 8) is configured to control the signal level of the first node N1 to be opposite to that of the corresponding second sub-node (for example, N2-1 and N2-2 in FIG. 8);

[0124] Each second control sub-circuit (e.g., 40-1, 40-2 in FIG. 8) is configured to provide a signal of the third reference voltage signal terminal VREF3 to a corresponding second sub-node (e.g., N2-1, N2-2 in FIG. 8) in response to a signal of the output signal terminal OPT and a signal of the input signal terminal IPT.

[0125] In some embodiments of the present disclosure, as shown in FIG. 8, the second control sub-circuit (e.g., 40-1, 40-2 in FIG. 8) includes a tenth transistor (e.g., M10-1, M10-2 in FIG. 8) and an eleventh transistor (e.g., M11-1, M11-2 in FIG. 8); wherein a gate of the tenth transistor (e.g., M10-1, M10-2 in FIG. 8) is coupled with the output signal terminal OPT, a first pole of the tenth transistor (e.g., M10-1, M10-2 in FIG. 8) is coupled with the corresponding second sub-node (e.g., N2-1, N2-2 in FIG. 8), and a second pole of the tenth transistor (e.g., M10-1, M10-2 in FIG. 8) is coupled with the third reference voltage signal terminal VREF3; a gate of the eleventh transistor (e.g., M11-1, M11-2 in FIG. 8) is coupled with the input signal terminal IPT, a first pole of the eleventh transistor (e.g., M11-1, M11-2 in FIG. 8) is coupled with the corresponding second sub-node (e.g., N2-1, N2-2 in FIG. 8), and a second pole of the eleventh transistor (e.g., M11-1, M11-2 in FIG. 8) is coupled with the third reference voltage signal terminal VREF3.

[0126] In some embodiments of the present disclosure, as shown in FIG. 8, the first control sub-circuit (e.g., 30-1, 30-2 in FIG. 8) includes a twelfth transistor (e.g., M12-1, M12-2 in FIG. 8) and a thirteenth transistor (e.g., M13-1, M13-2 in FIG. 8); wherein a gate of the twelfth transistor (e.g., M12-1, M12-2 in FIG. 8) is coupled with the corresponding second sub-node (e.g., N2-1, N2-2 in FIG. 8), a first pole of the twelfth transistor (e.g., M12-1, M12-2 in FIG. 8) is coupled with the first node N1, and a second pole of the twelfth transistor (e.g., M12-1, M12-2 in FIG. 8) is coupled with the third reference voltage signal terminal VREF3; a gate of the thirteenth transistor (e.g., M13-1, M13-2 in FIG. 8) is coupled with the fifth reference voltage signal terminal (e.g., VREF5-1, VREF5-2 in FIG. 8), a first pole of the thirteenth transistor is coupled with the fifth reference voltage signal terminal (e.g., VREF5-1, VREF5-2 in FIG. 8), and a second pole of the thirteenth transistor is coupled with the corresponding second sub-node (e.g., N2-1, N2-2 in FIG. 8).

[0127] In some embodiments of the present disclosure, as shown in FIG. 8, the output circuit 50 comprises: a first output transistor MC1, a second output transistor (e.g. MC2-1, MC2-2 in FIG. 8), and a first capacitor C1; wherein the gate of the first output transistor MC1 is coupled with the first node N1, the first pole of the first output transistor MC1 is coupled with the clock signal terminal CLK, and the second pole of the first output transistor MC1 is coupled with the output signal terminal OPT; the gate of the second output transistor (e.g. MC2-1, MC2-2 in FIG. 8) is coupled with the corresponding second sub-node (e.g. N2-1, N2-2 in FIG. 8), the first pole of the second output transistor (e.g. MC2-1, MC2-2 in FIG. 8) is coupled with the output signal terminal OPT, and the second pole of the second output transistor (e.g. MC2-1, MC2-2 in FIG. 8) is coupled with the third reference voltage signal terminal VREF3; the first electrode of the first capacitor C1 is coupled with the first node N1, and the second electrode of the first capacitor C1 is coupled with the output signal terminal OPT.

[0128] Further, since the first input circuit and the second input circuit in the shift register unit provided in some embodiments of the present disclosure are symmetrically designed and the functions can be interchanged, the shift register unit provided in the embodiments of the present disclosure can realize bidirectional scanning. When reverse scanning, the functions of the first input circuit and the second input circuit of the shift register unit are interchanged, i.e. with respect to forward scanning, the second input circuit serves as the first input circuit, the reset signal terminal serves as the input signal terminal, the first input circuit serves as the second input circuit, and the input signal terminal serves as the reset signal terminal.

[0129] For example, when the above-mentioned transistors are all N-type transistors, in forward scanning, the first reference voltage signal terminal VREF1 can be configured to load a constant first reference voltage signal, and the first reference voltage signal is positive, i.e. the first reference voltage signal is a high-level signal. In addition, the second reference voltage signal terminal VREF2 can be configured to load a constant second reference voltage signal, and the second reference voltage signal is negative, i.e. the second reference voltage signal is a low-level signal. In reverse scanning, the first reference voltage signal terminal VREF1 can be configured to load a constant first reference voltage signal, and the first reference voltage signal is positive, i.e. the first reference voltage signal is a high-level signal. In addition, the second reference voltage signal terminal VREF2 can be configured to load a constant second reference voltage signal, and the second reference voltage signal is negative, i.e. the second reference voltage signal is a low-level signal.

[0130] For example, the third reference voltage signal end VREF3 can be configured to load a constant third reference voltage signal, and the third reference voltage signal is generally negative, and the third reference voltage signal is a low-level signal. The fifth reference voltage signal end (for example, VREF5-1, VREF5-2 in FIG. 8) can be configured to load a constant fifth reference voltage signal, and the fifth reference voltage signal is generally positive, and the fifth reference voltage signal is a high-level signal.

[0131] Next, taking the shift register unit structure shown in FIG. 8 as an example, and combining the signal timing diagram shown in FIG. 9, the working process of the above-mentioned shift register unit provided by the embodiment of the present disclosure is described taking the forward scanning as an example.

[0132] As shown in FIG. 9, ipt represents the signal of the input signal end IPT, n1 represents the signal of the first node N1, n2-1 represents the signal of the second sub-node N2-1, n2-2 represents the signal of the second sub-node N2-2, opt represents the signal of the output signal end OPT, rst represents the signal of the reset signal end RST, and trst represents the signal of the frame reset signal end TRST.

[0133] In the input stage F1, the signal ipt of the input signal terminal IPT is a high-level signal, the signal opt of the output signal terminal OPT is a low-level signal, the signal rst of the reset signal terminal RST is a low-level signal, and the signal trst of the frame reset signal terminal TRST is a low-level signal; the first input transistor MR1, the eleventh transistor M11-1 and the eleventh transistor M11-2 are turned on under the control of the high level of the signal ipt, the turned-on first input transistor MR1 provides the high-level first reference voltage signal to the first node N1, thereby charging the first node N1, and the signal n1 of the first node N1 rises from a low-level signal to a high-level signal; the turned-on eleventh transistor M11-1 provides the low-level third reference voltage signal to the second sub-node N2-1, so that the signal n2-1 of the second sub-node N2-1 is a low-level signal, thereby preventing the signal n2-1 of the second sub-node N2-1 from being unstable and further avoiding affecting the charging of the first node N1; the turned-on eleventh transistor M11-2 provides the low-level third reference voltage signal to the second sub-node N2-2, so that the signal n2-2 of the second sub-node N2-2 is a low-level signal, thereby preventing the signal n2-2 of the second sub-node N2-2 from being unstable and further avoiding affecting the charging of the first node N1; the second input transistor MR2 is turned off under the control of the low level of the signal rst; the tenth transistor M10-1 and the tenth transistor M10-2 are turned off under the control of the low level of the signal opt; the twelfth transistor M12-1 is turned off under the control of the low level of the signal n2-1; the twelfth transistor M12-2 is turned off under the control of the low level of the signal n2-2; the thirteenth transistor M13-1 is turned on under the control of the high level of the fifth reference voltage signal, and the turned-on thirteenth transistor M13-1 provides the fifth reference voltage signal to the second sub-node N2-1; the thirteenth transistor M13-2 is turned on under the control of the high level of the fifth reference voltage signal, and the turned-on thirteenth transistor M13-2 provides the fifth reference voltage signal to the second sub-node N2-2; the first reset transistor MF1 and the second reset transistor MF2 are turned off under the control of the low level of the signal trst; the first output transistor MC1 is turned on under the control of the high level of the signal n1, and the turned-on first output transistor MC1 provides the signal of the clock signal terminal CLK to the output signal terminal OPT; the second output transistor MC2-1 is turned off under the control of the low level of the signal n2-1; and the second output transistor MC2-2 is turned off under the control of the low level of the signal n2-2.

[0134] In the output stage F2, the signal ipt of the input signal terminal IPT is a low-level signal, the signal opt of the output signal terminal OPT is a high-level signal, the signal rst of the reset signal terminal RST is a low-level signal, and the signal trst of the frame reset signal terminal TRST is a low-level signal; the first input transistor MR1, the eleventh transistor M11-1, and the eleventh transistor M11-2 are turned off under the control of the low level of the signal ipt; the second input transistor MR2 is turned off under the control of the low level of the signal rst; the tenth transistor M10-1 and the tenth transistor M10-2 are turned on under the control of the high level of the signal opt, the turned-on tenth transistor M10-1 provides the low-level third reference voltage signal to the second sub-node N2-1, and thus the signal n2-1 of the second sub-node N2-1 is a low-level signal, thereby preventing the signal n2-1 of the second sub-node N2-1 from being unstable and further avoiding affecting the charging of the first node N1 by the first capacitor C1; the turned-on tenth transistor M10-2 provides the low-level third reference voltage signal to the second sub-node N2-2, and thus the signal n2-2 of the second sub-node N2-2 is a low-level signal, thereby preventing the signal n2-2 of the second sub-node N2-2 from being unstable and further avoiding affecting the charging of the first node N1 by the first capacitor C1; the twelfth transistor M12-1 is turned off under the control of the low level of the signal n2-1; the twelfth transistor M12-2 is turned off under the control of the low level of the signal n2-2; the thirteenth transistor M13-1 is turned on under the control of the high level of the fifth reference voltage signal, and the turned-on thirteenth transistor M13-1 provides the fifth reference voltage signal to the second sub-node N2-1; the thirteenth transistor M13-2 is turned on under the control of the high level of the fifth reference voltage signal, and the turned-on thirteenth transistor M13-2 provides the fifth reference voltage signal to the second sub-node N2-2; the first reset transistor MF1 and the second reset transistor MF2 are turned off under the control of the low level of the signal trst; the first output transistor MC1 is turned on under the control of the high level of the signal n1, and the turned-on first output transistor MC1 provides the signal of the clock signal terminal CLK to the output signal terminal OPT; the second output transistor MC2-1 is turned off under the control of the low level of the signal n2-1; and the second output transistor MC2-2 is turned off under the control of the low level of the signal n2-2.

[0135] In the reset stage F3, the signal ipt of the input signal terminal IPT is a low-level signal, the signal opt of the output signal terminal OPT is a low-level signal, the signal rst of the reset signal terminal RST is a high-level signal, and the signal trst of the frame reset signal terminal TRST is a high-level signal; the first input transistor MR1, the eleventh transistor M11-1, and the eleventh transistor M11-2 are turned off under the control of the low level of the signal ipt; the second input transistor MR2 is turned on under the control of the high level of the signal rst, the turned-on second input transistor MR2 provides the second reference voltage signal to the first node N1, and thus the signal n1 of the first node N1 is a low-level signal; the tenth transistor M10-1 and the tenth transistor M10-2 are turned off under the control of the low level of the signal opt; the twelfth transistor M12-1 is turned on under the control of the high level of the signal n2-1, the turned-on twelfth transistor M12-1 provides the third reference voltage signal to the first node N1, and thus the signal n1 of the first node N1 is a low-level signal; the twelfth transistor M12-2 is turned on under the control of the high level of the signal n2-2, the turned-on twelfth transistor M12-2 provides the third reference voltage signal to the first node N1, and thus the signal n1 of the first node N1 is a low-level signal; the thirteenth transistor M13-1 is turned on under the control of the high level of the fifth reference voltage signal, the turned-on thirteenth transistor M13-1 provides the fifth reference voltage signal to the second sub-node N2-1, and thus the signal n2-1 of the second sub-node N2-1 is a high-level signal; the thirteenth transistor M13-2 is turned on under the control of the high level of the fifth reference voltage signal, the turned-on thirteenth transistor M13-2 provides the fifth reference voltage signal to the second sub-node N2-2, and thus the signal n2-2 of the second sub-node N2-2 is a high-level signal; the first reset transistor MF1 and the second reset transistor MF2 are turned on under the control of the high level of the signal trst, the turned-on first reset transistor MF1 provides the third reference voltage signal to the first node N1, and thus the signal n1 of the first node N1 is a low-level signal, and the turned-on second reset transistor MF2 provides the third reference voltage signal to the output signal terminal OPT, and thus the signal opt of the output signal terminal OPT is a low-level signal; the first output transistor MC1 is turned off under the control of the low level of the signal n1; the second output transistor MC2-1 is turned on under the control of the high level of the signal n2-1, the turned-on second output transistor MC2-1 provides the third reference voltage signal to the output signal terminal OPT, and thus the signal opt of the output signal terminal OPT is a low-level signal; and the second output transistor MC2-2 is turned on under the control of the high level of the signal n2-2, the turned-on second output transistor MC2-2 provides the third reference voltage signal to the output signal terminal OPT, and thus the signal opt of the output signal terminal OPT is a low-level signal.

[0136] The embodiment of the present disclosure further provides another structural diagram of the shift register unit, as shown in Fig. 10, which is deformed for the implementation in the above embodiment. The following only describes the difference between the present embodiment and the above embodiment, and the same parts are not described here.

[0137] In some other embodiments of the present disclosure, as shown in Fig. 10, the signal of the output signal terminal IPT is the same as that of the first reference voltage signal terminal VREF1; the gate and the first electrode of the first input transistor MR1 are both coupled with the output signal terminal IPT; the signal of the second reference voltage signal terminal VREF2 is the same as that of the third reference voltage signal terminal VREF3, and the second electrode of the second input transistor MR2 is coupled with the third reference voltage signal terminal VREF3. In this way, the number of signal lines can be reduced, the wiring difficulty can be reduced, and the circuit can be simplified.

[0138] It should be noted that, since the first input circuit and the second input circuit are not symmetrically designed in the above shift register unit provided by some other embodiments of the present disclosure, the function cannot be interchanged, and therefore the above shift register unit provided by the embodiment of the present disclosure cannot realize bidirectional scanning, but only forward scanning.

[0139] The signal timing diagram corresponding to the shift register unit shown in Fig. 10 can be as shown in Fig. 9. The working process of the forward scanning of the present embodiment is similar to that of the forward scanning of the above shift register unit, and therefore the working process of the forward scanning of the present embodiment can refer to the working process of the forward scanning of the above shift register unit, and the repeated parts are not described here.

[0140] The embodiment of the present disclosure further provides another structural diagram of the shift register unit, as shown in Fig. 11, which is deformed for the implementation in the above embodiment. The following only describes the difference between the present embodiment and the above embodiment, and the same parts are not described here.

[0141] In yet some embodiments of the present disclosure, as shown in FIG. 11, the first control sub-circuit (e.g. 30-1, 30-2 in FIG. 11) coupled with the first node N1, the corresponding second sub-node (e.g. N2-1, N2-2 in FIG. 11) and the third node (e.g. N3-1, N3-2 in FIG. 11) is configured to provide the signal of the third reference voltage signal terminal VREF3 to the third node (e.g. N3-1, N3-2 in FIG. 11) in response to the signal of the output signal terminal OPT and the signal of the input signal terminal IPT, provide the signal of the fifth reference voltage signal terminal (e.g. VREF5-1, VREF5-2 in FIG. 11) to the third node (e.g. N3-1, N3-2 in FIG. 11) and the corresponding second sub-node (e.g. N2-1, N2-2 in FIG. 11) in response to the signal of the fifth reference voltage signal terminal (e.g. VREF5-1, VREF5-2 in FIG. 11) and the signal of the third node (e.g. N3-1, N3-2 in FIG. 11), and provide the signal of the third reference voltage signal terminal VREF3 to the first node N1 in response to the signal of the corresponding second sub-node (e.g. N2-1, N2-2 in FIG. 11).

[0142] In some embodiments of the present disclosure, as shown in FIG. 11, the first control sub-circuit (e.g., 30-1, 30-2 in FIG. 11) comprises: a fourteenth transistor (e.g., M14-1, M14-2 in FIG. 11), a fifteenth transistor (e.g., M15-1, M15-2 in FIG. 11), a sixteenth transistor (e.g., M16-1, M16-2 in FIG. 11), a seventeenth transistor (e.g., M17-1, M17-2 in FIG. 11), and an eighteenth transistor (e.g., M18-1, M18-2 in FIG. 11); a gate of the fourteenth transistor (e.g., M14-1, M14-2 in FIG. 11) is coupled to a corresponding second sub-node (e.g., N2-1, N2-2 in FIG. 11), a first electrode of the fourteenth transistor (e.g., M14-1, M14-2 in FIG. 11) is coupled to the first node N1, and a second electrode of the fourteenth transistor (e.g., M14-1, M14-2 in FIG. 11) is coupled to the third reference voltage signal terminal VREF3; a gate of the fifteenth transistor (e.g., M15-1, M15-2 in FIG. 11) is coupled to the third node (e.g., N3-1, N3-2 in FIG. 11), a first electrode of the fifteenth transistor (e.g., M15-1, M15-2 in FIG. 11) is coupled to the fifth reference voltage signal terminal (e.g., VREF5-1, VREF5-2 in FIG. 11), and a second electrode of the fifteenth transistor (e.g., M15-1, M15-2 in FIG. 11) is coupled to the corresponding second sub-node (e.g., N2-1, N2-2 in FIG. 11); a gate of the sixteenth transistor (e.g., M16-1, M16-2 in FIG. 11) is coupled to the fifth reference voltage signal terminal (e.g., VREF5-1, VREF5-2 in FIG. 11), a first electrode of the sixteenth transistor (e.g., M16-1, M16-2 in FIG. 11) is coupled to the fifth reference voltage signal terminal (e.g., VREF5-1, VREF5-2 in FIG. 11), and a second electrode of the sixteenth transistor (e.g., M16-1, M16-2 in FIG. 11) is coupled to the third node (e.g., N3-1, N3-2 in FIG. 11); a gate of the seventeenth transistor (e.g., M17-1, M17-2 in FIG. 11) is coupled to the output signal terminal OPT, a first electrode of the seventeenth transistor (e.g., M17-1, M17-2 in FIG. 11) is coupled to the third node (e.g., N3-1, N3-2 in FIG. 11), and a second electrode of the seventeenth transistor (e.g., M17-1, M17-2 in FIG. 11) is coupled to the third reference voltage signal terminal VREF3; a gate of the eighteenth transistor (e.g., M18-1, M18-2 in FIG. 11) is coupled to the input signal terminal IPT, a first electrode of the eighteenth transistor (e.g., M18-1, M18-2 in FIG. 11) is coupled to the third node (e.g., N3-1, N3-2 in FIG. 11), and a second electrode of the eighteenth transistor (e.g., M18-1, M18-2 in FIG. 11) is coupled to the third reference voltage signal terminal VREF3.

[0143] Further, since the first input circuit and the second input circuit are symmetrically designed in the shift register unit provided in some embodiments of the present disclosure, the function can be interchanged, and thus the shift register unit provided in the embodiments of the present disclosure can realize bidirectional scanning. When reverse scanning, the functions of the first input circuit and the second input circuit of the shift register unit are interchanged, that is, with respect to forward scanning, the second input circuit serves as the first input circuit, the reset signal end serves as the input signal end, the first input circuit serves as the second input circuit, and the input signal end serves as the reset signal end.

[0144] For example, when forward scanning, the first reference voltage signal end VREF1 can be configured to load a constant first reference voltage signal, and the first reference voltage signal is positive, and the first reference voltage signal is a high-level signal. In addition, the second reference voltage signal end VREF2 can be configured to load a constant second reference voltage signal, and the second reference voltage signal is negative, and the second reference voltage signal is a low-level signal. When reverse scanning, the first reference voltage signal end VREF1 can be configured to load a constant first reference voltage signal, and the first reference voltage signal is positive, and the first reference voltage signal is a high-level signal. In addition, the second reference voltage signal end VREF2 can be configured to load a constant second reference voltage signal, and the second reference voltage signal is negative, and the second reference voltage signal is a low-level signal.

[0145] For example, the third reference voltage signal end VREF3 can be configured to load a constant third reference voltage signal, and the third reference voltage signal is generally negative, and the third reference voltage signal is a low-level signal. The fifth reference voltage signal end (for example, VREF5-1 and VREF5-2 in FIG. 11) can be configured to load a constant fifth reference voltage signal, and the fifth reference voltage signal is generally positive, and the fifth reference voltage signal is a high-level signal.

[0146] Next, taking the shift register unit structure shown in FIG. 11 as an example, and combining the signal timing diagram shown in FIG. 9, the working process of the shift register unit provided in the embodiments of the present disclosure is described taking forward scanning as an example.

[0147] As shown in FIG. 9, ipt represents the signal of the input signal end IPT, n1 represents the signal of the first node N1, n2-1 represents the signal of the second sub-node N2-1, n2-2 represents the signal of the second sub-node N2-2, opt represents the signal of the output signal end OPT, rst represents the signal of the reset signal end RST, and trst represents the signal of the frame reset signal end TRST.

[0148] In the input stage F1, the signal ipt of the input signal terminal IPT is a high-level signal, the signal opt of the output signal terminal OPT is a low-level signal, the signal rst of the reset signal terminal RST is a low-level signal, and the signal trst of the frame reset signal terminal TRST is a low-level signal; the first input transistor MR1, the eleventh transistor M11-1, the eleventh transistor M11-2, the eighteenth transistor M18-1 and the eighteenth transistor M18-2 are turned on under the control of the high level of the signal ipt, the turned-on first input transistor MR1 provides the high-level first reference voltage signal to the first node N1, thereby charging the first node N1, and the signal n1 of the first node N1 rises from a low-level signal to a high-level signal; the turned-on eleventh transistor M11-1 provides the low-level third reference voltage signal to the second sub-node N2-1, so that the signal n2-1 of the second sub-node N2-1 is a low-level signal, thereby preventing the signal n2-1 of the second sub-node N2-1 from being unstable and further avoiding affecting the charging of the first node N1; the turned-on eleventh transistor M11-2 provides the low-level third reference voltage signal to the second sub-node N2-2, so that the signal n2-2 of the second sub-node N2-2 is a low-level signal, thereby preventing the signal n2-2 of the second sub-node N2-2 from being unstable and further avoiding affecting the charging of the first node N1; the turned-on eighteenth transistor M18-1 provides the low-level third reference voltage signal to the third node N3-1; the turned-on eighteenth transistor M18-2 provides the low-level third reference voltage signal to the third node N3-2; the second input transistor MR2 is turned off under the control of the low level of the signal rst; the tenth transistor M10-1, the tenth transistor M10-2, the seventeenth transistor M17-1 and the seventeenth transistor M17-2 are turned off under the control of the low level of the signal opt; the fourteenth transistor M14-1 is turned off under the control of the low level of the signal n2-1; the fourteenth transistor M14-2 is turned off under the control of the low level of the signal n2-2; the fifteenth transistor M15-1 is turned off under the control of the low level of the signal of the third node N3-1; the fifteenth transistor M15-2 is turned off under the control of the low level of the signal of the third node N3-2; the sixteenth transistor M16-1 is turned on under the control of the high level of the fifth reference voltage signal, the turned-on sixteenth transistor M16-1 provides the fifth reference voltage signal to the third node N3-1; the sixteenth transistor M16-2 is turned on under the control of the high level of the fifth reference voltage signal, the turned-on sixteenth transistor M16-2 provides the fifth reference voltage signal to the third node N3-2; the first reset transistor MF1 and the second reset transistor MF2 are turned off under the control of the low level of the signal trst; the first output transistor MC1 is turned on under the control of the high level of the signal n1, the turned-on first output transistor MC1 provides the signal of the clock signal terminal CLK to the output signal terminal OPT;The second output transistor MC2-1 is turned off under the control of the low level of the signal n2-1; the second output transistor MC2-2 is turned off under the control of the low level of the signal n2-2.

[0149] In the output stage F2, the signal ipt of the input signal terminal IPT is a low-level signal, the signal opt of the output signal terminal OPT is a high-level signal, the signal rst of the reset signal terminal RST is a low-level signal, and the signal trst of the frame reset signal terminal TRST is a low-level signal; the first input transistor MR1, the eleventh transistor M11-1, the eleventh transistor M11-2, the eighteenth transistor M18-1, and the eighteenth transistor M18-2 are cut off under the control of the low level of the signal ipt; the second input transistor MR2 is cut off under the control of the low level of the signal rst; the tenth transistor M10-1, the tenth transistor M10-2, the seventeenth transistor M17-1, and the seventeenth transistor M17-2 are turned on under the control of the high level of the signal opt, the turned-on tenth transistor M10-1 provides the low-level third reference voltage signal to the second sub-node N2-1, so that the signal n2-1 of the second sub-node N2-1 is a low-level signal, thereby preventing the signal n2-1 of the second sub-node N2-1 from being unstable, and further avoiding affecting the charging of the first capacitor C1 to the first node N1; the turned-on tenth transistor M10-2 provides the low-level third reference voltage signal to the second sub-node N2-2, so that the signal n2-2 of the second sub-node N2-2 is a low-level signal, thereby preventing the signal n2-2 of the second sub-node N2-2 from being unstable, and further avoiding affecting the charging of the first capacitor C1 to the first node N1; the turned-on seventeenth transistor M17-1 provides the low-level third reference voltage signal to the third node N3-1; the turned-on seventeenth transistor M17-2 provides the low-level third reference voltage signal to the third node N3-2; the fourteenth transistor M14-1 is cut off under the control of the low level of the signal n2-1; the fourteenth transistor M14-2 is cut off under the control of the low level of the signal n2-2; the fifteenth transistor M15-1 is cut off under the control of the low level of the signal of the third node N3-1; the fifteenth transistor M15-2 is cut off under the control of the low level of the signal of the third node N3-2; the sixteenth transistor M16-1 is turned on under the control of the high level of the fifth reference voltage signal, the turned-on sixteenth transistor M16-1 provides the fifth reference voltage signal to the third node N3-1; the sixteenth transistor M16-2 is turned on under the control of the high level of the fifth reference voltage signal, the turned-on sixteenth transistor M16-2 provides the fifth reference voltage signal to the third node N3-2; the first reset transistor MF1 and the second reset transistor MF2 are cut off under the control of the low level of the signal trst; the first output transistor MC1 is turned on under the control of the high level of the signal n1, the turned-on first output transistor MC1 provides the signal of the clock signal terminal CLK to the output signal terminal OPT; the second output transistor MC2-1 is cut off under the control of the low level of the signal n2-1; the second output transistor MC2-2 is cut off under the control of the low level of the signal n2-2.

[0150] In the output stage F2, the signal ipt of the input signal terminal IPT is a low-level signal, the signal opt of the output signal terminal OPT is a high-level signal, the signal rst of the reset signal terminal RST is a low-level signal, and the signal trst of the frame reset signal terminal TRST is a low-level signal; the first input transistor MR1, the eleventh transistor M11-1, the eleventh transistor M11-2, the eighteenth transistor M18-1 and the eighteenth transistor M18-2 are cut off under the control of the low level of the signal ipt; the second input transistor MR2 is turned on under the control of the high level of the signal rst, the turned-on second input transistor MR2 provides the second reference voltage signal to the first node N1, and thus the signal n1 of the first node N1 is a low-level signal; the tenth transistor M10-1, the tenth transistor M10-2, the seventeenth transistor M17-1 and the seventeenth transistor M17-2 are cut off under the control of the low level of the signal opt; the fourteenth transistor M14-1 is turned on under the control of the high level of the signal n2-1, the turned-on fourteenth transistor M14-1 provides the third reference voltage signal to the first node N1, and thus the signal n1 of the first node N1 is a low-level signal; the fourteenth transistor M14-2 is turned on under the control of the high level of the signal n2-2, the turned-on fourteenth transistor M14-2 provides the third reference voltage signal to the first node N1, and thus the signal n1 of the first node N1 is a low-level signal; the fifteenth transistor M15-1 is turned on under the control of the high level of the third node N3-1 signal, the turned-on fifteenth transistor M15-1 provides the fifth reference voltage signal to the second sub-node N2-1, and thus the signal n2-2 of the second sub-node N2-2 is a high-level signal; the fifteenth transistor M15-2 is turned on under the control of the high level of the third node N3-2 signal, the turned-on fifteenth transistor M15-2 provides the fifth reference voltage signal to the second sub-node N2-2, and thus the signal n2-2 of the second sub-node N2-2 is a high-level signal; the sixteenth transistor M16-1 is turned on under the control of the high level of the fifth reference voltage signal, the turned-on sixteenth transistor M16-1 provides the fifth reference voltage signal to the third node N3-1; the sixteenth transistor M16-2 is turned on under the control of the high level of the fifth reference voltage signal, the turned-on sixteenth transistor M16-2 provides the fifth reference voltage signal to the third node N3-2; the first reset transistor MF1 and the second reset transistor MF2 are turned on under the control of the high level of the signal trst, the turned-on first reset transistor MF1 provides the third reference voltage signal to the first node N1, and thus the signal n1 of the first node N1 is a low-level signal, the turned-on second reset transistor MF2 provides the third reference voltage signal to the output signal terminal OPT, and thus the signal opt of the output signal terminal OPT is a low-level signal; the first output transistor MC1 is cut off under the control of the low level of the signal n1.The second output transistor MC2-1 is turned on under the control of the high level of the signal n2-1, the turned-on second output transistor MC2-1 provides the third reference voltage signal to the output signal terminal OPT, and the signal opt of the output signal terminal OPT is a low level signal; the second output transistor MC2-2 is turned on under the control of the high level of the signal n2-2, the turned-on second output transistor MC2-2 provides the third reference voltage signal to the output signal terminal OPT, and the signal opt of the output signal terminal OPT is a low level signal.

[0151] The embodiment of the present disclosure further provides another structure diagram of the shift register unit, as shown in FIG. 12, which is a transformation of the implementation in the above embodiment. The following only describes the difference between the present embodiment and the above embodiment, and the same parts are not described here.

[0152] In some other embodiments of the present disclosure, as shown in FIG. 12, the signal of the output signal terminal IPT is the same as the signal of the first reference voltage signal terminal VREF1; the gate and the first electrode of the first input transistor MR1 are both coupled with the output signal terminal IPT; the signal of the second reference voltage signal terminal VREF2 is the same as the signal of the third reference voltage signal terminal VREF3, and the second electrode of the second input transistor MR2 is coupled with the third reference voltage signal terminal VREF3. In this way, the number of signal lines can be reduced, the wiring difficulty can be reduced, and the circuit can be simplified.

[0153] It should be noted that, since the first input circuit and the second input circuit are not symmetrically designed in the above shift register unit provided by some other embodiments of the present disclosure, the function cannot be interchanged, and therefore the above shift register unit provided by the embodiment of the present disclosure cannot realize bidirectional scanning, but can only realize forward scanning.

[0154] The signal timing diagram corresponding to the shift register unit shown in FIG. 12 can be as shown in FIG. 9. The working process of the forward scanning of the present embodiment is similar to the working process of the forward scanning of the above shift register unit, and therefore the working process of the forward scanning of the present embodiment can be referred to the working process of the forward scanning of the above shift register unit, and the repeated parts are not described here.

[0155] The gate drive circuit provided by the embodiments of the present disclosure includes the shift register unit described above, as shown in FIG. 13, the input signal end IPT of the first stage shift register unit SR1 is connected to the frame start signal end STV, and the input signal end IPT of each stage shift register unit is connected to the output signal end OPT of the previous stage shift register unit, except for the first stage shift register unit SR1 (for example, SR2, SR3, SR4, …, SRn-3, SRn-2, SRn-1, SRn); and the reset signal end RST of each stage shift register unit is connected to the output signal end OPT of the adjacent next stage shift register unit, except for the last stage shift register unit SRn (for example, SR1, SR2, SR3, SR4, …, SRn-3, SRn-2, SRn-1).

[0156] The embodiments of the present disclosure also provide another structure diagram of the shift register unit, as shown in FIG. 14, which is a variation of the implementation in the above-described embodiments. The differences between the present embodiment and the above-described embodiments are described below, and the same parts are not described herein.

[0157] In some other embodiments of the present disclosure, as shown in FIG. 14, the cascade circuit 70 is further coupled to the first node N1 and the second node N2 (including the second sub-nodes N2-1 and N2-2), and is configured to provide the signal of the clock signal end CLK to the cascade signal end OT in response to the signal of the first node N1, and provide the signal of the third reference voltage signal end VREF3 to the cascade signal end OT in response to the signal of the second node N2 (including the second sub-nodes N2-1 and N2-2).

[0158] In some other embodiments of the present disclosure, as shown in FIG. 14, the cascade circuit 70 includes a first cascade transistor MJ1, a second cascade transistor MJ2, and a third cascade transistor MJ3; the gate of the first cascade transistor MJ1 is coupled to the first node N1, the first pole of the first cascade transistor MJ1 is coupled to the clock signal end CLK, and the second pole of the first cascade transistor MJ1 is coupled to the cascade signal end OT; the gate of the second cascade transistor MJ2 is coupled to the second node N2 (the second sub-node N2-1), the first pole of the second cascade transistor MJ2 is coupled to the cascade signal end OT, and the second pole of the second cascade transistor MJ2 is coupled to the third reference voltage signal end VREF3; the gate of the third cascade transistor MJ3 is coupled to the second node N2 (the second sub-node N2-2), the first pole of the third cascade transistor MJ3 is coupled to the cascade signal end OT, and the second pole of the third cascade transistor MJ3 is coupled to the third reference voltage signal end VREF3.

[0159] Further, since the first input circuit and the second input circuit are symmetrically designed in the shift register unit provided in the further embodiments of the present disclosure, the function of the first input circuit and the second input circuit can be interchanged, and thus the shift register unit provided in the embodiments of the present disclosure can realize bidirectional scanning. When reverse scanning, the functions of the first input circuit and the second input circuit of the shift register unit are interchanged, that is, with respect to forward scanning, the second input circuit serves as the first input circuit, the reset signal terminal serves as the input signal terminal, the first input circuit serves as the second input circuit, and the input signal terminal serves as the reset signal terminal.

[0160] For example, when forward scanning, the first reference voltage signal terminal VREF1 can be configured to load a constant first reference voltage signal, and the first reference voltage signal is positive, and the first reference voltage signal is a high-level signal. In addition, the second reference voltage signal terminal VREF2 can be configured to load a constant second reference voltage signal, and the second reference voltage signal is negative, and the second reference voltage signal is a low-level signal. When reverse scanning, the first reference voltage signal terminal VREF1 can be configured to load a constant first reference voltage signal, and the first reference voltage signal is positive, and the first reference voltage signal is a high-level signal. In addition, the second reference voltage signal terminal VREF2 can be configured to load a constant second reference voltage signal, and the second reference voltage signal is negative, and the second reference voltage signal is a low-level signal.

[0161] For example, the third reference voltage signal terminal VREF3 can be configured to load a constant third reference voltage signal, and the third reference voltage signal is generally negative, and the third reference voltage signal is a low-level signal. The fifth reference voltage signal terminal (for example, VREF5-1 and VREF5-2 in FIG. 14) can be configured to load a constant fifth reference voltage signal, and the fifth reference voltage signal is generally positive, and the fifth reference voltage signal is a high-level signal.

[0162] Next, taking the shift register unit structure shown in FIG. 14 as an example, and combining the signal timing diagram shown in FIG. 9, the working process of the shift register unit provided in the embodiments of the present disclosure is described taking forward scanning as an example.

[0163] For example, as shown in FIG. 9, ipt represents the signal of the input signal terminal IPT, n1 represents the signal of the first node N1, n2-1 represents the signal of the second sub-node N2-1, n2-2 represents the signal of the second sub-node N2-2, opt represents the signal of the output signal terminal OPT, rst represents the signal of the reset signal terminal RST, and trst represents the signal of the frame reset signal terminal TRST.

[0164] In the input stage F1, the signal ipt of the input signal terminal IPT is a high-level signal, the signal opt of the output signal terminal OPT is a low-level signal, the signal rst of the reset signal terminal RST is a low-level signal, and the signal trst of the frame reset signal terminal TRST is a low-level signal; the first input transistor MR1, the eleventh transistor M11-1, the eleventh transistor M11-2, the eighteenth transistor M18-1 and the eighteenth transistor M18-2 are turned on under the control of the high level of the signal ipt, the turned-on first input transistor MR1 provides the high-level first reference voltage signal to the first node N1, thereby charging the first node N1, and the signal n1 of the first node N1 rises from a low-level signal to a high-level signal; the turned-on eleventh transistor M11-1 provides the low-level third reference voltage signal to the second sub-node N2-1, so that the signal n2-1 of the second sub-node N2-1 is a low-level signal, thereby preventing the signal n2-1 of the second sub-node N2-1 from being unstable and further avoiding affecting the charging of the first node N1; the turned-on eleventh transistor M11-2 provides the low-level third reference voltage signal to the second sub-node N2-2, so that the signal n2-2 of the second sub-node N2-2 is a low-level signal, thereby preventing the signal n2-2 of the second sub-node N2-2 from being unstable and further avoiding affecting the charging of the first node N1; the turned-on eighteenth transistor M18-1 provides the low-level third reference voltage signal to the third node N3-1; the turned-on eighteenth transistor M18-2 provides the low-level third reference voltage signal to the third node N3-2; the second input transistor MR2 is turned off under the control of the low level of the signal rst; the tenth transistor M10-1, the tenth transistor M10-2, the seventeenth transistor M17-1 and the seventeenth transistor M17-2 are turned off under the control of the low level of the signal opt; the fourteenth transistor M14-1 is turned off under the control of the low level of the signal n2-1; the fourteenth transistor M14-2 is turned off under the control of the low level of the signal n2-2; the fifteenth transistor M15-1 is turned off under the control of the low level of the signal of the third node N3-1; the fifteenth transistor M15-2 is turned off under the control of the low level of the signal of the third node N3-2; the sixteenth transistor M16-1 is turned on under the control of the high level of the fifth reference voltage signal, the turned-on sixteenth transistor M16-1 provides the fifth reference voltage signal to the third node N3-1; the sixteenth transistor M16-2 is turned on under the control of the high level of the fifth reference voltage signal, the turned-on sixteenth transistor M16-2 provides the fifth reference voltage signal to the third node N3-2; the first reset transistor MF1 and the second reset transistor MF2 are turned off under the control of the low level of the signal trst; the first output transistor MC1 is turned on under the control of the high level of the signal n1, the turned-on first output transistor MC1 provides the signal of the clock signal terminal CLK to the output signal terminal OPT;The second output transistor MC2-1 is turned off under the control of the low level of the signal n2-1; the second output transistor MC2-2 is turned off under the control of the low level of the signal n2-2; the first cascade transistor MJ1 is turned on under the control of the high level of the signal nl, and the turned-on first cascade transistor MJ1 provides the signal of the clock signal end CLK to the cascade signal end OT; the second cascade transistor MJ2 is turned off under the control of the low level of the signal n2-1; and the third cascade transistor MJ3 is turned off under the control of the low level of the signal n2-2.

[0165] In the output stage F2, the signal ipt of the input signal terminal IPT is a low-level signal, the signal opt of the output signal terminal OPT is a high-level signal, the signal rst of the reset signal terminal RST is a low-level signal, and the signal trst of the frame reset signal terminal TRST is a low-level signal; the first input transistor MR1, the eleventh transistor M11-1, the eleventh transistor M11-2, the eighteenth transistor M18-1 and the eighteenth transistor M18-2 are cut off under the control of the low level of the signal ipt; the second input transistor MR2 is cut off under the control of the low level of the signal rst; the tenth transistor M10-1, the tenth transistor M10-2, the seventeenth transistor M17-1 and the seventeenth transistor M17-2 are turned on under the control of the high level of the signal opt, the turned-on tenth transistor M10-1 provides the low-level third reference voltage signal to the second sub-node N2-1, so that the signal n2-1 of the second sub-node N2-1 is a low-level signal, thereby preventing the signal n2-1 of the second sub-node N2-1 from being unstable and further avoiding affecting the charging of the first capacitor C1 to the first node N1; the turned-on tenth transistor M10-2 provides the low-level third reference voltage signal to the second sub-node N2-2, so that the signal n2-2 of the second sub-node N2-2 is a low-level signal, thereby preventing the signal n2-2 of the second sub-node N2-2 from being unstable and further avoiding affecting the charging of the first capacitor C1 to the first node N1; the turned-on seventeenth transistor M17-1 provides the low-level third reference voltage signal to the third node N3-1; the turned-on seventeenth transistor M17-2 provides the low-level third reference voltage signal to the third node N3-2; the fourteenth transistor M14-1 is cut off under the control of the low level of the signal n2-1; the fourteenth transistor M14-2 is cut off under the control of the low level of the signal n2-2; the fifteenth transistor M15-1 is cut off under the control of the low level of the signal of the third node N3-1; the fifteenth transistor M15-2 is cut off under the control of the low level of the signal of the third node N3-2; the sixteenth transistor M16-1 is turned on under the control of the high level of the fifth reference voltage signal, the turned-on sixteenth transistor M16-1 provides the fifth reference voltage signal to the third node N3-1; the sixteenth transistor M16-2 is turned on under the control of the high level of the fifth reference voltage signal, the turned-on sixteenth transistor M16-2 provides the fifth reference voltage signal to the third node N3-2; the first reset transistor MF1 and the second reset transistor MF2 are cut off under the control of the low level of the signal trst; the first output transistor MC1 is turned on under the control of the high level of the signal n1, the turned-on first output transistor MC1 provides the signal of the clock signal terminal CLK to the output signal terminal OPT; the second output transistor MC2-1 is cut off under the control of the low level of the signal n2-1; the second output transistor MC2-2 is cut off under the control of the low level of the signal n2-2.The first cascode transistor MJ1 is turned on under the control of the high level of the signal nl, and the turned-on first cascode transistor MJ1 provides the signal of the clock signal end CLK to the cascode signal end OT; the second cascode transistor MJ2 is turned off under the control of the low level of the signal n2-1; and the third cascode transistor MJ3 is turned off under the control of the low level of the signal n2-2.

[0166] In the output stage F2, the signal ipt of the input signal terminal IPT is a low-level signal, the signal opt of the output signal terminal OPT is a high-level signal, the signal rst of the reset signal terminal RST is a low-level signal, and the signal trst of the frame reset signal terminal TRST is a low-level signal; the first input transistor MR1, the eleventh transistor M11-1, the eleventh transistor M11-2, the eighteenth transistor M18-1 and the eighteenth transistor M18-2 are cut off under the control of the low level of the signal ipt; the second input transistor MR2 is turned on under the control of the high level of the signal rst, the turned-on second input transistor MR2 provides the second reference voltage signal to the first node N1, and thus the signal n1 of the first node N1 is a low-level signal; the tenth transistor M10-1, the tenth transistor M10-2, the seventeenth transistor M17-1 and the seventeenth transistor M17-2 are cut off under the control of the low level of the signal opt; the fourteenth transistor M14-1 is turned on under the control of the high level of the signal n2-1, the turned-on fourteenth transistor M14-1 provides the third reference voltage signal to the first node N1, and thus the signal n1 of the first node N1 is a low-level signal; the fourteenth transistor M14-2 is turned on under the control of the high level of the signal n2-2, the turned-on fourteenth transistor M14-2 provides the third reference voltage signal to the first node N1, and thus the signal n1 of the first node N1 is a low-level signal; the fifteenth transistor M15-1 is turned on under the control of the high level of the third node N3-1 signal, the turned-on fifteenth transistor M15-1 provides the fifth reference voltage signal to the second sub-node N2-1, and thus the signal n2-2 of the second sub-node N2-2 is a high-level signal; the fifteenth transistor M15-2 is turned on under the control of the high level of the third node N3-2 signal, the turned-on fifteenth transistor M15-2 provides the fifth reference voltage signal to the second sub-node N2-2, and thus the signal n2-2 of the second sub-node N2-2 is a high-level signal; the sixteenth transistor M16-1 is turned on under the control of the high level of the fifth reference voltage signal, the turned-on sixteenth transistor M16-1 provides the fifth reference voltage signal to the third node N3-1; the sixteenth transistor M16-2 is turned on under the control of the high level of the fifth reference voltage signal, the turned-on sixteenth transistor M16-2 provides the fifth reference voltage signal to the third node N3-2; the first reset transistor MF1 and the second reset transistor MF2 are turned on under the control of the high level of the signal trst, the turned-on first reset transistor MF1 provides the third reference voltage signal to the first node N1, and thus the signal n1 of the first node N1 is a low-level signal, the turned-on second reset transistor MF2 provides the third reference voltage signal to the output signal terminal OPT, and thus the signal opt of the output signal terminal OPT is a low-level signal; the first output transistor MC1 is cut off under the control of the low level of the signal n1.The second output transistor MC2-1 is turned on under the control of the high level of the signal n2-1, the turned-on second output transistor MC2-1 provides the third reference voltage signal to the output signal terminal OPT, and the signal opt of the output signal terminal OPT is a low level signal; the second output transistor MC2-2 is turned on under the control of the high level of the signal n2-2, the turned-on second output transistor MC2-2 provides the third reference voltage signal to the output signal terminal OPT, and the signal opt of the output signal terminal OPT is a low level signal; the first cascade transistor MJ1 is turned off under the control of the low level of the signal n1; the second cascade transistor MJ2 is turned on under the control of the high level of the signal n2-1, the turned-on second cascade transistor MJ2 provides the third reference voltage signal to the cascade signal terminal OT; and the third cascade transistor MJ3 is turned on under the control of the high level of the signal n2-2, the turned-on third cascade transistor MJ3 provides the third reference voltage signal to the cascade signal terminal OT.

[0167] The embodiment of the present disclosure further provides another structure diagram of the shift register unit, as shown in FIG. 15, which is a transformation of the implementation in the above embodiment. The following only describes the difference between the present embodiment and the above embodiment, and the same parts are not described here.

[0168] In still another embodiment of the present disclosure, as shown in FIG. 15, the signal of the output signal terminal IPT is the same as the signal of the first reference voltage signal terminal VREF1; the gate and the first pole of the first input transistor MR1 are both coupled with the output signal terminal IPT; the signal of the second reference voltage signal terminal VREF2 is the same as the signal of the third reference voltage signal terminal VREF3, and the second pole of the second input transistor MR2 is coupled with the third reference voltage signal terminal VREF3. In this way, the number of signal lines can be reduced, the wiring difficulty can be reduced, and the circuit can be simplified.

[0169] It should be noted that, since the first input circuit and the second input circuit are not symmetrically designed in the above shift register unit provided in still another embodiment of the present disclosure, the function cannot be interchanged, and therefore the above shift register unit provided in the embodiment of the present disclosure cannot realize bidirectional scanning, but can only realize forward scanning.

[0170] The signal timing diagram corresponding to the shift register unit shown in FIG. 15 can be as shown in FIG. 9. The working process of the forward scanning of the present embodiment is similar to the working process of the forward scanning of the above shift register unit, and therefore the working process of the forward scanning of the present embodiment can be referred to the working process of the forward scanning of the above shift register unit, and the repeated parts are not described here.

[0171] The gate drive circuit provided by the embodiments of the present disclosure includes the shift register unit as described above, as shown in FIG. 16, and includes cascaded shift register units. The input signal terminal IPT of the first stage shift register unit SR1 is connected to the frame start signal terminal STV. The input signal terminal IPT of each shift register unit, except the first stage shift register unit SR1 (for example, SR2, SR3, SR4, …, SRn-3, SRn-2, SRn-1, SRn), is connected to the cascade signal terminal OT of the previous stage shift register unit. The reset signal terminal RST of each shift register unit, except the last stage shift register unit SRn (for example, SR1, SR2, SR3, SR4, …, SRn-3, SRn-2, SRn-1), is connected to the cascade signal terminal OT of the next stage shift register unit adjacent thereto. The output signal terminal OPT of each shift register unit is connected to the corresponding gate line (for example, GA1, GA2, GA3, GA4, …, GAn-3, GAn-2, GAn-1, GAn).

[0172] Based on the same disclosure concept, the embodiments of the present disclosure further provide a display device including the above-described gate drive circuit. The principle of solving problems of the display device is similar to that of the above-described gate drive circuit, and therefore the implementation of the display device can be referred to the implementation of the above-described gate drive circuit, and the repeated parts will not be described here.

[0173] In specific implementation, the display device can include a plurality of pixel units arranged in an array, and each pixel unit includes a plurality of sub-pixels. For example, each pixel unit includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that color display can be realized by mixing red, green, and blue. Alternatively, each pixel unit can include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that color display can be realized by mixing red, green, blue, and white. Of course, the light-emitting colors of the sub-pixels in the pixel unit can be designed according to the actual application environment, which is not limited herein.

[0174] In specific implementation, in the embodiments of the present disclosure, the display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like. Other essential components of the display device should be understood by those skilled in the art, which will not be described here, and should not be regarded as a limitation on the present disclosure.

[0175] Although the preferred embodiments of the present disclosure have been described, those skilled in the art can make additional changes and modifications to the embodiments once they understand the basic inventive concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0176] It will be apparent to those skilled in the art that various modifications and variations can be made to the present embodiments without departing from the spirit or scope of the present embodiments. Thus, it is intended that the present embodiments cover the modifications and variations of this application provided they come within the scope of the appended claims and their equivalents.

Claims

1. A shift register unit, wherein, The first input circuit is coupled to the first node and is configured to provide a signal of the first reference voltage signal terminal to the first node in response to a signal of the input signal terminal. The second input circuit is coupled to the first node and is configured to provide a signal of the second reference voltage signal terminal to the first node in response to a signal of the reset signal terminal. The first control circuit is coupled to the first node and the second node and is configured to control the signal levels of the first node and the second node to be opposite. The second control circuit is coupled to the second node and is configured to provide a signal of the third reference voltage signal terminal to the second node in response to signals of the input signal terminal and the output signal terminal. The output circuit is coupled to the first node and the second node and is configured to provide a signal of the clock signal terminal to the output signal terminal in response to a signal of the first node, and provide a signal of the third reference voltage signal terminal to the output signal terminal in response to a signal of the second node. The second control circuit includes a first transistor and a second transistor.

2. The shift register cell of claim 1, wherein, The gate of the first transistor is coupled to the input signal terminal, the first electrode of the first transistor is coupled to the second node, and the second electrode of the first transistor is coupled to the third reference voltage signal terminal. The gate of the second transistor is coupled to the output signal terminal, the first electrode of the second transistor is coupled to the second node, and the second electrode of the second transistor is coupled to the third reference voltage signal terminal. The first control circuit includes a third transistor and a fourth transistor.

3. The shift register cell of claim 2, wherein, The gate of the third transistor is coupled to the second node, the first electrode of the third transistor is coupled to the first node, and the second electrode of the third transistor is coupled to the third reference voltage signal terminal. The gate of the fourth transistor is coupled to the fourth reference voltage signal terminal, the first electrode of the fourth transistor is coupled to the fourth reference voltage signal terminal, and the second electrode of the fourth transistor is coupled to the second node. The first control circuit is coupled to the first node, the second node, and the third node and is configured to provide a signal of the fourth reference voltage signal terminal to the second node and the third node in response to signals of the fourth reference voltage signal terminal and the third node, provide a signal of the third reference voltage signal terminal to the second node in response to signals of the input signal terminal and the output signal terminal, and provide a signal of the third reference voltage signal terminal to the first node in response to a signal of the second node.

4. The shift register cell of claim 2, wherein, The first control circuit includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor.

5. The shift register cell of claim 4, wherein, The gate of the fifth transistor is coupled to the second node, the first electrode of the fifth transistor is coupled to the first node, and the second electrode of the fifth transistor is coupled to the third reference voltage signal terminal. The gate of the sixth transistor is coupled to the third node, the first electrode of the sixth transistor is coupled to the fourth reference voltage signal terminal, and the second electrode of the sixth transistor is coupled to the second node. The gate of the seventh transistor is coupled to the fourth reference voltage signal terminal, the first electrode of the seventh transistor is coupled to the fourth reference voltage signal terminal, and the second electrode of the seventh transistor is coupled to the third node. The gate of the eighth transistor is coupled to the second node, the first electrode of the eighth transistor is coupled to the third node, and the second electrode of the eighth transistor is coupled to the fourth reference voltage signal terminal. The gate of the ninth transistor is coupled to the first node, the first electrode of the ninth transistor is coupled to the third node, and the second electrode of the ninth transistor is coupled to the fourth reference voltage signal terminal. A gate of the seventh transistor is coupled with the fourth reference voltage signal terminal, a first pole of the seventh transistor is coupled with the fourth reference voltage signal terminal, and a second pole of the seventh transistor is coupled with the third node; A gate of the eighth transistor is coupled with the input signal terminal, a first pole of the eighth transistor is coupled with the third node, and a second pole of the eighth transistor is coupled with the third reference voltage signal terminal; A gate of the ninth transistor is coupled with the output signal terminal, a first pole of the ninth transistor is coupled with the third node, and a second pole of the ninth transistor is coupled with the third reference voltage signal terminal.

6. The shift register cell of claim 1, wherein, The second node comprises a plurality of second sub-nodes; The first control circuit comprises a plurality of first control sub-circuits, and the second control circuit comprises a plurality of second control sub-circuits; The plurality of first control sub-circuits correspond to the plurality of second sub-nodes one by one, and the plurality of second control sub-circuits correspond to the plurality of second sub-nodes one by one; Each first control sub-circuit is configured to control the signal level of the first node to be opposite to that of the corresponding second sub-node; Each second control sub-circuit is configured to provide the signal of the third reference voltage signal terminal to the corresponding second sub-node in response to the signals of the output signal terminal and the input signal terminal.

7. The shift register cell of claim 6, wherein, The second control sub-circuit comprises a tenth transistor and an eleventh transistor; A gate of the tenth transistor is coupled with the output signal terminal, a first pole of the tenth transistor is coupled with the corresponding second sub-node, and a second pole of the tenth transistor is coupled with the third reference voltage signal terminal; A gate of the eleventh transistor is coupled with the input signal terminal, a first pole of the eleventh transistor is coupled with the corresponding second sub-node, and a second pole of the eleventh transistor is coupled with the third reference voltage signal terminal.

8. The shift register cell of claim 6, wherein, The first control sub-circuit comprises a twelfth transistor and a thirteenth transistor; A gate of the twelfth transistor is coupled with the corresponding second sub-node, a first pole of the twelfth transistor is coupled with the first node, and a second pole of the twelfth transistor is coupled with the third reference voltage signal terminal; A gate of the thirteenth transistor is coupled with a fifth reference voltage signal terminal, a first pole of the thirteenth transistor is coupled with the fifth reference voltage signal terminal, and a second pole of the thirteenth transistor is coupled with the corresponding second sub-node.

9. The shift register cell of claim 7, wherein, The first control sub-circuit, coupled with the first node, the corresponding second sub-node, and a third node, is configured to provide the signal of the third reference voltage signal terminal to the third node in response to the signals of the output signal terminal and the input signal terminal, provide the signal of the fifth reference voltage signal terminal to the third node and the corresponding second sub-node in response to the signals of the fifth reference voltage signal terminal and the third node, and provide the signal of the third reference voltage signal terminal to the first node in response to the signal of the corresponding second sub-node.

10. The shift register cell of claim 9, wherein, The first control sub-circuit comprises a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor and an eighteenth transistor; a gate of the fourteenth transistor is coupled with the corresponding second sub-node, a first pole of the fourteenth transistor is coupled with the first node, and a second pole of the fourteenth transistor is coupled with the third reference voltage signal terminal; a gate of the fifteenth transistor is coupled with the third node, a first pole of the fifteenth transistor is coupled with the fifth reference voltage signal terminal, and a second pole of the fifteenth transistor is coupled with the corresponding second sub-node; a gate of the sixteenth transistor is coupled with the fifth reference voltage signal terminal, a first pole of the sixteenth transistor is coupled with the fifth reference voltage signal terminal, and a second pole of the sixteenth transistor is coupled with the third node; a gate of the seventeenth transistor is coupled with the output signal terminal, a first pole of the seventeenth transistor is coupled with the third node, and a second pole of the seventeenth transistor is coupled with the third reference voltage signal terminal; a gate of the eighteenth transistor is coupled with the input signal terminal, a first pole of the eighteenth transistor is coupled with the third node, and a second pole of the eighteenth transistor is coupled with the third reference voltage signal terminal.

11. The shift register cell of any of claims 1-10, wherein, The signal of the output signal terminal is the same as the signal of the first reference voltage signal terminal; The signal of the second reference voltage signal terminal is the same as the signal of the third reference voltage signal terminal.

12. The shift register cell of any of claims 1-11, wherein, A cascade circuit is further included, which is coupled with the first node and the second node, and is configured to provide the signal of the clock signal terminal to a cascade signal terminal in response to the signal of the first node, and provide the signal of the third reference voltage signal terminal to the cascade signal terminal in response to the signal of the second node.

13. The shift register cell of claim 12, wherein, The cascade circuit comprises a first cascade transistor, a second cascade transistor and a third cascade transistor; a gate of the first cascade transistor is coupled with the first node, a first pole of the first cascade transistor is coupled with the clock signal terminal, and a second pole of the first cascade transistor is coupled with the cascade signal terminal; a gate of the second cascade transistor is coupled with the second node, a first pole of the second cascade transistor is coupled with the cascade signal terminal, and a second pole of the second cascade transistor is coupled with the third reference voltage signal terminal; a gate of the third cascade transistor is coupled with the second node, a first pole of the third cascade transistor is coupled with the cascade signal terminal, and a second pole of the third cascade transistor is coupled with the third reference voltage signal terminal.

14. A gate drive circuit, wherein, The shift register unit as claimed in any one of claims 1-11 is cascaded, an input signal terminal of a first stage shift register unit is connected to a frame start signal terminal, an input signal terminal of each stage shift register unit except the first stage shift register unit is connected to an output signal terminal of a previous stage shift register unit, and a reset signal terminal of each stage shift register unit except the last stage shift register unit is connected to an output signal terminal of a next stage shift register unit adjacent thereto.

15. A gate drive circuit, wherein, The shift register unit as claimed in claim 12 or 13 is connected in cascade, an input signal terminal of a first stage shift register unit is connected to a frame start signal terminal, an input signal terminal of each stage shift register unit is connected to a cascade signal terminal of a previous stage shift register unit except the first stage shift register unit; a reset signal terminal of each stage shift register unit is connected to a cascade signal terminal of a next stage shift register unit except the last stage shift register unit, and an output signal terminal of each stage shift register unit is connected to a corresponding gate line.

16. A display device comprising: The gate driving circuit as claimed in claim 14 or 15.

17. A driving method of the shift register unit as claimed in any one of claims 1-13, comprising: in an input stage, the first input circuit provides a signal of the first reference voltage signal terminal to the first node in response to a signal of the input signal terminal; the second control circuit provides a signal of the third reference voltage signal terminal to the second node in response to the input signal terminal; in an output stage, the second control circuit provides a signal of the third reference voltage signal terminal to the second node in response to a signal of the output signal terminal; the output circuit provides a signal of the clock signal terminal to the output signal terminal in response to a signal of the first node; in a reset stage, the second input circuit provides a signal of the second reference voltage signal terminal to the first node in response to a signal of the reset signal terminal; the first control circuit controls the signal of the first node to be opposite to that of the second node; the output circuit provides a signal of the third reference voltage signal terminal to the output signal terminal in response to a signal of the second node.

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