Communication method and apparatus

Abstract

A communication method and apparatus, used for reducing the blind detection complexity of a PDCCH. According to the method, an encoded bit sequence is generated on the basis of a pre-frozen bit set when the aggregation level (AL) of a PDCCH is high (for example, the AL is equal to 8 / 16), so that the encoding structure (i.e., an information bit / frozen bit) of some of bits in the encoded bit sequence is the same as the encoding structure of an encoded bit sequence when the AL of the PDCCH is low (for example, the Al is equal to 4), and thus even if the AL of the PDCCH is high, a receiving end can decode a small number of CCEs to acquire data, and does not need to continue to decode other CCEs, thereby stopping blind detection as early as possible, and reducing the receiver complexity.

Description

A communication method and apparatus

[0001] Cross-reference to Related Applications

[0002] This application claims priority to the Chinese Patent Application No. 202410411808.2, filed on April 7, 2024, entitled “A communication method and apparatus”, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] Embodiments of the present application relate to the field of communication technology, and in particular to a communication method and apparatus. BACKGROUND

[0004] A physical downlink control channel (PDCCH) is used to carry downlink control information (DCI). The scheduling unit of the PDCCH is a control channel element (CCE). A CCE can carry a coded bit sequence of 108 bits. Currently, the PDCCH can support aggregation levels of 1 / 2 / 4 / 8 / 16, i.e., the PDCCH can include 1 / 2 / 4 / 8 / 16 CCEs.

[0005] Currently, the terminal device needs to decode all the PDCCH before stopping decoding, even if the terminal device has obtained the data sent by the network device through the PDCCH when decoding part of the code blocks of the PDCCH. For example, the network device sends a PDCCH with an aggregation level of 8 to the terminal device. When the terminal device decodes the first 4 CCEs and obtains the data sent by the network device through the PDCCH, it still cannot stop decoding. SUMMARY

[0006] The present application provides a communication method and apparatus to reduce the blind decoding complexity of the PDCCH.

[0007] In a first aspect, a communication method is provided, which can be executed by a sending end. The sending end can be a network device, or a chip / chip system applied to the network device. Taking the network device as an example, in the method, the network device determines a pre-frozen bit set corresponding to a first coded bit sequence according to a first bit sequence length, the first coded bit sequence is carried in a PDCCH, and the length of the first coded bit sequence is greater than the maximum mother code length of the PDCCH n maxis a positive integer. The network device generates a first coded bit sequence according to the pre-frozen bit set and transmits the first coded bit sequence.

[0008] The pre-frozen bit set is determined for a PDCCH with a high aggregation level, so that part of bits carried by the PDCCH with the high aggregation level are constructed in the same way as bits carried by a PDCCH with a low aggregation level, so that even if the aggregation level of the PDCCH is high, the receiver can decode a small number of CCEs to obtain data, without continuing to decode other CCEs, thereby achieving early stopping of blind detection and reducing receiver complexity.

[0009] In a possible design, the pre-frozen bit set corresponding to the first coded bit sequence is the same as the pre-frozen bit set corresponding to the second coded bit sequence, and the length of the second coded bit sequence is less than the maximum mother code length of the PDCCH

[0010] Since the second coded bit sequence with the length less than the maximum mother code length of the PDCCH is also generated according to the pre-frozen bit set, the coding construction of part of bits in the first coded bit sequence can be made the same as the coding construction of the second coded bit sequence in the foregoing manner.

[0011] In a possible design, the first bit sequence length is determined based on the length of the first coded bit sequence; or the first bit sequence length is 432; or the first bit sequence length is the length of the second coded bit sequence, and the length of the second coded bit sequence is less than the maximum mother code length of the PDCCH

[0012] In the foregoing design, the coded bit sequence with the rate matching manner being repetition can be generated based on the pre-frozen bit set.

[0013] In a possible design, the first bit sequence length satisfies the following formula:

[0014] wherein E is the length of the first coded bit sequence, and N is the maximum mother code length of the PDCCH

[0015] In a possible design, part of bits in the first coded bit sequence are mapped to the same control channel element (CCE) as the CCE to which the second coded bit sequence is mapped, the information bits corresponding to the part of bits are the same as the information bits corresponding to the second coded bit sequence, and the length of the second coded bit sequence is less than the maximum mother code length of the PDCCH ​Through the above design, the receiving end can decode a small amount of CCE to obtain data, without continuing to decode other CCEs, thereby realizing early stopping of blind detection and reducing complexity of the receiver.

[0016] In a possible design, the starting point of bit selection corresponding to the first encoded bit sequence is related to at least one of the following parameters: the aggregation level of the first encoded bit sequence, the code rate of the first encoded bit sequence, and the rate matching manner of the first encoded bit sequence.

[0017] In a possible design, the starting point of bit selection corresponding to the first encoded bit sequence is the same as the starting point of bit selection corresponding to the second encoded bit sequence. Through the above design, the receiving end can decode a small amount of CCE using the decoding manner corresponding to the second encoded bit sequence, thereby realizing early stopping of blind detection after obtaining data.

[0018] In a possible design, the first encoded bit sequence satisfies the following formula:

[0019] where e k is a bit numbered k in the first encoded bit sequence, is a first bit length, E is a length of the first encoded bit sequence, and N is a maximum mother code length of a PDCCH y n is a bit numbered n in the third encoded bit sequence, and the third encoded bit sequence is a bit sequence obtained by encoding and interleaving information bits.

[0020] Through the above design, part of bits carried by a PDCCH with a higher AL is the same as bits carried by a PDCCH with a lower AL, and the mapped CCEs are also the same, so that if the communication environment of the terminal device is good, data can be obtained by decoding the part of CCEs, without decoding all CCEs of the PDCCH with the higher AL.

[0021] In a possible design, the first encoded bit sequence satisfies the following formula:

[0022] where e k is a bit numbered k in the first encoded bit sequence is a first bit length, and N is a maximum mother code length of a PDCCH d n is a bit numbered n in the fourth encoded bit sequence, and the fourth encoded bit sequence is a bit sequence obtained by encoding information bits.

[0023] The above design makes the part of bits carried by the PDCCH with a higher AL same as the bits carried by the PDCCH with a lower AL, and the mapped CCEs also same, so that if the communication environment of the terminal device is good, the data can be obtained by decoding the part of CCEs, without decoding all the CCEs of the PDCCH with a higher AL.

[0024] Also, the scheme can omit the sub-block interleaver before bit selection, so that the complexity of PDCCH blind detection can be further reduced.

[0025] In a possible design, the first coded bit sequence is obtained by interleaving a fifth coded bit sequence, and the fifth coded bit sequence is obtained by encoding and bit selection on information bits. The above design can make the receiving end decode a small amount of CCEs by using the decoding mode corresponding to the second coded bit sequence, so that early stopping of blind detection can be implemented after the data is obtained.

[0026] In a possible design, the first M bits in the first coded bit sequence are same as the last M bits in the fifth coded bit sequence, where M is the length of the second coded bit sequence, and the length of the second coded bit sequence is smaller than the maximum mother code length of the PDCCH.

[0027] The above design makes the part of bits carried by the PDCCH with a higher AL same as the bits carried by the PDCCH with a lower AL, and the mapped CCEs also same, so that if the communication environment of the terminal device is good, the data can be obtained by decoding the part of CCEs, without decoding all the CCEs of the PDCCH with a higher AL.

[0028] In a possible design, the first coded bit sequence can be obtained by cyclically shifting the fifth coded bit sequence according to the starting point of the second coded bit sequence. In this way, the first M bits in the first coded bit sequence are same as the second coded bit sequence.

[0029] In a possible design, the rate matching manner of the first coded bit sequence is repetition.

[0030] In a possible design, the first coded bit sequence is generated according to a pre-frozen bit set, including: determining information bits according to the pre-frozen bit set; encoding the information bits after mapping; performing bit selection on the coded bit sequence; and generating the first coded bit sequence according to the bit sequence obtained after the bit selection.

[0031] In a possible design, n max = 9.

[0032] In one possible design, the aggregation level of the second coded bit sequence is 4.

[0033] In a second aspect, a communication method is provided, which can be performed by a receiving end. The receiving end can be a terminal device, or a chip / chip system applied to the terminal device. Taking the terminal device as an example, in this method, the terminal device receives a first symbol sequence, the first symbol sequence is carried on the PDCCH, and the length of the first symbol sequence is greater than the maximum mother code length of the PDCCH. n max is a positive integer; the terminal device determines a pre-frozen bit set corresponding to the first symbol sequence according to the length of the first bit sequence, and decodes the first symbol sequence according to the pre-frozen bit set.

[0034] The present application determines a pre-frozen bit set for a PDCCH with a high aggregation level, so that the coding construction method of some bits carried by the PDCCH with a high aggregation level is the same as that of bits carried by the PDCCH with a low aggregation level. Therefore, even if the aggregation level of the PDCCH is high, the receiving end can decode a small number of CCEs to obtain data without continuing to decode other CCEs, thereby realizing blind detection early stopping and reducing the complexity of the receiver.

[0035] In one possible design, the pre-frozen bit set corresponding to the first symbol sequence is determined in the same manner as the pre-frozen bit set corresponding to the second symbol sequence, and the length of the second symbol sequence is less than the maximum mother code length of the PDCCH.

[0036] Since the length is less than the maximum mother code length of PDCCH The second coded bit sequence is also generated based on the pre-frozen bit set, so the coding structure of some bits in the first coded bit sequence can be made the same as the coding structure of the second coded bit sequence through the above method.

[0037] In one possible design, the length of the first bit sequence is determined based on the length of the first symbol sequence; or, the length of the first bit sequence is 432; or, the length of the first bit sequence is the length of the second symbol sequence, and the length of the second symbol sequence is less than the maximum mother code length of the PDCCH.

[0038] Through the above design, a coded bit sequence with a repetitive rate matching mode can be generated based on the pre-frozen bit set.

[0039] In one possible design, the first bit sequence length is Satisfies the following formula:

[0040] Wherein, E is the length of the first symbol sequence, N is the maximum mother code length of the PDCCH

[0041] In a possible design, the CCEs to which part of the bits in the first symbol sequence are mapped are the same as the CCEs to which the second symbol sequence is mapped, the information bits corresponding to the part of the bits are the same as the information bits corresponding to the second symbol sequence, and the length of the second symbol sequence is less than the maximum mother code length of the PDCCH Through the above design, the receiving end can decode a small number of CCEs to obtain data, without continuing to decode other CCEs, thereby achieving early stopping of blind detection and reducing the complexity of the receiver.

[0042] In a possible design, the starting point of selection of the bits corresponding to the first symbol sequence is related to at least one of the following parameters: the aggregation level of the first symbol sequence, the code rate of the first symbol sequence, and the rate matching manner of the first symbol sequence.

[0043] In a possible design, the starting point of selection of the bits corresponding to the first symbol sequence is the same as the starting point of selection of the bits corresponding to the second symbol sequence. Through the above design, the receiving end can decode a small number of CCEs by using the decoding manner corresponding to the second encoded bit sequence, thereby achieving early stopping of blind detection after obtaining data.

[0044] In a possible design, the encoded bit sequence corresponding to the first symbol sequence satisfies the following formula:

[0045] Wherein, e k is the k th bit in the encoded bit sequence corresponding to the first symbol sequence, is the length of the first bit, E is the length of the first symbol sequence, and N is the maximum mother code length of the PDCCH y n is the n th bit in the third encoded bit sequence, and the third encoded bit sequence is obtained by encoding and interleaving information bits.

[0046] Through the above design, part of the bits carried by a PDCCH with a higher AL are the same as the bits carried by a PDCCH with a lower AL, and the mapped CCEs are also the same, so that, in the case that the communication environment of the terminal device is good, data can be obtained by decoding the part of CCEs, without decoding all the CCEs of the PDCCH with the higher AL.

[0047] In a possible design, the encoded bit sequence corresponding to the first symbol sequence satisfies the following formula:

[0048] Wherein, e ka bit numbered k in the coded bit sequence corresponding to the first symbol sequence, N is the maximum mother code length of the PDCCH d n a bit numbered n in the fourth coded bit sequence, the fourth coded bit sequence being a bit sequence obtained after encoding the information bits.

[0049] Through the above design, the part of bits carried by the PDCCH with a higher AL is the same as the bits carried by the PDCCH with a lower AL, and the mapped CCEs are also the same, so that if the communication environment of the terminal device is good, the data can be obtained by decoding the part of CCEs, without decoding all the CCEs of the PDCCH with a higher AL.

[0050] Moreover, the scheme can omit the sub-block interleaver before the bit selection, so that the complexity of PDCCH blind detection can be further reduced.

[0051] In a possible design, the coded bit sequence corresponding to the first symbol sequence is obtained by interleaving a fifth coded bit sequence, and the fifth coded bit sequence is obtained after encoding and bit selection of the information bits. Through the above design, the receiving end can decode a small amount of CCEs by using a second decoding manner corresponding to the second coded bit sequence, so that early stopping of blind detection can be realized after the data is obtained.

[0052] In a possible design, the first M bits in the coded bit sequence corresponding to the first symbol sequence are the same as the last M bits in a fifth coded bit sequence, where M is the length of a second symbol sequence, and the length of the second symbol sequence is less than the maximum mother code length of the PDCCH

[0053] Through the above design, the part of bits carried by the PDCCH with a higher AL is the same as the bits carried by the PDCCH with a lower AL, and the mapped CCEs are also the same, so that if the communication environment of the terminal device is good, the data can be obtained by decoding the part of CCEs, without decoding all the CCEs of the PDCCH with a higher AL.

[0054] In a possible design, the coded bit sequence corresponding to the first symbol sequence can be obtained by cyclically shifting the fifth coded bit sequence according to the starting point of the second coded bit sequence. Through this way, the first M bits in the first symbol sequence are the same as the second symbol sequence.

[0055] In a possible design, the rate matching manner of the first symbol sequence is repetition.

[0056] In a possible design, the decoding the first symbol sequence according to the pre-frozen bit set comprises: determining information bits according to the pre-frozen bit set; recovering the first symbol sequence according to a bit selection method corresponding to the first symbol sequence to obtain a third symbol sequence; and decoding the third symbol sequence according to the information bits; and obtaining the information bits from the decoded bit sequence.

[0057] In a possible design, n max = 9.

[0058] In a possible design, the aggregation level of the second symbol sequence is 4.

[0059] In a third aspect, the present application provides a communication apparatus, which is a network device or a chip in a network device. The communication apparatus has the function of implementing any of the methods provided in the first aspect. The communication apparatus can be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more units or modules corresponding to the above functions.

[0060] In a possible design, the communication apparatus includes a processor configured to support the communication apparatus to perform the corresponding functions of the network device in the above methods. The communication apparatus can further include a memory coupled to the processor, which stores program instructions and data necessary for the communication apparatus. Optionally, the communication apparatus further includes an interface circuit configured to support the communication apparatus to communicate with devices such as terminal devices, for example, to transmit or receive data or signals. Exemplarily, the communication interface can be a transceiver, a circuit, a bus, a module or other types of communication interfaces.

[0061] In a possible design, the communication apparatus includes corresponding functional modules for implementing the steps in the above methods. The functions can be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions.

[0062] In a possible design, the structure of the communication apparatus includes a processing unit (or a processing module) and a communication unit (or a communication module), which can perform the corresponding functions in the above method examples, and details are described in the methods provided in the first aspect, which will not be repeated here.

[0063] In a fourth aspect, the present application provides a communication apparatus, which is a terminal device or a chip in a terminal device. The communication apparatus has the function of implementing any of the methods provided in the second aspect. The communication apparatus can be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more units or modules corresponding to the above functions.

[0064] In a possible design, the communication apparatus includes a processor configured to support the communication apparatus to perform the corresponding functions of the terminal device in the above-described method. The communication apparatus can further include a memory coupled to the processor, which stores program instructions and data necessary for the communication apparatus. Optionally, the communication apparatus further includes an interface circuit configured to support the communication apparatus to perform communication, such as data or signal transmission and reception, with another device, such as a network device. For example, the communication interface can be a transceiver, a circuit, a bus, a module, or another type of communication interface.

[0065] In a possible design, the communication apparatus includes corresponding functional modules for implementing the steps in the above-described method. The functions can be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-described functions.

[0066] In a possible design, the structure of the communication apparatus includes a processing unit (or a processing module) and a communication unit (or a communication module), which can perform the corresponding functions in the above-described method, details of which can be referred to the description of the method in the second aspect, which will not be repeated here.

[0067] In the fifth aspect, a communication apparatus is provided, which includes a processor and an interface circuit configured to receive a signal from another communication apparatus outside the communication apparatus and transmit the signal to the processor or send a signal from the processor to another communication apparatus outside the communication apparatus. The processor is configured to implement the method in the first aspect and any possible design by means of a logic circuit or by executing code instructions.

[0068] In the sixth aspect, a communication apparatus is provided, which includes a processor and an interface circuit configured to receive a signal from another communication apparatus outside the communication apparatus and transmit the signal to the processor or send a signal from the processor to another communication apparatus outside the communication apparatus. The processor is configured to implement the method in the second aspect and any possible design by means of a logic circuit or by executing code instructions.

[0069] In the seventh aspect, a computer readable storage medium is provided, which stores a computer program or instructions, and when the computer program or instructions are executed by a processor, the method in the first aspect or the second aspect and any possible design is implemented.

[0070] In the eighth aspect, a computer program product is provided, which stores instructions, and when the instructions are executed by a processor, the method in the first aspect or the second aspect and any possible design is implemented.

[0071] In a ninth aspect, a chip system is provided, which includes a processor and can further include a memory for implementing the method in the first aspect or the second aspect and any possible design. The chip system can be composed of a chip or can include a chip and other discrete devices.

[0072] In a tenth aspect, a communication system is provided, which includes the apparatus (e.g., a network device) in the first aspect and the apparatus (e.g., a terminal device) in the second aspect.

[0073] The technical effects that can be achieved by the technical solutions in any of the third aspect to the tenth aspect can be described with reference to the technical effects that can be achieved by the technical solutions in the first aspect, and the repeated parts will not be described herein. BRIEF DESCRIPTION OF DRAWINGS

[0074] FIG. 1 is a schematic diagram of an architecture of a communication system according to an embodiment of the present application;

[0075] FIG. 2 is a schematic diagram of a polar encoding according to an embodiment of the present application;

[0076] FIG. 3 is a schematic diagram of a communication method according to an embodiment of the present application;

[0077] FIG. 4 is a schematic diagram of an encoding process according to an embodiment of the present application;

[0078] FIG. 5 is a schematic diagram of bit selection according to an embodiment of the present application;

[0079] FIG. 6 is a schematic diagram of sub-block interleaving according to an embodiment of the present application;

[0080] FIG. 7 is a schematic diagram of sub-block interleaving according to an embodiment of the present application;

[0081] FIG. 8 is a schematic diagram of a structure of a communication apparatus according to an embodiment of the present application;

[0082] FIG. 9 is a schematic diagram of a structure of a communication apparatus according to an embodiment of the present application. DETAILED DESCRIPTION

[0083] The embodiments of the present application can be applied to various fields using polar coding, such as data storage field, optical network communication field, and wireless communication field, and the like. The foregoing wireless communication field can include, but is not limited to, 5G communication system, future communication system (such as 6G communication system), satellite communication system, device-to-device (D2D) communication system, machine to machine (M2M) communication system, internet of things (IoT), unmanned aerial vehicle communication system, narrow band-internet of things (NB-IoT) system, long term evolution (LTE) system, and three application scenarios of 5G mobile communication system, eMBB, ultra reliable low latency communication (URLLC), and massive machine-type communications (mMTC).

[0084] The communication system to which the data transmission method provided by the embodiments of the present application is applied will be introduced below in combination with FIG. 1. Referring to FIG. 1, the communication system 100 includes a sending end 101 and a receiving end 102. The sending end 101 can be a network device or a terminal device, and the receiving end 102 can be a network device or a terminal device. Optionally, when the sending end 101 is a network device, the receiving end 102 can be a terminal device; when the receiving end 102 is a network device, the sending end 101 can be a terminal device.

[0085] The sending end 101 can include an encoder, and the sending end 101 can perform polar coding on the to-be-coded bits through the encoder and output the coded codewords. The coded codewords can be transmitted to the receiving end 102 through rate matching, interleaving, and modulation on the channel. The receiving end 102 can include a decoder, and the receiving end 102 can receive and demodulate the signal from the sending end 101, and the receiving end 102 can perform decoding on the received signal through the decoder.

[0086] The terminal device to which the present application relates includes a device that provides voice and / or data connectivity to a user, and specifically includes a device that provides voice connectivity to a user, or a device that provides data connectivity to a user, or a device that provides both voice and data connectivity to a user. For example, the terminal device can include a handheld device having wireless connection capability, or a processing device connected to a wireless modem. The terminal device can include a user equipment (UE), a wireless terminal device, a mobile terminal device, a device-to-device (D2D) terminal device, a vehicle to everything (V2X) terminal device, a machine-to-machine / Machine-Type Communications (M2M / MTC) terminal device, an Internet of Things (IoT) terminal device, a subscriber unit, a subscriber station, a mobile station, a remote station, an access point (AP), a remote terminal, an access terminal, a user terminal, a user agent, or a user device, a satellite, a drone, a balloon, an airplane, etc. For example, the terminal device can include a mobile telephone (also known as a "cellular" telephone), a computer with mobile termination, a portable, pocket, hand-held, computer-included mobile device, etc. For example, the terminal device can include a personal communication service (PCS) telephone, a cordless telephone, a session initiation protocol (SIP) telephone, a wireless local loop (WLL) station, a personal digital assistant (PDA), etc. The terminal device can also include a restricted device, such as a device with lower power consumption, or a device with limited storage capacity, or a device with limited computing capability, etc. For example, the terminal device can include a bar code, a radio frequency identification (RFID), a sensor, a global positioning system (GPS), a laser scanner, etc. As an example and not a limitation, the terminal device can also be a wearable device in embodiments of the present application.The wearable device can also be referred to as a smart wearable device or a smart wearable device, etc., which is a general term for devices that can be worn by applying wearable technology to smart design and development of daily wear. The various terminal devices introduced above can be considered as vehicle-mounted terminal devices if they are located on a vehicle (e.g., placed inside or installed inside a vehicle), and the vehicle-mounted terminal device is also referred to as an on-board unit (OBU), for example.

[0087] The network device involved in the present application, for example, includes an access network (AN) device, such as a base station (e.g., an access point), which can refer to a device in an access network that communicates with a wireless terminal device through one or more cells over the air interface, or for example, a network device in a vehicle-to-everything (V2X) technology is a road side unit (RSU). The network device can include an evolved base station (NodeB or eNB or e-NodeB, evolutional Node B) in a long term evolution (LTE) system or long term evolution-advanced (LTE-A), or can also include a next generation node B (gNB) in an evolved packet core (EPC), a 5th generation (5G), a new radio (NR) system (also referred to as an NR system), or can also include a centralized unit (CU) and a distributed unit (DU) in a cloud radio access network (Cloud RAN) system, satellites, drones, balloons, and aircraft, etc., and the embodiments of the present application are not limited.

[0088] At present, since the polar coding can be strictly proved to reach the channel capacity of the channel coding scheme, it has high performance, low complexity, flexible matching mode, etc. At present, it has been determined by the third generation partnership project (3 rd generation partnership project, 3GPP) to be the control channel coding scheme for the 5G control channel enhanced mobile broadband (eMBB) scenario.

[0089] Referring to FIG. 2, a polar encoding schematic diagram is shown. In FIG. 2, the corresponding encoding code length is 8, and each circle in each row represents a summation between the row where the circle is located and the row where the circle reaches, and the bit on the right side of the circle is the summation result. For example, the first circle in the row where the first frozen bit is located means that the summation between the frozen bit 0 in the first row where the circle is located and the bit 0 in the second row where the circle reaches is 0.

[0090] wherein u0 to u7 are to-be-encoded bits, and the to-be-encoded bits are divided into two categories of fixed bits (frozen) and information bits (data) according to the reliability of the corresponding bit subchannels. The bit subchannels with lower reliability are set as fixed bit subchannels, and the bit values are usually 0. The bit subchannels with higher reliability are set as information bit subchannels, and are used to carry information bits. As shown in FIG. 2, u7, u6, u5, and u3 are four bit subchannels with higher reliability, which are set as information bits, and u4, u2, u1, and u0 are four bits with lower reliability, which are set as fixed bits (frozen).

[0091] It should be noted that during data transmission, the receiving end and the transceiving end of the fixed bit subchannel are known. It can be understood that the bit subchannel can also be referred to as a subchannel in this paper. Similarly, the bit subchannel set can also be referred to as a subchannel set.

[0092] At present, polar encoding can be applied to a physical downlink control channel (PDCCH). The PDCCH is introduced below.

[0093] The PDCCH is used to carry downlink control information (DCI). The scheduling unit of the PDCCH is a control channel element (CCE). A CCE can carry a coded bit sequence of 108 bits. At present, the aggregation level (AL) that can be supported by the PDCCH is 1 / 2 / 4 / 8 / 16, that is, the PDCCH can include 1 / 2 / 4 / 8 / 16 CCEs, and therefore, the length E of the coded bit sequence of the PDCCH is 108 bits, 216 bits, 432 bits, 864 bits, and 1728 bits. At present, the maximum mother code length N of the PDCCH coding and decoding is 512 bits, and therefore, for the PDCCH with AL of 8\16, a 512-bit sequence can be obtained by polar encoding, and then 864-bit and 1728-bit coded bit sequences can be obtained by repeatedly selecting bits in the 512-bit sequence.

[0094] For example, when the AL of the PDCCH is 8\16, a coded bit sequence d0, d1, d2,..., d511 of length 512 can be obtained by Polar code encoding. N-1 After sub-block interleaving, the coded bit sequence after interleaving can be denoted as y0, y1, y2,..., y511. N-1 Then bit selection can be performed in y0, y1, y2,..., y511 according to the following pseudo code to obtain a coded bit sequence of length 864 / 1728: N-1

[0095] for k = 0 to E-1

[0096] e = y k ; mod(k,N)

[0097] end for

[0098] It can be known from the above pseudo code that when the AL is 8\16, the starting point e0 of bit selection is the first bit y0.

[0099] When the AL of the PDCCH is 4, a coded bit sequence of length 512 can be obtained by Polar code encoding, and after sub-block interleaving, the coded bit sequence after interleaving can be denoted as y0, y1, y2,..., y511. N-1 Then bit selection can be performed in y0, y1, y2,..., y511 according to the following pseudo code to obtain a coded bit sequence of length 432: N-1

[0100] for k = 0 to E-1

[0101] e = y k ; k+N-E

[0102] end for

[0103] It can be known from the above pseudo code that when the AL is 4, the first 80 bits are skipped in bit selection, and the starting point e0 of bit selection is the 81st bit y 80 .

[0104] ​​​​Currently, the terminal device needs to decode all the PDCCH before stopping decoding, even if the terminal device has obtained the data sent by the network device through the PDCCH when decoding part of the code blocks of the PDCCH. For example, the network device sends a PDCCH with AL=8 to the terminal device. If the communication environment of the terminal device is good, the data can be obtained through 4 CCEs, but the terminal device still needs to decode all the 8 CCEs of the PDCCH according to the decoding mode corresponding to AL=8, resulting in high complexity of PDCCH blind detection.

[0105] Based on this, the embodiment of the present application provides a communication method and device. When the aggregation level of the PDCCH is high (for example, AL=8 / 16), the encoding bit sequence is generated based on the pre-frozen bit set, so that the encoding structure (that is, the information bit / frozen bit) of part of the bits in the encoding bit sequence is the same as that of the encoding bit sequence when the aggregation level of the PDCCH is low (for example, AL=4), so that even if the aggregation level of the PDCCH is high, the receiving end can decode a small number of CCEs to obtain data, without continuing to decode other CCEs, thereby realizing early stopping of blind detection and reducing the complexity of the receiver. The method and the device are based on the same concept. Since the principles of the method and the device for solving the problem are similar, the implementation of the device and the method can be mutually referred to, and the repeated parts will not be described again.

[0106] In the embodiments of the present application, "when", "if" and "whether" all refer to the objective situation that the device will make corresponding processing, and are not limited by time, and do not require the device to have a judgment action when it is implemented, and do not mean that there are other limitations. Unless otherwise specified, "if" and "whether" can be replaced, and "when" and "in the case of" can be replaced. "When" and "if" / "whether" can be replaced.

[0107] In the embodiments of the present application, "at least one" means one or more, and "multiple" means two or more. "And / or" describes the association relationship of the associated objects, which means that there can be three kinds of relationships, for example, A and / or B, which can represent the following three cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it. "At least one of the following" or similar expressions means any combination of these items, including single item or any combination of multiple items. For example, at least one of a, b, or c, can represent a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, and c can be single or multiple.

[0108] And, unless otherwise indicated, the ordinal numbers "first", "second", and the like in the embodiments of the present application are used to distinguish multiple objects, and are not used to limit the size, content, order, timing, priority, or importance of the multiple objects. For example, the first encoding bit sequence and the second encoding bit sequence are only used to distinguish different encoding bit sequences, and do not represent different lengths, priorities, or importance of the two encoding bit sequences.

[0109] The network architecture and service scenarios described in the embodiments of the present application are used to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those skilled in the art can know that, as the network architecture evolves and new service scenarios appear, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0110] In the present application, the encoding structure can be understood as the position of the information bit / frozen bit. The same encoding structure can be understood as the same information bit. The same information bit also means the same frozen bit, and the information bit and the frozen bit can be derived from each other.

[0111] Referring to FIG. 3, a flowchart of a communication method provided by the present application is shown. The method comprises:

[0112] S301, the network device generates a first encoding bit sequence.

[0113] The first encoding bit sequence is carried in the PDCCH, and the length E of the first encoding bit sequence is greater than the maximum mother code length of the PDCCH n max is a positive integer.

[0114] In the present application, when generating the first encoding bit sequence, the network device can first determine the pre-frozen bit set corresponding to the first encoding bit sequence according to the length of the first bit sequence, and then generate the first encoding bit sequence according to the pre-frozen bit set. The specific generation (or encoding) process of the first encoding bit sequence will be described in detail below.

[0115] Since the length of the second encoding bit sequence is less than the maximum mother code length of the PDCCH , the second encoding bit sequence is also generated according to the pre-frozen bit set, so that the encoding structure of part of the bits in the first encoding bit sequence is the same as the encoding structure of the second encoding bit sequence. For example, the aggregation level of the second encoding bit sequence can be 4.

[0116] In a possible embodiment, the CCEs to which the part of the first coded bit sequence is mapped are the same as the CCEs to which the second coded bit sequence is mapped. For example, taking the aggregation level of the first coded bit sequence as 8 and the aggregation level of the second coded bit sequence as 4, assuming that the first coded bit sequence is mapped on CCEs #0-#7 and the second coded bit sequence is mapped on CCEs #0-#3, in this application, the part of the first coded bit sequence that has the same coding structure as the second coded bit sequence can be mapped on CCEs #0-#3.

[0117] Two implementation manners of the embodiment will be described below in combination with the generation process of the first coded bit sequence.

[0118] S302, the network device sends the first coded bit sequence. Correspondingly, the terminal device receives the first symbol sequence.

[0119] It should be understood that the first symbol sequence can be a signal received by a spatial channel after the first coded bit sequence has undergone modulation, frequency conversion, and the like.

[0120] S303, the terminal device decodes the first symbol sequence.

[0121] In this application, when decoding the first symbol sequence, the terminal device can first determine the pre-frozen bit set corresponding to the first coded bit sequence according to the first bit sequence length, and then decode the first symbol sequence according to the pre-frozen bit set. The specific decoding process will be described below in combination with the coding process of the first coded bit sequence.

[0122] In this application, the pre-frozen bit set is determined for the PDCCH with a high aggregation level, so that part of the bits carried by the PDCCH with a high aggregation level has the same coding structure as the bits carried by the PDCCH with a low aggregation level, thereby even if the aggregation level of the PDCCH is high, the receiving end can decode a small number of CCEs to obtain data, without the need to continue decoding other CCEs, thereby realizing early stopping of blind detection and reducing the complexity of the receiver.

[0123] First, the generation / coding process of the first coded bit sequence will be described below.

[0124] As shown in FIG. 4, the generation process of the first coded bit sequence can include the following steps.

[0125] S401, determine the maximum mother code length N of the PDCCH.

[0126] In an implementation manner, the parameter n can be first determined according to the following pseudo code, and then the maximum mother code length N of the PDCCH can be obtained according to N=2 n ​

[0127] According to the pseudo code, in an example, the maximum mother code length N of the PDCCH n max is a positive integer, for example, n max = 9, etc.

[0128] In another implementation, the parameter n1 can be determined according to the length E of the first coded bit sequence, and then the parameter n2 can be determined according to N = 2 n , to obtain the maximum mother code length N of the PDCCH: R min = 1 / 8; n = max{min{n1, n2, n max}, n min};

[0129] Compared with the previous implementation, this implementation can remove the method of forcibly reducing the mother code length, and improve the performance stability of the Polar code construction.

[0130] S402, determining a rate matching manner of the first coded bit sequence.

[0131] In a possible implementation, if E > N, the rate matching manner adopts repetition; if E ≤ N, when K / E ≤ 7 / 16, puncturing is adopted, and when K / E > 7 / 16, shorten is adopted.

[0132] In the present application, since the length E of the first coded bit sequence is greater than the maximum mother code length N of the PDCCH, it can be determined that the rate matching manner of the first coded bit sequence is repetition.

[0133] S403, determining a pre-frozen bit set corresponding to the first coded bit sequence according to the length of the first bit sequence.

[0134] Optionally, the pre-frozen bit set corresponding to the first coded bit sequence is the same as the pre-frozen bit set corresponding to the second coded bit sequence.

[0135] For example, the pre-frozen bit set can be determined by the following pseudo code:

[0136] wherein J(n) is a rate matching bit, and E is the length of the first bit sequence.

[0137] For example, the length of the first bit sequence can be determined based on the length E of the first coded bit sequence. For example, the length of the first bit sequence satisfies the following formula:

[0138] Alternatively, the first bit sequence length may also be a fixed value, such as 432, etc.

[0139] Alternatively, the first bit sequence length is the length of the second encoded bit sequence. For example, the first bit sequence length can be the length of the encoded bit sequence of the aggregation level = 4.

[0140] S404, determine information bits / frozen bits.

[0141] In one possible implementation, according to reliability ranking determines information bits and frozen bits. For example, the K sub-channels with high reliability in the N sub-channels corresponding sub-channels are removed, and the remaining sub-channels are selected as information bits according to the reliability ranking, and the remaining positions are selected as frozen bits.

[0142] S405, map the information bits to the information bits, and perform Polar code encoding to obtain an N-long encoded bit vector d0, d1, d2, …, d N-1 .

[0143] S406, perform sub-block interleaving on d0, d1, d2, …, d N-1 to obtain an N-long encoded bit vector y0, y1, y2, …, y N-1 .

[0144] It should be noted that S406 is an optional step.

[0145] S407, perform bit selection on the N-long encoded bit vector (which can be d0, d1, d2, …, d N-1 , or y0, y1, y2, …, y N-1 ), and obtain a first encoded bit sequence according to the bit sequence after bit selection.

[0146] Optionally, the starting point of the bit selection corresponding to the first encoded bit sequence in the above S407 is related to the aggregation level, code rate, rate matching manner, etc.

[0147] The starting point of the bit selection corresponding to the first encoded bit sequence can refer to the position of the first bit selected in the N-long encoded bit vector, or it can be understood as the position of the first bit of the first encoded bit sequence in the N-long encoded bit vector.

[0148] In a possible implementation manner, in order to make the part of the CCEs in the first encoded bit sequence that are mapped by the same part of the CCEs in the second encoded bit sequence same as the CCEs in the second encoded bit sequence, the starting point of the bit selection corresponding to the first encoded bit sequence can be modified, for example, the starting point of the bit selection corresponding to the first encoded bit sequence can be related to the aggregation level, the code rate, the rate matching manner, and the like.

[0149] In a specific manner, the starting point of the bit selection corresponding to the first encoded bit sequence is same as the starting point of the bit selection corresponding to the second encoded bit sequence. That is, the position of the first bit in the first encoded bit sequence in the N-length encoded bit vector is same as the position of the first bit in the second encoded bit sequence in the N-length encoded bit vector.

[0150] For example, the first encoded bit sequence can satisfy the following formula, or the first encoded bit sequence is determined by the following formula:

[0151] wherein e k is the kth bit in the first encoded bit sequence, wherein e0 is the first bit in the first encoded bit sequence, that is, the starting point of the bit selection corresponding to the first encoded bit sequence.

[0152] The above manner can be implemented by the following pseudo code:

[0153] Bit selection part:

[0154] According to the foregoing background description, when AL=4, the first 80 bits are skipped in the bit selection, and the starting point e0 of the bit selection is from the 81st bit y 80 . Through the above scheme, for the PDCCH with AL=8 or 16 or higher, the first 80 bits are skipped in the bit selection, and the starting point e0 of the bit selection is also from the 81st bit y 80 . Therefore, through the above design, the first 432 bits carried by the PDCCH with AL=8 or 16 or higher are same as the first 432 bits carried by the PDCCH with AL=4, and the mapped CCEs are also same, so that if the communication environment of the terminal device is good, the data can be obtained by decoding the CCEs, without decoding all the CCEs of the PDCCH with AL=8 or 16 or higher. As shown in FIG. 5.

[0155] For example, the first encoded bit sequence can satisfy the following formula, or the first encoded bit sequence is determined by the following formula:

[0156] The above manner can be implemented by the following pseudo code:

[0157] bit selection part:

[0158] Similar reasons as the implementation of the previous formula can also make the first 432 bits of PDCCH carrying AL = 8 or 16 or higher be the same as the first 432 bits of PDCCH carrying AL = 4, and the mapped CCEs are also the same. And this scheme can save the sub-block interleaver of S406 compared to the implementation of the previous formula, thereby further reducing the complexity of PDCCH blind detection.

[0159] In another possible implementation, in order to make the part of the first encoded bit sequence that has the same encoding construction as the second encoded bit sequence mapped to the same CCE as the second encoded bit sequence, interleaving can be performed after the bit selection of S407 described above. For example, assuming that the bit selection of S407 described above obtains an encoded bit sequence 1, the first encoded bit sequence is obtained after interleaving the encoded bit sequence 1.

[0160] For example, the first M bits of the first encoded bit sequence are the same as the last M bits of the encoded bit sequence 1, where M is the length of the second encoded bit sequence.

[0161] In one specific implementation, the encoded bit sequence 1 can be circularly shifted forward according to the starting point of the PDCCH (or encoded bit sequence) when AL = 4, so that the first M bits of the first encoded bit sequence are the same as the bit sequence of the PDCCH when AL = 4.

[0162] For example, the encoded bit sequence 1 can be divided into several sub-blocks according to the length of the PDCCH (or encoded bit sequence) when AL = 4. For example, if the AL of the encoded bit sequence 1 is 8, the encoded bit sequence 1 can be divided into 2 sub-blocks. If the AL of the encoded bit sequence 1 is 16, the encoded bit sequence 1 can be divided into 4 sub-blocks. When the encoded bit sequence 1 is interleaved into sub-blocks, the last sub-block can be interleaved first. For example, assuming that the AL of the encoded bit sequence 1 is 8, the encoded bit sequence 1 can be divided into 2 sub-blocks, i.e., sub-block 0 and sub-block 1, and after sub-block interleaving, sub-block 1 is located before sub-block 0, as shown in FIG. 6. Assuming that the AL of the encoded bit sequence 1 is 16, the encoded bit sequence 1 can be divided into 4 sub-blocks, i.e., sub-block 0 to sub-block 3, and after sub-block interleaving, sub-block 3 is located before sub-block 0, sub-block 1, and sub-block 2, as shown in FIG. 7.

[0163] For another example, the coded bit sequence 1 can be interleaved in reverse order. For example, the coded bit sequence 1 can be divided into R sub-blocks, which are sub-block 0, sub-block R-1 in sequence. After interleaving, the order of the sub-blocks is sub-block R-1, sub-block R-2, …, sub-block 0.

[0164] The above two implementation manners improve the determination manner of the starting point of the bit selection corresponding to the first coded bit sequence or the interleaving manner, so that the CCEs to which the part of bits in the first coded bit sequence are mapped are the same as the CCEs to which the part of bits in the second coded bit sequence are mapped. Another implementation manner is introduced below. The starting point of the bit selection corresponding to the PDCCH (or the coded bit sequence) when AL=4 is modified, so that the CCEs to which the part of bits in the first coded bit sequence are mapped are the same as the CCEs to which the part of bits in the second coded bit sequence are mapped. For example, when the AL of the PDCCH is 4, a coded bit sequence with a length of 512 can be obtained by Polar code encoding. The coded bit sequence after sub-block interleaving can be denoted as y0, y1, y2, …, y N-1 The bit selection can be performed in y0, y1, y2, …, y N-1 to obtain a coded bit sequence with a length of 432 according to the following pseudo code:

[0165] for k=0 to E-1

[0166] e k = y k ;

[0167] end for

[0168] This manner modifies the starting point of the bit selection corresponding to the PDCCH (or the coded bit sequence) when AL=4, so that the same starting point can be used when the rate matching manner is puncturing and when the rate matching manner is repetition, which simplifies the standard description and reduces the implementation complexity.

[0169] The generation process of the first coded bit sequence is introduced above. The decoding process of the first symbol sequence is introduced below in combination with the generation process of the first coded bit sequence.

[0170] The decoding process of the first symbol sequence can include:

[0171] A1, determining a pre-frozen bit set corresponding to the first coded bit sequence according to the length of the first bit sequence.

[0172] The terminal device determines the pre-frozen bit set in the same manner as the network device, and the specific manner can refer to the related description of S403 in the foregoing, which is not repeated here.

[0173] A2, determine the information bits and frozen bits.

[0174] The terminal device determines the information bits and frozen bits in the same manner as the network device, and the specific manner can refer to the related description of S404 in the foregoing, which is not repeated here.

[0175] A3, perform the inverse process of S407 on the E-length symbol sequence to obtain a third symbol sequence of N length.

[0176] For example, the E-length symbol sequence is actually a bit sequence after bit selection, and thus the E-length symbol sequence can be inversely deduced to obtain a bit sequence before bit selection according to the bit selection method in S407. For another example, the E-length symbol sequence is actually a bit sequence after interleaving, and thus the E-length symbol sequence can be inversely deduced to obtain a bit sequence before sub-block interleaving according to the sub-block interleaving method in S407.

[0177] A4, decode the third symbol sequence according to the information bits and frozen bits to obtain the recovered original bit sequence.

[0178] For example, the log likelihood ratio (LLR) of each bit in the third symbol sequence is calculated. For an information bit, if the LLR>0, the bit is determined as 0, and if the LLR<0, the bit is determined as 1. For a frozen bit, the bit is set as 0 regardless of the LLR.

[0179] A5, obtain the information bits from the information bits.

[0180] The present application determines the pre-frozen bit set for the PDCCH of the high aggregation level, so that part of the bits carried by the PDCCH of the high aggregation level have the same encoding and construction manner as the bits carried by the PDCCH of the low aggregation level, so that even if the aggregation level of the PDCCH is high, the receiving end can decode a small number of CCEs to obtain data, without the need to continue decoding other CCEs, thereby realizing early stopping of blind detection and reducing the complexity of the receiver.

[0181] Moreover, by modifying the starting point of the bit selection corresponding to the first coding bit sequence or performing interleaving after the bit selection, the CCE mapped to some bits in the first coding bit sequence that have the same coding structure as the second coding bit sequence can be made the same as the CCE mapped to the second coding bit sequence, so that the receiving end can decode a small number of CCEs to obtain data, which is further conducive to achieving blind detection early stopping and reducing the complexity of the receiver.

[0182] Based on the same inventive concept as the method embodiment, an embodiment of the present application provides a communication device, the structure of which may be as shown in FIG8 , including a communication unit 801 and a processing unit 802 .

[0183] In one embodiment, a communication device can be specifically used to implement the method performed by the network device in the embodiment of Figure 3. The device can be the network device itself, or a chip or chipset in the network device, or a part of the chip used to perform the function of the relevant method. Among them, the processing unit 802 is used to determine a pre-frozen bit set corresponding to a first coding bit sequence based on the length of the first bit sequence, the first coding bit sequence is carried on the PDCCH, and the length of the first coding bit sequence is greater than the maximum mother code length of the PDCCH. n max is a positive integer; and generating a first coded bit sequence according to the pre-frozen bit set. The communication unit 801 is configured to send the first coded bit sequence.

[0184] Optionally, when the processing unit 802 generates the first coded bit sequence according to the pre-frozen bit set, the processing specifically includes: determining information bits according to the pre-frozen bit set; mapping the information bits to the information bits and then encoding them; performing bit selection on the encoded bit sequence; and generating the first coded bit sequence according to the bit sequence obtained after the bit selection.

[0185] In one embodiment, a communication device can be specifically used to implement the method executed by the terminal device in the embodiment of Figure 3. The device can be the terminal device itself, or a chip or chipset in the terminal device or a part of the chip used to execute the function of the relevant method. Among them, the communication unit 801 is used to receive a first symbol sequence, the first symbol sequence is carried on the PDCCH, and the length of the first symbol sequence is greater than the maximum mother code length of the PDCCH. n max The processing unit 802 is configured to determine a pre-frozen bit set corresponding to the first symbol sequence according to the first bit sequence length, and decode the first symbol sequence according to the pre-frozen bit set.

[0186] Optionally, the processing unit 802 is specifically configured to determine information bits according to the pre-frozen bit set when decoding the first symbol sequence according to the pre-frozen bit set, recover the first symbol sequence according to a bit selection method corresponding to the first symbol sequence to obtain a third symbol sequence, decode the third symbol sequence according to the information bits, and obtain information bits from the decoded bit sequence.

[0187] The division of the modules in the embodiments of the present application is illustrative, and is merely a logical function division. In actual implementation, another division manner can be used. In addition, each function module in each embodiment of the present application can be integrated in one processor, or can be physically separated, or two or more modules can be integrated in one module. The integrated module can be implemented in the form of hardware or in the form of a software function module. It can be understood that the functions or implementation of each module in the embodiments of the present application can be further referred to the related description of the method embodiments.

[0188] In a possible manner, a communication device can be as shown in FIG. 9. The device can be a communication device or a chip in a communication device. The communication device can be a terminal device in the above embodiments, or can be a network device in the above embodiments. The device includes a processor 901 and a communication interface 902, and can further include a memory 903. The processing unit 802 can be the processor 901. The communication unit 801 can be the communication interface 902. Optionally, the processor 901 and the memory 903 can be integrated together.

[0189] The processor 901 can be a CPU or a digital processing unit, etc. The communication interface 902 can be a transceiver, an interface circuit such as a transceiver circuit, a transceiver chip, etc. The device further includes a memory 903 for storing programs executed by the processor 901. The memory 903 can be a non-volatile memory such as a hard disk drive (HDD) or a solid-state drive (SSD), etc., and can also be a volatile memory such as a random-access memory (RAM). The memory 903 can be any other medium capable of carrying or storing desired program codes in the form of instructions or data structures and capable of being accessed by a computer, but is not limited thereto.

[0190] The processor 901 is configured to execute the program codes stored in the memory 903, and is specifically configured to execute the actions of the processing unit 802 described above. The communication interface 902 is specifically configured to execute the actions of the communication unit 801 described above.

[0191] The specific connection medium between the communication interface 902, the processor 901 and the memory 903 is not limited in the embodiments of the present application. In FIG. 9, the memory 903, the processor 901 and the communication interface 902 are connected through a bus 904, which is represented by a thick line in FIG. 9, and the connection mode between other components is only illustrative and is not limited. The bus can be divided into an address bus, a data bus, a control bus and the like. In order to facilitate representation, only one thick line is used in FIG. 9, but it does not mean that there is only one bus or only one type of bus.

[0192] The embodiments of the present application also provide a computer readable storage medium for storing computer software instructions required for the processor to execute the above-mentioned processes, which contains programs required for the processor to execute.

[0193] The embodiments of the present application also provide a communication system, which comprises a communication device for realizing the function of the terminal device in the embodiment of FIG. 3 and a communication device for realizing the function of the network device in the embodiment of FIG. 3.

[0194] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system or a computer program product. Therefore, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage and the like) containing computer-usable program code.

[0195] The present application is described with reference to flowcharts and / or block diagrams of the method, device (system) and computer program product according to the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of flows and / or blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing apparatus to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing apparatus produce a device that implements the functions specified in one or more flows in the flowcharts and / or one or more blocks in the block diagrams.

[0196] These computer program instructions can also be stored in a computer readable storage medium, which can guide the computer or other programmable data processing apparatus to work in a specific way, so that the instructions stored in the computer readable storage medium produce a product including instruction devices, which implement the functions specified in one or more flows in the flowcharts and / or one or more blocks in the block diagrams.

[0197] These computer program instructions can also be loaded into computer or other programmable data processing devices, so that a series of operation steps are performed on the computer or other programmable data processing devices to generate computer-implemented processes, thus the instructions executed on the computer or other programmable data processing devices provide steps for implementing the functions specified in one or more flows of the flowchart and / or one or more blocks of the block diagram.

[0198] Obviously, various modifications and changes can be made to the present application by those skilled in the art without departing from the scope of the present application. Thus, it is intended that the present application include all such modifications and changes that fall within the scope of the appended claims and their equivalents.

Claims

1. A communication method, characterized in that: The method comprises: A pre-frozen bit set corresponding to a first coded bit sequence is determined according to a first bit sequence length, the first coded bit sequence is carried on a physical downlink control channel PDCCH, and the length of the first coded bit sequence is greater than a maximum mother code length of the PDCCH. n max is a positive integer; generating a first coded bit sequence according to the pre-frozen bit set; The first coded bit sequence is transmitted.

2. The method according to claim 1, wherein The pre-frozen bit set corresponding to the first coded bit sequence is the same as the pre-frozen bit set corresponding to the second coded bit sequence, and the length of the second coded bit sequence is less than the maximum mother code length of the PDCCH 3. The method according to claim 1 or 2, wherein: The length of the first bit sequence is determined based on the length of the first coded bit sequence; Alternatively, the first bit sequence length is 432; Alternatively, the length of the first bit sequence is the length of the second coded bit sequence, and the length of the second coded bit sequence is less than the maximum mother code length of the PDCCH 4. The method according to claim 3, wherein The first bit sequence length Satisfies the following formula: Wherein, E is the length of the first coded bit sequence, and N is the maximum mother code length of PDCCH.

5. The method according to any one of claims 1 to 4, characterized in that The control channel element CCE mapped to some bits in the first coded bit sequence is the same as the CCE mapped to the second coded bit sequence, the information bits corresponding to the some bits are the same as the information bits corresponding to the second coded bit sequence, and the length of the second coded bit sequence is less than the maximum mother code length of the PDCCH 6. The method according to claim 5, wherein The starting point of the bit selection corresponding to the first coded bit sequence is related to at least one of the following parameters: the aggregation level of the first coded bit sequence, the code rate of the first coded bit sequence, and the rate matching mode of the first coded bit sequence.

7. The method according to claim 6, wherein A starting point of bit selection corresponding to the first coded bit sequence is the same as a starting point of bit selection corresponding to the second coded bit sequence.

8. The method according to any one of claims 1 to 7, wherein: The first coded bit sequence satisfies the following formula: Among them, e k is the bit numbered k in the first coded bit sequence, is the first bit length, E is the length of the first coded bit sequence, and N is the maximum mother code length of the PDCCH The y n is the bit numbered n in a third coded bit sequence, where the third coded bit sequence is a bit sequence obtained by encoding and interleaving the information bits; Alternatively, the first coded bit sequence satisfies the following formula: Among them, e k is the bit numbered k in the first coded bit sequence, is the first bit length, and N is the maximum mother code length of the PDCCH The d n is the bit numbered n in the fourth coded bit sequence, where the fourth coded bit sequence is a bit sequence obtained by encoding the information bits.

9. The method according to claim 5, wherein The first coded bit sequence is obtained by interleaving the fifth coded bit sequence, and the fifth coded bit sequence is a bit sequence obtained by encoding and selecting information bits.

10. The method according to claim 9, wherein The first M bits in the first coded bit sequence are the same as the last M bits in the fifth coded bit sequence, where M is the length of the second coded bit sequence, and the length of the second coded bit sequence is less than the maximum mother code length of the PDCCH 11. The method according to claim 5, wherein The first coded bit sequence is obtained by cyclically shifting the fifth coded bit sequence forward according to a starting point of the second coded bit sequence.

12. The method according to any one of claims 1 to 11, wherein: The rate matching mode of the first coded bit sequence is repetition.

13. The method according to any one of claims 1 to 12, wherein: Generating a first coded bit sequence according to the pre-frozen bit set includes: determining information bits according to the pre-frozen bit set; Mapping the information bits to the information bits and then encoding them; Perform bit selection on the encoded bit sequence; The first coded bit sequence is generated according to the bit sequence obtained after the bit selection.

14. The method according to any one of claims 1 to 13, wherein: The n max =9.

15. The method according to any one of claims 2, 3, 5-7, 10, and 11, wherein: The aggregation level of the second coded bit sequence is 4.

16. A communication method, characterized in that: The method comprises: Receive a first symbol sequence, where the first symbol sequence is carried on a physical downlink control channel (PDCCH), and the length of the first symbol sequence is greater than the maximum mother code length of the PDCCH. n max is a positive integer; determining a pre-frozen bit set corresponding to the first symbol sequence according to the first bit sequence length; The first symbol sequence is decoded according to the pre-frozen bit set.

17. The method according to claim 16, wherein The pre-frozen bit set corresponding to the first symbol sequence is determined in the same manner as the pre-frozen bit set corresponding to the second symbol sequence, and the length of the second symbol sequence is less than the maximum mother code length of the PDCCH.

18. The method according to claim 16 or 17, wherein: The length of the first bit sequence is determined based on the length of the first symbol sequence; Alternatively, the first bit sequence length is 432; Alternatively, the length of the first bit sequence is the length of the second symbol sequence, and the length of the second symbol sequence is less than the maximum mother code length of the PDCCH 19. The method according to claim 18, wherein The first bit sequence length Satisfies the following formula: Wherein, E is the length of the first symbol sequence, and N is the maximum mother code length of PDCCH.

20. The method according to any one of claims 16 to 19, wherein: The control channel element CCE mapped to some bits in the first symbol sequence is the same as the CCE mapped to the second symbol sequence, the information bits corresponding to the some bits are the same as the information bits corresponding to the second symbol sequence, and the length of the second symbol sequence is less than the maximum mother code length of the PDCCH 21. The method according to claim 20, wherein The starting point of the bit selection corresponding to the first symbol sequence is related to at least one of the following parameters: the aggregation level of the first symbol sequence, the code rate of the first symbol sequence, and the rate matching mode of the first symbol sequence.

22. The method according to claim 21, wherein A starting point for selecting bits corresponding to the first symbol sequence is the same as a starting point for selecting bits corresponding to the second symbol sequence.

23. The method according to any one of claims 16 to 22, wherein: The coded bit sequence corresponding to the first symbol sequence satisfies the following formula: Among them, e k is the bit numbered k in the coded bit sequence corresponding to the first symbol sequence, is the first bit length, E is the length of the first symbol sequence, and N is the maximum mother code length of the PDCCH The y n is the bit numbered n in a third coded bit sequence, where the third coded bit sequence is a bit sequence obtained by encoding and interleaving the information bits; Alternatively, the coded bit sequence corresponding to the first symbol sequence satisfies the following formula: Among them, e k is the bit numbered k in the coded bit sequence corresponding to the first symbol sequence, is the first bit length, and N is the maximum mother code length of the PDCCH The d n is the bit numbered n in a fourth coded bit sequence, where the fourth coded bit sequence is a bit sequence obtained by encoding the information bits.

24. The method of claim 20, wherein: The coded bit sequence corresponding to the first symbol sequence is obtained by interleaving the fifth coded bit sequence, and the fifth coded bit sequence is a bit sequence obtained by encoding and selecting information bits.

25. The method of claim 24, wherein: The first M bits in the coded bit sequence corresponding to the first symbol sequence are the same as the last M bits in the fifth coded bit sequence, where M is the length of the second symbol sequence, and the length of the second symbol sequence is less than the maximum mother code length of the PDCCH 26. The method of claim 24, wherein: The first coded bit sequence is obtained by cyclically shifting the fifth coded bit sequence forward according to a starting point of the second coded bit sequence.

27. The method according to any one of claims 16 to 26, wherein: The rate matching mode of the first symbol sequence is repetition.

28. The method according to any one of claims 16 to 27, wherein: The decoding the first symbol sequence according to the pre-frozen bit set includes: determining information bits according to the pre-frozen bit set; Recover the first symbol sequence according to the bit selection method corresponding to the first symbol sequence to obtain a third symbol sequence; Decoding the third symbol sequence according to the information bits; The information bits are obtained from the decoded bit sequence.

29. The method according to any one of claims 16 to 28, wherein: The n max =9.

30. The method according to any one of claims 17, 18, 20-22, 25, and 26, wherein: The aggregation level of the second symbol sequence is 4.

31. A communication device, characterized in that: The method comprises a processor and a memory, wherein the memory is used to store program instructions, and when the processor executes the program instructions, the method according to any one of claims 1 to 15 is executed, or the method according to any one of claims 16 to 30 is executed.

32. A computer-readable storage medium, characterized in that The computer storage medium stores computer-readable instructions, and when the computer-readable instructions are executed on the communication device, the method according to any one of claims 1 to 15 is executed, or the method according to any one of claims 16 to 30 is executed.

33. A computer program product, characterized in that When the computer program product is run on a device, the device is caused to perform the method according to any one of claims 1 to 15 or the method according to any one of claims 16 to 30.

34. A communication system, characterized in that The system includes a first device and a second device, wherein the first device is used to execute the method according to any one of claims 1 to 15, and the second device is used to execute the method according to any one of claims 16 to 30.

35. A communication device, characterized in that: The method comprises a unit or module for executing the method according to any one of claims 1 to 15, or comprises a unit or module for executing the method according to any one of claims 16 to 30.

36. A chip, characterized in that: The chip is coupled to the memory and is configured to read and execute program instructions stored in the memory to implement the method according to any one of claims 1 to 15, or to implement the method according to any one of claims 16 to 30.

37. A communication device, characterized in that: The method comprises a processor and an interface circuit, wherein the interface circuit is used to receive a signal and transmit it to the processor or send a signal from the processor, and the processor is used to execute the method according to any one of claims 1 to 15 or the method according to any one of claims 16 to 30 through a logic circuit or executing code instructions.

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