Display substrate and display device

Abstract

A display substrate, comprising: a base (10); a plurality of sub-pixels (PX) provided on one side of the base (10) and located in a display area (AA); a plurality of first data lines (DLa); a plurality of second data lines (DLb); a plurality of data connecting lines (25); a plurality of data lead-out lines located in a lead-out routing area; a plurality of first transfer units (300a, 300b) and a plurality of second transfer units (32a, 32b); and a plurality of data contact pads (27) located in a first signal access area (B134). The plurality of first transfer units (300a, 300b) are located on the side of the plurality of second transfer units (32a, 32b) distant from the display area (AA). The plurality of data lead-out lines are connected to the plurality of data contact pads (27) by means of the plurality of first transfer units (300a, 300b), and are connected to the plurality of second data lines (DLb) and the plurality of data connection lines (25) by means of the plurality of second transfer units (32a, 32b).

Description

Display substrate and display device TECHNICAL FIELD

[0001] The present document relates to, but is not limited to, the technical field of display, and in particular to a display substrate and a display device. BACKGROUND

[0002] Organic light emitting diode (OLED) and quantum dot light emitting diode (QLED) are active light emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost.

[0003] SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0005] The present embodiment provides a display substrate and a display device.

[0006] In one aspect, the present embodiment provides a display substrate, comprising: a substrate, a plurality of sub-pixels, a plurality of first data lines, a plurality of second data lines, a plurality of data connection lines, a plurality of data lead-out lines, a plurality of data contact pads, and a plurality of groups of switching units. The substrate comprises a display area and a first frame area located on one side of the display area along a first direction, and the first frame area comprises a first signal access area and a lead-out area of wires located between the first signal access area and the display area. The plurality of sub-pixels are arranged on one side of the substrate and located in the display area. The plurality of first data lines, the plurality of second data lines, and the plurality of data connection lines are located in the display area; the plurality of first data lines and the plurality of second data lines are configured to provide data signals to the plurality of sub-pixels, and the plurality of first data lines are connected to the plurality of data connection lines. The plurality of data lead-out lines are located in the lead-out area of wires. The plurality of data contact pads are located in the first signal access area. The plurality of groups of first switching units and the plurality of groups of second switching units are located in the lead-out area of wires, the plurality of groups of first switching units are located on the side of the plurality of groups of second switching units away from the display area, the plurality of groups of first switching units are arranged along a second direction, the plurality of groups of second switching units are arranged along the second direction, and the second direction intersects the first direction. The plurality of data lead-out lines are connected to the plurality of data contact pads through the plurality of groups of first switching units, and are connected to the plurality of second data lines and the plurality of data connection lines through the plurality of groups of second switching units, so that the order of the data signals provided by the plurality of data contact pads matches the order of the data signals required by the plurality of second data lines and the plurality of data connection lines arranged along the second direction.

[0007] In some example embodiments, each group of first adapting units comprises m first connection ends, m second connection ends, and m first adapting lines; each first adapting line is connected between one first connection end and one second connection end; each first connection end is connected with one data lead-out line, and each second connection end is connected with one data contact pad; the m first connection ends are arranged along the second direction and correspond to different first arrangement serial numbers, and the m second connection ends are arranged along the second direction and correspond to different second arrangement serial numbers. The m first adapting lines in each group of first adapting units comprise a first-order adapting line, wherein the first arrangement serial number corresponding to the first connection end connected by the first-order adapting line is different from the second arrangement serial number corresponding to the second connection end connected by the first-order adapting line; m and a are integers greater than 1, and m is greater than or equal to a. The second direction intersects the first direction.

[0008] In some example embodiments, the a first-order adapting lines in each group of first adapting units comprise a1 first-order adapting lines and a2 second-order adapting lines, a1 and a2 are integers greater than 0, and the sum of a1 and a2 is a; the first arrangement serial number corresponding to the first connection end connected by the first-order adapting line is less than the second arrangement serial number corresponding to the second connection end connected by the first-order adapting line; the first arrangement serial number corresponding to the first connection end connected by the second-order adapting line is greater than the second arrangement serial number corresponding to the second connection end connected by the second-order adapting line.

[0009] In some example embodiments, the difference between the second arrangement serial number corresponding to the second connection end connected by the first-order adapting line and the first arrangement serial number corresponding to the first connection end connected by the first-order adapting line is greater than or equal to the difference between the first arrangement serial number corresponding to the first connection end connected by the second-order adapting line and the second arrangement serial number corresponding to the second connection end connected by the second-order adapting line.

[0010] In some example embodiments, the first-order adapting line in the substrate has an overlapping projection with at least one second-order adapting line in the substrate.

[0011] In some example embodiments, the m adapting lines in each group of first adapting units further comprise b first-order adapting lines, wherein the first arrangement serial number corresponding to the first connection end connected by the first-order adapting line is the same as the second arrangement serial number corresponding to the second connection end connected by the first-order adapting line; b is an integer greater than 1, and b is less than or equal to a.

[0012] In some example embodiments, the b first-order adapting lines and the first-order adapting line are in the same layer structure, or at least one first-order adapting line is located on the side close to the substrate of the first-order adapting line and the second-order adapting line.

[0013] In some example embodiments, m is 8; each group of first adapter units comprises eight first connection terminals, eight second connection terminals, and eight first adapter lines; the eight first connection terminals are arranged in sequence along the second direction, the eight second connection terminals are arranged in sequence along the second direction and located on a side of the eight first connection terminals close to the first signal access area, and the eight first adapter lines comprise two first plug sequence adapter lines, two second plug sequence adapter lines, and four first order adapter lines; the first plug sequence adapter line is configured to connect an i-th first connection terminal and an (i+1)-th second connection terminal; the second plug sequence adapter line is configured to connect an (i+1)-th first connection terminal and an i-th second connection terminal; and the value of i includes 1 and 5.

[0014] In some example embodiments, one pixel unit located in the display area comprises one first sub-pixel emitting first color light, one second sub-pixel emitting second color light, and two third sub-pixels emitting third color light. The plurality of data contact pads are configured to provide data signals to the sub-pixels of an e-th row of pixel units in the display area in a first time period and to the sub-pixels of an (e+1)-th row of pixel units in the display area in a second time period, where e is an integer greater than 0. In the first time period, the data signals transmitted by the eight second connection terminals in each group of first adapter units are configured to correspond to the third sub-pixel, the first sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the first sub-pixel, and the third sub-pixel in sequence, or are configured to correspond to the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, and the first sub-pixel in sequence. In the second time period, the data signals transmitted by the eight second connection terminals in each group of first adapter units are configured to correspond to the third sub-pixel, the second sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the second sub-pixel, and the third sub-pixel in sequence, or are configured to correspond to the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, and the second sub-pixel in sequence.

[0015] In some example embodiments, m is 12. Each group of first adapter units comprises twelve first connection ends, twelve second connection ends, and twelve first adapter lines; the twelve first connection ends are arranged in sequence along the second direction, the twelve second connection ends are arranged in sequence along the second direction and located on the side of the twelve first connection ends close to the first signal access area, and the twelve first adapter lines comprise four first plug sequence adapter lines, four second plug sequence adapter lines, and four first order adapter lines; the first plug sequence adapter line is configured to connect the i-th first connection end and the (i+1)-th second connection end; the second plug sequence adapter line is configured to connect the (i+1)-th first connection end and the i-th second connection end; and the value of i includes 1, 3, 7, and 9.

[0016] In some example embodiments, one pixel unit located in the display area comprises one first sub-pixel emitting first color light, one second sub-pixel emitting second color light, and two third sub-pixels emitting third color light. The plurality of data contact pads are configured to provide data signals to the sub-pixels of the e-th row of pixel units in the display area in a first time period and to the sub-pixels of the (e+1)-th row of pixel units in the display area in a second time period, where e is an integer greater than 0. In the first time period, the data signals transmitted by the twelve second connection ends in each group of first adapter units are configured to correspond to the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the first sub-pixel, the second sub-pixel, and the third sub-pixel in sequence; or, are configured to correspond to the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the second sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, and the first sub-pixel in sequence. In the second time period, the data signals transmitted by the twelve second connection ends in each group of first adapter units are configured to correspond to the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the second sub-pixel, the first sub-pixel, and the third sub-pixel in sequence, or, are configured to correspond to the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the first sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, and the second sub-pixel in sequence.

[0017] In some example embodiments, m is 16. Each group of first adapter units comprises sixteen first connection ends, sixteen second connection ends, and sixteen first adapter lines. The sixteen first connection ends are arranged in sequence along the second direction. The sixteen second connection ends are arranged in sequence along the second direction and located on a side of the sixteen first connection ends close to the first signal access area. The sixteen first adapter lines comprise four first plug sequence adapter lines, four second plug sequence adapter lines, and eight first order adapter lines. The first plug sequence adapter line is configured to connect an i-th first connection end and an (i+1)-th second connection end. The second plug sequence adapter line is configured to connect an (i+1)-th first connection end and an i-th second connection end. The value of i includes 1, 3, 9, and 11.

[0018] In some example embodiments, one pixel unit located in the display area comprises one first sub-pixel emitting first color light, one second sub-pixel emitting second color light, and two third sub-pixels emitting third color light. The plurality of data contact pads are configured to provide data signals to the sub-pixels of an e-th row of pixel units in the display area in a first time period and to the sub-pixels of an (e+1)-th row of pixel units in the display area in a second time period, where e is an integer greater than 0. In the first time period, the data signals transmitted by the sixteen second connection ends in each group of first adapter units are configured to correspond to the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, and the third sub-pixel in sequence, or are configured to correspond to the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, and the first sub-pixel in sequence. In the second time period, the data signals transmitted by the sixteen second connection ends in each group of first adapter units are configured to correspond to the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, and the third sub-pixel in sequence, or are configured to correspond to the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, and the second sub-pixel in sequence.

[0019] In some example embodiments, m is 20. Each group of first adapter units comprises twenty first connection ends, twenty second connection ends, and twenty first adapter lines; the twenty first connection ends are arranged in sequence along the second direction, the twenty second connection ends are arranged in sequence along the second direction and located on a side of the twenty first connection ends close to the first signal access area, and the twenty first adapter lines comprise six first plug sequence adapter lines, six second plug sequence adapter lines, and eight first order adapter lines; the first plug sequence adapter line is configured to connect an i-th first connection end and an (i+1)-th second connection end; the second plug sequence adapter line is configured to connect an (i+1)-th first connection end and an i-th second connection end; and the value of i includes 1, 3, 5, 11, 13, and 15.

[0020] In some example embodiments, one pixel unit located in the display area comprises one first sub-pixel emitting first color light, one second sub-pixel emitting second color light, and two third sub-pixels emitting third color light. The plurality of data contact pads are configured to provide data signals to the sub-pixels of an e-th row of pixel units in the display area in a first time period and to the sub-pixels of an (e+1)-th row of pixel units in the display area in a second time period, where e is an integer greater than 0. In the first time period, the data signals transmitted by the twenty second connection ends in each group of first adapter units are configured to correspond to the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the second sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, and the third sub-pixel in sequence, or are configured to correspond to the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the second sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, and the first sub-pixel in sequence. In the second time period, the data signals transmitted by the sixteen second connection ends in each group of first adapter units are configured to correspond to the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, and the third sub-pixel in sequence, or are configured to correspond to the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, and the second sub-pixel in sequence.

[0021] In some example embodiments, one pixel unit located in the display area includes: one first sub-pixel for emitting light of a first color, one second sub-pixel for emitting light of a second color, and two third sub-pixels for emitting light of a third color. The plurality of data lead lines connected with the first connection end of the plurality of groups of first adapter units includes: a first group of data lead lines and a second group of data lead lines, the first group of data lead lines and the second group of data lead lines are located in different conductive layers and are arranged alternately along the second direction, the first group of data lead lines are configured to transmit data signals required by the third sub-pixels, and the second group of data lead lines are configured to transmit data signals required by the first sub-pixel and the second sub-pixel.

[0022] In some example embodiments, the display substrate further includes: a plurality of groups of test circuits located in the lead-out area and arranged in sequence along the second direction; the plurality of groups of test circuits are located on the side of the plurality of groups of first adapter units away from the first signal access area along the first direction; wherein one group of test circuits is connected with m data lead lines connected with one group of first adapter units; the second direction intersects the first direction; each group of test circuits includes: a first test circuit and b second test circuits; twice the sum of a and b is equal to m, and a and b are both integers greater than 0. The first test circuit includes: a first test transistor, a second test transistor, and a third test transistor; the gate of the first test transistor is connected with a first test control line, the first electrode of the first test transistor is connected with a first test data line, the gate of the second test transistor is connected with a second test control line, the first electrode of the second test transistor is connected with a second test data line, and the second electrode of the first test transistor and the second electrode of the second test transistor are connected with the same data lead line; the gate of the third test transistor is connected with a third test control line, and the first electrode of the third test transistor is connected with a third test data line. The second test circuit includes: a fourth test transistor, a fifth test transistor, and a sixth test transistor; the gate of the fourth test transistor is connected with the second test control line, the first electrode of the fourth test transistor is connected with the first test data line, the gate of the fifth test transistor is connected with the first test control line, the first electrode of the fifth test transistor is connected with the second test data line, and the second electrode of the fourth test transistor and the second electrode of the fifth test transistor are connected with the same data lead line; the gate of the sixth test transistor is connected with the third test control line, and the first electrode of the third test transistor is connected with the third test data line; the second electrode of the first test transistor, the second electrode of the third test transistor, the second electrode of the fourth test transistor, and the second electrode of the sixth test transistor are connected with different data lead lines.

[0023] In some example embodiments, the first test transistor, the second test transistor and the third test transistor of the first test circuit are arranged along the first direction; the fourth test transistor, the fifth test transistor and the sixth test transistor of the second test circuit are arranged along the first direction. The first test transistor and the fourth test transistor are arranged in alignment in the second direction, the second test transistor and the fifth test transistor are arranged in alignment in the second direction, and the third test transistor and the sixth test transistor are arranged in alignment in the second direction.

[0024] In some example embodiments, m is 8. Each group of test circuits comprises two first test circuits and two second test circuits; wherein one first test circuit, two second test circuits and one first test circuit are arranged along the second direction.

[0025] In some example embodiments, m is 12. Each group of test circuits comprises three first test circuits and three second test circuits; wherein one first test circuit, two second test circuits, two first test circuits and one second test circuit are arranged along the second direction; or one first test circuit, one second test circuit, one first test circuit, two second test circuits and one first test circuit are arranged along the reverse direction of the second direction.

[0026] In some example embodiments, m is 16. Each group of test circuits comprises four first test circuits and four second test circuits; wherein one first test circuit, two second test circuits, one first test circuit, one second test circuit, two first test circuits and one second test circuit are arranged along the second direction; or one first test circuit, one second test circuit, one first test circuit, two second test circuits, one first test circuit, one second test circuit and one first test circuit are arranged along the reverse direction of the second direction.

[0027] In some example embodiments, m is 20. Each group of test circuits comprises five first test circuits and five second test circuits; wherein one first test circuit, two second test circuits, one first test circuit, one second test circuit, one first test circuit, one second test circuit, two first test circuits and one second test circuit are arranged along the second direction; or one first test circuit, one second test circuit, one first test circuit, one second test circuit, one first test circuit, two second test circuits, one first test circuit, one second test circuit and one first test circuit are arranged along the reverse direction of the second direction.

[0028] In some example embodiments, a single pixel unit of the display area includes c sub-pixels, m is k times of c, and k is an integer greater than 1.

[0029] In another aspect, the present embodiments provide a display device including the display substrate as described above.

[0030] In another aspect, the embodiment provides a display substrate, comprising: a substrate, a plurality of sub-pixels, a plurality of first data lines, a plurality of second data lines, a plurality of data connection lines, a plurality of data lead-out lines, and a plurality of test circuits. The substrate comprises: a display area and a first frame area located at one side of the display area along a first direction, the first frame area comprising: a first signal access area and a trace lead-out area located between the first signal access area and the display area. The plurality of sub-pixels are arranged at one side of the substrate and located in the display area. The plurality of first data lines, the plurality of second data lines, and the plurality of data connection lines are located in the display area; the plurality of first data lines and the plurality of second data lines are configured to provide data signals to the plurality of sub-pixels, and the plurality of first data lines are connected to the plurality of data connection lines. The plurality of data lead-out lines are located in the trace lead-out area, and the plurality of data lead-out lines are connected to the plurality of second data lines and the plurality of data connection lines. The plurality of test circuits are located in the trace lead-out area and arranged in sequence along a second direction, each test circuit is connected to m continuously arranged data lead-out lines, and the second direction intersects the first direction; m is an integer greater than 1. Each test circuit comprises: a first test circuit and a second test circuit, a and b are both integers greater than 0, and twice the sum of a and b is equal to m. The first test circuit comprises: a first test transistor, a second test transistor, and a third test transistor; a gate of the first test transistor is connected to a first test control line, a first electrode of the first test transistor is connected to a first test data line, a gate of the second test transistor is connected to a second test control line, a first electrode of the second test transistor is connected to a second test data line, a second electrode of the first test transistor and a second electrode of the second test transistor are connected to the same data lead-out line; a gate of the third test transistor is connected to a third test control line, and a first electrode of the third test transistor is connected to a third test data line. The second test circuit comprises: a fourth test transistor, a fifth test transistor, and a sixth test transistor; a gate of the fourth test transistor is connected to the second test control line, a first electrode of the fourth test transistor is connected to the first test data line, a gate of the fifth test transistor is connected to the first test control line, a first electrode of the fifth test transistor is connected to the second test data line, a second electrode of the fourth test transistor and a second electrode of the fifth test transistor are connected to the same data lead-out line; a gate of the sixth test transistor is connected to the third test control line, and a first electrode of the third test transistor is connected to the third test data line; a second electrode of the first test transistor, a second electrode of the third test transistor, a second electrode of the fourth test transistor, and a second electrode of the sixth test transistor are connected to different data lead-out lines.

[0031] In some example embodiments, the first test transistor, the second test transistor and the third test transistor of the first test circuit are arranged along the first direction; the fourth test transistor, the fifth test transistor and the sixth test transistor of the second test circuit are arranged along the first direction. The first test transistor and the fourth test transistor are arranged in alignment in the second direction, the second test transistor and the fifth test transistor are arranged in alignment in the second direction, and the third test transistor and the sixth test transistor are arranged in alignment in the second direction.

[0032] In some example embodiments, m is 8. Each group of test circuits comprises two first test circuits and two second test circuits; wherein one first test circuit, two second test circuits and one first test circuit are arranged along the second direction.

[0033] In some example embodiments, m is 12. Each group of test circuits comprises three first test circuits and three second test circuits; wherein one first test circuit, two second test circuits, two first test circuits and one second test circuit are arranged along the second direction; or one first test circuit, one second test circuit, one first test circuit, two second test circuits and one first test circuit are arranged along the reverse direction of the second direction.

[0034] In some example embodiments, m is 16. Each group of test circuits comprises four first test circuits and four second test circuits; wherein one first test circuit, two second test circuits, one first test circuit, one second test circuit, two first test circuits and one second test circuit are arranged along the second direction; or one first test circuit, one second test circuit, one first test circuit, two second test circuits, one first test circuit, one second test circuit and one first test circuit are arranged along the reverse direction of the second direction.

[0035] In some example embodiments, m is 20. Each group of test circuits comprises five first test circuits and five second test circuits; wherein one first test circuit, two second test circuits, one first test circuit, one second test circuit, one first test circuit, one second test circuit, two first test circuits and one second test circuit are arranged along the second direction; or one first test circuit, one second test circuit, one first test circuit, one second test circuit, one first test circuit, two second test circuits, one first test circuit, one second test circuit and one first test circuit are arranged along the reverse direction of the second direction.

[0036] Other aspects can become apparent upon reading the following detailed description and upon understanding the appended claims.

[0037] SUMMARY

[0038] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute a part of the specification, and together with the embodiments of the present disclosure serve to explain the technical solutions of the present disclosure, but do not constitute a limitation on the technical solutions of the present disclosure.

[0039] FIG. 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0040] FIG. 2 is a schematic diagram of a first bezel area according to at least one embodiment of the present disclosure;

[0041] FIG. 3A is a schematic diagram of a partial cross section of a display area according to at least one embodiment of the present disclosure;

[0042] FIG. 3B is another schematic diagram of a partial cross section of a display area according to at least one embodiment of the present disclosure;

[0043] FIG. 4 is a schematic diagram of an arrangement of a sub-pixel of a display area according to at least one embodiment of the present disclosure;

[0044] FIG. 5 is a schematic diagram of a partial wiring of a first bezel area according to at least one embodiment of the present disclosure;

[0045] FIG. 6 is a schematic diagram of a plurality of groups of first-side first switching units according to at least one embodiment of the present disclosure;

[0046] FIG. 7A is a schematic diagram of a first gate metal layer and a second gate metal layer in FIG. 6;

[0047] FIG. 7B is a schematic diagram of a first source-drain metal layer in FIG. 6;

[0048] FIG. 7C is a schematic diagram of a second source-drain metal layer in FIG. 6;

[0049] FIG. 8 is a schematic diagram of a partial cross section along a direction Q-Q' in FIG. 6;

[0050] FIGS. 9A and 9B are schematic diagrams of an insertion order principle of a data signal transmitted by a second connection end of a group of first-side first switching units shown in FIG. 6;

[0051] FIG. 10 is a schematic diagram of a plurality of groups of second-side first switching units according to at least one embodiment of the present disclosure;

[0052] FIG. 11 is a schematic diagram of an insertion order principle of a data signal transmitted by a second connection end of a group of second-side first switching units shown in FIG. 10;

[0053] FIG. 12 is a schematic diagram of a group of first-side second switching units according to at least one embodiment of the present disclosure;

[0054] FIG. 13 is an equivalent circuit diagram of the first test circuit and the second test circuit according to at least one embodiment of the present disclosure;

[0055] FIG. 14A is a plan view of a first set of test circuits according to at least one embodiment of the present disclosure;

[0056] FIG. 14B is a schematic diagram of the first source / drain metal layer in FIG. 14A;

[0057] FIG. 14C is a schematic diagram of the first semiconductor layer, the first gate metal layer, and the second gate metal layer in FIG. 14A;

[0058] FIG. 15 is an equivalent circuit diagram of a third test circuit according to at least one embodiment of the present disclosure;

[0059] FIG. 16 is another schematic diagram of a first set of first side first switch units according to at least one embodiment of the present disclosure;

[0060] FIG. 17 is a schematic diagram of the first gate metal layer and the second gate metal layer in FIG. 16;

[0061] FIG. 18 is a schematic diagram of the insertion order of data signals transmitted by the second connection ends of the first set of first side first switch units in FIG. 16;

[0062] FIG. 19 is a schematic diagram of a first set of first side second switch units according to at least one embodiment of the present disclosure;

[0063] FIG. 20 is a plan view of a first set of test circuits according to at least one embodiment of the present disclosure;

[0064] FIG. 21 is a schematic diagram of a first set of second side first switch units according to at least one embodiment of the present disclosure;

[0065] FIG. 22 is a schematic diagram of the insertion order of data signals transmitted by the second connection ends of the first set of second side first switch units in FIG. 21;

[0066] FIG. 23 is a plan view of a second set of test circuits according to at least one embodiment of the present disclosure;

[0067] FIG. 24 is another schematic diagram of a first set of first side first switch units according to at least one embodiment of the present disclosure;

[0068] FIG. 25 is a schematic diagram of the insertion order of data signals transmitted by the second connection ends of the first set of first side first switch units in FIG. 24;

[0069] FIG. 26 is a plan view of a first set of test circuits corresponding to the first set of first side first switch units in FIG. 24 according to at least one embodiment of the present disclosure;

[0070] FIG. 27 is a schematic diagram of a first set of second side first switch units according to at least one embodiment of the present disclosure;

[0071] FIG. 28 is a schematic diagram of the insertion order of data signals transmitted by the second connection end of the second group of first adapter units shown in FIG. 27;

[0072] FIG. 29 is a plan view of a second group of test circuits according to at least one embodiment of the present disclosure;

[0073] FIG. 30 is another schematic diagram of a first group of first adapter units according to at least one embodiment of the present disclosure;

[0074] FIG. 31 is a schematic diagram of the insertion order of data signals transmitted by the second connection end of the first group of first adapter units shown in FIG. 30;

[0075] FIG. 32 is a plan view of a first group of test circuits corresponding to the first group of first adapter units shown in FIG. 30;

[0076] FIG. 33 is a schematic diagram of a second group of first adapter units according to at least one embodiment of the present disclosure;

[0077] FIG. 34 is a schematic diagram of the insertion order of data signals transmitted by the second connection end of the second group of first adapter units shown in FIG. 33;

[0078] FIG. 35 is a plan view of a second group of test circuits according to at least one embodiment of the present disclosure;

[0079] FIGS. 36A to 36C are schematic diagrams of connection manners of a plurality of first adapter units according to at least one embodiment of the present disclosure;

[0080] FIG. 37 is another schematic diagram of an arrangement of sub-pixels of a display area according to at least one embodiment of the present disclosure;

[0081] FIGS. 38A to 38F are schematic diagrams of connection manners of a plurality of first adapter units according to at least one embodiment of the present disclosure;

[0082] FIG. 39 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0083] DETAILED DESCRIPTION

[0084] Embodiments of the present disclosure will be described below in detail with reference to the accompanying drawings. Embodiments can be implemented in various forms. It would be easily understood by those skilled in the art that the embodiments and the contents can be changed into other forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the contents described in the following embodiments. Embodiments in the present disclosure and features in the embodiments can be arbitrarily combined with each other without conflict.

[0085] In the drawings, the size, the thickness, or the region of one or a plurality of components is sometimes exaggerated, and thus, the present disclosure is not necessarily limited to the size, the shape, and the relative arrangement of the components illustrated in the drawings. In addition, the drawings are schematically illustrate ideal examples, and the present disclosure is not limited to the shape or the numerical value illustrated in the drawings.

[0086] The ordinal numbers, such as "first", "second", and "third", are used for the purpose of avoiding ambiguity, and do not necessarily limit the number or the order of the components. The "plurality" in the present disclosure indicates two or more.

[0087] In the present specification, the words "over", "above", "under", "below", "front", "back", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like used to describe the positional relationship of components are used for the purpose of facilitating the description of the present specification and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be construed as limiting the present disclosure. The positional relationship of the components is appropriately changed according to the direction of the components described. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0088] In the present specification, unless explicitly defined and limited otherwise, the terms "mount", "connected", "connected" should be broadly understood. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or connected; it can be directly connected, or indirectly connected through an intermediate piece, or communication between two elements. The above terms in the present disclosure can be understood according to the situation by those skilled in the art. Among them, "connected" can include "electrically connected", and "electrically connected" can include the case where the components are connected together through elements having certain electrical effects. The "element having certain electrical effects" is not particularly limited as long as it can transmit electrical signals between the connected components. Examples of "elements having certain electrical effects" include not only electrodes and wires, but also switching elements such as transistors, resistors, inductors, capacitors, other elements with multiple functions, and the like.

[0089] In the present specification, a transistor refers to an element including at least a gate (gate electrode), a drain, and a source. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In the present specification, the channel region refers to a region where current mainly flows.

[0090] In this specification, the first electrode can be a drain electrode, the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. In addition, the gate electrode can also be referred to as a control electrode. The functions of the "source" and "drain" are sometimes interchanged with each other in the case of using a transistor whose polarity is reversed or in the case where the direction of current flowing in a circuit is changed, and the like. Therefore, the "source" and "drain" can be interchanged with each other in this specification.

[0091] In this specification, "parallel" means a state where an angle formed by two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus, a state where the angle is greater than or equal to -5° and less than or equal to 5° is also included. In addition, "perpendicular" means a state where an angle formed by two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus, a state where the angle is greater than or equal to 85° and less than or equal to 95° is also included.

[0092] In this specification, a circle, an ellipse, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not strictly a circle, an ellipse, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, and can be an approximate circle, an approximate ellipse, an approximate triangle, an approximate rectangle, an approximate trapezoid, an approximate pentagon, or an approximate hexagon, and can include some small deformations due to a tolerance, such as a fillet, a rounded corner, and a deformation.

[0093] In this specification, "approximately" and "substantially" mean that a limit is not strictly defined and a range of process and measurement errors is allowed. In this specification, "the same" includes a case where a value is different by 10 % or less, such as a case where a value is different by 5 % or less.

[0094] In this specification, A extends along a direction of B means that A can include a main portion and a sub portion connected to the main portion, the main portion is a line, a line segment, or a bar-shaped body, the main portion extends along the direction of B, and a length by which the main portion extends along the direction of B is longer than a length by which the sub portion extends along another direction. In this specification, "A extends along a direction of B" means "a main portion of A extends along a direction of B".

[0095] In this specification, "A and B are in the same layer" means that A and B are formed at the same time by one photolithography process. The "same layer" does not always mean that the thicknesses or the heights of layers are the same in a cross-sectional view. "A orthographic projection contains B orthographic projection" means that the orthographic projection of B falls within the orthographic projection of A or the orthographic projection of A covers the orthographic projection of B.

[0096] FIG. 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 1, the display substrate can be a closed polygon including linear sides. The display substrate can include a display area AA and a bezel area BB located around the display area AA. For example, the display area AA can include a first display side (a lower display side) and a second display side (an upper display side) oppositely arranged in a first direction D1, and a third display side (a left display side) and a fourth display side (a right display side) oppositely arranged in a second direction D2. The first display side and the second display side can be linear sides parallel to each other, and the third display side and the fourth display side can be linear sides parallel to each other. Adjacent linear sides can be connected by a curved side (e.g., an arc-shaped side).

[0097] In some examples, as shown in FIG. 1, the bezel area BB can include a first bezel area B1 and a fourth bezel area B4 located on both sides of the display area AA along the first direction D1, and a second bezel area B2 and a third bezel area B3 located on both sides of the display area AA along the second direction D2. The first bezel area B1 can be connected to the first display side, the second bezel area B2 can be connected to the third display side, the third bezel area B3 can be connected to the fourth display side, and the fourth bezel area B4 can be connected to the second display side. The first bezel area B1 can be in communication with the second bezel area B2 and the third bezel area B3, and the fourth bezel area B4 can be in communication with the second bezel area B2 and the third bezel area B3. After the first bezel area B1, the second bezel area B2, the third bezel area B3, and the fourth bezel area B4 are in communication, they can surround the display area AA. For example, the first bezel area B1 can also be referred to as a lower bezel area of the display substrate, the second bezel area B2 can also be referred to as a left bezel area of the display substrate, the third bezel area B3 can also be referred to as a right bezel area of the display substrate, and the fourth bezel area B4 can also be referred to as an upper bezel area of the display substrate. However, the present embodiment is not limited thereto.

[0098] FIG. 2 is a schematic diagram of a first bezel area according to at least one embodiment of the present disclosure. In some examples, as shown in FIGS. 1 and 2, the first bezel area B1 can include a first sub-area B11, a bending area B12, and a second sub-area B13 arranged in sequence along a side away from the display area AA in the first direction D1. The first sub-area B11 can also be referred to as a first fan-out area. The first sub-area B11 can be in communication with the second bezel area B2 and the third bezel area B3, and connected to the display area AA. The bending area B12 can be connected between the first sub-area B11 and the second sub-area B13. The bending area B12 can be configured to bend the second sub-area B13 to the back of the display area AA.

[0099] In some examples, as shown in FIG. 2, the second sub-region B13 of the first bezel region B1 can include, in sequence along a direction away from the bending region B12 in the first direction D1, a second fan-out region B131, a circuit arrangement region B132, a third fan-out region B133, a first signal access region B134, and a second signal access region B135. The first signal access region B134 can also be referred to as a trace lead-out region, which is located adjacent to the display region AA. The trace lead-out region of the present example can include the first sub-region B11, the bending region B12, the second fan-out region B131, the circuit arrangement region B132, and the third fan-out region B133. However, the present embodiment is not limited thereto.

[0100] In some examples, the circuit arrangement region B132 can be provided with a plurality of test circuits, which can be configured to provide test data signals to the data lines of the display region AA. In other examples, the circuit arrangement region can also be provided with a plurality of electrostatic discharge circuits, which can be configured to prevent electrostatic damage to the display substrate by eliminating static electricity. The present embodiment is not limited thereto.

[0101] In some examples, the first signal access region B134 can be provided with a plurality of first contact pads, which can be configured to connect an integrated circuit (IC). The second signal access region B135 can be provided with a plurality of second contact pads, which can be configured to be bonded to an external flexible printed circuit board (FPC). At least one of the first contact pads in the first signal access region B134 and at least one of the second contact pads in the second signal access region B135 can be connected by a trace.

[0102] In some examples, as shown in FIG. 1, the display region AA of the display substrate can include at least a plurality of sub-pixels PX, a plurality of gate lines GL, and a plurality of data lines (e.g., including a plurality of first data lines DLa and a plurality of second data lines DLb). The plurality of gate lines GL can extend along the second direction D2 and be arranged along the first direction D1; the plurality of data lines can extend along the first direction D1 and be arranged along the second direction D2, for example, the plurality of first data lines DLa can be located outside the plurality of second data lines DLb in the second direction D2. The plurality of data lines can be electrically connected to the plurality of sub-pixels PX, and can be configured to provide data signals to the plurality of sub-pixels PX. The plurality of gate lines GL can be electrically connected to the plurality of sub-pixels PX, and can be configured to provide pixel control signals to the plurality of sub-pixels PX. For example, the pixel control signals can include a scan signal, or can include a scan signal and a light-emitting control signal, or can include a scan signal, a reset control signal, and a light-emitting control signal.

[0103] In some examples, the second direction D2 can be an extension direction (e.g., a row direction) of the gate lines GL within the display region AA; the first direction D1 can be an extension direction (e.g., a column direction) of the data lines within the display region AA. The first direction D1 and the second direction D2 can cross each other, for example, can be perpendicular to each other.

[0104] In some examples, the display region AA can further be provided with a plurality of data connection lines 25. The first data line DLa can be connected with the first data lead-out line of the first sub-region B11 through the data connection line 25. The second data line DLb can directly extend to the first sub-region B11 and be connected with the first data lead-out line of the first sub-region B11. The data connection line 25 can include a first data connection segment 251 extending along the second direction D2 and a second data connection segment 252 extending along the first direction D1. The first data connection segment 251 can be connected between the first data line DLa and the second data connection segment 252, and the second data connection segment 252 can be connected with the first data lead-out line of the first sub-region B11. The second data connection segment 252 can be located on a side of the connected first data line DLa away from an edge of the display substrate. In some examples, the first data connection segment 251 and the second data connection segment 252 can be located on a side of the first data line DLa and the second data line DLb away from the substrate. However, the present embodiment is not limited thereto. By providing the data connection line in the display region, the first data lead-out line in the first sub-region is connected with the first data line through the data connection line, which can effectively reduce the length of the first sub-region along the first direction, thereby greatly reducing the size of the lower bezel.

[0105] In some examples, one pixel unit of the display region AA can include three sub-pixels, which can be a first sub-pixel emitting first color light (e.g., red light), a second sub-pixel emitting second color light (e.g., blue light), and a third sub-pixel emitting third color light (e.g., green light). However, the present embodiment is not limited thereto. In some examples, one pixel unit can include four sub-pixels, which can be a sub-pixel emitting red light, a sub-pixel emitting green light, a sub-pixel emitting blue light, and a sub-pixel emitting white light. For example, one pixel unit can include four sub-pixels, which can include a sub-pixel emitting red light, a sub-pixel emitting blue light, and two sub-pixels emitting green light.

[0106] In some examples, one sub-pixel can include a pixel circuit and a light emitting element electrically connected with the pixel circuit. The pixel circuit can include a plurality of transistors and at least one capacitor. For example, the pixel circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. Wherein, T in the above circuit structure refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the plurality of transistors in the pixel circuit can include P-type transistors and N-type transistors. In other examples, the plurality of transistors in the pixel circuit can be P-type transistors or can be N-type transistors, and the use of the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product.

[0107] In some examples, the shape of the light emitting element of the sub-pixel can be rectangular, rhombic, pentagonal or hexagonal. When one pixel unit includes three sub-pixels, the light emitting elements of the three sub-pixels can be arranged in a horizontal parallel, vertical parallel or triangular manner; when one pixel unit includes four sub-pixels, the light emitting elements of the four sub-pixels can be arranged in a horizontal parallel, vertical parallel or square manner. However, the present embodiment is not limited thereto.

[0108] In some examples, the light emitting element can be any one of a light emitting diode (LED), an organic light emitting diode (OLED), a quantum dot light emitting diode (QLED), a micro-LED (including: mini-LED or micro-LED), etc. For example, the light emitting element can be an OLED, and the light emitting element can emit red light, green light, blue light, white light, etc. under the driving of the corresponding pixel circuit. The color of the light emitted by the light emitting element can be determined as needed. In some examples, the light emitting element can include an anode, a cathode and an organic light emitting layer between the anode and the cathode. The anode of the light emitting element can be electrically connected with the corresponding pixel circuit. However, the present embodiment is not limited thereto.

[0109] FIG. 3A is a partial cross-sectional schematic view of a display area according to at least one embodiment of the present disclosure. In FIG. 3A, the structure of one sub-pixel of the display area is taken as an example for illustration. In the present example, the pixel circuit is taken as an example including a low-temperature polysilicon thin film transistor and an oxide thin film transistor for illustration.

[0110] In some examples, as shown in FIG. 3A, in a direction perpendicular to the display substrate, the display area of the display substrate can at least include: the substrate 10, and the circuit structure layer 12, the light-emitting structure layer 13 and the encapsulation structure layer 14 arranged on the substrate 10 in sequence. The circuit structure layer 12 can at least include: pixel circuits of a plurality of sub-pixels, each of which can include a plurality of transistors and at least one capacitor. The light-emitting structure layer 13 can at least include: light-emitting elements of a plurality of sub-pixels. In other examples, the display substrate can further include a touch structure layer located on the side of the encapsulation structure layer away from the substrate.

[0111] In some examples, FIG. 3A is shown by taking one first type transistor 21, one second type transistor 22 and one capacitor 23 included in each sub-pixel as an example. Among them, the first type transistor 21 can be a low-temperature polysilicon thin film transistor, and the second type transistor 22 can be an oxide thin film transistor.

[0112] In some examples, the circuit structure layer 12 of the display area can include a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, and a second source-drain metal layer disposed on the substrate 10. A first insulating layer 101 can be disposed between the first semiconductor layer and the first gate metal layer, a second insulating layer 102 can be disposed between the first gate metal layer and the second gate metal layer; a third insulating layer 103 can be disposed between the second gate metal layer and the second semiconductor layer; a fourth insulating layer 104 can be disposed between the second semiconductor layer and the third gate metal layer; a fifth insulating layer 105 can be disposed between the third gate metal layer and the first source-drain metal layer; a sixth insulating layer 106 (may also be referred to as a passivation layer) and a seventh insulating layer 107 (may also be referred to as a first planarization layer) can be disposed between the first source-drain metal layer and the second source-drain metal layer, the seventh insulating layer 107 can be located on a side of the sixth insulating layer 106 away from the substrate 10; an eighth insulating layer 108 (may also be referred to as a second planarization layer) can be disposed on a side of the second source-drain metal layer away from the substrate 10. Among them, the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, the fifth insulating layer 105, and the sixth insulating layer 106 can be inorganic insulating layers, and the seventh insulating layer 107 and the eighth insulating layer 108 can be organic insulating layers. However, the present embodiment is not limited thereto. In other examples, a buffer layer can also be disposed on a side of the first semiconductor layer close to the substrate, the buffer layer can prevent harmful substances in the substrate from invading the inside of the display substrate, and also can increase the adhesion of the film layers in the display substrate on the substrate. In other examples, a bottom shielding metal layer (BSM) can also be disposed on a side of the buffer layer close to the substrate, the bottom shielding metal layer can be configured to at least partially cover the active layer of the transistor of the pixel circuit to avoid the influence of external light on the performance of the transistor. In other examples, the sixth insulating layer can be omitted between the first source-drain metal layer and the second source-drain metal layer, and only the seventh insulating layer can be disposed between the first source-drain metal layer and the second source-drain metal layer.

[0113] In some examples, as shown in FIG. 3A, the first semiconductor layer of the display region can include at least: a first active layer 210 of a first type transistor 21. The first active layer 210 of the first type transistor 21 can include: a first region 2101, a second region 2102, and a channel region 2100 between the first region 2101 and the second region 2102. The first gate metal layer can include at least: a first gate 213 of the first type transistor 21, and a first plate 231 of a capacitor 23. The first gate 213 of the first type transistor 21 can cover the channel region 2100 of the first active layer 210 in the orthographic projection of the substrate 10. The second gate metal layer can include at least: a second plate 232 of the capacitor 23, and a third gate 224 of a second type transistor 22. The second plate 232 and the first plate 231 of the capacitor 23 can at least partially overlap in the orthographic projection of the substrate 10, for example, the two can coincide. The second semiconductor layer can include at least: a second active layer 220 of the second type transistor 22. The third gate metal layer can include at least: a second gate 223 of the second type transistor 22. The second gate 223 of the second type transistor 22 can partially overlap with the second active layer 220 in the orthographic projection of the substrate 10. The third gate 224 of the second type transistor 22 can partially overlap with the second active layer 220 in the orthographic projection of the substrate 10. The third gate 224 can be a bottom gate of the second type transistor 22, and the second gate 223 can be a top gate of the second type transistor 22.

[0114] In some examples, as shown in FIG. 3A, the first source-drain metal layer of the display area can at least include: the first source 211 and the first drain 212 of the first type transistor 21, the second source 221 and the second drain 222 of the second type transistor 22. The fifth insulating layer 105 can be provided with a plurality of pixel vias (for example, including a first pixel via, a second pixel via, a third pixel via, and a fourth pixel via) in the display area. The fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 in the first pixel via can be removed to expose at least part of the surface of the first region 2101 of the first active layer 210; the fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 in the second pixel via can be removed to expose at least part of the surface of the second region 2102 of the first active layer 210. The fifth insulating layer 105, the fourth insulating layer 104, and the third insulating layer 103 in the third pixel via and the fourth pixel via can be removed to expose at least part of the surface of both ends of the second active layer 220. The first source 211 of the first type transistor 21 can be electrically connected to the first region 2101 of the first active layer 210 through the first pixel via, and the first drain 212 can be electrically connected to the second region 2102 of the first active layer 210 through the second pixel via. The second source 221 of the second type transistor 22 can be electrically connected to one end of the second active layer 220 through the third pixel via, and the second drain 222 of the second type transistor 22 can be electrically connected to the other end of the second active layer 220 through the fourth pixel via. The second source-drain metal layer can at least include: the first transfer electrode 241. The first transfer electrode 241 can be electrically connected to the first drain 212 of the first type transistor 21 of the pixel circuit through the fifth pixel via provided by the sixth insulating layer 106 and the seventh insulating layer 107. The present example can realize electrical connection between the pixel circuit and the light-emitting element through the first transfer electrode 241.

[0115] In some examples, the gate lines of the display area can be located in the first gate metal layer and the third gate metal layer, for example, the data lines of the display area can be located in the second source-drain metal layer, the first power supply lines of the display area can be located in the second source-drain metal layer, the first data connection segment of the data connection lines of the display area can be located in the first source-drain metal layer, and the second data connection segment can be located in the second source-drain metal layer. The present embodiment is not limited thereto. In other examples, the circuit structure layer of the display area can further include: a third source-drain metal layer located on the side away from the substrate of the second source-drain metal layer, and the data connection lines can be located in the third source-drain metal layer.

[0116] In some examples, as shown in FIG. 3A, the light-emitting structure layer 13 can include a pixel definition layer 134 and a plurality of light-emitting elements. For example, each light-emitting element can include a first electrode 131, an organic light-emitting layer 132, and a second electrode 133 stacked. The first electrode 131 of the light-emitting element can be an anode, and the first electrode 131 can be electrically connected to the first transfer electrode 241 through a sixth pixel via hole of the eighth insulating layer 108 provided on the eighth insulating layer 108. The pixel definition layer 134 is provided on the first electrode 131 and the eighth insulating layer 108, and the pixel definition layer 134 can be provided with a plurality of pixel openings, and each pixel opening can expose at least part of the surface of the corresponding first electrode 131. At least part of the organic light-emitting layer 132 can be provided in one pixel opening and connected to the corresponding first electrode 131. The second electrode 133 can be provided on the organic light-emitting layer 132 and connected to the organic light-emitting layer 132. The organic light-emitting layer 132 can emit light of a corresponding color under the drive of the first electrode 131 and the second electrode 133.

[0117] In some examples, the organic light-emitting layer 132 of the light-emitting element can include an emitting layer (EML) and at least one of a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 131 and the second electrode 133, the organic light-emitting layer 132 can emit light according to the required gray scale by utilizing the light-emitting characteristics of the organic material.

[0118] In some examples, the light-emitting layers of the light-emitting elements of different colors can be different. For example, the red light-emitting element includes a red light-emitting layer, the green light-emitting element includes a green light-emitting layer, and the blue light-emitting element includes a blue light-emitting layer. In order to reduce the process difficulty and improve the yield, the hole injection layer and the hole transport layer located on one side of the light-emitting layer can adopt a common layer, and the electron injection layer and the electron transport layer located on the other side of the light-emitting layer can adopt a common layer. In some examples, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer can be made by one process (one evaporation process or one inkjet printing process), and isolation can be achieved by forming a film layer surface step difference or by surface treatment. For example, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be prepared by evaporation using a fine metal mask (FMM) or an open mask, or by using an inkjet process.

[0119] In some examples, as shown in FIG. 3A, the encapsulation structure layer 14 can include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 stacked. The first encapsulation layer 141 and the third encapsulation layer 143 can be made of inorganic materials, such as silicon nitride, silicon oxide, silicon oxynitride, etc. The inorganic materials have high compactness and can prevent the invasion of water, oxygen, etc. The second encapsulation layer 142 can be arranged between the first encapsulation layer 141 and the third encapsulation layer 143 to prevent external water vapor from entering the light-emitting element. The second encapsulation layer 142 can be made of organic materials, such as a high polymer material containing a desiccant or a high polymer material capable of blocking water vapor, etc., or a high polymer resin, etc. to perform a planarization process on the surface of the display substrate, and can relieve the stress of the first encapsulation layer 141 and the third encapsulation layer 143, and can also include a water-absorbing material such as a desiccant to absorb water, oxygen, etc. invading the inside. However, the present embodiment is not limited thereto. For example, the encapsulation structure layer can adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0120] FIG. 3B is another partial cross-sectional view of a display area according to at least one embodiment of the present disclosure. In some examples, the transistor types of the plurality of pixel transistors in the pixel circuit can be the same, for example, they can all be low-temperature polysilicon thin film transistors. In FIG. 3B, a first type of transistor 21 and a capacitor 23 included in each sub-pixel are taken as an example for illustration.

[0121] In some examples, as shown in FIG. 3B, the circuit structure layer 12 of the display area can include a first semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer disposed on the substrate 10. A first insulating layer 101 can be disposed between the first semiconductor layer and the first gate metal layer, a second insulating layer 102 can be disposed between the first gate metal layer and the second gate metal layer, a third insulating layer 103 can be disposed between the second gate metal layer and the first source-drain metal layer, a sixth insulating layer 106 and a seventh insulating layer 107 can be disposed between the first source-drain metal layer and the second source-drain metal layer, and an eighth insulating layer 108 can be disposed on a side of the second source-drain metal layer away from the substrate 10. The seventh insulating layer 107 and the eighth insulating layer 108 can be organic insulating layers, and the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103 can be inorganic insulating layers. The remaining structures of the display area of the display substrate of the present example can be referred to the description of the embodiment shown in FIG. 3A, and thus will not be described here.

[0122] With the wide application of OLED display technology, consumers have higher requirements for OLED display products, and high-resolution (PPI) display products and narrow-frame display products have become new trends in the development of display products. In order to realize a narrow frame, by arranging a data connection line in the display area, the data lead-out line in the first frame area can be connected to the first data line through the data connection line, which can effectively reduce the length of the first sub-area, thereby greatly reducing the size of the lower frame. However, in the process of connecting the first data line through the data connection line, the order of the data lead-out line in the first frame area will be disturbed, so that the order of the data lead-out line in the first frame area is different from the order of the data line in the display area. In some implementations, in order to be compatible with conventional integrated circuits, a jumper design needs to be performed in the first frame area (for example, the second fan-out area), so that the data signal transmitted by the data contact pad of the first signal access area is the same as the order of the data line of the display area. However, the jumper arranged in the second fan-out area is easy to cause various malfunctions: for example, part of the jumpers in the second fan-out area will overlap with other data lead-out lines or power lines, thereby easily causing problems such as load mutation of the data signal, difficulty in resistance compensation, and the like; for example, due to the space limitation of the second fan-out area, the wiring of the jumpers in the second fan-out area is dense and the gap is small, which is easy to have metal material etching residue (Remain), thereby causing a short circuit (Short) of the wire.

[0123] The embodiment provides a display substrate, which comprises a substrate, a plurality of sub-pixels, a plurality of first data lines, a plurality of second data lines, a plurality of data connection lines, a plurality of data lead-out lines, a plurality of data contact pads, a plurality of first switching units and a plurality of second switching units. The substrate comprises a display area and a first frame area located on one side of the display area along a first direction, and the first frame area comprises a first signal access area and a wire lead-out area located between the first signal access area and the display area. The plurality of sub-pixels are arranged on one side of the substrate and located in the display area. The plurality of first data lines, the plurality of second data lines and the plurality of data connection lines are located in the display area; the plurality of first data lines and the plurality of second data lines are configured to provide data signals for the plurality of sub-pixels, and the plurality of first data lines are connected with the plurality of data connection lines. The plurality of data lead-out lines are located in the wire lead-out area. The plurality of data contact pads are located in the first signal access area. The plurality of first switching units and the plurality of second switching units are located in the wire lead-out area, the plurality of first switching units are located on one side of the plurality of second switching units away from the display area, the plurality of first switching units are arranged along a second direction, and the plurality of second switching units are arranged along the second direction. The second direction intersects the first direction, for example, the second direction can be perpendicular to the first direction. The plurality of data lead-out lines are connected with the plurality of data contact pads through the plurality of first switching units, and are connected with the plurality of second data lines and the plurality of data connection lines through the plurality of second switching units, so that the order of the data signals provided by the plurality of data contact pads matches the order of the data signals required by the plurality of second data lines and the plurality of data connection lines arranged along the second direction.

[0124] The display substrate provided by the embodiment can connect the plurality of data lead-out lines and the plurality of data contact pads through the plurality of first switching units, and connect the plurality of data lead-out lines with the plurality of second data lines and the plurality of data connection lines through the plurality of second switching units, so that the order of the data signals transmitted by the plurality of data contact pads matches the order of the data signals required by the plurality of second data lines and the plurality of data connection lines, the jumper design in the second fan-out area can be avoided, the adverse effects caused by the jumper design can be reduced, and the reliability of the display substrate is improved.

[0125] In some examples, the order of the data signals provided by the plurality of data contact pads can adapt to the arrangement order of the second data lines and the data connection lines in the display area. The data signals provided by the plurality of data contact pads have a first order, the order of the data signals changes after passing through the plurality of first switching units, for example, has a second order, and the order of the data signals changes again after passing through the plurality of second switching units, for example, returns to the first order, so that the second data lines and the data connection lines in the display area can receive the required data signals.

[0126] In some example embodiments, each group of the first transfer units comprises m first connection ends, m second connection ends, and m first transfer lines; each first transfer line is connected between one first connection end and one second connection end; each first connection end is connected with one data lead-out line, and each second connection end is connected with one data contact pad; the m first connection ends are arranged along the second direction and correspond to different first arrangement serial numbers, and the m second connection ends are arranged along the second direction and correspond to different second arrangement serial numbers. The m first transfer lines in each group of the first transfer units comprise a first insertion sequence transfer line, the first arrangement serial number corresponding to the first connection end connected by each first insertion sequence transfer line is different from the second arrangement serial number corresponding to the second connection end connected by each first insertion sequence transfer line; wherein m and a are both integers greater than 1, and m is greater than or equal to a. In some examples, one first transfer unit can comprise a first connection end, a first transfer line, and a second connection end connected in sequence, and one first transfer unit can realize the transmission of one-way data signals between the data contact pad and the data lead-out line. In some examples, one second transfer unit can comprise a second transfer line, and one second transfer unit can realize the transmission of one-way data signals between the data lead-out line and the second data line or the data connection line. The display substrate provided in the present embodiment can connect multiple data lead-out lines and multiple data contact pads by multiple groups of first transfer units, and the order of the data signals transmitted by the data contact pads can be adjusted by the multiple groups of first transfer units. In combination with the adjustment of the order of the data signals by the multiple groups of second transfer units, the jumper design in the second fan-out area can be avoided, which is beneficial to reducing the defects caused by the jumper design, thereby improving the reliability of the display substrate.

[0127] In some example embodiments, a single pixel unit of the display area can comprise c sub-pixels, and m is a k multiple of c, wherein k is an integer greater than 1. For example, one pixel unit comprises four sub-pixels, and m can be an integer multiple of 4, such as 8, 12, 16, or 20; one pixel unit comprises three sub-pixels, and m can be an integer multiple of 3, such as 6, 9, 12, or 15.

[0128] In some example embodiments, the a plug-in order adapter lines in each group of the first adapter units can include a1 first plug-in order adapter lines and a2 second plug-in order adapter lines, a1 and a2 are integers greater than 0, and the sum of a1 and a2 is a. The first arrangement serial number corresponding to the first connection end connected by the first plug-in order adapter line is less than the second arrangement serial number corresponding to the second connection end connected by the first plug-in order adapter line. The first arrangement serial number corresponding to the first connection end connected by the second plug-in order adapter line is greater than the second arrangement serial number corresponding to the second connection end connected by the second plug-in order adapter line. In some examples, the difference between the second arrangement serial number corresponding to the second connection end connected by the first plug-in order adapter line and the first arrangement serial number corresponding to the first connection end connected by the first plug-in order adapter line can be greater than or equal to the difference between the first arrangement serial number corresponding to the first connection end connected by the second plug-in order adapter line and the second arrangement serial number corresponding to the second connection end connected by the second plug-in order adapter line. The present example adjusts the transmission order of the data signal by arranging the first plug-in order adapter line and the second plug-in order adapter line in each group of the first adapter units, which can avoid the jumper design in the second fan-out area, is conducive to reducing the adverse effects caused by the jumper design, and thus improves the reliability of the display substrate.

[0129] In some example embodiments, the m first adapter lines in each group of the first adapter units can further include b first order adapter lines, the first arrangement serial number corresponding to the first connection end connected by each first order adapter line is the same as the second arrangement serial number corresponding to the second connection end connected by the first order adapter line, b is an integer greater than 1, and b is less than or equal to a. In some examples, the b order adapter lines and the first plug-in order adapter line can be a same layer structure, or at least one first order adapter line can be located on the side of the first plug-in order adapter line and the second plug-in order adapter line close to the substrate. The present example adjusts the transmission order of the data signal by using the cooperation of the first order adapter line and the plug-in order adapter line in each group of the first adapter units, which can avoid the jumper design in the second fan-out area, is conducive to reducing the adverse effects caused by the jumper design, and thus improves the reliability of the display substrate.

[0130] In some example embodiments, m can be 8, each group of the first adapter units can include two first plug-in order adapter lines, two second plug-in order adapter lines, and four first order adapter lines. The first plug-in order adapter line can be configured to connect the i th first connection end and the i+1 th second connection end. The second plug-in order adapter line can be configured to connect the i+1 th first connection end and the i th second connection end. The value of i can include 1 and 5.

[0131] In some example embodiments, m can be 12, each group of first adapter units can include four first plug order adapter lines, four second plug order adapter lines, and four first order adapter lines. The first plug order adapter line can be configured to connect the ith first connection end and the (i+1)th second connection end; the second plug order adapter line can be configured to connect the (i+1)th first connection end and the ith second connection end; wherein the value of i can include 1, 3, 7, 9.

[0132] In some example embodiments, m can be 16, each group of first adapter units can include four first plug order adapter lines, four second plug order adapter lines, and eight first order adapter lines. The first plug order adapter line can be configured to connect the ith first connection end and the (i+1)th second connection end; the second plug order adapter line can be configured to connect the (i+1)th first connection end and the ith second connection end; wherein the value of i can include 1, 3, 9, 11.

[0133] In some example embodiments, m can be 20, each group of first adapter units can include six first plug order adapter lines, six second plug order adapter lines, and eight first order adapter lines. The first plug order adapter line can be configured to connect the ith first connection end and the (i+1)th second connection end; the second plug order adapter line can be configured to connect the (i+1)th first connection end and the ith second connection end; wherein the value of i can include 1, 3, 5, 11, 13, 15.

[0134] In some example embodiments, a pixel unit located in the display area includes: a first sub-pixel emitting first color light, a second sub-pixel emitting second color light, and two third sub-pixels emitting third color light. The plurality of data lead-out lines connected with the first connection ends of the plurality of groups of first adapter units can include: a first group of data lead-out lines and a second group of data lead-out lines, the first group of data lead-out lines and the second group of data lead-out lines are located in different conductive layers and are alternately arranged along the second direction, the first group of data lead-out lines are configured to transmit data signals required by the third sub-pixels, and the second group of data lead-out lines are configured to transmit data signals required by the first sub-pixels and the second sub-pixels. For example, the data signals corresponding to the third sub-pixels (such as green sub-pixels G) can be transmitted by the data lead-out lines located in the first gate metal layer, and the data signals corresponding to the first sub-pixels (such as red sub-pixels R) and the second sub-pixels (such as blue sub-pixels B) can be transmitted by the data lead-out lines located in the second gate metal layer, which can ensure the uniform arrangement of signal transmission traces and avoid the arrangement of data lead-out lines transmitting data signals corresponding to the third sub-pixels in different conductive layers, thereby causing load differences and affecting display effects.

[0135] In some example embodiments, the display substrate can further include a plurality of groups of test circuits arranged in the second direction in the trace lead-out area. The plurality of groups of test circuits can be located on a side of the plurality of groups of first conversion units away from the first signal access area in the first direction. Each group of test circuits can be connected to m data lead-out lines connected to a group of first conversion units. Each group of test circuits can include a first test circuit and a second test circuit, and the sum of a and b is twice m, where a and b are integers greater than 0. The first test circuit can include a first test transistor, a second test transistor, and a third test transistor. The gate of the first test transistor can be connected to a first test control line, the first electrode of the first test transistor can be connected to a first test data line, the gate of the second test transistor can be connected to a second test control line, the first electrode of the second test transistor can be connected to a second test data line, and the second electrode of the first test transistor and the second electrode of the second test transistor can be connected to the same data lead-out line. The gate of the third test transistor can be connected to a third test control line, and the first electrode of the third test transistor can be connected to a third test data line. The second test circuit can include a fourth test transistor, a fifth test transistor, and a sixth test transistor. The gate of the fourth test transistor can be connected to the second test control line, the first electrode of the fourth test transistor can be connected to the first test data line, the gate of the fifth test transistor can be connected to the first test control line, the first electrode of the fifth test transistor can be connected to the second test data line, and the second electrode of the fourth test transistor and the second electrode of the fifth test transistor can be connected to the same data lead-out line. The gate of the sixth test transistor can be connected to the third test control line, and the first electrode of the third test transistor can be connected to the third test data line. The second electrode of the first test transistor, the second electrode of the third test transistor, the second electrode of the fourth test transistor, and the second electrode of the sixth test transistor can be connected to different data lead-out lines. By arranging a plurality of groups of test circuits, the transmission order of test data signals can be adjusted, jumper design in the second fan-out area can be avoided, and the display substrate reliability can be improved.

[0136] The scheme of the present embodiment is illustrated below by some examples.

[0137] FIG. 4 is a schematic diagram of an arrangement of sub-pixels of a display area according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 4, each pixel unit of the display area can include a first sub-pixel 15 emitting a first color light, a second sub-pixel 16 emitting a second color light, and two third sub-pixels 17a and 17b emitting a third color light. A plurality of pixel units can be arranged in an array in the display area AA. Pixel circuits of the plurality of sub-pixels can be arranged in an array along a first direction D1 and a second direction D2. In a single pixel unit, light emitting elements of the four sub-pixels can be arranged in different columns along the second direction D2, light emitting elements of the first sub-pixel 15 and the second sub-pixel 16 can be arranged in a same row, and light emitting elements of the two third sub-pixels 17a and 17b can be arranged in a same row. The row in which the light emitting elements of the first sub-pixel 15 and the third sub-pixel 17a are arranged can be spaced apart from the row in which the light emitting elements of the second sub-pixel 16 and the third sub-pixel 17b are arranged along the first direction D1. In the present example, the first sub-pixel 15 can be a red sub-pixel (R), the second sub-pixel 16 can be a blue sub-pixel (B), and the third sub-pixels 17a and 17b can be green sub-pixels (G), such as the first third sub-pixel 17a being a first green sub-pixel (G1) and the second third sub-pixel 17b being a second green sub-pixel (G2).

[0138] In some examples, as shown in FIG. 4, the plurality of pixel units arranged along the second direction D2 can be a row of pixel units, and the plurality of pixel units arranged along the first direction D1 can be a column of pixel units. The plurality of pixel units can include a plurality of first pixel units and a plurality of second pixel units, and the arrangement order of the four sub-pixels in the first pixel units and the second pixel units can be different. For example, the e-th row of pixel units can include a plurality of first pixel units arranged along the second direction D2 in sequence, and the first sub-pixel 15, the third sub-pixel 17a, the second sub-pixel 16, and the third sub-pixel 17b of the first pixel units can be arranged along the second direction D2 in sequence. The (e+1)-th row of pixel units can include a plurality of second pixel units arranged along the second direction D2 in sequence, and the second sub-pixel 16, the third sub-pixel 17b, the first sub-pixel 15, and the third sub-pixel 17a of the second pixel units can be arranged along the second direction D2 in sequence. A column of pixel units can include first pixel units and second pixel units arranged alternately along the first direction D1. Wherein, e can be an integer greater than 0. For example, the sub-pixels of the odd-numbered rows of pixel units in the display area can adopt the arrangement manner of RG1BG2, and the sub-pixels of the even-numbered rows of pixel units can adopt the arrangement manner of BG2RG1; or the sub-pixels of the odd-numbered rows of pixel units in the display area can adopt the arrangement manner of BG2RG1, and the sub-pixels of the even-numbered rows of pixel units can adopt the arrangement manner of RG1BG2.

[0139] In some examples, the plurality of sub-pixels arranged along the first direction D1 can be a column of sub-pixels. The jth column of sub-pixels can include the first sub-pixels 15 and the second sub-pixels 16 arranged alternately along the first direction D1. The (j+1)th column of sub-pixels can include the third sub-pixels 17a and 17b arranged alternately along the first direction D1. j can be an integer greater than 1. The pixel circuits of each column of sub-pixels can be connected to the same data line. For example, the jth column of sub-pixels can be connected to the data line DLj, and the (j+1)th column of sub-pixels can be connected to the data line DLj+1.

[0140] FIG. 5 is a schematic diagram of partial wirings of a first border area according to at least one embodiment of the present disclosure. In FIG. 5, only data lead-out lines of the first border area are shown, and the remaining wirings of the first border area are omitted.

[0141] In some examples, as shown in FIG. 5, the first sub-area B11 can be provided with a plurality of first data lead-out lines 261, which can be configured to connect the plurality of second data lines DLb and the plurality of data connection lines 25 of the display area AA in a fan-out wiring manner. The plurality of first data lead-out lines 261 can be electrically connected to the plurality of second data lines DLb and the plurality of data connection lines 25 one by one. For example, the plurality of first data lead-out lines 261 can be arranged alternately in the first gate metal layer and the second gate metal layer.

[0142] In some examples, the bending area B12 can be provided with a plurality of data bending connection lines 264. The plurality of data bending connection lines 264 can be electrically connected to the plurality of first data lead-out lines 261 one by one. For example, the plurality of data bending connection lines 264 can be located in the second source-drain metal layer. However, the present embodiment is not limited thereto. In other examples, the plurality of data bending connection lines of the bending area can be located in the first source-drain metal layer.

[0143] In some examples, the second fan-out area B131 can be provided with a plurality of second data lead-out lines 262. The plurality of second data lead-out lines 262 can be electrically connected to the plurality of data bending connection lines 264 one by one. For example, the plurality of second data lead-out lines 262 can be arranged alternately in the first gate metal layer and the second gate metal layer.

[0144] In some examples, the third fan-out area B133 can be provided with a plurality of third data lead-out lines 263. The plurality of third data lead-out lines 263 can be connected to the plurality of second data lead-out lines 262, for example, electrically connected one by one. For example, the plurality of third data lead-out lines 263 can be arranged alternately in the first gate metal layer and the second gate metal layer.

[0145] In the present example, the trace leading-out area can include a first sub-area B11, a bending area B12, a second fan-out area B131, a circuit setting area B132, and a third fan-out area B133. One data leading-out line located in the trace leading-out area can include a first data leading-out line 261, a data bending connection line 264, a second data leading-out line 262, and a third data leading-out line 263 connected in sequence.

[0146] In some examples, the circuit setting area B132 can be provided with a plurality of test circuits, and the plurality of third data leading-out lines 263 can be electrically connected with the plurality of test circuits. In a test stage of the display substrate, the plurality of test circuits can be used to provide test data signals to the plurality of second data lines DLb of the display area AA through the plurality of data leading-out lines (e.g., each data leading-out line includes the third data leading-out line 263, the second data leading-out line 262, the data bending connection line 264, and the first data leading-out line 261 connected in sequence), and the plurality of test circuits can also provide test data signals to the plurality of first data lines DLa through the plurality of data leading-out lines and the plurality of data connection lines 25 of the display area AA.

[0147] In some examples, the first signal access area B134 can be provided with a plurality of first contact pads, and the plurality of first contact pads can include a plurality of data contact pads 27. The plurality of data contact pads 27 can be configured to provide data signals. The plurality of data contact pads 27 can be arranged in a row along the second direction D2, and a plurality of rows (e.g., two rows or three rows) of data contact pads 27 can be arranged along the first direction D1. The plurality of data contact pads 27 can be connected with the plurality of third data leading-out lines 263, e.g., one-to-one electrical connection. In a normal display stage of the display substrate, the plurality of data contact pads 27 can provide data signals to the plurality of second data lines DLb of the display area AA through the plurality of data leading-out lines (e.g., each data leading-out line includes the third data leading-out line 263, the second data leading-out line 262, the data bending connection line 264, and the first data leading-out line 261 connected in sequence), and the plurality of data contact pads 27 can also provide data signals to the plurality of first data lines DLa through the plurality of data leading-out lines and the plurality of data connection lines 25 of the display area AA.

[0148] In some examples, as shown in FIG. 5, the first sub-region B11 can be provided with a plurality of groups of second transfer units, and the third fan-out region B133 can be provided with a plurality of groups of first transfer units. The plurality of groups of second transfer units can be arranged in sequence along the second direction D2 and located on a side of the plurality of first data lead-out lines 261 close to the display region AA. The plurality of first data lead-out lines 261 can be connected to the plurality of second data lines DLb and the plurality of data connection lines 25 of the display region AA through the plurality of groups of second transfer units. The plurality of groups of first transfer units can be arranged in sequence along the second direction D2 and located on a side of the plurality of third data lead-out lines 263 close to the first signal access region B134. The plurality of third data lead-out lines 263 can be connected to the plurality of data contact pads 27 in the first signal access region B134 through the plurality of groups of first transfer units.

[0149] In some examples, as shown in FIG. 5, the plurality of groups of first transfer units can include a plurality of groups of first side first transfer units 300a and a plurality of groups of second side first transfer units 300b. The plurality of groups of first side first transfer units 300a and the plurality of groups of second side first transfer units 300b can be located on both sides of the middle line of the first frame region B1 parallel to the first direction D1. For example, the plurality of groups of first side first transfer units 300a can be connected to the data lines of the left half region of the display region AA, and the plurality of groups of second side first transfer units 300b can be connected to the data lines of the right half region of the display region.

[0150] In some examples, the plurality of data contact pads 27 of the first signal access region B134 can include a first group of data contact pads and a second group of data contact pads. The first group of data contact pads and the second group of data contact pads can be arranged along the second direction D2. The first group of data contact pads can be connected to the plurality of third data lead-out lines 263 through the plurality of groups of first side first transfer units 300a, and the second group of data contact pads can be connected to the plurality of third data lead-out lines 263 through the plurality of groups of second side first transfer units 300b.

[0151] In some examples, as shown in FIG. 5, the plurality of groups of second transfer units can include a plurality of groups of first-side second transfer units 32a and a plurality of groups of second-side second transfer units 32b. The plurality of groups of first-side second transfer units 32a and the plurality of groups of second-side second transfer units 32b can be located on both sides of the middle line of the first bezel area B1 parallel to the first direction D1. For example, the plurality of groups of first-side second transfer units 32a can be connected with the second data lines and data connection lines of the left half of the display area AA, and the plurality of groups of second-side second transfer units 32b can be connected with the second data lines and data connection lines of the right half of the display area. In some examples, the plurality of groups of first-side second transfer units 32a can be connected with the plurality of groups of first-side first transfer units 300a through a plurality of data lead-out lines, and the plurality of groups of second-side second transfer units 32b can be connected with the plurality of groups of second-side first transfer units 300b through a plurality of data lead-out lines. For example, the number of groups of first-side second transfer units can be the same as the number of groups of first-side first transfer units, and the number of groups of second-side second transfer units can be the same as the number of groups of second-side first transfer units.

[0152] FIG. 6 is a schematic diagram of a plurality of groups of first-side first transfer units according to at least one embodiment of the present disclosure. In FIG. 6, two groups of first-side first transfer units are taken as an example for illustration. FIG. 7A is a schematic diagram of the first gate metal layer and the second gate metal layer in FIG. 6. FIG. 7B is a schematic diagram of the first source-drain metal layer in FIG. 6. FIG. 7C is a schematic diagram of the second source-drain metal layer in FIG. 6. FIG. 8 is a partial cross-sectional view along the direction Q-Q’ in FIG. 6. In the present example, the number m of first transfer lines included in each group of first transfer units can be 8.

[0153] In some examples, as shown in FIGS. 6-8, a group of first-side first transfer units 300a can include eight first connection ends 311, eight second connection ends 312, and eight first transfer lines. Within a group of first-side first transfer units 300a, the eight first connection ends 311 can be sequentially arranged along the second direction D2, for example, the first arrangement numbers of the eight first connection ends 311 sequentially arranged along the second direction D2 can correspond to 1-8. The eight first connection ends 311 can be connected one by one with eight continuously arranged third data lead-out lines (for example, including third data lead-out lines 263-1, 263-2, 263-3, 263-4, 263-5, 263-6, 263-7, and 263-8). Among them, the third data lead-out lines 263-1, 263-3, 263-5, and 263-7 can be located in the second gate metal layer, and the third data lead-out lines 263-2, 263-4, 263-6, and 263-8 can be located in the first gate metal layer. For example, as shown in FIG. 8, the third data lead-out lines located in the first gate metal layer can include third data lead-out lines 263a.

[0154] In some examples, the single first connection end 311 can include a first connection electrode 311-1 and a second connection electrode 311-2 located at different conductive layers. The first connection electrode 311-1 and the second connection electrode 311-2 can have a strip shape extending along the first direction D1 in the orthographic projection of the substrate. The length of the first connection electrode 311-1 along the first direction D1 can be greater than the length of the second connection electrode 311-2 along the first direction D1. For example, the first connection electrode 311-1 can be located at the first source-drain metal layer, and the second connection electrode 311-2 can be located at the second source-drain metal layer. For example, in the film layer structure of the display substrate shown in FIG. 3B, the first connection electrode 311-1 can be connected to the third data lead line located at the first gate metal layer through a plurality of vias formed in the third insulating layer 103 and the second insulating layer 102, or can be connected to the third data lead line located at the second gate metal layer through a plurality of vias formed in the third insulating layer 103. The second connection electrode 311-2 can be connected to the first connection electrode 311-1 through a plurality of vias formed in the seventh insulating layer 107 and the sixth insulating layer 106. The orthographic projection of the second connection electrode 311-2 on the substrate can not overlap with the orthographic projection of the third data lead line on the substrate, or can partially overlap. The present embodiment is not limited in this regard.

[0155] In some examples, within a group of first side first adapter units 300a, eight second connection ends 312 can be located on the side of the eight first connection ends 311 close to the first signal access area B134 in the first direction D1. The eight second connection ends 312 can be arranged in sequence along the second direction D2, for example, the second arrangement numbers of the eight second connection ends 312 arranged in sequence along the second direction D2 can correspond to 1 to 8. The eight second connection ends 312 and the eight first connection ends 311 can be arranged in alignment in the first direction D1. The eight second connection ends 312 can be connected one by one with the eight continuously arranged contact pad connection lines 265. The plurality of contact pad connection lines 265 can be located at the first gate metal layer. The plurality of contact pad connection lines 265 can be electrically connected one by one with the plurality of data contact pads 27 continuously arranged in the first signal access area B134.

[0156] In some examples, the single second connection end 312 can include a third connection electrode 312-1 and a fourth connection electrode 312-2 located at different conductive layers. The third connection electrode 312-1 and the fourth connection electrode 312-2 can have a strip shape in the orthographic projection of the substrate extending along the first direction D1. The third connection electrode 312-1 can have a length along the first direction D1 greater than a length of the fourth connection electrode 312-2 along the first direction D1. For example, the third connection electrode 312-1 can be located at the first source-drain metal layer, and the fourth connection electrode 312-2 can be located at the second source-drain metal layer. For example, in the film layer structure of the display substrate shown in FIG. 3B, the third connection electrode 312-1 can be connected to the contact pad connection line 265 located at the first gate metal layer through a plurality of vias formed in the third insulating layer 103 and the second insulating layer 102. The fourth connection electrode 312-2 can be connected to the third connection electrode 312-1 through a plurality of vias formed in the seventh insulating layer 107 and the sixth insulating layer 106. The orthographic projection of the fourth connection electrode 312-2 on the substrate can not overlap with the orthographic projection of the contact pad connection line 265 on the substrate, or can partially overlap. The present embodiment is not limited thereto.

[0157] In some examples, in a group of first side first switch units 300a, eight first switch lines can be located between eight first connection ends 311 and eight second connection ends 312. Each first switch line can be connected between one first connection end 311 and one second connection end 312. The eight first switch lines can include four first sequential switch lines 314, two first plug-in switch lines 313a, and two second plug-in switch lines 313b. In the present example, the eight first switch lines can include two first switch sequence changing units, each of which can include at least one first plug-in switch line (e.g., including one first plug-in switch line 313a) and at least one second plug-in switch line (e.g., including one second plug-in switch line 313b) having an overlap in the orthographic projection of the substrate. In the second direction D2, one first switch sequence changing unit, two first sequential switch lines 314, one first switch sequence changing unit, and two first sequential switch lines 314 can be arranged in sequence.

[0158] In some examples, the first sequential switch line 314 can have a strip shape in the orthographic projection of the substrate extending along the first direction D1. The first plug-in switch line 313a and the second plug-in switch line 313b can have a zigzag shape in the orthographic projection of the substrate extending along the first direction D1. One first switch sequence changing unit can have an X shape in the orthographic projection of the substrate. The present embodiment is not limited thereto.

[0159] In some examples, in a first side first adapter unit 300a in the group, in the second direction D2, a first first-order adapter line 313a can connect a first first connection end and a second second connection end; a first second-order adapter line 313b can connect a second first connection end and a first second connection end; a second first-order adapter line 313a can connect a fifth first connection end and a sixth second connection end; a second second-order adapter line 313b can connect a sixth first connection end and a fifth second connection end. A first first-order sequence adapter line 314 can connect a third first connection end and a third second connection end; a second first-order sequence adapter line 314 can connect a fourth first connection end and a fourth second connection end; a third first-order sequence adapter line 314 can connect a seventh first connection end and a seventh second connection end; a fourth first-order sequence adapter line 314 can connect an eighth first connection end and an eighth second connection end.

[0160] In some examples, a plurality of first-order sequence adapter lines 314 can be a same layer structure, for example, can be located in a second source-drain metal layer. For example, a first-order sequence adapter line 314, a second connection electrode 311-2 of a connected first connection end 311, and a fourth connection electrode 312-2 of a connected second connection end 312 can be an integrally connected structure.

[0161] In some examples, a first-order sequence adapter line 313a and a second-order sequence adapter line 313b can be located in different conductive layers. For example, a first-order sequence adapter line 313a can be located in a first source-drain metal layer, and a second-order sequence adapter line 313b can be located in a second source-drain metal layer. A first-order sequence adapter line 313a, a first connection electrode 311-1 of a connected first connection end 311, and a third connection electrode 312-1 of a connected second connection end 312 can be an integrally connected structure. A second-order sequence adapter line 313b, a second connection electrode 311-2 of a connected first connection end 311, and a fourth connection electrode 312-2 of a connected second connection end 312 can be an integrally connected structure.

[0162] FIGS. 9A and 9B are schematic diagrams of the insertion order of the data signals transmitted by the second connection end of the first group of first side first conversion units shown in FIG. 6. In some examples, as shown in FIGS. 9A and 9B, taking the eight data signals transmitted by the second connection end of the first group of first side first conversion units as an example, the sub-pixel arrangement of the display area is shown in FIG. 4. Each data signal can be configured to provide a data line for the display area. In this example, the order of the data lines that have not been adjusted by the insertion order corresponds to the arrangement order of the data lines of the display area; the first sub-pixel (for example, the red sub-pixel R) and the second sub-pixel (for example, the blue sub-pixel B) arranged in the same column are connected to the same data line, and the third sub-pixel (for example, including the first green sub-pixel G1 and the second green sub-pixel G2) arranged in the same column is connected to the same data line.

[0163] In some examples, as shown in FIGS. 9A and 9B, taking the eight data lines (for example, the nth-3th to nth+4th data lines) that have not been adjusted by the insertion order as an example, the eight data lines can be arranged along the second direction, and the data connection lines connected to the nth-3th to nth-1th data lines can be inserted between the nth+1th to nth+4th data lines in a 1-in-1 manner. For example, the data connection line connected to the nth-1th data line can be inserted between the nth+1th and nth+2th data lines, the data connection line connected to the nth-2th data line can be inserted between the nth+2th and nth+3th data lines, and the data connection line connected to the nth-3th data line can be inserted between the nth+3th and nth+4th data lines. The minimum cycle number of the data signals adjusted by the 1-in-1 manner is 8.

[0164] In some examples, as shown in FIG. 9A, taking the sub-pixel arrangement order of the pixel units in the odd-numbered rows in the display area as an example, the sub-pixel cycle corresponding to the eight data lines (the nth to nth+4th data lines after the insertion order adjustment) obtained by the 1-in-1 manner is: G2RBG1 G1BRG2. As shown in FIG. 9B, taking the sub-pixel arrangement order of the pixel units in the even-numbered rows in the display area as an example, the sub-pixel cycle corresponding to the eight data lines (the nth to nth+4th data lines after the insertion order adjustment) obtained by the 1-in-1 manner is: G1BRG2 G2RBG1.

[0165] In some examples, the first data lines in the display area are connected to the data leads of the first bezel area through the data connection lines, and thus the order of the data signals required by the plurality of data lines in the display area is different from the arrangement order of the plurality of data lines. According to the interleaving principle shown in FIGS. 9A and 9B, the plurality of data contact pads can provide the data signals satisfying the order of the plurality of second data lines and the plurality of data connection lines. Due to the different arrangement orders of the sub-pixels of the odd and even rows of pixel units in the display area, the plurality of data contact pads can provide the corresponding data signals to the sub-pixels of the odd and even rows of pixel units in different time periods. For example, the plurality of data contact pads can provide the corresponding data signals to G2RBG1 G1BRG2 in the second direction D2 according to the sub-pixel cyclic order in the first time period, to satisfy the data signals required by the odd rows of pixel units in the display area; and the plurality of data contact pads can provide the corresponding data signals to G1BRG2 G2RBG1 in the second direction D2 according to the sub-pixel cyclic order in the second time period, to satisfy the data signals required by the even rows of pixel units in the display area. In some examples, the plurality of data contact pads can sequentially provide the data signals to the plurality of rows of pixel units in the display area according to the cyclic order of the first time period and the second time period. For example, the plurality of data contact pads can provide the data signals to the sub-pixels of a row of pixel units (e.g., the first row of pixel units) in the display area in the first first time period, and provide the data signals to the sub-pixels of a row of pixel units (e.g., the second row of pixel units) in the display area in the first second time period; the plurality of data contact pads can provide the data signals to the sub-pixels of a row of pixel units (e.g., the third row of pixel units) in the display area in the second first time period, and provide the data signals to the sub-pixels of a row of pixel units (e.g., the fourth row of pixel units) in the display area in the second second time period, and so on, to provide the required data signals to the sub-pixels of the plurality of rows of pixel units in the display area, respectively.

[0166] In other examples, when the arrangement order of the sub-pixels of the even rows of pixel units in the display area is RG1BG2, and the arrangement order of the sub-pixels of the odd rows of pixel units in the display area is BG2RG1, the plurality of data contact pads can provide the corresponding data signals to G2RBG1 G1BRG2 in the second direction D2 according to the sub-pixel cyclic order in the first time period, to satisfy the data signals required by the even rows of pixel units in the display area; and the plurality of data contact pads can provide the corresponding data signals to G1BRG2 G2RBG1 in the second direction D2 according to the sub-pixel cyclic order in the second time period, to satisfy the data signals required by the odd rows of pixel units in the display area.

[0167] In some examples, in a first time period, as shown in FIG. 6, the corresponding sub-pixel cycle of the data signals transmitted by the plurality of data contact pads in the second direction D2 can be G2RBG1 G1BRG2. The data signals transmitted by the plurality of data contact pads are provided to the second connection ends 312 of the plurality of first side first transfer units 300a, for example. After passing through the plurality of first side first transfer units 300a, the minimum cycle number of the data signals output by the first connection ends 311 of the first side first transfer units 300a is still 8, and the corresponding sub-pixel cycle of the data signals output by the first connection ends 311 can be RG2BG1 BG1RG2. In a second time period, the corresponding sub-pixel cycle of the data signals transmitted by the plurality of data contact pads in the second direction D2 can be G1BRG2 G2RBG1. After passing through the plurality of first side first transfer units 300a, the corresponding sub-pixel cycle of the data signals output by the first connection ends 311 of the plurality of first side first transfer units 300a can be BG1RG2 RG2BG1.

[0168] In some examples, as shown in FIG. 6, after passing through a group of first side first transfer units 300a, the data signals corresponding to the third sub-pixel (e.g., including the first green sub-pixel G1 and the second green sub-pixel G2) can be transmitted by the third data lead lines located in the first gate metal layer, and the data signals corresponding to the first sub-pixel (e.g., the red sub-pixel R) and the second sub-pixel (e.g., the blue sub-pixel B) can be transmitted by the third data lead lines located in the second gate metal layer, which can ensure the uniform arrangement of the signal transmission traces and avoid the arrangement of the data lead lines transmitting the data signals corresponding to the third sub-pixel in different conductive layers, thereby avoiding the load difference and affecting the display effect.

[0169] FIG. 10 is a schematic diagram of a plurality of second side first transfer units according to at least one embodiment of the present disclosure. In FIG. 10, two groups of second side first transfer units are taken as an example for illustration. In some examples, as shown in FIG. 10, a group of second side first transfer units 300b can include eight first connection ends 311, eight second connection ends 312, and eight first transfer lines.

[0170] In some examples, within a group of the second-side first adapter units 300b, the eight first connection ends 311 can be sequentially arranged in the reverse direction of the second direction D2, for example, the first arrangement serial numbers of the eight first connection ends 311 sequentially arranged in the reverse direction of the second direction D2 can correspond to 1 to 8. The eight first connection ends 311 can be connected to the eight continuously arranged third data lead-out lines one by one. Among them, the third data lead-out lines connected by the first, third, fifth and seventh first connection ends can be located in the first gate metal layer, and the third data lead-out lines connected by the second, fourth, sixth and eighth first connection ends can be located in the second gate metal layer.

[0171] In some examples, within a group of the second-side first adapter units 300b, the eight second connection ends 312 can be located on the side of the eight first connection ends 311 close to the first signal access area in the first direction D1. The eight second connection ends 312 can be sequentially arranged in the reverse direction of the second direction D2, for example, the second arrangement serial numbers of the eight second connection ends 312 sequentially arranged in the reverse direction of the second direction D2 can correspond to 1 to 8. The eight second connection ends 312 and the eight first connection ends 311 can be arranged in alignment in the first direction D1. The eight second connection ends 312 can be connected to the eight continuously arranged contact pad connection lines 265 one by one. Among them, the plurality of contact pad connection lines 265 can be located in the first gate metal layer. The plurality of contact pad connection lines 265 can be electrically connected to the plurality of data contact pads 27 continuously arranged in the first signal access area B134 one by one.

[0172] In some examples, within a group of the second-side first adapter units 300b, the eight first adapter lines can include four first sequential adapter lines 314, two first plug-in adapter lines 313a and two second plug-in adapter lines 313b. The first arrangement serial number of the first connection end 311 connected by the first plug-in adapter line 313a is smaller than the second arrangement serial number of the second connection end 312 connected; the first arrangement serial number of the first connection end 311 connected by the second plug-in adapter line 313b is greater than the second arrangement serial number of the second connection end 312 connected. For example, the first plug-in adapter line 313a can be located in the second source-drain metal layer, and the second plug-in adapter line 313b can be located in the first source-drain metal layer.

[0173] In some examples, the eight first transition lines can include two first reordering units, each of which can include a first insertion-ordered transition line (e.g., including one first insertion-ordered transition line 313a) and a second insertion-ordered transition line (e.g., including one second insertion-ordered transition line 313b) whose orthographic projections on the substrate overlap. In the opposite direction of the second direction D2, one first reordering unit, two first order transition lines 314, one first reordering unit, and two first order transition lines 314 can be arranged in sequence.

[0174] In some examples, the insertion order of the data signals transmitted by the second connection ends of the first side first transition units 300a can be mirror set to the insertion order of the data signals transmitted by the second connection ends of the second side first transition units 300b, to match the arrangement of the data lines and the data connection lines of the display area. For example, the plurality of data lines and the plurality of data connection lines of the display area can be arranged symmetrically about the center line parallel to the first direction of the display area.

[0175] FIG. 11 is a schematic diagram of the insertion order of the data signals transmitted by the second connection ends of a group of second side first transition units shown in FIG. 10. In the present example, the order without insertion order adjustment corresponds to the arrangement order of the plurality of data lines of the display area; the first sub-pixels (e.g., red sub-pixels R) and the second sub-pixels (e.g., blue sub-pixels B) arranged in the same column are connected to the same data line, and the third sub-pixels (e.g., including first green sub-pixels G1 and second green sub-pixels G2) arranged in the same column are connected to the same data line. In some examples, as shown in FIG. 11, the eight data lines (e.g., the n-3th to the n+4th data lines) without insertion order adjustment are arranged in the opposite direction of the second direction D2, and can be sequentially adjusted in the manner of inserting one data line every one data line. The minimum cycle number of the data signals obtained by adjusting in the 1-in-1 manner is 8.

[0176] In some examples, as shown in FIG. 11, taking the sub-pixel arrangement sequence in the display area (for example, the sub-pixel arrangement sequence of the odd row pixel unit) as an example, the sub-pixel cycle corresponding to the eight data lines (the nth to the nth+4th data lines after the insertion sequence adjustment) obtained in the reverse direction of the second direction D2 according to the 1-in-1 mode is: RG2G1B BG1G2R. As shown in FIG. 10, the sub-pixel cycle corresponding to the data signals provided by the plurality of data contact pads in the reverse direction of the second direction D2 can be: RG2G1B BG1G2R. The data signals transmitted by the plurality of data contact pads are provided to the second connection end 312 of the plurality of second-side first switching units 300b, for example, after passing through the plurality of second-side first switching units 300b, the minimum cycle number of the data signals output by the first connection end 311 of the plurality of second-side first switching units 300b is still 8, and the sub-pixel cycle corresponding to the data signals output by the first connection end 311 can be: G2RG1B G1BG2R.

[0177] In some examples, taking the sub-pixel arrangement sequence in the display area (for example, the sub-pixel arrangement sequence of the even row pixel unit) as an example, the sub-pixel cycle corresponding to the eight data lines (the nth to the nth+4th data lines after the insertion sequence adjustment) obtained in the reverse direction of the second direction D2 according to the 1-in-1 mode is: BG1G2R RG2G1B; the sub-pixel cycle corresponding to the data signals provided by the plurality of data contact pads in the reverse direction of the second direction D2 is: BG1G2R RG2G1B, and then the sub-pixel cycle corresponding to the data signals output by the first connection end after passing through the second group of first switching units 300b can be: G1BG2R G2RG1B. The remaining description of the insertion sequence principle can refer to the description of the foregoing embodiments, and thus will not be described here.

[0178] In some examples, as shown in FIG. 10, after being switched by the group of second-side first switching units 300b, the data signals corresponding to the third sub-pixel (for example, including the first green sub-pixel G1 and the second green sub-pixel G2) can be transmitted by the third data lead line located in the first gate metal layer, and the data signals corresponding to the first sub-pixel (for example, the red sub-pixel R) and the second sub-pixel (for example, the blue sub-pixel B) can be transmitted by the third data lead line located in the second gate metal layer, which can ensure the uniform arrangement of the signal transmission lines and avoid the arrangement of the data lead line transmitting the data signals corresponding to the third sub-pixel in different conductive layers, thereby causing load difference and affecting the display effect.

[0179] FIG. 12 is a schematic diagram of a set of first-side second adapter units according to at least one embodiment of the present disclosure. In some examples, each set of second adapter units can include m second adapter lines, and m can be 8 in the present example. As shown in FIG. 12, a set of first-side second adapter units 32a can include eight second adapter lines (e.g., including four second sequential adapter lines 324, two third plug-in sequential adapter lines 323a, and two fourth plug-in sequential adapter lines 323b). In the present example, the eight second adapter lines can include two second permutation units, each of which can include at least one third plug-in sequential adapter line (e.g., including one third plug-in sequential adapter line 323a) and at least one fourth plug-in sequential adapter line (e.g., including one fourth plug-in sequential adapter line 323b) whose orthographic projections on the substrate overlap. In the second direction D2, one second permutation unit, two second sequential adapter lines 324, one second permutation unit, and two second sequential adapter lines 324 can be arranged in sequence.

[0180] In some examples, one end of each second adapter line can be connected to a second data line DLb or a data connection line 25, and the other end can be connected to a first data lead-out line 261. Taking the example of providing data signals to at least one row of pixel units in the display area whose sub-pixel arrangement order is RG1BG2, the corresponding sub-pixel cycle of the data signals transmitted by the plurality of first data lead-out lines 261 in the second direction D2 can be RG2BG1 BG1RG2, and the corresponding sub-pixel cycle of the data signals after being output by the first-side second adapter units 32a can be G2RBG1 G1BRG2, so that the order of the data signals transmitted by the plurality of data contact pads in the second direction matches the order of the data signals required by the second data lines and data connection lines connected to the corresponding row of pixel units in the display area in the second direction D2. Taking the example of providing data signals to at least one row of pixel units in the display area whose sub-pixel arrangement order is BG2RG1, the corresponding sub-pixel cycle of the data signals transmitted by the plurality of first data lines 261 in the second direction D2 can be BG1RG2 RG2BG1, and the corresponding sub-pixel cycle of the data signals after being output by the first-side second adapter units 32a can be G1BRG2 G2RBG1. The film layer of the second adapter lines of the second adapter units in the present embodiment is not limited, for example, the film layer can be arranged similarly to the first adapter lines, and thus will not be described again here.

[0181] In some examples, a set of second-side second adapter units 32b can adjust the order of the data signals output by the first connection end of a set of second-side first adapter units 300b to be the same as the order of the data signals input by the second connection end. The structure of the second-side second adapter units 32b in the present example can refer to the structure of the first-side second adapter units 32a, and thus will not be described again here.

[0182] The example can make the order of the data signals transmitted by the plurality of data contact pads match the order of the data signals required by the second data lines and the data connection lines in the display area, so as to avoid the jumper design in the second fan-out area, and thus ensure the reliability of the display product. The setting mode of the example can ensure the display effect of a display product with full high definition (FHD) resolution and RGBG sub-pixel arrangement.

[0183] In some example embodiments, the circuit arrangement area can be configured to arrange a plurality of groups of test circuits in sequence along the second direction, and the plurality of groups of test circuits can be located on a side of the plurality of groups of first adapter units away from the first signal access area along the first direction. Each group of test circuits can be connected to a plurality of (e.g., eight) data leads connected to the group of first adapter units. Each group of test circuits can include at least one first test circuit and at least one second test circuit, and the sum of the number of first test circuits and the number of second test circuits in each group of test circuits can be twice the number of data leads connected to each group of first adapter units. For example, each first test circuit can be connected to two data leads, and each second test circuit can be connected to two data leads.

[0184] FIG. 13 is an equivalent circuit diagram of a first test circuit and a second test circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 13, the first test circuit 401 can include a first test transistor CT1, a second test transistor CT2, and a third test transistor CT3. The gate of the first test transistor CT1 can be connected to a first test control line SW1, and the first pole of the first test transistor CT1 can be connected to a first test data line DR. The gate of the second test transistor CT2 can be connected to a second test control line SW2, and the first pole of the second test transistor CT2 can be connected to a second test data line DB. The gate of the third test transistor CT3 can be connected to a third test control line SW3, and the first pole of the third test transistor CT3 can be connected to a third test data line DG. The second pole of the first test transistor CT1 and the second pole of the second test transistor CT2 can be connected to the same data lead (e.g., a data lead DA-n). The second pole of the third test transistor CT3 can be connected to another data lead (e.g., a data lead DA-n+1).

[0185] In some examples, the second test circuit 402 can include a fourth test transistor CT4, a fifth test transistor CT5, and a sixth test transistor CT6. The gate of the fourth test transistor CT4 can be connected with the second test control line SW2, and the first pole of the fourth test transistor CT4 can be connected with the first test data line DR. The gate of the fifth test transistor CT5 can be connected with the first test control line SW1, and the first pole of the fifth test transistor CT5 can be connected with the second test data line DB. The gate of the sixth test transistor CT6 can be connected with the third test control line SW3, and the first pole of the sixth test transistor CT6 can be connected with the third test data line DG. The second pole of the fourth test transistor CT4 and the second pole of the fifth test transistor CT5 can be connected with the same data lead-out line (for example, the data lead-out line DA-n+2). The second pole of the sixth test transistor CT6 can be connected with another data lead-out line (for example, the data lead-out line DA-n+3).

[0186] In some examples, the sub-pixels connected with the data lead-out line DA-n can include a red sub-pixel (R) and a blue sub-pixel (B), the sub-pixels connected with the data lead-out line DA-n+2 can include a red sub-pixel (R) and a blue sub-pixel (B), and the sub-pixels connected with the data lead-out lines DA-n+1 and DA-n+3 can include a first green sub-pixel (G1) and a second green sub-pixel (G2).

[0187] In some examples, the second pole of the first test transistor CT1, the second pole of the third test transistor CT3, the second pole of the fourth test transistor CT4, and the second pole of the sixth test transistor CT6 can be connected with different data lines through different data lead-out lines.

[0188] In some examples, the first test control line SW1 can be configured to control the first test transistor CT1 in the first test circuit 401 and the fifth test transistor CT5 in the second test circuit 402 to be turned on, and the second test control line SW2 can be configured to control the second test transistor CT2 in the first test circuit 401 and the fourth test transistor CT4 in the second test circuit 402 to be turned on, so that the first test data signal transmitted by the first test data line DR and the second test data signal transmitted by the second test data line DB can be written to different data lines.

[0189] In some examples, when performing a display test (e.g., a color display test), the control device can provide a conductive signal to the first test control line SW1 (or the second test control line SW2) and the third test control line SW3, and provide a required test data signal to each of the plurality of test data lines, so that the plurality of data lines in the display area obtain the test data signal, and determine whether there is a defective sub-pixel by the color of the display screen, and locate the defective sub-pixel.

[0190] In some example embodiments, a group of first adapter units can correspond to a group of test circuits. For example, a plurality of groups of test circuits can include a plurality of first groups of test circuits and a plurality of second groups of test circuits; a plurality of data lead-out lines connected to a group of first side first adapter units can be connected to a first group of test circuits, and a plurality of data lead-out lines connected to a group of second side first adapter units can be connected to a second group of test circuits. In other words, a group of first side first adapter units corresponds to a first group of test circuits, and a group of second side first adapter units corresponds to a second group of test circuits.

[0191] FIG. 14A is a plan view of a first group of test circuits according to at least one embodiment of the present disclosure. FIG. 14B is a schematic view of a first source-drain metal layer in FIG. 14A. FIG. 14C is a schematic view of a first semiconductor layer, a first gate metal layer, and a second gate metal layer in FIG. 14A.

[0192] In some examples, as shown in FIGS. 14A-14C, the first group of test circuits can include two first test circuits 401 and two second test circuits 402. The two first test circuits 401, the two second test circuits 402, and the two first test circuits 401 can be arranged in sequence along the second direction D2. The first test transistor CT1, the second test transistor CT2, and the third test transistor CT3 of each first test circuit 401 can be arranged along the first direction D1, and the fourth test transistor CT4, the fifth test transistor CT5, and the sixth test transistor CT6 of each second test circuit 402 can be arranged along the first direction D1.

[0193] In some examples, the first test transistor CT1 and the fourth test transistor CT4 can be arranged in alignment along the second direction D2, the second test transistor CT2 and the fifth test transistor CT5 can be arranged in alignment along the second direction D2, and the third test transistor CT3 and the sixth test transistor CT6 can be arranged in alignment along the second direction D2.

[0194] In some examples, the first first test circuit 401 can be located between the third data leads 263-1 and 263-2; the first second test circuit 402 can be located between the third data leads 263-3 and 263-4; the second second test circuit 402 can be located between the third data leads 263-5 and 263-6, and the second first test circuit 401 can be located between the third data leads 263-7 and 263-8.

[0195] In some examples, the first test transistor CT1 and the second test transistor CT2 of the first first test circuit 401 can be connected with the third data lead 263-1, and the third test transistor CT3 can be connected with the third data lead 263-2. The fourth test transistor CT4 and the fifth test transistor CT5 of the first second test circuit 402 can be connected with the third data lead 263-3, and the sixth test transistor CT6 can be connected with the third data lead 263-4. The fourth test transistor CT4 and the fifth test transistor CT5 of the second second test circuit 402 can be connected with the third data lead 263-5, and the sixth test transistor CT6 can be connected with the third data lead 263-6. The first test transistor CT1 and the second test transistor CT2 of the second first test circuit 401 can be connected with the third data lead 263-7, and the third test transistor CT3 can be connected with the third data lead 263-8.

[0196] In some examples, the first semiconductor layer of the first frame area of the display substrate can include: the active layers 411 and 412 of the first test transistor CT1, the active layers 421 and 422 of the second test transistor CT2, the active layer 431 of the third test transistor CT3 of the first test circuit 401, the active layers 441 and 442 of the fourth test transistor CT4, the active layers 451 and 452 of the fifth test transistor CT5, and the active layer 461 of the sixth test transistor CT6 of the second test circuit 402. The active layers 411 and 412 of the first test transistor CT1, the active layers 421 and 422 of the second test transistor CT2, and the active layer 431 of the third test transistor CT3 can be arranged along the first direction D1; the active layers 441 and 442 of the fourth test transistor CT4, the active layers 451 and 452 of the fifth test transistor CT5, and the active layer 461 of the sixth test transistor CT6 can be arranged along the first direction D1.

[0197] In some examples, the first gate metal layer of the first frame area of the display substrate can include: the gates 413a and 413b of the first test transistor CT1, the gates 423a and 423b of the second test transistor CT2, the gate 433 of the third test transistor CT3, the gates 443a and 443b of the fourth test transistor CT4, the gates 453a and 453b of the fifth test transistor CT5, and the gate 463 of the sixth test transistor CT6. The gates 413a and 413b of the first test transistor CT1 can be an integral structure connected to each other, the gates 423a and 423b of the second test transistor CT2 can be an integral structure connected to each other, the gates 443a and 443b of the fourth test transistor CT4 can be an integral structure connected to each other, and the gates 453a and 453b of the fifth test transistor CT5 can be an integral structure connected to each other.

[0198] In some examples, the first gate metal layer of the first frame area of the display substrate can further include: the third data lead-out lines 263-2, 263-4, 263-6, and 263-8. The second gate metal layer of the display substrate can include: the third data lead-out lines 263-1, 263-3, 263-5, and 263-7.

[0199] In some examples, the first source-drain metal layer of the first frame area of the display substrate can include: the first test control line SW1, the second test control line SW2, the third test control line SW3, the first test data lines DR1 and DR2, the second test data lines DB1 and DB2, the third test data line DG, the second electrode 414 of the first test transistor CT1, the second electrode 424 of the second test transistor CT2, the second electrode 434 and the first electrode 435 of the third test transistor CT3, the second electrode 444 of the fourth test transistor CT4, the second electrode 454 of the fifth test transistor CT5, the second electrode 464 and the first electrode 465 of the sixth test transistor CT6.

[0200] In some examples, the first test control line SW1, the second test control line SW2, the third test control line SW3, the first test data line DR1 and DR2, the second test data line DB1 and DB2, the third test data line DG can extend at least along the second direction D2. The first test transistor CT1 and the fourth test transistor CT4 can be located between the first test data line DR1 and DR2 in the first direction D1, the second test transistor CT2 and the fifth test transistor CT5 can be located between the second test data line DB1 and DB2 in the first direction D1. The third test transistor CT3 and the sixth test transistor CT6 can be located on one side of the third test data line DG in the first direction D1. The first test control line SW1 and the second test control line SW2 can be located between the first test data line DR2 and the second test data line DB1, and the third test control line SW3 can be located between the second test data line DB2 and the third test data line DG.

[0201] In some examples, the second pole 414 of the first test transistor CT1 of the first first test circuit 401 can be connected with the third data lead-out line 263-1, the active layer 411 and 412 of the first test transistor CT1; the second pole 424 of the second test transistor CT2 can be connected with the third data lead-out line 263-1, the active layer 421 and 422 of the second test transistor CT2; the second pole 434 of the third test transistor CT3 can be connected with the third data lead-out line 263-2, the active layer 431 of the third test transistor CT3; and the first pole 435 of the third test transistor CT3 can be connected with the active layer 431 of the third test transistor CT3.

[0202] In some examples, the second pole 444 of the fourth test transistor CT4 of the first second test circuit 402 can be connected with the third data lead-out line 263-3, the active layer 441 and 442 of the fourth test transistor CT4; the second pole 454 of the fifth test transistor CT5 can be connected with the third data lead-out line 263-3, the active layer 451 and 452 of the fifth test transistor CT5; the second pole 464 of the sixth test transistor CT6 can be connected with the third data lead-out line 263-4, the active layer 461 of the sixth test transistor CT6; and the first pole 465 of the sixth test transistor CT6 can be connected with the active layer 461 of the sixth test transistor CT6.

[0203] In some examples, the first test data line DR1 can be connected with the active layer 411 of the first test transistor CT1 and the active layer 441 of the fourth test transistor CT4, and the first test data line DR2 can be connected with the active layer 412 of the first test transistor CT1 and the active layer 442 of the fourth test transistor CT4. The second test data line DB1 can be connected with the active layer 421 of the second test transistor CT2 and the active layer 451 of the fifth test transistor CT5, and the second test data line DB2 can be connected with the active layer 422 of the second test transistor CT2 and the active layer 452 of the fifth test transistor CT5. The third test data line DG can be an integrated structure connected with the first electrode 435 of the third test transistor CT3 and the first electrode 465 of the sixth test transistor CT6.

[0204] In some examples, in the test phase, the test circuit can provide test data signals to the sub-pixels of different rows of pixel units in the display area in time periods. The first group of test circuits can provide corresponding test data signals to the plurality of third data lead-out lines (for example, including third data lead-out lines 263-1 to 263-8) in a first test period in a cyclic order of RGBG BGRG, and the test data signals are provided to the second data lines and the data connection lines of the display area after being reordered by the plurality of second switching units, so as to detect the display of the odd (or even) row of pixel units. The first group of test circuits can provide corresponding test data signals to the plurality of third data lead-out lines in a second test period in a cyclic order of BGRG RGBG, and the test data signals are provided to the second data lines and the data connection lines of the display area after being reordered by the plurality of second switching units, so as to detect the display of the even (or odd) row of pixel units. The test data signals corresponding to the first green sub-pixel G1 and the second green sub-pixel G2 can be the same. The order of the data signals provided by the first group of test circuits can be the same as the order of the data signals output by the first output end of the first group of first switching units. In some examples, the first group of test circuits can provide test data signals to the sub-pixels of the first row of pixel units in a first first test period, and provide test data signals to the sub-pixels of the second row of pixel units in a first second test period; provide test data signals to the sub-pixels of the third row of pixel units in a second first test period, and provide test data signals to the sub-pixels of the fourth row of pixel units in a second second test period, and so on, to provide corresponding test data signals to the plurality of rows of pixel units.

[0205] In the example, the first test transistor of the first test circuit and the fourth test transistor of the second test circuit are connected to different test control lines and the same test data line, and the second test transistor of the first test circuit and the fifth test transistor of the second test circuit are connected to different test control lines and the same test data line. In the test phase, test data signals can be sequentially provided according to the data signals corresponding to the first output end of the first side first switching unit in each group, so as to meet the demand of the data line for the test data signal.

[0206] In some examples, the structure of the second group of test circuits corresponding to each group of second side first switching units is similar to that of the first group of test circuits, and thus is not described here.

[0207] The embodiment adjusts the transmission sequence of the test data signal by arranging multiple groups of test circuits, which can avoid the jumper design in the second fan-out area, is conducive to reducing the adverse effects caused by the jumper design, and thus improves the reliability of the display substrate.

[0208] FIG. 15 is an equivalent circuit diagram of a third test circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 15, the third test circuit can include a seventh test transistor CT7, an eighth test transistor CT8, a ninth test transistor CT9, and a tenth test transistor CT10.

[0209] In some examples, the gates of the seventh test transistor CT7, the eighth test transistor CT8, the ninth test transistor CT9, and the tenth test transistor CT10 are connected to the fourth test control line SW4, the first poles of the seventh test transistor CT7 and the eighth test transistor CT8 are connected to the fourth test data line DD1, and the first poles of the ninth test transistor CT9 and the tenth test transistor CT10 are connected to the fifth test data line DD2. The second poles of the seventh test transistor CT7, the eighth test transistor CT8, the ninth test transistor CT9, and the tenth test transistor CT10 can be connected to different data lines through different data lead-out lines. For example, the second pole of the seventh test transistor CT7 can be connected to the data lead-out line DA-n, the second pole of the eighth test transistor CT8 can be connected to the data lead-out line DA-n+1, the second pole of the ninth test transistor CT9 can be connected to the data lead-out line DA-n+2, and the second pole of the tenth test transistor CT10 can be connected to the data lead-out line DA-n+3.

[0210] In some examples, the third test circuit can be located on the side close to the first signal access area of the first test circuit and the second test circuit in the circuit setting area, or can be located on the side close to the bending area. The embodiment is not limited thereto.

[0211] In some examples, the third test circuit can be configured to provide a test data signal to the data line during the black and white display test to perform the black and white display test.

[0212] FIG. 16 is another schematic view of a set of first-side first adapter units according to at least one embodiment of the present disclosure. FIG. 17 is a schematic view of the first gate metal layer and the second gate metal layer in FIG. 16. FIG. 18 is a schematic view of the insertion order of data signals transmitted by the second connection ends of the set of first-side first adapter units shown in FIG. 16. In the present example, m can be 12. In the present example and the following examples, the data signals required by the first green sub-pixel G1 and the second green sub-pixel G2 are taken as examples for description, and the required test data signals are the same.

[0213] In some examples, as shown in FIG. 16 and FIG. 17, the set of first-side first adapter units 300a can include twelve first connection ends 311, twelve second connection ends 312, and twelve first adapter lines. The twelve first adapter lines can include four first order adapter lines 314, four first insertion order adapter lines 313a, and four second insertion order adapter lines 313b. The twelve first adapter lines can include four first order change units, and each first order change unit can include a first insertion order adapter line (e.g., including one first insertion order adapter line 313a) and a second insertion order adapter line (e.g., including one second insertion order adapter line 313b) whose orthographic projections on the substrate overlap. In the second direction D2, two first order change units, two first order adapter lines 314, two first order change units, and two first order adapter lines 314 can be arranged in sequence.

[0214] In some examples, the twelve first connection ends 311 can be connected to the twelve third data lead-out lines 263-1 to 263-12 arranged in sequence one by one. Among them, the third data lead-out lines 263-1, 263-3, 263-5, 263-7, 263-9, and 263-11 can be located on the second gate metal layer, and the third data lead-out lines 263-2, 263-4, 263-6, 263-8, 263-10, and 263-12 can be located on the first gate metal layer.

[0215] In some examples, in a first group of first side first adapter units 300a, in the second direction D2, the first first plug order adapter line 313a can connect a first first connection end and a second second connection end; the second first plug order adapter line 313a can connect a third first connection end and a fourth second connection end; the third first plug order adapter line 313a can connect a seventh first connection end and an eighth second connection end; the fourth first plug order adapter line 313a can connect a ninth first connection end and a tenth second connection end. The first second plug order adapter line 313b can connect a second first connection end and a first second connection end; the second second plug order adapter line 313b can connect a fourth first connection end and a third second connection end; the third second plug order adapter line 313b can connect an eighth first connection end and a seventh second connection end; the fourth second plug order adapter line 313b can connect a tenth first connection end and a ninth second connection end.

[0216] In some examples, the first first order adapter line 314 can connect a fifth first connection end and a fifth second connection end; the second first order adapter line 314 can connect a sixth first connection end and a sixth second connection end; the third first order adapter line 314 can connect an eleventh first connection end and an eleventh second connection end; the fourth first order adapter line 314 can connect a twelfth first connection end and a twelfth second connection end.

[0217] In some examples, as shown in FIG. 18, the sub-pixel arrangement of the display area is as shown in FIG. 4, and the sub-pixel arrangement order of the odd row pixel units of the display area is taken as RGBG, and twelve data lines (for example, the data lines with serial numbers n-3 to n+8) that have not undergone plug order adjustment are taken as examples, the data connection lines connected to the n-3th to n-1th data lines can be inserted between the n+1th to n+8th data lines in a manner of inserting one data line every two data lines (i.e., a 2-insert-1 manner). For example, the data connection line connected to the n-1th data line can be inserted between the n+2th and n+3th data lines, the n-2th data line can be inserted between the n+4th and n+5th data lines, and the n-3th data line can be inserted between the n+6th and n+7th data lines. The minimum cycle number of the data signal obtained in the 2-insert-1 manner is 12, and the sub-pixel cycle corresponding to the twelve data lines obtained in the 2-insert-1 manner is GRGB BGGR GRBG. In some examples, the sub-pixel arrangement order of the even row pixel units of the display area is taken as BGRG, and the sub-pixel cycle corresponding to the twelve data lines obtained in the 2-insert-1 manner can be GBGR RGGB GBRG.

[0218] In some examples, the plurality of data contact pads can provide data signals to the sub-pixels of different row pixel units of the display area in time periods. In a first time period, as shown in FIG. 16, the corresponding sub-pixel cycle of the data signals transmitted by the plurality of data contact pads in the second direction D2 can be: GRGB BGGR GRBG. The data signals transmitted by the plurality of data contact pads are provided to the second connection end 312 of the plurality of first-side first adapter units 300a, for example, after the plurality of first-side first adapter units 300a, the minimum cycle number of the data signals output by the first connection end 311 is still 12, and in the second direction D2, the corresponding sub-pixel cycle of the data signals output by the first connection end 311 can be: RGBG BGRG RGBG. In a second time period, the corresponding sub-pixel cycle of the data signals transmitted by the plurality of data contact pads in the second direction D2 can be: GBGR RGGB GBRG. After the plurality of first-side first adapter units 300a, the corresponding sub-pixel cycle of the data signals output by the first connection end 311 of the plurality of first-side first adapter units 300a can be: BGRG RGBG BGRG.

[0219] FIG. 19 is a schematic diagram of a group of first-side second adapter units according to at least one embodiment of the present disclosure. In some examples, each group of second adapter units can include m second adapter lines, and m in the present example can be 12. As shown in FIG. 19, a group of first-side second adapter units 32a can include twelve second adapter lines (for example, including four second sequential adapter lines 324, two third interleaved adapter lines 323a, and two fourth interleaved adapter lines 323b). In the present example, the twelve second adapter lines can include four second permutation units, and each second permutation unit can include at least one third interleaved adapter line (for example, including one third interleaved adapter line 323a) and at least one fourth interleaved adapter line (for example, including one fourth interleaved adapter line 323b) whose orthographic projections on the substrate overlap. In the second direction D2, two second permutation units, two second sequential adapter lines 324, two second permutation units, and two second sequential adapter lines 324 can be arranged in sequence.

[0220] In some examples, one end of each second transfer line can be connected to one second data line DLb or one data connection line 25, and the other end can be connected to one first data lead-out line 261. In the first time period, the corresponding sub-pixel cycle of the data signals transmitted by the plurality of first data lead-out lines 261 along the second direction D2 can be RGBG BGRG RGBG, and the corresponding sub-pixel cycle of the data signals after being transferred and output by the plurality of groups of first-side second transfer units 32a can be GRGB BGGR GRBG; in the second time period, the corresponding sub-pixel cycle of the data signals transmitted by the plurality of first data lead-out lines 261 along the second direction D2 can be BGRG RGBG BGRG, and the corresponding sub-pixel cycle of the data signals after being transferred and output by the plurality of groups of first-side second transfer units 32a can be GBGR RGGB GBRG, so that the order of the data signals transmitted by the plurality of data contact pads along the second direction D2 matches the order of the data signals required by the second data lines and the data connection lines in the display area along the second direction D2. For example, the first time period can be configured to provide data signals for the odd-numbered row pixel units in the display area, and the second time period can be configured to provide data signals for the even-numbered row pixel units in the display area. The film layer of the second transfer line of the second transfer unit in this embodiment is not limited, for example, the film layer is arranged similarly to the first transfer line, and thus is not described here.

[0221] In some examples, in the first signal access area, the first data contact pad arranged along the second direction can transmit the 384th data signal, and provide the third data lead-out line located in the first gate metal layer through the second connection end of the first transfer unit, one first transfer line, and the first connection end, and transmit the third data lead-out line to the first data lead-out line through the second data lead-out line and the data bending connection line, and transmit the first data lead-out line to one data line connected with the green sub-pixel (for example, the data line with serial number 384 arranged along the second direction) through the second transfer line of the second transfer unit. In this example, by adjusting the order of the data signals transmitted by the data contact pads and arranging the plurality of groups of first transfer units and the plurality of groups of second transfer units, the jumper design in the second fan-out area can be avoided in the scheme of arranging the data connection lines in the display area, thereby ensuring the reliability of the display product.

[0222] FIG. 20 is a plan view of a first group of test circuits according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 20, the first group of test circuits is connected to twelve third data lead-out lines (for example, third data lead-out lines 263-1 to 263-12) connected to one group of first-side first transfer units. The first group of test circuits can include three first test circuits 401 and three second test circuits 402. Among them, one first test circuit 401, two second test circuits 402, two first test circuits 401, and one second test circuit 402 can be arranged along the second direction D2 in sequence.

[0223] In some examples, the first test transistor CT1 and the second test transistor CT2 of the first first test circuit 401 can be connected with the third data lead-out line 263-1, and the third test transistor CT3 can be connected with the third data lead-out line 263-2. The first test transistor CT1 and the second test transistor CT2 of the second first test circuit 401 can be connected with the third data lead-out line 263-7, and the third test transistor CT3 can be connected with the third data lead-out line 263-8. The first test transistor CT1 and the second test transistor CT2 of the third first test circuit 401 can be connected with the third data lead-out line 263-9, and the third test transistor CT3 can be connected with the third data lead-out line 263-10.

[0224] In some examples, the fourth test transistor CT4 and the fifth test transistor CT5 of the first second test circuit 402 can be connected with the third data lead-out line 263-3, and the sixth test transistor CT6 can be connected with the third data lead-out line 263-4. The fourth test transistor CT4 and the fifth test transistor CT5 of the second second test circuit 402 can be connected with the third data lead-out line 263-5, and the sixth test transistor CT6 can be connected with the third data lead-out line 263-6. The fourth test transistor CT4 and the fifth test transistor CT5 of the third second test circuit 402 can be connected with the third data lead-out line 263-11, and the sixth test transistor CT6 can be connected with the third data lead-out line 263-12.

[0225] In some examples, the test circuit can provide test data signals to the sub-pixels of different rows of pixel units in the display area in time periods. In a test phase, the first group of test circuits can provide corresponding test data signals to the plurality of third data lead-out lines (e.g., including the third data lead-out lines 263-1 to 263-12) in a first test period in a cyclic order of RGBG BGRG RGBG, and the test data signals are provided to the second data lines and the data connection lines of the display area after being reordered by the plurality of second switching units, so as to detect the display of the odd (or even) row of pixel units. The first group of test circuits can provide corresponding test data signals to the plurality of third data lead-out lines in a second test period in a cyclic order of BGRG RGBG BGRG, and the test data signals are provided to the second data lines and the data connection lines of the display area after being reordered by the plurality of second switching units, so as to detect the display of the even (or odd) row of pixel units. Other descriptions about the test circuit can refer to the descriptions of the foregoing embodiments, and thus will not be described here.

[0226] FIG. 21 is a schematic diagram of a second-side first adapter unit group according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 21, the second-side first adapter unit group 300b can include twelve first connection ends 311, twelve second connection ends 312, and twelve first adapter lines. Within the second-side first adapter unit group 300b, the twelve first connection ends 311 can be arranged in sequence in the reverse direction of the second direction D2, for example, the first arrangement serial numbers of the twelve first connection ends 311 arranged in sequence in the reverse direction of the second direction D2 can correspond to 1-12. The twelve first connection ends 311 can be connected to the twelve third data lead-out lines arranged in sequence one by one. Among them, the third data lead-out lines connected by the first first connection end, the third first connection end, the fifth first connection end, the seventh first connection end, the ninth first connection end, and the eleventh first connection end can be located in the first gate metal layer, and the third data lead-out lines connected by the second first connection end, the fourth first connection end, the sixth first connection end, the eighth first connection end, the tenth first connection end, and the twelfth first connection end can be located in the second gate metal layer.

[0227] In some examples, within the second-side first adapter unit group 300b, the twelve second connection ends 312 can be arranged in sequence in the reverse direction of the second direction D2, for example, the second arrangement serial numbers of the twelve second connection ends 312 arranged in sequence in the reverse direction of the second direction D2 can correspond to 1-12. The twelve first adapter lines can include four first sequential adapter lines 314, four first plug-sequential adapter lines 313a, and four second plug-sequential adapter lines 313b.

[0228] FIG. 22 is a schematic diagram of the insertion order of the data signals transmitted by the second connection end of a second-side first adapter unit of a group of second-side first adapter units shown in FIG. 21. In the example, the order of the data lines before insertion order adjustment corresponds to the arrangement order of the data lines of the display area. The first sub-pixels (e.g., red sub-pixels R) and the second sub-pixels (e.g., blue sub-pixels B) arranged in the same column are connected to the same data line, and the third sub-pixels (e.g., green sub-pixels G) arranged in the same column are connected to the same data line. In some examples, as shown in FIG. 22, the twelve data lines (e.g., the nth-3th to nth+8th data lines) before insertion order adjustment can be arranged in the opposite direction of the second direction D2, and can be adjusted in the order of inserting one data line every two data lines. The minimum cycle number of the data signals obtained by adjusting in the order of 2 insertion 1 is 12. Taking the sub-pixel arrangement order (e.g., the sub-pixel arrangement order of the pixel units in the odd-numbered rows) of RGBG as an example, as shown in FIG. 22, the sub-pixel cycle corresponding to the twelve data lines (the nth to nth+8th data lines after insertion order adjustment) obtained by adjusting in the order of 2 insertion 1 is RGBG GRBG BGGR. Taking the sub-pixel arrangement order (e.g., the sub-pixel arrangement order of the pixel units in the even-numbered rows) of BGRG as an example, the sub-pixel cycle corresponding to the twelve data lines (the nth to nth+8th data lines after insertion order adjustment) obtained by adjusting in the order of 2 insertion 1 can be BGRG GBRG RGGB.

[0229] In some examples, the plurality of data contact pads can provide data signals to the sub-pixels of different rows of pixel units of the display area in different time periods. In a first time period, as shown in FIG. 21, the sub-pixel cycle corresponding to the data signals provided by the plurality of data contact pads in the opposite direction of the second direction D2 can be RGBG GRBG BGGR. The data signals transmitted by the plurality of data contact pads are provided to the second connection end 312 of a group of second-side first adapter units 300b, for example, after passing through the group of second-side first adapter units 300b, the minimum cycle number of the data signals output by the first connection end 311 of the group of second-side first adapter units 300b is still 12, and the sub-pixel cycle corresponding to the twelve data signals in the opposite direction of the second direction D2 can be GRGB GRGB GBGR. In a second time period, the sub-pixel cycle corresponding to the data signals transmitted by the plurality of data contact pads in the second direction D2 can be BGRG GBRG RGGB, and the sub-pixel cycle corresponding to the data signals output by the first connection end 311 of the group of second-side first adapter units 300b after passing through the group of second-side first adapter units 300b can be GBGR GBGR GRGB.

[0230] FIG. 23 is a plan view of a second set of test circuits according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 23, the second set of test circuits can be connected with twelve third data leads 263 connected with a second set of first side first adapter units. The second set of test circuits can include three first test circuits 401 and three second test circuits 402. Among them, one first test circuit 401, one second test circuit 402, one first test circuit 401, two second test circuits 402 and one first test circuit 401 can be arranged in the reverse direction of the second direction D2 in turn.

[0231] In some examples, the test data signals provided by the test circuits at different time periods can be different in the test phase. The test circuits can provide corresponding test data signals according to the rule of row-by-row scanning of the display area. For example, for odd row pixel units, the second set of test circuits can provide corresponding test data signals to the plurality of data leads in the reverse direction of the second direction D2 in the cyclic order of GRGB GRGB GBGR; for even row pixel units, the second set of test circuits can provide corresponding test data signals to the plurality of data leads in the reverse direction of the second direction D2 in the cyclic order of GBGR GBGR GRGB. The remaining description of the test circuits of the present example can refer to the description of the foregoing embodiments, and will not be repeated here.

[0232] FIG. 24 is another schematic view of a set of first side first adapter units according to at least one embodiment of the present disclosure. FIG. 25 is a schematic view of the insertion order principle of the data signals transmitted by the second connection end of the set of first side first adapter units shown in FIG. 24. In the present example, m can be 16.

[0233] In some examples, as shown in FIG. 24, a set of first side first adapter units 300a can include sixteen first connection ends 311, sixteen second connection ends 312, and sixteen first adapter lines. The sixteen first adapter lines can include eight first order adapter lines 314, four first insertion order adapter lines 313a, and four second insertion order adapter lines 313b. The sixteen first adapter lines can include four first order changing units, and each first order changing unit can include a first insertion order adapter line (e.g., including one first insertion order adapter line 313a) and a second insertion order adapter line (e.g., including one second insertion order adapter line 313b) whose orthographic projections on the substrate overlap. In the second direction D2, two first order changing units, four first order adapter lines 314, two first order changing units, and four first order adapter lines 314 can be arranged in turn.

[0234] In some examples, the sixteen first connection ends 311 can be connected one by one with sixteen continuously arranged third data leads. The sixteen third data leads can be alternately arranged in the first gate metal layer and the second gate metal layer.

[0235] In some examples, within a first set of first side first adapter units 300a, in the second direction D2, a first first-order adapter wire 313a can connect a first first connection end and a second second connection end; a second first-order adapter wire 313a can connect a third first connection end and a fourth second connection end; a third first-order adapter wire 313a can connect a ninth first connection end and a tenth second connection end; a fourth first-order adapter wire 313a can connect an eleventh first connection end and a twelfth second connection end. A first second-order adapter wire 313b can connect a second first connection end and a first second connection end; a second second-order adapter wire 313b can connect a fourth first connection end and a third second connection end; a third second-order adapter wire 313b can connect a tenth first connection end and a ninth second connection end; a fourth second-order adapter wire 313b can connect a twelfth first connection end and an eleventh second connection end.

[0236] In some examples, a first first-order adapter wire 314 can connect a fifth first connection end and a fifth second connection end; a second first-order adapter wire 314 can connect a sixth first connection end and a sixth second connection end; a third first-order adapter wire 314 can connect a seventh first connection end and a seventh second connection end; a fourth first-order adapter wire 314 can connect an eighth first connection end and an eighth second connection end; a fifth first-order adapter wire 314 can connect a thirteenth first connection end and a thirteenth second connection end; a sixth first-order adapter wire 314 can connect a fourteenth first connection end and a fourteenth second connection end; a seventh first-order adapter wire 314 can connect a fifteenth first connection end and a fifteenth second connection end; an eighth first-order adapter wire 314 can connect a sixteenth first connection end and a sixteenth second connection end.

[0237] In some examples, as shown in FIG. 25, the sub-pixel arrangement of the display region is as shown in FIG. 4, the sub-pixel arrangement sequence of the odd row pixel units of the display region is taken as RGBG, and sixteen data lines (for example, the data lines with serial numbers n-3 to n+12) that have not been adjusted by the insertion sequence are taken as an example for description. The sixteen data lines can be arranged along the second direction D2, and the data connection lines connected to the data lines with serial numbers n-3 to n-1 can be inserted between the data lines with serial numbers n+1 to n+12 in a manner of inserting one data line every three data lines (i.e., a 3-insert-1 manner). For example, the data line with serial number n-1 can be inserted between the data lines with serial numbers n+3 and n+4, the data line with serial number n-2 can be inserted between the data lines with serial numbers n+6 and n+7, and the data line with serial number n-3 can be inserted between the data lines with serial numbers n+9 and n+10. The minimum cycle number of the data signals obtained in the 3-insert-1 manner is 16. Taking the sub-pixel arrangement sequence of the display units in one row as RGBG, the sub-pixel cycle corresponding to the sixteen data lines obtained in the 3-insert-1 manner is: GRGB BGRG GBGR RGBG. Taking the sub-pixel arrangement sequence of the display units in one row as BGRG, the sub-pixel cycle corresponding to the sixteen data lines obtained in the 3-insert-1 manner can be: GBGR RGBG GRGB BGRG.

[0238] In some examples, the plurality of data contact pads can provide data signals to the sub-pixels of different row pixel units of the display region in different time periods. In a first time period, as shown in FIG. 24, the corresponding sub-pixel cycle of the data signals transmitted by the plurality of data contact pads along the second direction D2 can be: GRGB BGRG GBGR RGBG. After the multiplexed data signals pass through the plurality of groups of first-side first switching units 300a, the minimum cycle number of the data signals is still 16, and the corresponding sub-pixel cycle of the sixteen multiplexed data signals along the second direction D2 can be: RGBG BGRG BGRG RGBG. In a second time period, the corresponding sub-pixel cycle of the data signals transmitted by the plurality of data contact pads along the second direction D2 can be: GBGR RGBG GRGB BGRG. After the data signals pass through the plurality of groups of first-side first switching units 300a, the corresponding sub-pixel cycle of the data signals output by the first connection ends 311 of the plurality of groups of first-side first switching units 300a can be: BGRG RGBG RGBG BGRG.

[0239] FIG. 26 is a plan view of a first set of test circuits corresponding to the first set of first side first adapter units shown in FIG. 24. In some examples, as shown in FIG. 26, a first set of test circuits is connected to the sixteen third data leads connected to the first set of first side first adapter units. The first set of test circuits can include four first test circuits 401 and four second test circuits 402. Among them, one first test circuit 401, two second test circuits 402, one first test circuit 401, one second test circuit 402, two first test circuits 401 and one second test circuit 402 can be arranged in the second direction D2 in sequence.

[0240] In some examples, the test circuits can provide test data signals to the sub-pixels of different rows of pixel units in the display area in different time periods. In the test phase, the first set of test circuits can provide corresponding test data signals to the plurality of third data leads in the first test period in the cyclic order of RGBG BGRG BGRG RGBG, and the test data signals are provided to the second data lines and the data connection lines of the display area after being reordered by the plurality of second adapter units, so as to detect the display of the odd (or even) row pixel units. The first set of test circuits can provide corresponding test data signals to the plurality of third data leads in the second test period in the cyclic order of BGRG RGBG RGBG BGRG, and the test data signals are provided to the second data lines and the data connection lines of the display area after being reordered by the plurality of second adapter units, so as to detect the display of the even (or odd) row pixel units. Other descriptions of the test circuits can refer to the descriptions of the foregoing embodiments, and will not be described here.

[0241] FIG. 27 is a schematic diagram of a second-side first adapter unit group according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 27, the second-side first adapter unit group 300b can include sixteen first connection ends 311, sixteen second connection ends 312, and sixteen first adapter lines. Within the second-side first adapter unit group 300b, the sixteen first connection ends 311 can be arranged in sequence in the reverse direction of the second direction D2, for example, the first arrangement serial numbers of the sixteen first connection ends 311 arranged in sequence in the reverse direction of the second direction D2 can correspond to 1-16. The sixteen first connection ends 311 can be connected with sixteen continuous third data lead-out lines. Among them, the first, third, fifth, seventh, ninth, eleventh, thirteenth, and fifteenth first connection ends are connected with the third data lead-out lines located in the first gate metal layer, and the second, fourth, sixth, eighth, tenth, twelfth, fourteenth, and sixteenth first connection ends are connected with the third data lead-out lines located in the second gate metal layer.

[0242] In some examples, within the second-side first adapter unit group 300b, the sixteen second connection ends 312 can be arranged in sequence in the reverse direction of the second direction D2, for example, the second arrangement serial numbers of the sixteen second connection ends 312 arranged in sequence in the reverse direction of the second direction D2 can correspond to 1-16. The sixteen first adapter lines can include eight first-order adapter lines 314, four first-order insertion adapter lines 313a, and four second-order insertion adapter lines 313b.

[0243] FIG. 28 is a schematic diagram of the insertion order of the data signals transmitted by the second connection ends of the second side first adapter units of the group shown in FIG. 27. In the present example, the order of the data signals that have not been adjusted by the insertion order adjustment corresponds to the arrangement order of the data lines of the display area. The first sub-pixels (e.g., red sub-pixels R) and the second sub-pixels (e.g., blue sub-pixels B) arranged in the same column are connected to the same data line, and the third sub-pixels (e.g., green sub-pixels G) arranged in the same column are connected to the same data line. In some examples, as shown in FIG. 28, the sixteen data lines (e.g., the nth-3th to the nth+12th) that have not been adjusted by the insertion order adjustment are arranged in the opposite direction of the second direction D2, and the order can be adjusted in a manner of inserting one data line every three data lines. The minimum cycle number of the data signals obtained by adjusting in the manner of 3 insertion 1 is 16. Taking the arrangement order of the sub-pixels of a row of pixel units as RGBG for example, as shown in FIG. 28, the sixteen data lines (the nth to the nth+12th after the insertion order adjustment) obtained by adjusting in the manner of 3 insertion 1 correspond to the sub-pixel cycle of: RGBG GRGB BGRG GBGR. Taking the arrangement order of the sub-pixels of a row of pixel units as BGRG for example, the sixteen data lines (the nth to the nth+12th after the insertion order adjustment) obtained by adjusting in the manner of 3 insertion 1 correspond to the sub-pixel cycle of: BGRG GBGR RGBG GRGB.

[0244] In some examples, the plurality of data contact pads can provide data signals to the sub-pixels of different rows of pixel units of the display area in different time periods. In a first time period, as shown in FIG. 27, the data signals provided by the plurality of data contact pads correspond to the sub-pixel cycle of: RGBG GRGB BGRG GBGR in the opposite direction of the second direction D2. The minimum cycle number of the data signals after passing through the plurality of groups of second side first adapter units 300b is still 16, and the sixteen data signals correspond to the sub-pixel cycle of: GRGB GRGB GBGR GBGR in the opposite direction of the second direction D2. In a second time period, the data signals provided by the plurality of data contact pads correspond to the sub-pixel cycle of: BGRG GBGR RGBG GRGB in the opposite direction of the second direction D2. After passing through the plurality of groups of second side first adapter units 300b, the data signals output by the first connection ends 311 of the plurality of groups of second side first adapter units 300b correspond to the sub-pixel cycle of: GBGR GBGR GRGB GRGB in the opposite direction of the second direction D2.

[0245] FIG. 29 is a plan view of a second set of test circuits according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 29, the second set of test circuits can be connected with sixteen third data leads 263 connected with a second set of first adapter units on a second side. The second set of test circuits can include four first test circuits 401 and four second test circuits 402. In some examples, one first test circuit 401, one second test circuit 402, one first test circuit 401, two second test circuits 402, one first test circuit 401, one second test circuit 402, and one first test circuit 401 can be arranged in a reverse order of the second direction D2.

[0246] In some examples, the test data signals provided by the test circuits at different time periods can be different during the test phase. The test circuits can provide corresponding test data signals according to a rule of scanning the display area row by row. For example, for odd row pixel units, the second set of test circuits can provide corresponding test data signals to the plurality of data leads in a reverse order of the second direction D2 according to a cyclic order of GRGB GRGB GBGR GBGR. For even row pixel units, the second set of test circuits can provide corresponding test data signals to the plurality of data leads in a reverse order of the second direction D2 according to a cyclic order of GBGR GBGR GRGB GRGB. The remaining descriptions of the test circuits of the present example can be referred to the descriptions of the foregoing embodiments, which will not be repeated here.

[0247] FIG. 30 is another schematic view of a set of first adapter units on a first side according to at least one embodiment of the present disclosure. FIG. 31 is a schematic view of the insertion order of data signals transmitted by the second connection ends of the set of first adapter units shown in FIG. 30. In the present example, m can be 20.

[0248] In some examples, as shown in FIG. 30, a set of first adapter units 300a on a first side can include twenty first connection ends 311, twenty second connection ends 312, and twenty first adapter lines. The twenty first adapter lines can include eight first order adapter lines 314, six first insertion order adapter lines 313a, and six second insertion order adapter lines 313b. The twenty first adapter lines can include six first order change units, each of which can include a first insertion order adapter line (e.g., including one first insertion order adapter line 313a) and a second insertion order adapter line (e.g., including one second insertion order adapter line 313b) whose orthogonal projections on the substrate overlap. In the second direction D2, three first order change units, four first order adapter lines 314, three first order change units, and four first order adapter lines 314 can be arranged in turn.

[0249] In some examples, the twenty first connection terminals 311 can be connected with twenty third data leads arranged in series in one-to-one correspondence. The twenty third data leads can be alternately arranged in the first gate metal layer and the second gate metal layer.

[0250] In some examples, in a group of first side first adapter units 300a, in the second direction D2, the first first plug order adapter line 313a can connect a first first connection terminal and a second second connection terminal; the second first plug order adapter line 313a can connect a third first connection terminal and a fourth second connection terminal; the third first plug order adapter line 313a can connect a fifth first connection terminal and a sixth second connection terminal; the fourth first plug order adapter line 313a can connect an eleventh first connection terminal and a twelfth second connection terminal; the fifth first plug order adapter line 313a can connect a thirteenth first connection terminal and a fourteenth second connection terminal; and the sixth first plug order adapter line 313a can connect a fifteenth first connection terminal and a sixteenth second connection terminal.

[0251] In some examples, in a group of first side first adapter units 300a, in the second direction D2, the first second plug order adapter line 313b can connect a second first connection terminal and a first second connection terminal; the second second plug order adapter line 313b can connect a fourth first connection terminal and a third second connection terminal; the third second plug order adapter line 313b can connect a sixth first connection terminal and a fifth second connection terminal; the fourth second plug order adapter line 313b can connect a twelfth first connection terminal and an eleventh second connection terminal; the fifth second plug order adapter line 313b can connect a fourteenth first connection terminal and a thirteenth second connection terminal; and the sixth second plug order adapter line 313b can connect a sixteenth first connection terminal and a fifteenth second connection terminal.

[0252] In some examples, in a group of first side first adapter units 300a, in the second direction D2, the first first order adapter line 314 can connect a seventh first connection terminal and a seventh second connection terminal; the second first order adapter line 314 can connect an eighth first connection terminal and an eighth second connection terminal; the third first order adapter line 314 can connect a ninth first connection terminal and a ninth second connection terminal; the fourth first order adapter line 314 can connect a tenth first connection terminal and a tenth second connection terminal; the fifth first order adapter line 314 can connect a seventeenth first connection terminal and a seventeenth second connection terminal; the sixth first order adapter line 314 can connect an eighteenth first connection terminal and an eighteenth second connection terminal; the seventh first order adapter line 314 can connect a nineteenth first connection terminal and a nineteenth second connection terminal; and the eighth first order adapter line 314 can connect a twentieth first connection terminal and a twentieth second connection terminal.

[0253] In some examples, as shown in FIG. 31, the sub-pixel arrangement of the display region is as shown in FIG. 4, the sub-pixel arrangement sequence of the pixel units in the odd rows of the display region is taken as RGBG, and twenty data signals (for example, the data signals with serial numbers n-3 to n+16) that have not been adjusted by interleaving are taken as examples for description. The twenty data lines can be arranged along the second direction D1, and the data line connected to the data line with serial number n-3 to the data line with serial number n-1 can be inserted between the data line with serial number n+1 to the data line with serial number n+16 in a manner of inserting one data line every four data lines (i.e., a 4-insert-1 manner). For example, the data line with serial number n-1 can be inserted between the data line with serial number n+4 and the data line with serial number n+5, the data line with serial number n-2 can be inserted between the data line with serial number n+8 and the data line with serial number n+9, and the data line with serial number n-3 can be inserted between the data line with serial number n+12 and the data line with serial number n+13. The minimum cycle number of the data signals obtained by adjusting in the 4-insert-1 manner is 20. Taking the sub-pixel arrangement sequence of the pixel units in one row as RGBG, the sub-pixel cycle corresponding to the twenty data lines obtained by the 4-insert-1 manner is: GRGB GBRG BGGR GBGR RGBG. Taking the sub-pixel arrangement sequence of the pixel units in one row as BGRG, the sub-pixel cycle corresponding to the twenty data lines obtained by the 4-insert-1 manner can be: GBGR GRBG RGGB GRGB BGRG.

[0254] In some examples, the plurality of data contact pads can provide data signals to the sub-pixels of different rows of pixel units of the display region in different time periods. In a first time period, as shown in FIG. 30, the corresponding sub-pixel cycle of the data signals transmitted by the plurality of data contact pads along the second direction D2 can be: GRGB GBRG BGGR GBGR RGBG. After the multiplexed data signals pass through the plurality of groups of first-side first switching units 300a, the minimum cycle number of the data signals is still 20, and the corresponding sub-pixel cycle of the twenty multiplexed data signals along the second direction D2 can be: RGBG BGRG BGRG BGRG RGBG. In a second time period, the corresponding sub-pixel cycle of the data signals transmitted by the plurality of data contact pads along the second direction D2 can be: GBGR GRBG RGGB GRGB BGRG. After the data signals output by the first connection ends 311 of the plurality of groups of first-side first switching units 300a pass through the plurality of groups of first-side first switching units 300a, the corresponding sub-pixel cycle of the data signals output by the first connection ends 311 of the plurality of groups of first-side first switching units 300a can be: BGRG RGBG RGBG RGBG BGRG.

[0255] FIG. 32 is a plan view of a first set of test circuits corresponding to the first set of first adapter units shown in FIG. 30. In some examples, as shown in FIG. 32, a first set of test circuits is connected to twenty third data leads connected to the first set of first adapter units. The first set of test circuits can include five first test circuits 401 and five second test circuits 402. The first test circuit 401, the second test circuit 402, the first test circuit 401, the second test circuit 402, the first test circuit 401, the second test circuit 402, the first test circuit 401, and the second test circuit 402 can be arranged in the second direction D2 in sequence.

[0256] In some examples, the test data signals provided by the test circuits at different time periods can be different during the testing stage. The test circuits can provide corresponding test data signals according to the rule of the display area scanning line by line. For example, for the odd row pixel units, the first set of test circuits can provide corresponding test data signals to the plurality of data leads in the second direction D2 according to the cyclic order of RGBG BGRG BGRG BGRG RGBG; for the even row pixel units, the first set of test circuits can provide corresponding test data signals to the plurality of data leads in the second direction D2 according to the cyclic order of BGRG RGBG RGBG RGBG BGRG. Other descriptions of the test circuits can refer to the descriptions of the foregoing embodiments, and thus will not be described here.

[0257] FIG. 33 is a schematic view of a set of second-side first adapter units according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 33, a set of second-side first adapter units 300b can include twenty first connection ends 311, twenty second connection ends 312, and twenty first adapter lines. Within the set of second-side first adapter units 300b, the twenty first connection ends 311 can be arranged in sequence in the reverse direction of the second direction D2, for example, the first arrangement sequence number of the twenty first connection ends 311 arranged in sequence in the reverse direction of the second direction D2 can correspond to 1-20. The twenty first connection ends 311 can be connected with twenty third data lead-out lines arranged in sequence. Among them, the first, third, fifth, seventh, ninth, eleventh, thirteenth, fifteenth, seventeenth, and nineteenth first connection ends are connected with the third data lead-out lines located in the first gate metal layer, and the second, fourth, sixth, eighth, tenth, twelfth, fourteenth, sixteenth, eighteenth, and twentieth first connection ends are connected with the third data lead-out lines located in the second gate metal layer.

[0258] In some examples, within the set of second-side first adapter units 300b, the twenty second connection ends 312 can be arranged in sequence in the reverse direction of the second direction D2, for example, the second arrangement sequence number of the twenty second connection ends 312 arranged in sequence in the reverse direction of the second direction D2 can correspond to 1-20. The twenty first adapter lines can include eight first-order adapter lines 314, six first-order insertion adapter lines 313a, and six second-order insertion adapter lines 313b.

[0259] FIG. 34 is a schematic view of the insertion principle of the data signals transmitted by the second connection ends of the set of second-side first adapter units shown in FIG. 33. In some examples, as shown in FIG. 34, taking the sub-pixel arrangement sequence of a row of pixel units as RGBG as an example, the sub-pixel cycle corresponding to the twenty data lines obtained by the 4-in-1 mode is: RGBG RGGB GRBG BGRG GBGR. Taking the sub-pixel arrangement sequence of a row of pixel units as BGRG as an example, the sub-pixel cycle corresponding to the twenty data lines obtained by the 4-in-1 mode is: BGRG BGGR GBRG RGBG GRGB.

[0260] In some examples, the plurality of data contact pads can provide data signals to sub-pixels of different row pixel units of the display region in different time periods. In a first time period, as shown in FIG. 33, the data signals provided by the plurality of data contact pads can correspond to a sub-pixel cycle in the reverse direction of the second direction D2 as RGBG RGGB GRBG BGRG GBGR. After the plurality of groups of the second-side first conversion units 300b, the minimum cycle number of the data signals can still be 20, and the twenty data signals can correspond to a sub-pixel cycle in the reverse direction of the second direction as GRGB GRGB GRGB GBGR GBGR. In a second time period, the data signals provided by the plurality of data contact pads can correspond to a sub-pixel cycle in the reverse direction of the second direction D2 as BGRG BGGR GBRG RGBG GRGB. After the plurality of groups of the second-side first conversion units 300b, the data signals output by the first connection ends 311 of the plurality of groups of the second-side first conversion units 300b can correspond to a sub-pixel cycle as GBGR GBGR GBGR GRGB GRGB.

[0261] FIG. 35 is a plan view of a second group of test circuits according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 35, the second group of test circuits can be connected to the twenty third data leads 263 connected to the plurality of groups of the second-side first conversion units. The second group of test circuits can include five first test circuits 401 and five second test circuits 402. In some examples, the first test circuit 401, the second test circuit 402, the first test circuit 401, the second test circuit 402, the first test circuit 401, the second test circuit 402, the first test circuit 401, the second test circuit 402, and the first test circuit 401 can be arranged in the reverse direction of the second direction D2.

[0262] In some examples, the test data signals provided by the test circuits in different time periods can be different in the test stage. The test circuits can provide corresponding test data signals according to the rule of the row-by-row scanning of the display region. For example, for the odd row pixel units, the second group of test circuits can provide corresponding test data signals to the plurality of data leads in the reverse direction of the second direction D2 according to the cycle order of GRGB GRGB GRGB GBGR GBGR; for the even row pixel units, the second group of test circuits can provide corresponding test data signals to the plurality of data leads in the reverse direction of the second direction D2 according to the cycle order of GBGR GBGR GBGR GRGB GRGB. The remaining descriptions of the test circuits according to the present example can be referred to the descriptions of the foregoing embodiments, and thus will not be described herein.

[0263] FIGS. 36A-36C are schematic diagrams of connection manners of a plurality of first adapter units according to some embodiments of the present disclosure. FIGS. 36A-36C are described by taking the sub-pixel arrangement manner of the display area as shown in FIG. 4 as an example.

[0264] In some examples, as shown in FIG. 36A, in the second direction D2, the first insertion adapter line 313a can connect the first first connection end 311 and the fourth second connection end 312; the first second insertion adapter line 313b can connect the second first connection end 311 and the first second connection end 312; the second second insertion adapter line 313b can connect the third first connection end 311 and the second second connection end 312; and the third second insertion adapter line 313b can connect the fourth first connection end 311 and the third second connection end 312. The orthographic projection of the first insertion adapter line 313a on the substrate and the orthographic projection of the three second insertion adapter lines 313b on the substrate both exist overlapping. In some examples, the first insertion adapter line 313a can be located in the first source-drain metal layer, and the three second insertion adapter lines 313b can be located in the second source-drain metal layer. However, the present embodiment is not limited thereto. In other examples, the first insertion adapter line can be located in the second source-drain metal layer, and the second insertion adapter line can be located in the first source-drain metal layer.

[0265] In some examples, as shown in FIG. 36A, when the data signals transmitted by the second connection ends 312 are configured to correspond to GBGR in turn, the data signals transmitted by the first connection ends 311 are configured to correspond to RGBG in turn after passing through the four first adapter lines. In this example, the first adapter unit can be configured to make the data signals corresponding to the first sub-pixel (for example, the red sub-pixel R) and the second sub-pixel (for example, the blue sub-pixel B) be transmitted by the data lead-out lines located in the second gate metal layer (or the first gate metal layer), and make the data signals corresponding to the third sub-pixel (for example, the green sub-pixel G) be transmitted by the data lead-out lines located in the first gate metal layer (or the second gate metal layer), thereby ensuring the uniformity of signal transmission.

[0266] In some examples, as shown in FIG. 36B, in the second direction D2, the first plug sequence wire 313a can connect the first first connection end 311 and the third second connection end 312; the second plug sequence wire 313b can connect the third first connection end 311 and the first second connection end 312; the first first sequence wire 314 can connect the second first connection end and the second second connection end; and the second first sequence wire 314 can connect between the fourth first connection end and the fourth second connection end. The orthogonal projection of the first first sequence wire 314 on the substrate has an overlap with the orthogonal projection of the first plug sequence wire 313a and the second plug sequence wire 313b on the substrate. The orthogonal projection of the second first sequence wire 314 on the substrate has no overlap with the orthogonal projection of the first plug sequence wire 313a and the second plug sequence wire 313b on the substrate.

[0267] In some examples, as shown in FIG. 36B, the first plug sequence wire 313a can be located in the first source-drain metal layer, and the second plug sequence wire 313b can be located in the second source-drain metal layer. The first first sequence wire 314 can be located in the first gate metal layer. The first connection electrode of the first connection end 311 connected by the first first sequence wire 314 can be located in the first source-drain metal layer, and the second connection electrode can be located in the first gate metal layer. The third connection electrode of the second connection end 312 connected by the first first sequence wire 314 can be located in the first source-drain metal layer, and the fourth connection electrode can be located in the first gate metal layer. The second connection electrode of the first connection end 311 and the fourth connection electrode of the second connection end 312 connected by the first first sequence wire 314 can be an integrated structure connected with each other. The second first sequence wire 314 can be located in the second source-drain metal layer. However, the present embodiment is not limited thereto. In other examples, the first plug sequence wire can be located in the second source-drain metal layer, and the second plug sequence wire can be located in the first source-drain metal layer.

[0268] In some examples, as shown in FIG. 36B, when the data signal transmitted by the second connection end 312 is configured to correspond to BGRG in turn, after passing through the four first sequence wires, the data signal transmitted by the first connection end 311 is configured to correspond to RGBG in turn. The present example can make the data signal corresponding to the first sub-pixel (for example, the red sub-pixel R) and the second sub-pixel (for example, the blue sub-pixel B) transmitted by the data lead-out line located in the second gate metal layer (or the first gate metal layer), and the data signal corresponding to the third sub-pixel (for example, the green sub-pixel G) transmitted by the data lead-out line located in the first gate metal layer (or the second gate metal layer), thereby ensuring the uniformity of signal transmission.

[0269] In some examples, as shown in FIG. 36C, in the second direction D2, the first insertion sequence wire 313a can connect the first first connection end 311 and the fourth second connection end 312; the first second insertion sequence wire 313b can connect the third first connection end 311 and the first second connection end 312; the second second insertion sequence wire 313b can connect the fourth first connection end 311 and the third second connection end 312; and the first sequence wire 314 can connect the second first connection end and the second second connection end.

[0270] In some examples, as shown in FIG. 36C, the first sequence wire 314 can have an overlap with the first insertion sequence wire 313a and the first second insertion sequence wire 313b in the orthographic projection of the substrate, and can not have an overlap with the second second insertion sequence wire 313b in the orthographic projection of the substrate. The first insertion sequence wire 313a can have an overlap with both of the second insertion sequence wires 313b in the orthographic projection of the substrate. In some examples, the first insertion sequence wire 313a can be located in the first source-drain metal layer, the two second insertion sequence wires 313b can be located in the second source-drain metal layer, and the first sequence wire 314 can be located in the first gate metal layer. However, the present embodiment is not limited thereto.

[0271] FIG. 37 is another arrangement of sub-pixels of a display area according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 37, each pixel unit of the display area can include one first sub-pixel 15 emitting light of a first color, one second sub-pixel 16 emitting light of a second color, and one third sub-pixel 17 emitting light of a third color. The plurality of sub-pixels can be arranged in an array along a first direction D1 and a second direction D2. The plurality of first sub-pixels 15 can be arranged in a column along the first direction D1, the plurality of second sub-pixels 16 can be arranged in a column along the first direction D1, and the plurality of third sub-pixels 17 can be arranged in a column along the first direction D1. The first sub-pixels 15, the third sub-pixels 17, and the second sub-pixels 16 can be periodically arranged along the second direction D2. In the present example, the first sub-pixels 15 can be red sub-pixels (R), the second sub-pixels 16 can be blue sub-pixels (B), and the third sub-pixels 17 can be green sub-pixels (G); and the plurality of sub-pixels can adopt a Real RGB arrangement.

[0272] FIGS. 38A-38F are schematic diagrams of connection manners of a plurality of first adapter units according to some embodiments of the present disclosure. FIGS. 38A-38F are described by taking the sub-pixel arrangement of the display area as shown in FIG. 37 as an example. In some examples, a group of first adapter units of the first border area can adopt the connection manner of three first adapter units as shown in at least one of FIGS. 38A-38F. The transmission sequence of the data signals of the data contact pads connected by the second connection ends of the plurality of groups of first adapter units can be obtained by referring to the 1-in-1 or multi-in-1 manner of the foregoing embodiments.

[0273] In some examples, as shown in FIG. 38A, in the second direction D2, the three first connection ends 311 and the three second connection ends 312 can be connected one by one through three first sequential adapter lines 314. When the data signals transmitted by the second connection ends 312 are configured to correspond to RGB in turn, the data signals transmitted by the first connection ends 311 are configured to correspond to RGB in turn after passing through the three first sequential adapter lines 314. For example, the three first sequential adapter lines 314 can all be located in the second source-drain metal layer.

[0274] In some examples, as shown in FIG. 38B, in the second direction D2, the three first connection ends 311 and the three second connection ends 312 can be connected in turn through a first sequential adapter line 314, a first plug-in sequential adapter line 313a, and a second plug-in sequential adapter line 313b. Among them, the first sequential adapter line 314 can connect the first first connection end 311 and the first second connection end 312, the first plug-in sequential adapter line 313a can connect the second first connection end 311 and the third second connection end 312, and the second plug-in sequential adapter line 313b can connect the third first connection end 311 and the second second connection end 312. The first plug-in sequential adapter line 313a and the second plug-in sequential adapter line 313b can overlap in the orthographic projection of the substrate. For example, the first sequential adapter line 314 and the second plug-in sequential adapter line 313b can be located in the second source-drain metal layer, and the first plug-in sequential adapter line 313a can be located in the first source-drain metal layer. When the data signals transmitted by the three second connection ends 312 are configured to correspond to RBG in turn, the data signals transmitted by the three first connection ends 311 are configured to correspond to RGB in turn after passing through the three adapter lines.

[0275] In some examples, as shown in FIG. 38C, in the second direction D2, the three first connection terminals 311 and the three second connection terminals 312 can be connected in sequence by a first plug sequence connecting line 313a, a second plug sequence connecting line 313b and a first order connecting line 314. Among them, the first plug sequence connecting line 313a can connect the first first connection terminal and the second second connection terminal, the second plug sequence connecting line 313b can connect the second first connection terminal and the first second connection terminal, and the first order connecting line 314 can connect the third first connection terminal and the third second connection terminal. The first plug sequence connecting line 313a and the second plug sequence connecting line 313b can overlap in the orthographic projection of the substrate. For example, the first order connecting line 314 and the second plug sequence connecting line 313b can be located in the second source-drain metal layer, and the first plug sequence connecting line 313a can be located in the first source-drain metal layer. When the data signals transmitted by the three second connection terminals 312 are configured to correspond to GRB in sequence, after passing through the three first connecting lines, the data signals transmitted by the three first connection terminals 311 are configured to correspond to RGB in sequence.

[0276] In some examples, as shown in FIG. 38D, in the second direction D2, the three first connection terminals 311 and the three second connection terminals 312 can be connected in sequence by a first plug sequence connecting line 313a and two second plug sequence connecting lines 313b. Among them, the first plug sequence connecting line 313a can connect the first first connection terminal and the three second connection terminals, the first second plug sequence connecting line 313b can connect the second first connection terminal and the first second connection terminal, and the second second plug sequence connecting line 313b can connect the third first connection terminal and the second second connection terminal. The orthographic projection of the first plug sequence connecting line 313a in the substrate can overlap with the orthographic projection of the two second plug sequence connecting lines 313b in the substrate. For example, the first plug sequence connecting line 313a can be located in the first source-drain metal layer, and the two second plug sequence connecting lines 313b can be located in the second source-drain metal layer. When the data signals transmitted by the three second connection terminals 312 are configured to correspond to GBR in sequence, after passing through the three first connecting lines, the data signals transmitted by the three first connection terminals 311 are configured to correspond to RGB in sequence.

[0277] In some examples, as shown in FIG. 38E, in the second direction D2, the three first connection terminals 311 and the three second connection terminals 312 can be connected in sequence by two first plug sequence wires 313a and one second plug sequence wire 313b. Among them, the first first plug sequence wire 313a can connect the first first connection terminal and the second second connection terminal, the second first plug sequence wire 313a can connect the second first connection terminal and the third second connection terminal, and the second plug sequence wire 313b can connect the third first connection terminal and the first second connection terminal. The second plug sequence wire 313b in the orthographic projection of the substrate overlaps with the orthographic projection of the two first plug sequence wires 313a. For example, the two first plug sequence wires 313a can be located in the second source-drain metal layer, and the second plug sequence wire 313b can be located in the first source-drain metal layer. When the data signals transmitted by the three second connection terminals 312 are configured to correspond to BRG in sequence, after passing through the three first wires, the data signals transmitted by the three first connection terminals 311 are configured to correspond to RGB in sequence.

[0278] In some examples, as shown in FIG. 38F, in the second direction D2, the three first connection terminals 311 and the three second connection terminals 312 can be connected in sequence by one first plug sequence wire 313a, one first sequence wire 314 and one second plug sequence wire 313b. Among them, the first plug sequence wire 313a can connect the first first connection terminal and the third second connection terminal, the first sequence wire 314 can connect the second first connection terminal and the second second connection terminal, and the second plug sequence wire 313b can connect the third first connection terminal and the first second connection terminal. The orthographic projection of the first plug sequence wire 313a in the substrate overlaps with the orthographic projection of the first sequence wire 314 and the second plug sequence wire 313b in the substrate. For example, the first plug sequence wire 313a can be located in the second source-drain metal layer, the second plug sequence wire 313b can be located in the first source-drain metal layer, and the first sequence wire 314 can be located in the first gate metal layer. When the data signals transmitted by the three second connection terminals 312 are configured to correspond to BGR in sequence, after passing through the three first wires, the data signals transmitted by the three first connection terminals 311 are configured to correspond to RGB in sequence.

[0279] The display substrate provided by the embodiment can connect a plurality of data lead-out lines and a plurality of data contact pads by a plurality of first transfer units, adjust the sequence of data signals transmitted by the data contact pads by the plurality of first transfer units, and adjust the sequence of data signals by a plurality of second transfer units, thereby avoiding jumper design in the second fan-out area, reducing the adverse effects of jumper design, and improving the reliability of the display substrate.

[0280] The embodiment also provides a display substrate, comprising a substrate, a plurality of sub-pixels, a plurality of first data lines, a plurality of second data lines, a plurality of data connection lines, a plurality of data lead-out lines, and a plurality of test circuits. The substrate comprises a display area and a first frame area located at one side of the display area along a first direction, the first frame area comprising a first signal access area and a trace lead-out area located between the first signal access area and the display area. The plurality of sub-pixels are arranged at one side of the substrate and located in the display area. The plurality of first data lines, the plurality of second data lines, and the plurality of data connection lines are located in the display area; the plurality of first data lines and the plurality of second data lines are configured to provide data signals for the plurality of sub-pixels, and the plurality of first data lines are connected with the plurality of data connection lines. The plurality of data lead-out lines are located in the trace lead-out area, and the plurality of data lead-out lines are connected with the plurality of second data lines and the plurality of data connection lines. The plurality of test circuits are located in the trace lead-out area and arranged in sequence along a second direction, each test circuit is connected with m continuously arranged data lead-out lines, the second direction intersects the first direction; m is an integer greater than 1. Each test circuit comprises a first test circuit and a second test circuit, a and b are both integers greater than 0, and twice the sum of a and b is equal to m. The first test circuit comprises a first test transistor, a second test transistor, and a third test transistor; a gate of the first test transistor is connected with a first test control line, a first electrode of the first test transistor is connected with a first test data line, a gate of the second test transistor is connected with a second test control line, a first electrode of the second test transistor is connected with a second test data line, a second electrode of the first test transistor and a second electrode of the second test transistor are connected with the same data lead-out line; a gate of the third test transistor is connected with a third test control line, and a first electrode of the third test transistor is connected with a third test data line. The second test circuit comprises a fourth test transistor, a fifth test transistor, and a sixth test transistor; a gate of the fourth test transistor is connected with the second test control line, a first electrode of the fourth test transistor is connected with the first test data line, a gate of the fifth test transistor is connected with the first test control line, a first electrode of the fifth test transistor is connected with the second test data line, a second electrode of the fourth test transistor and a second electrode of the fifth test transistor are connected with the same data lead-out line; a gate of the sixth test transistor is connected with the third test control line, and a first electrode of the third test transistor is connected with the third test data line; a second electrode of the first test transistor, a second electrode of the third test transistor, a second electrode of the fourth test transistor, and a second electrode of the sixth test transistor are connected with different data lead-out lines.

[0281] The embodiment can adjust the transmission sequence of the test data signal by setting multiple groups of test circuits, avoid jumper design in the second fan-out area, reduce the defects caused by the jumper design, and improve the reliability of the display substrate.

[0282] In some example embodiments, the first test transistor, the second test transistor and the third test transistor of the first test circuit are arranged along the first direction; the fourth test transistor, the fifth test transistor and the sixth test transistor of the second test circuit are arranged along the first direction. The first test transistor and the fourth test transistor are arranged in alignment in the second direction, the second test transistor and the fifth test transistor are arranged in alignment in the second direction, and the third test transistor and the sixth test transistor are arranged in alignment in the second direction.

[0283] In some example embodiments, m is 8; each group of test circuits includes two first test circuits and two second test circuits; wherein one first test circuit, two second test circuits and one first test circuit are arranged along the second direction.

[0284] In some example embodiments, m is 12; each group of test circuits includes three first test circuits and three second test circuits; wherein one first test circuit, two second test circuits, two first test circuits and one second test circuit are arranged along the second direction; or one first test circuit, one second test circuit, one first test circuit, two second test circuits and one first test circuit are arranged in the opposite direction along the second direction.

[0285] In some example embodiments, m is 16; each group of test circuits includes four first test circuits and four second test circuits; wherein one first test circuit, two second test circuits, one first test circuit, one second test circuit, two first test circuits and one second test circuit are arranged along the second direction; or one first test circuit, one second test circuit, one first test circuit, two second test circuits, one first test circuit, one second test circuit and one first test circuit are arranged in the opposite direction along the second direction.

[0286] In some example embodiments, m is 20; each group of test circuits comprises five first test circuits and five second test circuits; wherein one first test circuit, two second test circuits, one first test circuit, one second test circuit, one first test circuit, one second test circuit, two first test circuits and one second test circuit are arranged along the second direction; or one first test circuit, one second test circuit, one first test circuit, one second test circuit, one first test circuit, two second test circuits, one first test circuit, one second test circuit and one first test circuit are arranged along the reverse direction of the second direction.

[0287] The related description of the present embodiment can refer to the description of the foregoing embodiments, and thus will not be repeated here.

[0288] FIG. 39 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 39, the display substrate 910 can be an OLED display substrate. The display device 91 can be an OLED display device, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or any product or component having a display function. However, the present embodiment is not limited thereto.

[0289] In the description of the present specification, the description referring to the terms “one embodiment”, “some embodiments”, “an example”, or “some examples” and the like means that the specific feature, structure, material or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. The illustrative representation of the above terms in the present specification does not necessarily refer to the same embodiment or example. Moreover, the specific feature, structure, material or characteristic described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, the person skilled in the art can combine and combine the different embodiments or examples described in the present specification and the features of the different embodiments or examples, without contradiction.

[0290] Although the embodiments of the present application have been shown and described above, it is to be understood that the above-described embodiments are exemplary, and are not to be construed as limiting the present application, and the person skilled in the art can make changes, modifications, replacements and variations to the above-described embodiments within the scope of the present application.

Claims

1. A display substrate, comprising: a substrate comprising a display area and a first bezel area located at one side of the display area along a first direction, the first bezel area comprising a first signal access area and a trace lead-out area located between the first signal access area and the display area; a plurality of sub-pixels located at one side of the substrate and in the display area; a plurality of first data lines, a plurality of second data lines, and a plurality of data connection lines located in the display area, the plurality of first data lines and the plurality of second data lines configured to provide data signals to the plurality of sub-pixels, the plurality of first data lines connected to the plurality of data connection lines; a plurality of data lead-out lines located in the trace lead-out area; a plurality of data contact pads located in the first signal access area; a plurality of first adapter units and a plurality of second adapter units located in the trace lead-out area, the plurality of first adapter units located at a side of the plurality of second adapter units away from the display area, the plurality of first adapter units arranged along a second direction, the plurality of second adapter units arranged along the second direction, the second direction intersecting the first direction; wherein the plurality of data lead-out lines are connected to the plurality of data contact pads through the plurality of first adapter units, and are connected to the plurality of second data lines and the plurality of data connection lines through the plurality of second adapter units, so that the order of the data signals provided by the plurality of data contact pads matches the order of the data signals required by the plurality of second data lines and the plurality of data connection lines arranged along the second direction. 2.The display substrate of claim 1, wherein, Each first adapter unit comprises m first connection ends, m second connection ends, and m first adapter lines, each first adapter line connected between one first connection end and one second connection end, each first connection end connected to one data lead-out line, and each second connection end connected to one data contact pad, the m first connection ends arranged along the second direction and corresponding to different first arrangement serial numbers, and the m second connection ends arranged along the second direction and corresponding to different second arrangement serial numbers. The m first adapter lines in each first adapter unit comprise a first insertion sequence adapter line, the first arrangement serial number corresponding to the first connection end connected by each first insertion sequence adapter line being different from the second arrangement serial number corresponding to the second connection end connected by each first insertion sequence adapter line, wherein m and a are both integers greater than 1, and m is greater than or equal to a. 3.The display substrate of claim 2, wherein, The a first insertion sequence adapter lines in each first adapter unit comprise a1 first insertion sequence adapter lines and a2 second insertion sequence adapter lines, a1 and a2 are both integers greater than 0, and the sum of a1 and a2 is a. The first arrangement serial number corresponding to the first connection end connected by the first insertion sequence adapter line is less than the second arrangement serial number corresponding to the second connection end connected by the first insertion sequence adapter line. The first arrangement serial number corresponding to the first connection end connected by the second insertion sequence adapter line is greater than the second arrangement serial number corresponding to the second connection end connected by the second insertion sequence adapter line. 4.The display substrate of claim 3, wherein, The difference between the second arrangement serial number corresponding to the second connecting end connected by the first plug-in sequence adapter line and the first arrangement serial number corresponding to the first connecting end connected by the first plug-in sequence adapter line is greater than or equal to the difference between the first arrangement serial number corresponding to the first connecting end connected by the second plug-in sequence adapter line and the second arrangement serial number corresponding to the second connecting end connected by the second plug-in sequence adapter line. 5.The display substrate of claim 3, wherein, The first plug-in sequence adapter line and at least one second plug-in sequence adapter line overlap in the orthographic projection on the substrate. 6.The display substrate according to any one of claims 3 to 5, wherein The m first adapter lines in each group of first adapter units further include b first sequence adapter lines, each first sequence adapter line has the same first arrangement serial number corresponding to the first connecting end connected by the first sequence adapter line and the second arrangement serial number corresponding to the second connecting end connected by the first sequence adapter line, b is an integer greater than 1, and b is less than or equal to a. 7.The display substrate of claim 6, wherein, The b first sequence adapter lines and the first plug-in sequence adapter line are in the same layer structure, or at least one first sequence adapter line is located on the side close to the substrate of the first plug-in sequence adapter line and the second plug-in sequence adapter line. 8.The display substrate of claim 6, wherein, M is 8. Each group of first adapter units includes eight first connecting ends, eight second connecting ends, and eight first adapter lines. The eight first connecting ends are arranged in sequence along the second direction. The eight second connecting ends are arranged in sequence along the second direction and located on the side close to the first signal access area of the eight first connecting ends. The eight first adapter lines include two first plug-in sequence adapter lines, two second plug-in sequence adapter lines, and four first sequence adapter lines. The first plug-in sequence adapter line is configured to connect the i th first connecting end and the i+1 th second connecting end. The second plug-in sequence adapter line is configured to connect the i+1 th first connecting end and the i th second connecting end. The value of i includes 1 and 5. 9.The display substrate of claim 8, wherein, One pixel unit located in the display area includes one first sub-pixel emitting first color light, one second sub-pixel emitting second color light, and two third sub-pixels emitting third color light. The plurality of data contact pads are configured to provide data signals to the sub-pixels of the e th row of pixel units in the display area in a first time period and to the sub-pixels of the e+1 th row of pixel units in the display area in a second time period, where e is an integer greater than 0. In the first time period, the data signals transmitted by the eight second connecting ends in each group of first adapter units are configured to correspond to the third sub-pixel, the first sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the first sub-pixel, and the third sub-pixel in sequence, or are configured to correspond to the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, and the first sub-pixel in sequence. In the second time period, the data signals transmitted by the eight second connection terminals in each group of first switching units are configured to correspond to the third sub-pixel, the second sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the second sub-pixel and the third sub-pixel in sequence, or are configured to correspond to the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel and the second sub-pixel in sequence. 10.The display substrate of claim 6, wherein, m is 12; Each group of first switching units comprises twelve first connection terminals, twelve second connection terminals and twelve first switching lines. The twelve first connection terminals are arranged in sequence along the second direction. The twelve second connection terminals are arranged in sequence along the second direction and located on the side of the twelve first connection terminals close to the first signal access area. The twelve first switching lines comprise four first plug sequence switching lines, four second plug sequence switching lines and four first sequence switching lines. The first plug sequence switching line is configured to connect the i-th first connection terminal and the i+1-th second connection terminal. The second plug sequence switching line is configured to connect the i+1-th first connection terminal and the i-th second connection terminal. The value of i includes 1, 3, 7 and 9. 11.The display substrate of claim 10, wherein, One pixel unit located in the display area comprises one first sub-pixel emitting first color light, one second sub-pixel emitting second color light and two third sub-pixels emitting third color light. The plurality of data contact pads are configured to provide data signals to the sub-pixels of the e-th row of pixel units in the display area in a first time period and to the sub-pixels of the e+1-th row of pixel units in the display area in a second time period, where e is an integer greater than 0. In the first time period, the data signals transmitted by the twelve second connection terminals in each group of first switching units are configured to correspond to the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the first sub-pixel, the second sub-pixel and the third sub-pixel in sequence, or are configured to correspond to the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the second sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel and the first sub-pixel in sequence. In the second time period, the data signals transmitted by the twelve second connection terminals in each group of first switching units are configured to correspond to the third sub-pixel, the second sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the second sub-pixel and the third sub-pixel in sequence, or are configured to correspond to the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the first sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel and the second sub-pixel in sequence. 12.The display substrate of claim 6, wherein, m is 16; Each group of first switching units comprises sixteen first connection ends, sixteen second connection ends, and sixteen first switching lines; the sixteen first connection ends are arranged in sequence along the second direction, the sixteen second connection ends are arranged in sequence along the second direction and located on the side of the sixteen first connection ends close to the first signal access area, and the sixteen first switching lines comprise four first plug sequence switching lines, four second plug sequence switching lines, and eight first order switching lines; The first plug sequence switching line is configured to connect the i-th first connection end and the i+1-th second connection end; The second plug sequence switching line is configured to connect the i+1-th first connection end and the i-th second connection end; Wherein, the value of i includes 1, 3, 9, and 11. 13.The display substrate of claim 12, wherein, One pixel unit located in the display area comprises a first sub-pixel emitting first color light, a second sub-pixel emitting second color light, and two third sub-pixels emitting third color light; The plurality of data contact pads are configured to provide data signals to the sub-pixels of the e-th row of pixel units in the display area in a first time period and to the sub-pixels of the e+1-th row of pixel units in the display area in a second time period, where e is an integer greater than 0; In the first time period, the data signals transmitted by the sixteen second connection ends in each group of first switching units are configured to correspond to the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, and the third sub-pixel in sequence, or are configured to correspond to the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, and the first sub-pixel in sequence; In the second time period, the data signals transmitted by the sixteen second connection ends in each group of first switching units are configured to correspond to the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, and the third sub-pixel in sequence, or are configured to correspond to the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, and the second sub-pixel in sequence. m is 20; 14.The display substrate of claim 6, wherein, ​ Each group of first switching units comprises twenty first connection ends, twenty second connection ends and twenty first switching lines; the twenty first connection ends are arranged in sequence along the second direction, the twenty second connection ends are arranged in sequence along the second direction and located on the side of the twenty first connection ends close to the first signal access area, and the twenty first switching lines comprise six first plug sequence switching lines, six second plug sequence switching lines and eight first order switching lines; The first plug sequence switching line is configured to connect the i-th first connection end and the i+1-th second connection end; The second plug sequence switching line is configured to connect the i+1-th first connection end and the i-th second connection end; Wherein, the value of i includes 1, 3, 5, 11, 13 and 15. 15.The display substrate of claim 14, wherein, One pixel unit located in the display area comprises a first sub-pixel emitting first color light, a second sub-pixel emitting second color light and two third sub-pixels emitting third color light; The plurality of data contact pads are configured to provide data signals to the sub-pixels of the e-th row of pixel units in the display area in a first time period and to the sub-pixels of the e+1-th row of pixel units in the display area in a second time period, where e is an integer greater than 0; In the first time period, the data signals transmitted by the twenty second connection ends in each group of first switching units are configured to correspond to the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the second sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel and the third sub-pixel in sequence; or, are configured to correspond to the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the second sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel and the first sub-pixel in sequence; In the second time period, the data signals transmitted by the twenty second connection ends in each group of first switching units are configured to correspond to the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the first sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel and the third sub-pixel in sequence; or, are configured to correspond to the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the first sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel and the second sub-pixel in sequence. 16.The display substrate of claim 2, wherein, One pixel unit located in the display region comprises: a first sub-pixel for emitting first color light, a second sub-pixel for emitting second color light, and two third sub-pixels for emitting third color light; The plurality of data lead-out lines connected with the first connection ends of the plurality of groups of first switching units comprises: a first group of data lead-out lines and a second group of data lead-out lines, the first group of data lead-out lines and the second group of data lead-out lines are located in different conductive layers and are arranged alternately along the second direction, the first group of data lead-out lines are configured to transmit data signals required by the third sub-pixels, and the second group of data lead-out lines are configured to transmit data signals required by the first sub-pixels and the second sub-pixels.

17. The display substrate of any one of claims 1-16, further comprising: The plurality of groups of test circuits are located in the lead-out region and are arranged in sequence along the second direction. The plurality of groups of test circuits are located on the side of the plurality of groups of first switching units away from the first signal access region in the first direction; one group of test circuits is connected with m data lead-out lines connected with one group of first switching units; the second direction intersects the first direction; Each group of test circuits comprises: a first test circuit and b second test circuits; the sum of a and b is twice m, and a and b are both integers greater than 0. The first test circuit comprises: a first test transistor, a second test transistor and a third test transistor; the gate of the first test transistor is connected with a first test control line, the first pole of the first test transistor is connected with a first test data line, the gate of the second test transistor is connected with a second test control line, the first pole of the second test transistor is connected with a second test data line, and the second pole of the first test transistor and the second pole of the second test transistor are connected with the same data lead-out line; the gate of the third test transistor is connected with a third test control line, and the first pole of the third test transistor is connected with a third test data line. The second test circuit comprises: a fourth test transistor, a fifth test transistor and a sixth test transistor; the gate of the fourth test transistor is connected with the second test control line, the first pole of the fourth test transistor is connected with the first test data line, the gate of the fifth test transistor is connected with the first test control line, the first pole of the fifth test transistor is connected with the second test data line, and the second pole of the fourth test transistor and the second pole of the fifth test transistor are connected with the same data lead-out line; the gate of the sixth test transistor is connected with the third test control line, and the first pole of the third test transistor is connected with the third test data line; the second pole of the first test transistor, the second pole of the third test transistor, the second pole of the fourth test transistor and the second pole of the sixth test transistor are connected with different data lead-out lines. 18.The display substrate of claim 17, wherein, The first test transistor, the second test transistor and the third test transistor of the first test circuit are arranged along the first direction; the fourth test transistor, the fifth test transistor and the sixth test transistor of the second test circuit are arranged along the first direction. The first test transistor and the fourth test transistor are arranged in alignment in the second direction, the second test transistor and the fifth test transistor are arranged in alignment in the second direction, and the third test transistor and the sixth test transistor are arranged in alignment in the second direction.

19. The display substrate of claim 17 or 18, wherein, m is 8; Each group of test circuits comprises two first test circuits and two second test circuits; wherein one first test circuit, two second test circuits and one first test circuit are arranged along the second direction. 20.The display substrate according to claim 17 or 18, wherein, m is 12; Each group of test circuits comprises three first test circuits and three second test circuits; wherein one first test circuit, two second test circuits, two first test circuits and one second test circuit are arranged along the second direction, or one first test circuit, one second test circuit, one first test circuit, two second test circuits and one first test circuit are arranged along the opposite direction of the second direction.

21. The display substrate of claim 17 or 18, wherein, m is 16; Each group of test circuits comprises four first test circuits and four second test circuits; wherein one first test circuit, two second test circuits, one first test circuit, one second test circuit, two first test circuits and one second test circuit are arranged along the second direction, or one first test circuit, one second test circuit, one first test circuit, two second test circuits, one first test circuit, one second test circuit and one first test circuit are arranged along the opposite direction of the second direction.

22. The display substrate of claim 17 or 18, wherein, m is 20; Each group of test circuits comprises five first test circuits and five second test circuits; wherein one first test circuit, two second test circuits, one first test circuit, one second test circuit, one first test circuit, one second test circuit, two first test circuits and one second test circuit are arranged along the second direction, or one first test circuit, one second test circuit, one first test circuit, one second test circuit, one first test circuit, two second test circuits, one first test circuit, one second test circuit and one first test circuit are arranged along the opposite direction of the second direction. The single pixel unit of the display area comprises c sub-pixels, m is k times of c, and k is an integer greater than 1. 23.The display substrate according to any one of claims 1 to 22, wherein 24. A display device comprising the display substrate according to any one of claims 1 to 23.

25. A display substrate comprising: a substrate comprising a display area and a first frame area located on one side of the display area along a first direction, the first frame area comprising a first signal access area and a wire leading-out area located between the first signal access area and the display area; a plurality of sub-pixels located on one side of the substrate and in the display area; a plurality of first data lines, a plurality of second data lines and a plurality of data connection lines located in the display area, the plurality of first data lines and the plurality of second data lines being configured to provide data signals to the plurality of sub-pixels, and the plurality of first data lines being connected to the plurality of data connection lines; ​ A plurality of data lead-out lines are located in the lead-out area, and are connected with the plurality of second data lines and the plurality of data connection lines; A plurality of test circuits are located in the lead-out area and are arranged in a second direction in sequence, each test circuit is connected with m continuously arranged data lead-out lines, the second direction is perpendicular to the first direction; m is an integer greater than 1; Each test circuit includes a first test circuit and a second test circuit, a and b are both integers greater than 0, and twice the sum of a and b is equal to m; The first test circuit includes a first test transistor, a second test transistor and a third test transistor; the gate of the first test transistor is connected with a first test control line, the first pole of the first test transistor is connected with a first test data line, the gate of the second test transistor is connected with a second test control line, the first pole of the second test transistor is connected with a second test data line, and the second pole of the first test transistor and the second pole of the second test transistor are connected with the same data lead-out line; the gate of the third test transistor is connected with a third test control line, and the first pole of the third test transistor is connected with a third test data line; The second test circuit includes a fourth test transistor, a fifth test transistor and a sixth test transistor; the gate of the fourth test transistor is connected with the second test control line, the first pole of the fourth test transistor is connected with the first test data line, the gate of the fifth test transistor is connected with the first test control line, the first pole of the fifth test transistor is connected with the second test data line, and the second pole of the fourth test transistor and the second pole of the fifth test transistor are connected with the same data lead-out line; the gate of the sixth test transistor is connected with the third test control line, and the first pole of the third test transistor is connected with the third test data line; the second pole of the first test transistor, the second pole of the third test transistor, the second pole of the fourth test transistor and the second pole of the sixth test transistor are connected with different data lead-out lines. 26.The display substrate of claim 25, wherein, The first test transistor, the second test transistor and the third test transistor of the first test circuit are arranged in the first direction; the fourth test transistor, the fifth test transistor and the sixth test transistor of the second test circuit are arranged in the first direction; The first test transistor and the fourth test transistor are arranged in alignment in the second direction, the second test transistor and the fifth test transistor are arranged in alignment in the second direction, and the third test transistor and the sixth test transistor are arranged in alignment in the second direction. m is 8; 27. The display substrate of claim 25, wherein, Each test circuit includes two first test circuits and two second test circuits; one first test circuit, two second test circuits and one first test circuit are arranged along the second direction. m is 12; 28.The display substrate of claim 25, wherein, ​ Each group of test circuits comprises three first test circuits and three second test circuits; wherein one first test circuit, two second test circuits, two first test circuits and one second test circuit are arranged along the second direction; or one first test circuit, one second test circuit, one first test circuit, two second test circuits and one first test circuit are arranged along the reverse direction of the second direction. 29.The display substrate of claim 25, wherein, m is 16; Each group of test circuits comprises four first test circuits and four second test circuits; wherein one first test circuit, two second test circuits, one first test circuit, one second test circuit, two first test circuits and one second test circuit are arranged along the second direction; or one first test circuit, one second test circuit, one first test circuit, two second test circuits, one first test circuit, one second test circuit and one first test circuit are arranged along the reverse direction of the second direction. 30.The display substrate of claim 25, wherein, m is 20; Each group of test circuits comprises five first test circuits and five second test circuits; wherein one first test circuit, two second test circuits, one first test circuit, one second test circuit, one first test circuit, one second test circuit, two first test circuits and one second test circuit are arranged along the second direction; or one first test circuit, one second test circuit, one first test circuit, one second test circuit, one first test circuit, two second test circuits, one first test circuit, one second test circuit and one first test circuit are arranged along the reverse direction of the second direction.

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