EC chip, multi-chip package, system and electronic device

Abstract

Embodiments of the present application provide an EC chip, a multi-chip package, a system and an electronic device. The EC chip of one embodiment comprises: a bus interface, configured to receive and transmit a data packet; one or more storage modules, configured to store at least part of replay protection-related data; and a processor, configured to parse the received data packet, and when a replay protection command is parsed from the data packet, execute a signature program to verify and execute the replay protection command. The EC chip of another embodiment comprises: a bus interface, configured to receive and transmit a data packet; one or more storage control modules, configured to access one or more external storage modules, the one or more external storage modules being configured to store at least part of replay protection-related data; and a processor, configured to parse the received data packet, and when a replay protection command is parsed from the data packet, execute a signature program to verify and execute the replay protection command.

Description

EC chip, package chip, system and electronic device

[0001] Cross-reference to Related Applications

[0002] The present application claims priority to the Chinese patent application No. 202410454376.3, filed on April 16, 2024, and entitled “EC chip, package chip, system and electronic device”, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the technical field of replay protection, in particular to an embedded controller (EC) chip, a package chip, a system and an electronic device. BACKGROUND

[0004] Replay attacks refer to an attack mode in which an attacker records legitimate communication data packets and then sends the recorded communication data packets again to deceive the system, so that the system mistakenly believes that the data packets are legitimate, thereby achieving the attack purpose. Replay protection monotonic counter (RPMC) can be used to detect replay attacks. For example, communication parties with RPMC record the same count value by means of the monotonic counter, the data sender adds the recorded count value as a variable to the data packet, encrypts and transmits the data packet on the bus. The data receiver must know the same variable and include it in the data verification algorithm to pass the authentication, thereby preventing replay attacks.

[0005] RPMC is an important function for computing devices such as personal computers. In the related art, an external Flash integrates the RPMC scheme, which communicates with the platform controller hub (PCH) through the serial peripheral interface (SPI). However, the external Flash is not necessary for computing devices such as notebook computers, and some notebook computers do not have an external Flash to reduce costs, which results in that some notebook computers do not have the RPMC function. How to enhance the security of computing devices without increasing the cost of computing devices has not yet been effectively solved. SUMMARY

[0006] In view of the above problems, the embodiments of the present application provide an EC chip, a package chip, a system and an electronic device to solve the above technical problems.

[0007] In a first aspect, an embodiment of the present application provides an EC chip, comprising: a bus interface configured to receive and send data packets; one or more storage modules configured to store at least part of replay protection related data; and a processor connected to the bus interface and the one or more storage modules, configured to parse the received data packets, and in a case that a replay protection command is parsed from the data packets, execute a signature program to verify and execute the replay protection command.

[0008] In a second aspect, an embodiment of the present application provides an EC chip, comprising: a bus interface configured to receive and send data packets; one or more storage control modules configured to access one or more external storage modules, the one or more external storage modules configured to store at least part of replay protection related data; and a processor connected to the bus interface and the one or more storage control modules, configured to parse the received data packets, and in a case that a replay protection command is parsed from the data packets, execute a signature program to verify and execute the replay protection command.

[0009] In a third aspect, an embodiment of the present application provides a packaged chip, comprising: one or more external storage modules; and the EC chip as described above.

[0010] In a fourth aspect, an embodiment of the present application provides a system, comprising: one or more external storage modules; and the EC chip as described above.

[0011] In a fifth aspect, an embodiment of the present application provides an electronic device, comprising: a device main body; and the EC chip as described above, or the packaged chip as described above, or the system as described above, arranged on the device main body.

[0012] These and other aspects of the present application will become more apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without any creative effort.

[0014] FIG. 1 shows a structural schematic diagram of an EC chip according to an embodiment of the present application.

[0015] FIG. 2 shows a structural schematic diagram of another EC chip according to an embodiment of the present application.

[0016] FIG. 3 shows a structural schematic diagram of another EC chip according to an embodiment of the present application.

[0017] FIG. 4a shows a structural schematic diagram of another EC chip according to an embodiment of the present application.

[0018] FIG. 4b shows a structure diagram of another EC chip according to an embodiment of the present application.

[0019] FIG. 4c shows a structure diagram of another EC chip according to an embodiment of the present application.

[0020] FIG. 4d shows a structure diagram of another EC chip according to an embodiment of the present application.

[0021] FIG. 5 shows a structure diagram of another EC chip according to an embodiment of the present application.

[0022] FIG. 6 shows a structure diagram of a sealing chip according to an embodiment of the present application.

[0023] FIG. 7 shows a flow chart of an exemplary root key binding process according to an embodiment of the present application.

[0024] FIG. 8 shows a flow chart of an exemplary signature key updating process according to an embodiment of the present application.

[0025] FIG. 9 shows a flow chart of an exemplary read replay protection monotonic counter value process according to an embodiment of the present application.

[0026] FIG. 10 shows a flow chart of an exemplary replay protection monotonic counter value increasing by 1 process according to an embodiment of the present application.

[0027] FIG. 11 shows a flow chart of an exemplary read RPMC parameter process according to an embodiment of the present application. DETAILED DESCRIPTION

[0028] The embodiments of the present application will be described in detail below with reference to the drawings, in which the same or similar components are denoted by the same or similar reference numerals, and therefore the description will be given only once. The embodiments described below are merely exemplary for explaining the present application, and should not be construed as limiting the present application.

[0029] In order to make the technical personnel in the art better understand the scheme of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0030] It should be noted that, in the embodiments of the present application, in this paper, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or sequence between the entities or operations.

[0031] Moreover, the terms "comprise", "contain" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or equipment. Without more limitations, the element defined by the sentence "comprises a" does not exclude the presence of another identical element in the process, method, article or equipment comprising the element.

[0032] In the description of the embodiments of the present application, the words "example" or "for example" are used to represent example, illustration or description. Any embodiment or design scheme described as "example" or "for example" in the embodiments of the present application is not interpreted as more preferred or having more advantages than another embodiment or design scheme. The words "example" or "for example" are intended to present relative concepts in a clear manner.

[0033] In addition, "multiple" in the embodiments of the present application means two or more, and therefore "multiple" in the embodiments of the present application can also be understood as "at least two". "At least one" can be understood as one or more, for example, as one, two or more. For example, including at least one means including one, two or more, and does not limit which ones are included, for example, including at least one of A, B and C, and the included can be A, B, C, A and B, A and C, B and C, or A and B and C.

[0034] It should be noted that, in the embodiments of the present application, the "and / or" describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / ", if not specially specified, generally represents a "or" relationship between the associated objects before and after it.

[0035] It should be noted that, in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical elements can be direct or indirect connection between the two electrical elements. For example, A and B are connected, which can be direct connection between A and B, or indirect connection between A and B through one or more other electrical elements.

[0036] The EC chip can be communicatively connected with a host processor, which can include a central processing unit (CPU). The communication interface between the EC chip and the host processor can include, but is not limited to, one or more of LPC (Low Pin Count), SPI (Serial Peripheral Interface), eSPI (Enhanced Serial Peripheral Interface), and the like. The EC chip can help the host processor manage peripherals (also referred to as peripheral devices). For example, the peripherals can include, but are not limited to, one or more of a fan, a keyboard, a mouse, a video, an audio, a USB, a power supply, and the like. The EC chip can include a processor, and as an example, the EC chip can employ an MCU core.

[0037] As an example, the EC chip can internally include a Flash memory, an SRAM, a command cache, support one or more interfaces such as eSPI, LPC, I2C Host, can have one or more interfaces such as a high-speed UART, a high-speed SPI interface, a multi-mode I2C, a USB, a PD / TYPE-C, a keyboard, a fan, a breathing light, an atmosphere light, and the like, can internally include a high-precision digital-to-analog conversion ADC / DAC, a comparator, a voltage monitoring, a temperature monitoring, and the like, and the like.

[0038] It should be understood that the foregoing EC chip is merely an example and is not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0039] Embodiments of the present application relate to implementing replay protection using an EC chip. Replay protection can be implemented in electronic devices such as notebook computers that use an EC chip. Replay protection commands are received and transmitted through a bus interface of the EC chip, and a signature program is executed by a processor of the EC chip to verify and execute the replay protection commands. Replay protection related functions can be completely implemented by a program, which can reduce hardware costs.

[0040] FIG. 1 shows a structural schematic diagram of an EC chip according to an embodiment of the present application. As shown in FIG. 1, the EC chip 100 can include a bus interface 101, a processor 102, and one or more storage modules 103. The bus interface 101 is configured to receive and transmit data packets. The one or more storage modules 103 are configured to store at least part of replay protection related data. The processor 102 is configured to parse the received data packets, and in the case that a replay protection command is parsed from the data packets, execute a signature program to verify and execute the replay protection command.

[0041] By the embodiment of the application, the bus interface of the EC chip is used to receive and send data packets, the processor is used to analyze the replay protection command and execute the signature program to verify and execute the replay protection command, and the replay protection is realized in the EC chip. Replay protection can be realized in electronic devices using the EC chip such as notebook computers, and compared with the technical solution of externally connecting the Flash in the electronic device using the EC chip, the hardware cost can be reduced. The processor and the bus interface of the EC chip are used to complete the signature by using a software algorithm. Moreover, the hardware of the EC chip changes less. The processor uses the software algorithm to complete the signature, which can reduce the cross hardware module transmission of data, reduce the risk of data transmission error, and reduce the data handling time.

[0042] In some examples, as shown in FIG. 2, the one or more storage modules 103 can include a first storage module 103-1 configured to store a root key.

[0043] In some examples, as shown in FIG. 2, the one or more storage modules 103 can include a second storage module 103-2 configured to store a signature key generated based on the root key.

[0044] In some examples, as shown in FIG. 2, the one or more storage modules 103 can include a third storage module 103-3 configured to store a replay protection monotonic counter value.

[0045] In some examples, as shown in FIG. 2, the one or more storage modules 103 can include a first storage module 103-1 configured to store a root key, and a second storage module 103-2 configured to store a signature key generated based on the root key.

[0046] In some examples, as shown in FIG. 2, the one or more storage modules 103 can include a first storage module 103-1 configured to store a root key, and a third storage module 103-3 configured to store a replay protection monotonic counter value.

[0047] In some examples, as shown in FIG. 2, the one or more storage modules 103 can include a second storage module 103-2 configured to store a signature key generated based on the root key, and a third storage module 103-3 configured to store a replay protection monotonic counter value.

[0048] In some examples, as shown in FIG. 2, the one or more storage modules 103 can include a first storage module 103-1 configured to store a root key, a second storage module 103-2 configured to store a signature key generated based on the root key, and a third storage module 103-3 configured to store a replay protection monotonic counter value.

[0049] In some examples, the first storage module 103-1 can be a non-volatile memory (NVM), and the first storage module 103-1 can be configured to be read and written only by the processor 102 to ensure the security of the root key. In some examples, the first storage module 103-1 can be a non-volatile one-time memory that can be written only once.

[0050] In some examples, the second storage module 103-2 can be a normal storage area that can be lost due to power failure. In some examples, the second storage module 103-2 can be configured to allow only the processor 102 to read and write to ensure the security of the signature key.

[0051] In some examples, the third storage module 103-3 can be a non-volatile memory, and the third storage module 103-3 can be configured to be repeatedly written. In some examples, the third storage module 103-3 can be configured to allow only the processor 102 to read and write to ensure the security of the replay protection monotonic counter value.

[0052] As shown in FIG. 2, the replay protection is implemented in the EC chip by receiving and sending data packets using the bus interface of the EC chip, the processor parsing the replay protection command and executing the signature program to verify and execute the replay protection command. The replay protection can be implemented in electronic devices such as notebook computers using the EC chip, which can reduce the hardware cost compared to the technical solution of externally connecting the Flash in the electronic devices using the EC chip. The processor and the bus interface of the EC chip are used to complete the signature using software algorithms, and the storage module is added, which has a lower hardware cost. The processor uses software algorithms to complete the signature, which can reduce the cross-module transmission of data, reduce the risk of data transmission errors, and reduce the data transfer time.

[0053] In some embodiments, one or more storage modules 103 can be external, that is, some replay protection related data is stored in one or more external storage modules outside the EC chip. The "external storage module" in the embodiments of the present application refers to a storage module located outside the EC chip.

[0054] In some embodiments, as shown in FIG. 3, the EC chip 100 can include one or more storage control modules 104 for accessing one or more external storage modules 201 for storing at least part of the replay protection related data. The processor 102 can access the one or more external storage modules 201 through the one or more storage control modules 104. By providing one or more storage control modules in the EC chip 100, the data in the one or more external storage modules 201 can be prevented from being obtained by the outside world.

[0055] In some examples, one storage control module 104 is configured to access a plurality of external storage modules 201. In other embodiments, at least one storage control module 104 corresponds to one external storage module 201, i.e. at least some of the external storage modules 201 are accessed by a respective storage control module 104.

[0056] In some examples, as shown in FIG. 3, the one or more storage control modules 104 can include a first storage control module 104-1 configured to access a first external storage module 201-1 for storing a root key.

[0057] In some examples, as shown in FIG. 3, the one or more storage control modules 104 can include a second storage control module 104-2 configured to access a second external storage module 201-2 for storing a signature key generated based on the root key.

[0058] In some examples, as shown in FIG. 3, the one or more storage control modules 104 can include a third storage control module 104-3 configured to access a third external storage module 201-3 for storing a replay protection monotonic count value.

[0059] In some examples, as shown in FIG. 3, the one or more storage control modules 104 can include a first storage control module 104-1 configured to access a first external storage module 201-1 for storing a root key; and a second storage control module 104-2 configured to access a second external storage module 201-2 for storing a signature key generated based on the root key.

[0060] In some examples, as shown in FIG. 3, the one or more storage control modules 104 can include a first storage control module 104-1 configured to access a first external storage module 201-1 for storing a root key; and a third storage control module 104-3 configured to access a third external storage module 201-3 for storing a replay protection monotonic count value.

[0061] In some examples, as shown in FIG. 3, the one or more storage control modules 104 can include a second storage control module 104-2 configured to access a second external storage module 201-2 for storing a signature key generated based on the root key; and a third storage control module 104-3 configured to access a third external storage module 201-3 for storing a replay protection monotonic count value.

[0062] In some examples, as shown in FIG. 3, the one or more storage control modules 104 can include: a first storage control module 104-1 for accessing a first external storage module 201-1 for storing a root key; a second storage control module 104-2 for accessing a second external storage module 201-2 for storing a signature key generated based on the root key; and a third storage control module 104-3 for accessing a third external storage module 201-3 for storing a replay protection monotonic counter value.

[0063] In some examples, the first external storage module 201-1 can be a non-volatile memory, and the first external storage module 201-1 can be configured to be read and written only by the processor 102 through the storage control module 104 to ensure the security of the root key. In some examples, the first external storage module 201-1 can be a non-volatile one-time memory that can be written only once.

[0064] In some examples, the second external storage module 201-2 can be a normal storage area that can lose power and be lost. In some examples, the second external storage module 201-2 can be configured to allow only the processor 102 to read and write through the storage control module 104 to ensure the security of the signature key.

[0065] In some examples, the third storage control module 104-3 can be a non-volatile memory, and the third storage control module 104-3 can be configured to be repeatedly written. In some examples, the third storage control module 104-3 can be configured to allow only the processor 102 to read and write through the storage control module 104 to ensure the security of the replay protection monotonic counter value.

[0066] As shown in FIG. 3, the bus interface of the EC chip receives and transmits data packets, the processor parses the replay protection command and executes the signature program to verify and execute the replay protection command, and the processor accesses the external storage module through the storage control module, thereby realizing replay protection in the EC chip. Replay protection can be realized in electronic devices such as notebook computers that use the EC chip, and compared with the technical solution of externally connecting a Flash in an electronic device that uses the EC chip, the hardware cost can be reduced. The processor and the bus interface of the EC chip are used, a software algorithm is used to complete the signature, a storage control module is added, and the hardware of the EC chip changes little. The processor uses a software algorithm to complete the signature, which can reduce the cross-module transmission of data, reduce the risk of data transmission errors, and reduce the data transfer time.

[0067] In some embodiments, the EC chip can further include one or more storage modules for storing a first part of replay protection related data, and one or more storage control modules for accessing one or more external storage modules for storing a second part of the replay protection related data.

[0068] Figures 4a to 4d respectively show structural diagrams of various EC chips provided by embodiments of the present application. As shown in Figures 4a to 4d, an EC chip 400 can include a bus interface 401, a processor 402, one or more storage modules 403, and one or more storage control modules 404. The bus interface 401 is configured to receive and send data packets. The one or more storage control modules 404 are configured to access one or more external storage modules 201. The processor 402 is configured to parse a received data packet and, in the case that a replay protection command is parsed from the data packet, execute a signing program to verify and execute the replay protection command. In the process of executing the signing program to verify and execute the replay protection command, the processor 402 can access the one or more storage modules 403 and access the one or more external storage modules 201 through the one or more storage control modules 404.

[0069] As shown in Figures 4a to 4d, replay protection is implemented in the EC chip by receiving and sending data packets using the bus interface of the EC chip, parsing a replay protection command using the processor, and executing a signing program to verify and execute the replay protection command. Replay protection can be implemented in electronic devices using the EC chip, such as notebook computers, and can reduce hardware costs compared to technical solutions in which a Flash is externally connected to electronic devices using the EC chip. The EC chip has little change in hardware by using the processor and the bus interface of the EC chip, using a software algorithm to complete signing, and adding storage modules and storage control modules. The processor uses a software algorithm to complete signing, which can reduce cross-module transmission of data, reduce the risk of data transmission errors, and reduce data transfer time.

[0070] In some examples, the one or more storage modules 403 are configured to store a first portion of replay protection related data, and the one or more external storage modules 201 are configured to store a second portion of the replay protection related data. For example, the one or more storage modules 403 are configured to store one or any two of a root key, a signing key generated based on the root key, and a replay protection monotonic counter value, and the one or more external storage modules 201 are configured to store the remaining portion of the root key, the signing key generated based on the root key, and the replay protection monotonic counter value.

[0071] In some examples, as shown in FIG. 4a, the one or more storage modules 403 can include a second storage module 403-2 for storing a signing key generated based on the root key, and a third storage module 403-3 for storing a replay protection monotonic counter value. The one or more external storage modules 201 can include a first external storage module 201-1 for storing the root key, and the storage control module 404 is configured to access the first external storage module 201-1. In this implementation, the EC chip stores the root key and the replay protection monotonic counter value in the one or more storage modules 403, and the signing key generated based on the root key is stored in the one or more external storage modules 201, and the storage control module 404 is configured to access the signing key stored in the one or more external storage modules 201.

[0072] In some examples, as shown in FIG. 4b, the one or more storage modules 403 can include a first storage module 403-1 for storing the root key, and a third storage module 403-3 for storing a replay protection monotonic counter value. The one or more external storage modules 201 can include a second external storage module 201-2 for storing a signing key generated based on the root key, and the storage control module 404 is configured to access the second external storage module 201-2. In this implementation, the EC chip stores the root key and the replay protection monotonic counter value in the one or more storage modules 403, and the signing key generated based on the root key is stored in the one or more external storage modules 201, and the storage control module 404 is configured to access the signing key stored in the one or more external storage modules 201.

[0073] In some examples, as shown in FIG. 4c, the one or more storage modules 403 can include a first storage module 403-1 for storing the root key, and a second storage module 403-2 for storing a signing key generated based on the root key. The one or more external storage modules 201 can include a third external storage module 201-3 for storing a replay protection monotonic counter value, and the storage control module 404 is configured to access the third external storage module 201-3. In this implementation, the EC chip stores the root key and the signing key in the one or more storage modules 403, and the replay protection monotonic counter value is stored in the one or more external storage modules 201, and the storage control module 404 is configured to access the replay protection monotonic counter value stored in the one or more external storage modules 201.

[0074] In some examples, as shown in FIG. 4d, the one or more storage modules 403 can include a third storage module 403-3 for storing a replay protection monotonic counter value. The one or more external storage modules 201 can include a first external storage module 201-1 for storing the root key, and a second external storage module 201-2 for storing a signing key, and the storage control module 404 is configured to access the first external storage module 201-1 and the second external storage module 201-2.

[0075] Although FIG. 4d shows the case that the first external storage module 201-1 and the second external storage module 201-2 are accessed by the storage control module 404, in embodiments of the present application, the first external storage module 201-1 and the second external storage module 201-2 can be respectively provided with corresponding storage control modules, such as the first storage control module and the second storage control module shown in FIG. 3, which will not be described herein.

[0076] It should be understood that FIG. 4d is only illustrative, and in embodiments of the present application, any two storage modules 403 can be externalized, and corresponding external storage modules 201 can be provided, which are not limited in embodiments of the present application.

[0077] In embodiments of the present application, the one or more external storage modules described above can include one or more storage chips.

[0078] In some embodiments, the EC chip generates a response corresponding to the replay protection command. The processor is further configured to generate a response corresponding to the replay protection command, encapsulate the response, and send the encapsulated data packet through the bus interface.

[0079] In order to improve the response speed, the EC chip can temporarily store predetermined data corresponding to the replay protection command in generating the replay protection related data, and synchronize the temporarily stored predetermined data to the corresponding storage module or external storage module after generating the response corresponding to the replay protection command.

[0080] FIG. 5 shows a structural schematic diagram of an EC chip according to an embodiment of the present application. As shown in FIG. 5, the EC chip 500 can include a bus interface 501, a processor 502, and a temporary storage module 505.

[0081] In some embodiments, as shown in FIG. 5, the EC chip 500 can further include one or more storage modules 503 for storing replay protection related data. The bus interface 501 is configured to receive and send data packets. The processor 502 is configured to parse the received data packets, and in the case that a replay protection command is parsed from the data packets, execute a signature program to verify and execute the replay protection command. The processor 502 can access the one or more storage modules 503 in the process of executing the signature program to verify and execute the replay protection command. The exemplary embodiments of the one or more storage modules 503 can refer to FIG. 2 and the description thereof, which will not be described herein.

[0082] In some examples, the processor 502 is further configured to, in the case that predetermined data corresponding to the replay protection command in generating the replay protection related data is generated, store the predetermined data to the temporary storage module 505, and synchronize the predetermined data stored in the temporary storage module 505 to the corresponding storage module 503 after generating the response corresponding to the replay protection command.

[0083] In some embodiments, the EC chip 500 can further comprise one or more storage control modules 504 for storing replay protection related data, as shown in FIG. 5. The processor 502 is configured to parse the received data packet and execute a signature procedure to verify and execute the replay protection command in the case that the replay protection command is parsed from the data packet. The processor 502 can access one or more external storage modules via the storage control module 504 in the process of executing the signature procedure to verify and execute the replay protection command. The exemplary embodiments of the one or more storage control modules 504 can be found in the description of FIG. 3, which will not be repeated here.

[0084] In some embodiments, the processor 502 is further configured to store the predetermined data corresponding to the replay protection command in the replay protection related data to the temporary storage module 505, and synchronize the predetermined data stored in the temporary storage module 505 to the corresponding external storage module via the one or more storage control modules 504 after generating the response corresponding to the replay protection command.

[0085] In some embodiments, the EC chip 500 can further comprise one or more storage modules 503 and one or more storage control modules 504, as shown in FIG. 5. The exemplary embodiments of the one or more storage modules 503 and the one or more storage control modules 504 can be found in the description of FIG. 4a to FIG. 4d, which will not be repeated here.

[0086] In some embodiments, the processor 502 is further configured to store the predetermined data corresponding to the replay protection command in the replay protection related data to the temporary storage module 505, and synchronize the predetermined data stored in the temporary storage module 505 to the corresponding external storage module via the one or more storage control modules 504 after generating the response corresponding to the replay protection command.

[0087] In some embodiments, the EC chip 500 can further comprise a synchronization module 506, as shown in FIG. 5. The processor 502 is further configured to store the predetermined data corresponding to the replay protection command in the replay protection related data to the temporary storage module 505, and generate the response corresponding to the replay protection command. The synchronization module 506 is configured to synchronize the predetermined data stored in the temporary storage module 505 to the corresponding storage module 503 or external storage module.

[0088] As an implementation, the temporary storage module 505 can include a backup register (BKP). The backup register includes a set of dedicated registers inside the processor 502, which the processor 502 can access efficiently. The backup register is in a backup domain, which is still powered by VBAT when the VDD power is cut off. They are also not reset when the system is woken up from the standby mode, or the system is reset or power reset. The reliability of the data storage can be guaranteed.

[0089] As an implementation, the processor shown in the foregoing figures 1 to 5 of the specification can be configured to read a key for signing from at least one of the one or more storage modules, the one or more external storage modules, and execute a signing program to sign a predetermined part of a replay protection command based on the key to generate signature information.

[0090] As an implementation, the EC chip shown in the foregoing figures 1 to 5 of the specification, the processor can be configured to, in a case where a binding root key command is received, execute a signing program to sign a predetermined part of the binding root key command based on a root key carried by the binding root key command to generate signature information, verify the binding root key command based on the generated signature information and signature information carried by the binding root key command, and in a case where the binding root key command is verified, write the root key into a corresponding storage module.

[0091] As an implementation, the EC chip shown in the foregoing figures 1 to 5 of the specification, the processor can be configured to, in a case where an update signature key command is received, execute a signing program to sign a predetermined part of the update signature key command based on a root key to generate signature information, verify the update signature key command based on the generated signature information and signature information carried by the update signature key command, and in a case where the update signature key command is verified, generate a signature key based on the root key and key data carried by the update signature key command, and write the signature key into a corresponding storage module.

[0092] As an implementation, the EC chip shown in the foregoing figures 1 to 5 of the specification, the processor can be configured to, in a case where an increase replay protection monotonic counter value command (also referred to as a replay protection monotonic counter value plus 1 command) is received, execute a signing program to sign a predetermined part of the increase replay protection monotonic counter value command based on a signature key to generate signature information, verify the increase replay protection monotonic counter value command based on the generated signature information and signature information carried by the increase replay protection monotonic counter value command, and in a case where the increase replay protection monotonic counter value command is verified, increase the replay protection monotonic counter value by one, and write the increased replay protection monotonic counter value into a corresponding storage module.

[0093] As an implementation form, the EC chip shown in FIGS. 1-5 of the foregoing description of the specification can be configured to, in a case where a read replay protection monotonic counter value command is received, execute a signature procedure to sign a predetermined part of the read replay protection monotonic counter value command based on a signature key to generate signature information, verify the read replay protection monotonic counter value command based on the generated signature information and signature information carried by the read replay protection monotonic counter value command, in a case where the read replay protection monotonic counter value command is verified, read a replay protection monotonic counter value from a corresponding storage module, and generate a response carrying the replay protection monotonic counter value.

[0094] As an implementation form, the EC chip shown in FIGS. 1-5 of the foregoing description of the specification can be configured to generate a response corresponding to a replay protection command, encapsulate the response, and send the encapsulated data packet through the bus interface.

[0095] As an implementation form, the EC chip shown in FIGS. 1-5 of the foregoing description of the specification can be configured to execute a signature procedure to sign a predetermined part of the response based on a signature key.

[0096] As an implementation form, the signature procedure of the foregoing description of the specification can include a hash message authentication code generation algorithm, and the signature information includes a hash message authentication code. The hash message authentication code is also referred to as hash-based message authentication code (HAMC). It should be understood that the embodiments of the present application do not limit the signature algorithm, and other algorithms capable of verifying data authenticity are also feasible, and the embodiments of the present application do not limit this.

[0097] As an implementation form, the bus interface shown in FIGS. 1-5 of the foregoing description of the specification can include an eSPI interface.

[0098] As an implementation form, the EC chip shown in FIGS. 1-5 of the foregoing description of the specification can include an eSPI interface, and the signature procedure can include an HMAC algorithm.

[0099] The embodiments of the present application also provide a system-in-package chip.

[0100] In some embodiments, the system-in-package chip packages an external storage module with the EC chip, that is, integrates the EC chip and the external storage module in one package, which can achieve higher integration and smaller size, reduce power consumption of the electronic device, improve performance, and simplify design. The external storage module can include one or more storage chips.

[0101] Figure 6 shows a structure diagram of a sealing chip according to an embodiment of the present application. As shown in Figure 6, the sealing chip 600 can include one or more storage chips 610 for storing at least part of the playback protection related data, an EC chip 620 including a bus interface 621, a processor 622, and one or more storage control modules 624. The bus interface 621 is configured to receive and send data packets. The one or more storage control modules 624 are configured to access the one or more storage chips 610. The processor 622 is configured to parse the received data packets and, in the case that a playback protection command is parsed from the data packets, execute a signature program to verify and execute the playback protection command. In the process of executing the signature program to verify and execute the playback protection command, the processor 622 can access the one or more storage chips 610 through the one or more storage control modules 624.

[0102] As shown in Figure 6, the playback protection is implemented in the EC chip by receiving and sending data packets using the bus interface of the EC chip, parsing the playback protection command using the processor, and executing a signature program to verify and execute the playback protection command. The playback protection can be implemented in electronic devices using the EC chip, such as notebook computers, and can reduce the hardware cost compared to the technical solution of externally connecting a Flash in the electronic devices using the EC chip. The processor and the bus interface of the EC chip are used to complete the signature using a software algorithm. The processor uses the software algorithm to complete the signature, which can reduce the cross-module transmission of data, reduce the risk of data transmission errors, and reduce the data transfer time.

[0103] In some embodiments, the one or more storage chips 610 can include a first storage chip 610-1 configured to store a root key.

[0104] In some embodiments, the one or more storage chips 610 can include a second storage chip 610-2 configured to store a signature key generated based on the root key.

[0105] In some embodiments, the one or more storage chips 610 can include a third storage chip 610-3 configured to store a playback protection monotonic counter value.

[0106] In some embodiments, the one or more storage chips 610 can include a first storage chip 610-1 configured to store a root key, a second storage chip 610-2 configured to store a signature key generated based on the root key, and a third storage chip 610-3 configured to store a playback protection monotonic counter value.

[0107] In some embodiments, the EC chip 620 can further include one or more storage modules 623. The one or more storage modules 623 can be configured to store a first part of the replay protection related data, and the one or more storage chips 610 can be configured to store a second part of the replay protection related data. The one or more storage modules 623 can include the following parts: a first storage module configured to store a root key; a second storage module configured to store a signature key generated based on the root key; and a third storage module configured to store a replay protection monotonic counter value.

[0108] As an example, as shown in FIG. 6, the one or more storage modules 623 can include a third storage module 623-3 configured to store a replay protection monotonic counter value. The one or more storage chips 610 include: a first storage chip 610-1 configured to store a root key; and a second storage chip 610-2 configured to store a signature key generated based on the root key. It should be understood that FIG. 6 is only an exemplary combination of storage modules and storage chips, and other combinations of storage modules and storage chips can be found in FIGS. 4a-4d, and the embodiments of the present application do not repeat the description here.

[0109] The EC chip 620 can refer to FIGS. 3-5 and the description thereof, and the embodiments of the present application do not repeat the description here.

[0110] The embodiments of the present application also provide a system, which can include the EC chip and the one or more storage modules of the embodiments of the present application. The structure and combination of the EC chip and the storage modules can refer to the foregoing description of the embodiments of the present application, and the description is not repeated here. The replay protection command is received and sent through the bus interface of the EC chip, and the signature program is executed by the processor of the EC chip to verify and execute the replay protection command, which can implement the replay protection in the electronic device using the EC chip such as a notebook computer, and can reduce the hardware cost compared to the technical solution of externally connecting the Flash in the electronic device using the EC chip. The processor and the bus interface of the EC chip are used to complete the signature using the software algorithm, and the hardware of the EC chip changes less. The processor uses the software algorithm to complete the signature, which can reduce the cross-module transmission of data, reduce the risk of data transmission error, and reduce the data transfer time.

[0111] The electronic device can be, but is not limited to, a body weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a human body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a vehicle-mounted charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a touch pen, a true wireless earphone, a car central control screen, a car, a smart wearable device, a mobile terminal, and a smart home device. The smart wearable device includes, but is not limited to, a smart watch, a smart bracelet, and a cervical vertebra massage instrument. The mobile terminal includes, but is not limited to, a smart phone, a notebook computer, a tablet computer, and a POS (point of sales terminal) machine. The smart home device includes, but is not limited to, a smart socket, a smart rice cooker, a smart sweeper, and a smart lamp. The electronic device receives and sends a replay protection command through the bus interface of the EC chip, and executes a signature program through the processor of the EC chip to verify and execute the replay protection command, so that replay protection can be implemented in an electronic device such as a notebook computer using the EC chip, and compared with a technical solution of externally hanging a Flash in an electronic device using the EC chip, the hardware cost can be reduced. The EC chip processor and the bus interface are used to complete the signature by using a software algorithm, and the EC chip hardware changes little. The processor uses a software algorithm to complete the signature, so that the cross-module transmission of data can be reduced, the risk of data transmission error can be reduced, and the data handling time can be reduced.

[0112] The following takes the implementation of eRPMC (RPMC over eSPI OOB) through an eSPI OOB channel as an example to describe an exemplary replay protection command verification and execution process implemented by the EC chip, the package chip, the system, and the electronic device provided by the embodiments of the present application. In the eRPMC solution, the bus interface of the embodiments of the present application is an eSPI interface, the signature program can implement the HAMC algorithm, and the signature key generated according to the root key can be an HMAC key (HMAC-key).

[0113] The EC chip, the package chip, and the system using the embodiments of the present application can include that the eSPI interface on the EC chip receives a data packet (eSPI OOB packet) including a replay protection command, the processor of the EC chip parses the received data packet to obtain the replay protection command, and processes according to the received replay protection command, such as executing a signature program calculation, verifying a signature, generating an HMAC-key value, and writing a Root key. After the processing is completed, the eSPI interface is used to reply to related information (i.e., a response corresponding to the replay protection command) according to the processing result.

[0114] An exemplary root key binding flow is shown in FIG. 7. The EC chip receives a command for binding a root key from the PCH using an eSPI interface, and then passes the received data packet to a core of the processor for parsing. A software algorithm is used to complete an HMAC calculation command information and to verify a signature. If the verification is correct, the root key carried in the command is written into a corresponding storage module (NVM 1), and a PCH command execution condition is returned. If the verification is incorrect, the PCH command execution condition is directly returned.

[0115] An exemplary update signature key (HMAC-key) flow is shown in FIG. 8. An update signature key command (update HMAC-key command) is sent each time the PCH is powered on. The EC chip eSPI interface receives information, and then passes the information to the core for parsing command information. Then, the core uses a software algorithm to complete an HMAC calculation to generate an HMAC-key value and a command signature according to the root key and the parsed information. If the signature result is correct, the core writes the HMAC-key into a corresponding storage module (Momery 1), and then returns a PCH command execution condition. If the signature is incorrect, the PCH command execution condition is directly returned.

[0116] An exemplary read replay protection monotonic counter value flow is shown in FIG. 9. When the EC chip eSPI interface receives a read replay protection monotonic counter value command (read Monotonic Counter command), the command is passed to the core of the processor for parsing. The core of the processor uses a software algorithm to complete an HMAC calculation and to verify a signature according to the parsed information. Whether the verification passes or not, a command execution condition is returned.

[0117] An exemplary Monotonic Counter increase 1 flow is shown in FIG. 10. The EC chip eSPI interface receives a Monotonic Counter increase 1 command, and passes the command to the core of the processor for parsing command related information. Then, a software algorithm is used to complete an HMAC calculation and a verification calculation result. If the verification result is correct, a Counter+1 value is written into a corresponding storage module (NVM 2), and a command execution condition is returned. If the verification result is incorrect, the command execution condition is directly returned.

[0118] An exemplary read RPMC parameter flow is shown in FIG. 11. The read RPMC parameter command is a non-standard RPMC command, and is dedicated to eRPMC. After the core of the processor of the EC chip receives the read RPMC parameter command of the eSPI interface, the command information is parsed, eRPMC information is read, and a command is returned.

[0119] The scheme uses the processor of the EC chip to realize the eRPMC function by software. The hardware on the EC chip provides the eSPI interface and the processor hardware resource. The software is responsible for parsing the received command, processing the command, and replying information through the interface.

[0120] The above is only a preferred embodiment of the present application, and does not limit the present application in any form. Although the preferred embodiment of the present application is disclosed as above, it is not intended to limit the present application. Any person skilled in the art can make slight changes or modifications to the above disclosed technical content to obtain equivalent embodiments with equivalent changes, without departing from the scope of the technical scheme of the present application. Any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, without departing from the technical scheme content of the present application, still belongs to the scope of the technical scheme of the present application.

Claims

1. An EC chip comprising: a bus interface configured to receive and transmit data packets; one or more storage modules configured to store at least part of replay protection related data; a processor connected to the bus interface and the one or more storage modules, and configured to parse the received data packets, and in case that a replay protection command is parsed from the data packets, execute a signing procedure to verify and execute the replay protection command.

2. The EC chip of claim 1, wherein, The one or more storage modules comprise: a first storage module configured to store a root key.

3. The EC chip of claim 1, wherein, The one or more storage modules comprise: a second storage module configured to store a signing key generated based on the root key.

4. The EC chip of claim 1, wherein, The one or more storage modules comprise: a third storage module configured to store a monotonic counter value.

5. The EC chip of claim 1, wherein, Further comprising: a temporary storage module; wherein the processor is further configured to, in case that predetermined data corresponding to the replay protection command is generated, store the predetermined data to the temporary storage module, and synchronize the predetermined data stored in the temporary storage module to the storage module corresponding thereto after a response corresponding to the replay protection command is generated.

6. The EC chip of claim 1, wherein, Further comprising: a temporary storage module and a synchronization module; wherein the processor is further configured to, in case that predetermined data corresponding to the replay protection command is generated, store the predetermined data to the temporary storage module, and generate a response corresponding to the replay protection command; the synchronization module is configured to synchronize the predetermined data stored in the temporary storage module to the storage module corresponding thereto.

7. The EC chip according to claim 5 or 6, wherein The temporary storage module comprises a backup register. 8.An EC chip comprising: a bus interface configured to receive and transmit data packets; one or more storage control modules configured to access one or more external storage modules configured to store at least part of replay protection related data; a processor connected to the bus interface and the one or more storage control modules, and configured to parse the received data packets, and in case that a replay protection command is parsed from the data packets, execute a signing procedure to verify and execute the replay protection command.

9. The EC chip of claim 8, wherein, The one or more storage control modules comprise: a first storage control module configured to access a first external storage module configured to store a root key.

10. The EC chip of claim 8, wherein, The one or more storage control modules comprise: a second storage control module configured to access a second external storage module configured to store a signing key generated based on the root key.

11. The EC chip of claim 8, wherein, The one or more storage control modules comprise: a third storage control module configured to access a third external storage module configured to store a monotonic counter value.

12. The EC chip according to any one of claims 8 to 11, wherein, Further comprising: one or more storage modules; wherein the one or more storage modules are configured to store a first part of the replay protection related data, and the one or more external storage modules are configured to store a second part of the replay protection related data.

13. The EC chip of claim 8, wherein, Further comprising: a temporary storage module; The processor is further configured to, in a case where predetermined data corresponding to the playback protection command is generated in playback protection related data, store the predetermined data to the temporary storage module, and after a response corresponding to the playback protection command is generated, synchronize the predetermined data stored in the temporary storage module to a storage module corresponding thereto.

14. The EC chip of claim 8, wherein, Further comprising: a temporary storage module and a synchronization module; The processor is further configured to, in a case where predetermined data corresponding to the playback protection command is generated in playback protection related data, store the predetermined data to the temporary storage module, and generate a response corresponding to the playback protection command. The synchronization module is configured to synchronize the predetermined data stored in the temporary storage module to a storage module corresponding thereto.

15. The EC chip according to claim 13 or 14, wherein, The temporary storage module comprises a backup register.

16. A packaged chip, comprising: one or more external storage modules; the EC chip of any one of claims 8 to 15.

17. A system, comprising: one or more external storage modules; the EC chip of any one of claims 8 to 15.

18. An electronic device, comprising a device body and the EC chip of any one of claims 1 to 15, or the packaged chip of claim 16, or the system of claim 17, provided in the device body.

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