EC chip, co-packaged chip, system, and electronic device

Abstract

Embodiments of the present application provide an EC chip, a co-packaged chip, a system, and an electronic device. The EC chip in one embodiment comprises: a bus interface, configured to receive and send a data packet; a signature module, configured to generate signature information; and a processor, connected to the bus interface and configured to: parse the received data packet, and when a replay protection command is obtained by parsing the received data packet, call the signature module to verify and execute the replay protection command.

Description

EC chip, package chip, system and electronic device

[0001] Cross-reference to Related Applications

[0002] This application claims priority to the Chinese Patent Application No. 202410454269.0, filed on April 16, 2024, and entitled “EC chip, package chip, system and electronic device”, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the technical field of replay protection, in particular to an embedded controller (EC) chip, a package chip, a system and an electronic device. BACKGROUND

[0004] Replay attacks refer to an attack mode in which an attacker records legitimate communication data packets and then sends the recorded communication data packets again to deceive the system, so that the system mistakenly believes that the data packets are legitimate, thereby achieving the attack purpose. Replay protection monotonic counter (RPMC) can be used to detect replay attacks. For example, communication parties with RPMC record the same count value by means of the monotonic counter. The data sender adds the recorded count value as a variable to the data packet, encrypts the data packet and transmits the data packet on the bus. The data receiver must know the same variable and include it in the data verification algorithm to pass the authentication, thereby preventing replay attacks.

[0005] RPMC is an important function for computing devices such as personal computers. In the related art, an external Flash integrates the RPMC scheme, which communicates with the platform controller hub (PCH) through the serial peripheral interface (SPI). However, the external Flash is not necessary for computing devices such as notebook computers, and some notebook computers do not have an external Flash to reduce costs, which results in that some notebook computers do not have the RPMC function. How to enhance the security of computing devices without increasing the cost of computing devices has not yet been effectively solved. SUMMARY

[0006] In view of the above problems, the embodiments of the present application provide an EC chip, a package chip, a system and an electronic device to solve the above technical problems.

[0007] In a first aspect, the embodiments of the present application provide an EC chip, comprising: a bus interface configured to receive and send data packets; a signature module configured to generate signature information; and a processor connected to the bus interface, configured to parse the received data packets, and in a case that a replay protection command is parsed from the received data packets, invoke the signature module to verify and execute the replay protection command.

[0008] In a second aspect, the embodiments of the present application provide a package chip, comprising: one or more external storage chips; and the EC chip as described above.

[0009] In a third aspect, the embodiments of the present application provide a system, comprising: one or more external storage modules; and the EC chip as described above.

[0010] In a fourth aspect, the embodiments of the present application provide an electronic device, comprising: a device main body; and the EC chip as described above, or the package chip as described above, or the system as described above, which are arranged on the device main body.

[0011] These and other aspects of the present application will become more apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without any creative effort.

[0013] FIG. 1a shows a structural schematic diagram of an EC chip according to an embodiment of the present application.

[0014] FIG. 1b shows a structural schematic diagram of an EC chip according to an embodiment of the present application.

[0015] FIG. 2 shows a structural schematic diagram of another EC chip according to an embodiment of the present application.

[0016] FIG. 3 shows a structural schematic diagram of another EC chip according to an embodiment of the present application.

[0017] FIG. 4a shows a structural schematic diagram of another EC chip according to an embodiment of the present application.

[0018] FIG. 4b shows a structural schematic diagram of another EC chip according to an embodiment of the present application.

[0019] FIG. 4c shows a structural schematic diagram of another EC chip according to an embodiment of the present application.

[0020] FIG. 4d shows a structural schematic diagram of another EC chip according to an embodiment of the present application.

[0021] FIG. 5 shows a structure diagram of another EC chip according to an embodiment of the present application.

[0022] FIG. 6 shows a structure diagram of a sealing chip according to an embodiment of the present application.

[0023] FIG. 7 shows a flow chart of an exemplary root key binding process according to an embodiment of the present application.

[0024] FIG. 8 shows a flow chart of an exemplary signature key updating process according to an embodiment of the present application.

[0025] FIG. 9 shows a flow chart of an exemplary read replay protection monotonic counter value process according to an embodiment of the present application.

[0026] FIG. 10 shows a flow chart of an exemplary replay protection monotonic counter value increment 1 process according to an embodiment of the present application.

[0027] FIG. 11 shows a flow chart of an exemplary read RPMC parameter process according to an embodiment of the present application. DETAILED DESCRIPTION

[0028] The embodiments of the present application will be described in detail below with reference to the drawings, in which the same or similar components are denoted by the same or similar reference numerals, and therefore the description will be given only once. The embodiments described below are merely exemplary for explaining the present application, and should not be construed as limiting the present application.

[0029] In order to make the technical personnel in the art better understand the scheme of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0030] It should be noted that in the embodiments of the present application, in this document, the relational terms such as first and second and the like are used only to differentiate one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations.

[0031] Also, the term "comprise", "comprising", or any other variant thereof, are intended to mean a non-exclusive inclusion, such that processes, methods, articles, or apparatuses that comprise a list of elements are not required to only comprise those elements, but can also comprise other elements not expressly listed, or inherent to such processes, methods, articles, or apparatuses. Without further limitation, an element preceded by "comprises a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the recited element.

[0032] In the description of the embodiments of the present application, the word "example" or "for example" is used to mean "an example of" or "for example". In the present application, any embodiment or design scheme described as "example" or "for example" is not necessarily preferred or has more advantages than another embodiment or design scheme. The word "example" or "for example" is used in the sense of clarity.

[0033] In addition, "multiple" in the embodiments of the present application means two or more, and therefore "multiple" in the embodiments of the present application can also be understood as "at least two". "At least one" can be understood as one or more, for example, as one, two or more. For example, including at least one means including one, two or more, and does not limit which ones are included, for example, including at least one of A, B and C, which can include A, B, C, A and B, A and C, B and C, or A and B and C.

[0034] It should be noted that in the embodiments of the present application, the association relationship of the associated objects described by "and / or" can represent three kinds of relationships, for example, A and / or B can represent three cases of A alone, A and B together, and B alone. In addition, the character " / ", if not specially stated, generally represents a "or" relationship between the associated objects before and after it.

[0035] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical elements can be direct or indirect connection between two electrical elements. For example, A and B are connected, which can be direct connection between A and B, or indirect connection between A and B through one or more other electrical elements.

[0036] The EC chip can be communicatively connected with a host processor, which can include a central processing unit (CPU). The communication interface between the EC chip and the host processor can include, but is not limited to, one or more of LPC (Low Pin Count), SPI (Serial Peripheral Interface), eSPI (Enhanced Serial Peripheral Interface), and the like. The EC chip can help the host processor manage peripherals (also referred to as peripheral devices). For example, the peripherals can include one or more of a fan, a keyboard, a mouse, a video, an audio, a USB, a power supply, and the like. The EC chip can include a processor, and as an example, the EC chip can employ an MCU core.

[0037] As an example, the EC chip can internally include a Flash memory, an SRAM, an instruction cache, support one or more interfaces such as eSPI, LPC, I2C Host, can have one or more interfaces such as a high-speed UART, a high-speed SPI interface, a multi-mode I2C, a USB, a PD / TYPE-C, a keyboard, a fan, a breathing light, an atmosphere light, and the like, can internally include one or more digital-to-analog interfaces such as a high-precision digital-to-analog conversion ADC / DAC, a comparator, a voltage monitoring, a temperature monitoring, and the like.

[0038] It should be understood that the foregoing EC chip is merely an example and is not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0039] Embodiments of the present application relate to implementing replay protection using an EC chip. Replay protection can be implemented in electronic devices such as notebook computers that use an EC chip.

[0040] Some embodiments of the present application provide a signature module in an EC chip, and replay protection is implemented using a processor of the EC chip and a bus interface and the signature module. In some embodiments of the present application, the signature module is independent of the processor, i.e., the signature module is located inside the EC chip and outside the processor thereof. In some embodiments of the present application, the signature module is integrated inside the processor of the EC chip.

[0041] Fig. 1a shows a structure diagram of an EC chip according to an embodiment of the present application, and Fig. 1b shows a structure diagram of another EC chip according to an embodiment of the present application. As shown in Fig. 1a and Fig. 1b, the EC chip 100 can include a bus interface 101, a processor 102 and a signature module 103. As shown in Fig. 1a, the signature module 103 is integrated in the processor 102. The signature module 103 is integrated in the processor 102, which can improve the speed of the processor 102 accessing the signature module 103. As shown in Fig. 1b, the signature module 103 is located outside the processor 102. The signature module 103 is located outside the processor 102, and the signature module 103 is a module outside the processor 102, which is convenient for hardware implementation.

[0042] In the embodiments of the present application, the bus interface 101 is configured to receive and send data packets. The signature module 103 is configured to generate signature information. The processor 102 is configured to parse the received data packets, and when a replay protection command is parsed, the processor 102 is configured to call the signature module 103 to verify and execute the replay protection command. According to the embodiments of the present application, the bus interface and the processor of the EC chip are used to receive and parse the replay protection command, and the processor calls the signature module to verify and execute the replay protection command, so that the replay protection is implemented in the EC chip. Moreover, the signature module can quickly generate the signature information in a hardware manner, which improves the processing speed. The embodiments of the present application can implement the replay protection in electronic devices using the EC chip, such as notebook computers, and can reduce the hardware cost compared with the technical solution of externally connecting the Flash.

[0043] In some embodiments, as shown in Fig. 2, the EC chip 100 can further include one or more storage modules 104 configured to store at least part of the replay protection related data.

[0044] In some examples, as shown in Fig. 2, the one or more storage modules 104 can include a first storage module 104-1 configured to store a root key.

[0045] In some examples, as shown in Fig. 2, the one or more storage modules 104 can include a second storage module 104-2 configured to store a signature key generated based on the root key.

[0046] In some examples, as shown in Fig. 2, the one or more storage modules 104 can include a third storage module 104-3 configured to store a replay protection monotonic counter value.

[0047] In some examples, as shown in Fig. 2, the one or more storage modules 104 can include a first storage module 104-1 configured to store a root key, and a second storage module 104-2 configured to store a signature key generated based on the root key.

[0048] In some examples, as shown in FIG. 2, the one or more storage modules 104 can include a first storage module 104-1 for storing a root key, a second storage module 104-2 for storing a signature key generated based on the root key, and a third storage module 104-3 for storing a replay protection monotonic count value.

[0049] In some examples, as shown in FIG. 2, the one or more storage modules 104 can include a first storage module 104-1 for storing a root key, a second storage module 104-2 for storing a signature key generated based on the root key, and a third storage module 104-3 for storing a replay protection monotonic count value.

[0050] In some examples, as shown in FIG. 2, the one or more storage modules 104 can include a first storage module 104-1 for storing a root key, a second storage module 104-2 for storing a signature key generated based on the root key, and a third storage module 104-3 for storing a replay protection monotonic count value.

[0051] In some examples, the first storage module 104-1 can be a non-volatile memory (NVM), and the first storage module 104-1 can be configured to be read and written only by the processor 102 to ensure the security of the root key. In some examples, the first storage module 104-1 can be a non-volatile one-time memory that can be written only once.

[0052] In some examples, the second storage module 104-2 can be a normal storage area that can lose data when power is lost. In some examples, the second storage module 104-2 can be configured to allow only the processor 102 to read and write to ensure the security of the signature key.

[0053] In some examples, the third storage module 104-3 can be a non-volatile memory, and the third storage module 104-3 can be configured to be repeatedly written. In some examples, the third storage module 104-3 can be configured to allow only the processor 102 to read and write to ensure the security of the replay protection monotonic count value.

[0054] In some embodiments, one or more storage modules 104 can be external, that is, some replay protection related data can be stored in one or more external storage modules outside the EC chip. In the embodiments of the present application, the "external storage module" refers to a storage module located outside the EC chip.

[0055] In some embodiments, as shown in FIG. 3, the EC chip 100 can further include one or more storage control modules 105 configured to access one or more external storage modules 201 configured to store at least part of the replay protection related data. By providing one or more storage control modules in the EC chip 100, the data in the one or more external storage modules 201 can be protected from being accessed by the outside world.

[0056] In some examples, one storage control module 105 is configured to access a plurality of external storage modules 201. In other examples, at least one storage control module 105 corresponds to one external storage module 201, i.e., at least part of the external storage modules 201 are accessed by the corresponding storage control module 105 respectively.

[0057] In some examples, as shown in FIG. 3, the one or more storage control modules 105 can include a first storage control module 105-1 configured to access a first external storage module 201-1 configured to store a root key.

[0058] In some examples, as shown in FIG. 3, the one or more storage control modules 105 can include a second storage control module 105-2 configured to access a second external storage module 201-2 configured to store a signature key generated based on the root key.

[0059] In some examples, as shown in FIG. 3, the one or more storage control modules 105 can include a third storage control module 105-3 configured to access a third external storage module 201-3 configured to store a replay protection monotonic counter value.

[0060] In some examples, as shown in FIG. 3, the one or more storage control modules 105 can include a first storage control module 105-1 configured to access a first external storage module 201-1 configured to store a root key; and a second storage control module 105-2 configured to access a second external storage module 201-2 configured to store a signature key generated based on the root key.

[0061] In some examples, as shown in FIG. 3, the one or more storage control modules 105 can include a first storage control module 105-1 configured to access a first external storage module 201-1 configured to store a root key; and a third storage control module 105-3 configured to access a third external storage module 201-3 configured to store a replay protection monotonic counter value.

[0062] In some examples, as shown in FIG. 3, the one or more storage control modules 105 can include a second storage control module 105-2 for accessing a second external storage module 201-2 for storing a signing key generated based on the root key; and a third storage control module 105-3 for accessing a third external storage module 201-3 for storing a replay protection monotonic count value.

[0063] In some examples, as shown in FIG. 3, the one or more storage control modules 105 can include a first storage control module 105-1 for accessing a first external storage module 201-1 for storing a root key; a second storage control module 105-2 for accessing a second external storage module 201-2 for storing a signing key generated based on the root key; and a third storage control module 105-3 for accessing a third external storage module 201-3 for storing a replay protection monotonic count value.

[0064] In some examples, the first external storage module 201-1 can be a non-volatile memory, which can be configured to be read and written only by the processor 102 through the storage control module 105 to ensure the security of the root key. In some examples, the first external storage module 201-1 can be a non-volatile one-time memory, which can be written only once.

[0065] In some examples, the second external storage module 201-2 can be a normal storage area, which can be lost when power is off. In some examples, the second external storage module 201-2 can be configured to allow only the processor 102 to read and write through the storage control module 105 to ensure the security of the signing key.

[0066] In some examples, the third storage control module 105-3 can be a non-volatile memory, which can be configured to be repeatedly written. In some examples, the third storage control module 105-3 can be configured to allow only the processor 102 to read and write through the storage control module 105 to ensure the security of the replay protection monotonic count value.

[0067] In some embodiments, the EC chip can further include one or more storage modules for storing a first part of the replay protection related data; and one or more storage control modules for accessing one or more external storage modules for storing a second part of the replay protection related data.

[0068] Figures 4a-4d respectively show structural diagrams of various EC chips according to embodiments of the present application. As shown in Figures 4a-4d, an EC chip 400 can include a bus interface 401, a processor 402, a signature module 403, one or more storage modules 404, and one or more storage control modules 405. The bus interface 401 is configured to receive and transmit data packets. The signature module 403 is configured to generate signature information. The processor 402 is configured to parse a received data packet, and when a replay protection command is parsed, invoke the signature module 403 to verify and execute the replay protection command. The processor 402 can access one or more storage modules 404 and access one or more external storage modules 201 via one or more storage control modules 405 in the process of verifying and executing the replay protection command.

[0069] In some examples, the one or more storage modules 404 are configured to store a first portion of replay protection related data, and the one or more external storage modules 201 are configured to store a second portion of the replay protection related data. For example, the one or more storage modules 404 are configured to store one or any two of a root key, a signature key generated based on the root key, and a replay protection monotonic counter value, and the one or more external storage modules 201 are configured to store the remaining portion of the root key, the signature key generated based on the root key, and the replay protection monotonic counter value.

[0070] In some examples, as shown in Figure 4a, the one or more storage modules 404 can include a second storage module 404-2 configured to store a signature key generated based on a root key, and a third storage module 404-3 configured to store a replay protection monotonic counter value. The one or more external storage modules 201 can include a first external storage module 201-1 configured to store the root key, and the storage control module 405 is configured to access the first external storage module 201-1. In this implementation, the EC chip stores the signature key generated based on the root key and the replay protection monotonic counter value, and the external storage module stores the root key, and the root key stored in the external storage module is accessed via the storage control module within the EC chip.

[0071] In some examples, as shown in Figure 4b, the one or more storage modules 404 can include a first storage module 404-1 configured to store a root key, and a third storage module 404-3 configured to store a replay protection monotonic counter value. The one or more external storage modules 201 can include a second external storage module 201-2 configured to store a signature key generated based on the root key, and the storage control module 405 is configured to access the second external storage module 201-2. In this implementation, the EC chip stores the root key and the replay protection monotonic counter value, and the external storage module stores the signature key generated based on the root key, and the signature key stored in the external storage module is accessed via the storage control module within the EC chip.

[0072] In some examples, as shown in FIG. 4c, the one or more storage modules 404 can include a first storage module 404-1 for storing the root key, and a second storage module 404-2 for storing the signature key generated based on the root key. The one or more external storage modules 201 can include a third external storage module 201-3 for storing the replay protection monotonic counter value, and the storage control module 405 is configured to access the third external storage module 201-3. In this embodiment, the EC chip stores the root key and the signature key in the storage modules, stores the replay protection monotonic counter value in the external storage module, and accesses the replay protection monotonic counter value stored in the external storage module through the storage control module in the EC chip.

[0073] In some examples, as shown in FIG. 4d, the one or more storage modules 404 can include a third storage module 404-3 for storing the replay protection monotonic counter value. The one or more external storage modules 201 can include a first external storage module 201-1 for storing the root key, and a second external storage module 201-2 for storing the signature key, and the storage control module 405 is configured to access the first external storage module 201-1 and the second external storage module 201-2.

[0074] Although FIG. 4d shows the case of accessing the first external storage module 201-1 and the second external storage module 201-2 through the storage control module 405, in the embodiments of the present application, a storage control module corresponding to each of the first external storage module 201-1 and the second external storage module 201-2 can be respectively arranged, such as the first storage control module and the second storage control module shown in FIG. 3, which will not be described herein.

[0075] It should be understood that FIG. 4d is only illustrative, and in the embodiments of the present application, any two storage modules 402 can be externalized, and a corresponding external storage module 201 can be arranged, which is not limited in the embodiments of the present application.

[0076] In the embodiments of the present application, the one or more external storage modules described above can include one or more storage chips.

[0077] In some embodiments, the EC chip generates a response corresponding to the replay protection command. The processor is further configured to generate a response corresponding to the replay protection command, and encapsulate the response and send the encapsulated data packet through the bus interface.

[0078] In order to improve the response speed, the EC chip can temporarily store predetermined data corresponding to the replay protection command in generating the replay protection related data, and synchronize the temporarily stored predetermined data to the storage module or the external storage module corresponding thereto after generating the response corresponding to the replay protection command.

[0079] Figure 5 shows a structure diagram of an EC chip according to an embodiment of the present application. As shown in Figure 5, the EC chip 500 can include a bus interface 501, a processor 502, a signature module 503, and a temporary storage module 506.

[0080] In some embodiments, the EC chip 500 can further include one or more storage modules 504 for storing at least part of the replay protection related data, as shown in Figure 5. The bus interface 501 is configured to receive and send data packets. The signature module 503 is configured to generate signature information. The processor 502 is configured to invoke the signature module 503 and control the one or more storage modules 504 to verify and execute the replay protection command. Exemplary embodiments of the one or more storage modules 504 can be found in Figure 2 and its description, which will not be repeated here.

[0081] In some examples, the processor 502 is further configured to, in a case where the predetermined data corresponding to the replay protection command in the generation of the replay protection related data is generated, store the predetermined data to the temporary storage module 506, and after generating the response corresponding to the replay protection command, synchronize the predetermined data stored in the temporary storage module 506 to the storage module 504 corresponding thereto.

[0082] In some embodiments, the EC chip 500 can further include one or more storage control modules 505 for storing at least part of the replay protection related data, as shown in Figure 5. The processor 502 is configured to invoke the signature module 503 and control the one or more storage control modules 505 to verify and execute the replay protection command. Exemplary embodiments of the one or more storage control modules 505 can be found in Figure 3 and its description, which will not be repeated here.

[0083] In some examples, the processor 502 is further configured to, in a case where the predetermined data corresponding to the replay protection command in the generation of the replay protection related data is generated, store the predetermined data to the temporary storage module 506, and after generating the response corresponding to the replay protection command, synchronize the predetermined data stored in the temporary storage module 506 to the external storage module corresponding thereto through the one or more storage control modules 505.

[0084] In some embodiments, the EC chip 500 can further include one or more storage modules 504 and one or more storage control modules 505, as shown in Figure 5. Exemplary embodiments of the one or more storage modules 504 and the one or more storage control modules 505 can be found in Figures 4a to 4d, which will not be repeated here.

[0085] In some examples, the processor 502 is further configured to, in a case that the predetermined data corresponding to the replay protection command in the replay protection related data is generated, store the predetermined data to the temporary storage module 506, and after the response corresponding to the replay protection command is generated, synchronize the predetermined data stored in the temporary storage module 506 to the external storage module corresponding thereto or the storage module 504 corresponding thereto by the one or more storage control modules 505.

[0086] In some embodiments, as shown in FIG. 5, the EC chip 500 can further include a synchronization module 507. The processor 502 is further configured to, in a case that the predetermined data corresponding to the replay protection command in the replay protection related data is generated, store the predetermined data to the temporary storage module 506, and generate the response corresponding to the replay protection command. The synchronization module 507 is configured to synchronize the predetermined data stored in the temporary storage module 506 to the storage module 504 corresponding thereto or the external storage module corresponding thereto.

[0087] Embodiments of the present application implement replay protection by combining software and hardware. The hardware provides resources such as storage and signature, and the software schedules the hardware resources, so that replay protection can be flexibly implemented.

[0088] As an implementation form, the processor shown in FIGS. 1 to 5 of the foregoing description of the present specification can be configured to read a key for signature from at least one of the one or more storage modules or the one or more external storage modules, and send the key and a predetermined part of the replay protection command to the signature module. The signature module can be configured to receive the key and the predetermined part of the replay protection command, and sign the predetermined part of the replay protection command based on the key to generate signature information, and return the generated signature information to the processor.

[0089] As an implementation form, the EC chip shown in FIGS. 1 to 5 of the foregoing description of the present specification, the processor can be configured to: in a case that the binding root key command is received, call the signature module to sign a predetermined part of the binding root key command based on a root key carried by the binding root key command to generate signature information; verify the binding root key command based on the generated signature information and the signature information carried by the binding root key command; and in a case that the binding root key command is verified, write the root key to the corresponding storage module.

[0090] As an implementation form, the EC chip shown in the foregoing figures 1 to 5 of the specification, the processor can be configured to: in the case of receiving an update signature key command, invoke the signature module to sign a predetermined part of the update signature key command based on the storage root key to generate signature information; verify the update signature key command based on the generated signature information and the signature information carried by the update signature key command; in the case of passing the verification of the update signature key command, generate a signature key based on the root key and the key data carried by the update signature key command, and write the signature key into the corresponding storage module.

[0091] As an implementation form, the EC chip shown in the foregoing figures 1 to 5 of the specification, the processor can be configured to: in the case of receiving an increase replay protection monotonic counter value command (also referred to as a replay protection monotonic counter value plus 1 command), invoke the signature module to sign a predetermined part of the increase replay protection monotonic counter value command based on the signature key to generate signature information; verify the increase replay protection monotonic counter value command based on the generated signature information and the signature information carried by the increase replay protection monotonic counter value command; in the case of passing the verification of the increase replay protection monotonic counter value command, increase the replay protection monotonic counter value by one, and write the replay protection monotonic counter value after the increase into the corresponding storage module.

[0092] As an implementation form, the EC chip shown in the foregoing figures 1 to 5 of the specification, the processor can be configured to: in the case of receiving a read replay protection monotonic counter value command, invoke the signature module to sign a predetermined part of the read replay protection monotonic counter value command based on the signature key to generate signature information; verify the read replay protection monotonic counter value command based on the generated signature information and the signature information carried by the read replay protection monotonic counter value command; in the case of passing the verification of the read replay protection monotonic counter value command, read the replay protection monotonic counter value from the corresponding storage module; and generate a response carrying the replay protection monotonic counter value.

[0093] As an implementation form, the EC chip shown in the foregoing figures 1 to 5 of the specification, the processor can be configured to: generate a response corresponding to a replay protection command, and encapsulate the response and send the encapsulated data packet through the bus interface.

[0094] As an implementation form, the EC chip shown in the foregoing figures 1 to 5 of the specification, the processor can be configured to: invoke the signature module to sign a predetermined part of the response based on the signature key.

[0095] As an implementation form, the signature module shown in FIGS. 1-5 of the foregoing of the specification can include a hash message authentication code generation unit, and the signature information includes a hash message authentication code. The hash message authentication code is also referred to as hash-based message authentication code (HAMC). It should be understood that the embodiments of the present application do not limit the signature algorithm, and other algorithms capable of verifying the authenticity of data are also feasible, and the embodiments of the present application do not limit this.

[0096] As an implementation form, the bus interface shown in FIGS. 1-5 of the foregoing of the specification can include an eSPI interface.

[0097] As an implementation form, the EC chip shown in FIGS. 1-5 of the foregoing of the specification can include an eSPI interface, and the signature module can include an HMAC calculation module.

[0098] The embodiments of the present application also provide a sealing chip, which seals an external storage chip and an EC chip, that is, integrates the EC chip and the external storage chip in one package, so as to realize higher integration and smaller size, reduce the power consumption of the electronic device, improve the performance and simplify the design.

[0099] FIG. 6 shows a structure schematic diagram of a sealing chip according to an embodiment of the present application. As shown in FIG. 6, the sealing chip 600 can include one or more storage chips 610 for storing at least part of the replay protection related data, and an EC chip 620 including a bus interface 621, a processor 622, a signature module 623 and one or more storage control modules 625. The bus interface 621 is configured to receive and send data packets. The signature module 623 is configured to generate signature information. The one or more storage control modules 625 are configured to access the one or more storage chips 610. The processor 622 is configured to parse the received data packets, and when a replay protection command is parsed, the processor 622 is configured to call the signature module 623 to verify and execute the replay protection command. In the process of verifying and executing the replay protection command, the processor 622 can access the one or more storage chips 610 through the one or more storage control modules 625.

[0100] In some embodiments, the one or more storage chips 610 can include a first storage chip 610-1 for storing a root key.

[0101] In some embodiments, the one or more storage chips 610 can include a second storage chip 610-2 for storing a signature key generated based on the root key.

[0102] In some embodiments, the one or more storage chips 610 can include a third storage chip 610-3 for storing a replay protection monotonic counter value.

[0103] In some embodiments, the one or more storage chips 610 can include: a first storage chip 610-1 for storing a root key; a second storage chip 610-2 for storing a signature key generated based on the root key; and a third storage chip 610-3 for storing a replay protection monotonic counter value.

[0104] In some embodiments, the EC chip 620 can further include: one or more storage modules 624. The one or more storage modules 624 can be used to store a first part of replay protection related data, and the one or more storage chips 610 can be used to store a second part of the replay protection related data. The one or more storage modules 624 can include the following parts: a first storage module for storing a root key; a second storage module for storing a signature key generated based on the root key; and a third storage module for storing a replay protection monotonic counter value.

[0105] As an example, as shown in FIG. 6, the one or more storage modules 624 can include a third storage module 624-3 for storing a replay protection monotonic counter value. The one or more storage chips 610 include: a first storage chip 610-1 for storing a root key; and a second storage chip 610-2 for storing a signature key generated based on the root key. It should be understood that FIG. 6 is only an exemplary combination of storage modules and storage chips, and other combinations of storage modules and storage chips can be referred to FIGS. 4a-4d, and the embodiments of the present application do not repeat them here.

[0106] The EC chip 620 can be referred to FIGS. 3-5 and the description thereof, and the embodiments of the present application do not repeat them here. In addition, although FIG. 6 shows an example in which the signature module 623 is located outside the processor 622, in the present specification, the signature module 623 can be integrated inside the processor 622, and the embodiments of the present application do not repeat them here.

[0107] The embodiments of the present application realize replay protection by combining software and hardware. The hardware provides storage, signature and other resources, and the software schedules the hardware resources, which can flexibly realize replay protection.

[0108] The embodiment of the present application further provides a system. In some embodiments, the system can include the EC chip of the embodiment of the present application and one or more storage modules outside the EC chip. The structure and combination of the EC chip and the storage module outside the EC chip are described above and will not be repeated here. The system receives and parses the replay protection command by using the bus interface and the processor of the EC chip, the processor calls the signature module to verify and execute the replay protection command, the replay protection is realized in the EC chip, and the signature information can be quickly generated in a hardware manner by the signature module, thereby improving the processing speed. The embodiment of the present application can realize the replay protection in electronic devices using the EC chip such as notebook computers. The possible implementation of the system can be referred to the description above and will not be repeated here.

[0109] The embodiment of the present application further provides an electronic device, which includes a device main body and a chip as described above arranged in the device main body. The electronic device can be, but is not limited to, a body weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a human body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a vehicle charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a touch pen, a true wireless earphone, a car central control screen, a car, a smart wearable device, a mobile terminal, and a smart home device. The smart wearable device includes, but is not limited to, a smart watch, a smart bracelet, and a cervical vertebra massage instrument. The mobile terminal includes, but is not limited to, a smart phone, a notebook computer, a tablet computer, and a POS (point of sales terminal) machine. The smart home device includes, but is not limited to, a smart socket, a smart rice cooker, a smart sweeper, and a smart lamp. The electronic device receives and parses the replay protection command by using the bus interface and the processor of the EC chip, the processor calls the signature module to verify and execute the replay protection command, the replay protection is realized in the EC chip, and the signature information can be quickly generated in a hardware manner by the signature module, thereby improving the processing speed. The embodiment of the present application can realize the replay protection in electronic devices using the EC chip such as notebook computers.

[0110] The following describes an exemplary replay protection command verification and execution process realized by the EC chip, the sealed chip, the system and the electronic device provided by the embodiment of the present application by taking the eSPI OOB channel implementation of the RPMC (RPMC over eSPI OOB, eRPMC) as an example. In the EPRMC scheme, the bus interface of the embodiment of the present application is an eSPI interface, the signature module can be an HMAC calculation module for implementing the HAMC algorithm, and the signature key generated according to the root key can be an HMAC key (HMAC-key).

[0111] The EC chip, the sealing chip, and the system adopting the embodiment of the application can include: the eSPI interface of the EC chip receives a data packet (eSPI OOB packet) including a replay protection command, the processor of the EC chip parses the received data packet to obtain the replay protection command, and processes according to the received replay protection command, such as calling a signature module to calculate, verify, generate an HMAC-key value, and write a Root key. After the processing is completed, relevant information (i.e., a response corresponding to the replay protection command) is replied using the eSPI interface according to the processing result.

[0112] An exemplary Root key binding process is shown in FIG. 7. The EC chip receives a command for binding a Root key from the PCH using the eSPI interface, and then transfers the received data packet to the Core of the processor for parsing. The Core calculates the command information and verifies the signature using the HMAC calculation module (or the HMAC calculation module outside the processor) of the Core. If the verification is correct, the Root key carried in the command is written into the corresponding storage module (NVM 1), and the PCH command execution condition is replied. If the verification is incorrect, the PCH command execution condition is directly replied.

[0113] An exemplary update signature key (HMAC-key) process is shown in FIG. 8. The command for updating the HMAC-key is sent each time the PCH is powered on. The EC chip eSPI interface receives the information, and then transfers the command information to the Core for parsing. Then, the Core generates the HMAC-key value and the command signature using the HMAC calculation module (or the HMAC calculation module outside the processor) of the Core according to the Root key and the parsed information. If the verification result is correct, the Core writes the HMAC-key into the corresponding storage module (Momery 1), and then replies the PCH command execution condition. If the verification is incorrect, the PCH command execution condition is directly replied.

[0114] An exemplary read replay protection monotonic counter value (Monotonic Counter) process is shown in FIG. 9. When the EC chip eSPI interface receives the read Monotonic Counter command, the Core is transferred for parsing. The Core calculates and verifies the signature using the internal HMAC calculation module (or the HMAC calculation module outside the processor) according to the parsed information. Whether the verification passes or not, the command execution condition is replied.

[0115] An exemplary replay protection monotonic counter value increase 1 (Monotonic Counter Increase 1) flow is shown in FIG. 10. The eSPI interface of the EC chip receives the Monotonic Counter Increase 1 command, which is parsed by the Core to obtain relevant information. Then the Core uses an internal HMAC calculation module (or an HMAC calculation module external to the processor) to calculate and verify the calculation result. If the verification result is correct, the value of Counter+1 is written to the corresponding storage module (NVM 2), and the command execution status is returned. If the verification result is incorrect, the command execution status is directly returned.

[0116] An exemplary read RPMC parameter flow is shown in FIG. 11. The read RPMC parameter command is a non-standard RPMC command and is specific to eRPMC. After the EC Core receives the eSPI command, the command information is parsed. Then the eRPMC information is read and the command is returned.

[0117] This scheme combines software and hardware to implement the eRPMC function. The hardware on the EC chip provides hardware resources such as the eSPI interface, the processor, and the HMAC calculation module. The software is responsible for parsing the received command, calling the HMAC calculation module, and returning information through the interface according to the processing result.

[0118] The above is only a preferred embodiment of the present application and does not limit the present application in any form. Although the preferred embodiment has been disclosed as above, it is not intended to limit the present application. Any person skilled in the art can make minor changes or modifications to the above disclosed technical content to obtain equivalent embodiments with equivalent changes without departing from the scope of the technical solution of the present application. Any simple modification, equivalent change, and modification of the above embodiments made in accordance with the technical essence of the present application are still within the scope of the technical solution of the present application.

Claims

1. An EC chip, comprising: a bus interface configured to receive and transmit data packets; a signature module configured to generate signature information; a processor coupled to the bus interface and configured to parse a received data packet and invoke the signature module to verify and execute a replay protection command if the replay protection command is parsed from the received data packet.

2. The EC chip of claim 1, wherein, The signature module is integrated in the processor.

3. The EC chip of claim 1, wherein, The signature module is external to the processor.

4. The EC chip of claim 1, wherein, Further comprising: one or more storage control modules configured to access one or more external storage modules configured to store at least part of replay protection related data; the processor configured to access the one or more external storage modules via the one or more storage control modules.

5. The EC chip of claim 1, wherein, Further comprising: one or more storage modules configured to store at least part of replay protection related data; wherein the processor is configured to access the one or more storage modules.

6. The EC chip of claim 1, wherein, Further comprising: one or more storage modules configured to store a first part of replay protection related data; one or more storage control modules configured to access one or more external storage modules configured to store a second part of replay protection related data; the processor configured to access the one or more storage modules and the one or more external storage modules via the one or more storage control modules.

7. The EC chip according to claim 5 or 6, wherein The one or more storage modules comprise: a first storage module configured to store a root key.

8. The EC chip according to claim 5 or 6, wherein, The one or more storage modules comprise: a second storage module configured to store a signature key generated based on the root key.

9. The EC chip of claim 5 or 6, wherein, The one or more storage modules comprise: a third storage module configured to store a replay protection monotonic counter value.

10. The EC chip of claim 4 or 6, wherein, The one or more storage control modules comprise: a first storage control module configured to access a first external storage module configured to store the root key.

11. The EC chip of claim 4 or 6, wherein, The one or more storage control modules comprise: a second storage control module configured to access a second external storage module configured to store the signature key generated based on the root key.

12. The EC chip of claim 4 or 6, wherein, The one or more storage control modules comprise: a third storage control module configured to access a third external storage module configured to store the monotonic counter value.

13. The EC chip of claim 1, wherein, Further comprising: a staging module; wherein the processor is further configured to store predetermined data corresponding to the replay protection command in the staging module if the predetermined data is generated, and synchronize the predetermined data stored in the staging module to a storage module corresponding thereto after a response corresponding to the replay protection command is generated.

14. The EC chip of claim 1, wherein, Further comprising: a staging module and a synchronization module; wherein the processor is further configured to store predetermined data corresponding to the replay protection command in the staging module if the predetermined data is generated, and generate a response corresponding to the replay protection command; the synchronization module configured to synchronize the predetermined data stored in the staging module to a storage module corresponding thereto.

15. The EC chip according to claim 13 or 14, wherein, The staging module comprises a backup register.

16. A package chip, comprising: one or more external storage chips; The EC chip of any one of claims 1 to 15.

17. A system comprising: one or more external storage modules; The EC chip of any one of claims 1 to 15.

18. An electronic device comprising a device body and an EC chip as claimed in any one of claims 1 to 15, or a hermetic chip as claimed in claim 16, or a system as claimed in claim 17, disposed in the device body.

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