Coding method and apparatus, and decoding method and apparatus

Abstract

The present application relates to the technical field of wireless communications, and provides a coding method and apparatus and a decoding method and apparatus, which are used to improve the error correction performance of coding. The method comprises: a first communication apparatus acquires a first sequence, the first sequence being a bit sequence to be coded, the first sequence comprising K0 information bits, C1 first check bits, and C2 second check bits, (C1+C2) being greater than 0, C1 being greater than or equal to 0, and C2 being greater than or equal to 0; and the first communication apparatus performs parity check polar coding on the first sequence, K0 being within a first length range, the first length range being [K1, K2], K2 being an integer greater than 19, and / or K1 being an integer less than 12. On the basis of the solution, the scope in which PC-CA polar is supported is broadened, thereby improving the range of applicability of the PC-CA polar in short error-correction code scenarios.

Description

Encoding and decoding method and device

[0001] Cross-reference to related applications

[0002] This application claims priority to the Chinese Patent Application No. 202410462575.9, filed on April 16, 2024, and entitled "Encoding and decoding method and device", the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present application relates to the technical field of wireless communication, and in particular to an encoding and decoding method and device. BACKGROUND

[0004] At present, the uplink control information (UCI) payload of new radio (NR) adopts polar encoding when it is greater than 11 bits. Among them, 12-19 bits of UCI payload need to add 6 cyclic redundancy check (CRC) bits, and UCI payload of more than 19 bits needs to add 11 CRC bits, which is called CRC aid polar (CA polar).

[0005] Among them, the polar encoding method of UCI greater than 11 bits is different from the CRC addition method. If the UCI length K after adding CRC satisfies 18≤K≤25, parity check (PC) needs to be performed before polar encoding, that is, the polar encoding method is PC-CA polar.

[0006] However, the coverage of PC-CA polar in the short code area is limited at present. SUMMARY

[0007] The present application provides an encoding and decoding method and device for improving the coverage of parity check polar encoding in the short code area.

[0008] In a first aspect, an encoding method is provided. The method can be performed by a first communication device or a module (such as a chip, a chip system, or a circuit, etc.) applied in the first communication device. Taking the first communication device as an example, the method includes: obtaining, by the first communication device, a first sequence, the first sequence being a bit sequence to be encoded, the first sequence including K0 information bits, C1 first check bits, and C2 second check bits. Wherein, C1+C2 is greater than 0, C1 is greater than or equal to 0, and C2 is greater than or equal to 0; K0 belongs to a first length range, the first length range being [K1, K2], K2 being an integer greater than 19, and / or K1 being an integer less than 12. The first communication device performs parity check polar encoding on the first sequence.

[0009] Based on the scheme, for a sequence in the range [K1, K2], C1 first check bits and C2 second check bits can be added. Since K2 is greater than 19, the range supported by PC-CA polar is expanded, so that the coverage of PC-CA polar in the short code area can be improved. Compared with the PC-CA polar in the related art which only covers the interval of 8 information bits from 12 to 19, the encoding method of PC-CA polar is provided for a larger interval of information bits, thereby providing stronger error correction capability for information bits falling outside the range from 12 to 19.

[0010] In a second aspect, a decoding method is provided. The method can be performed by a second communication device or a module (such as a chip, a chip system, or a circuit, etc.) applied in the second communication device. Taking the second communication device as an example, the method includes: receiving, by the second communication device, a second sequence, the second sequence being obtained by performing parity check polar encoding on a first sequence. Wherein, the first sequence is a bit sequence to be encoded, the first sequence including K0 information bits, C1 first check bits, and C2 second check bits. Wherein, C1+C2 is greater than 0, C1 is greater than or equal to 0, and C2 is greater than or equal to 0; K0 belongs to a first length range, the first length range being [K1, K2], K2 being an integer greater than 19, and / or K1 being an integer less than 12. The second communication device decodes the second sequence based on a check relationship among the first check bits, the second check bits, and the information bits to obtain the information bits.

[0011] In a third aspect, a communication apparatus is provided, which includes a processing unit and a transceiver unit. The processing unit is configured to obtain a first sequence, the first sequence being a bit sequence to be encoded, the first sequence including K0 information bits, C1 first check bits and C2 second check bits. Wherein C1+C2 is greater than 0, C1 is greater than or equal to 0, and C2 is greater than or equal to 0; K0 belongs to a first length range, the first length range being [K1, K2], K2 being an integer greater than 19, and / or K1 being an integer less than 12. The processing unit is further configured to perform parity check polar encoding on the first sequence. The transceiver unit is configured to transmit the sequence after parity check polar encoding.

[0012] In a fourth aspect, a communication apparatus is provided, which includes a processing unit and a transceiver unit. The transceiver unit is configured to receive a second sequence, the second sequence being obtained by performing parity check polar encoding on a first sequence. Wherein the first sequence is a bit sequence to be encoded, the first sequence including K0 information bits, C1 first check bits and C2 second check bits. Wherein C1+C2 is greater than 0, C1 is greater than or equal to 0, and C2 is greater than or equal to 0; K0 belongs to a first length range, the first length range being [K1, K2], K2 being an integer greater than 19, and / or K1 being an integer less than 12. The processing unit is configured to decode the second sequence based on a check relationship between the first check bits, the second check bits and the information bits, to obtain the information bits.

[0013] According to any one of the first aspect to the fourth aspect, when K0 belongs to a second length range, C1 is a first length, the second length range being [K1, K3), K3 being less than or equal to K2. When K0 belongs to a third length range, C1 is a second length, the third length range being (K3, K2]. When K0=K3, C1 is the first length or the second length.

[0014] According to the above scheme, using different numbers of CRC bits in PC-CA polar encoding can improve the flexibility of encoding, so that it can be applied to various scenarios, and the number of CRC bits can be configured to adapt to different scenarios.

[0015] According to any one of the first aspect to the fourth aspect, the second check bits are obtained based on a check relationship between the information bits and the second check bits.

[0016] According to any one of the first aspect to the fourth aspect, the check relationship between the information bits and the second check bits is obtained through a multi-tap shift register with feedback.

[0017] In any of the first to fourth aspects, when the position of the multi-tap shift register is a message bit for placing the information bit, the output of the multi-tap shift register is the input of the multi-tap shift register. Alternatively, when the position of the multi-tap shift register is a dynamic frozen bit, the output of the multi-tap shift register is the value of the tap at the end of the moving direction of the multi-tap shift register. Alternatively, when the position of the multi-tap shift register is a frozen bit, the output of the multi-tap shift register is 0.

[0018] According to the above scheme, the multi-tap shift register is used to determine the second check bit according to the check relationship between the information bit and the second check bit, and the complexity of encoding can be reduced.

[0019] According to any of the first to fourth aspects, the check relationship between the information bit and the second check bit is determined according to K0 and a target transmission code length E, and E is a transmission code length after rate matching of the first sequence after the parity check polar encoding.

[0020] According to any of the first to fourth aspects, K1=12 and K3=19.

[0021] According to any of the first to fourth aspects, the check relationship between the information bit and the second check bit satisfies any one of the following polynomials:

[0022] E is a transmission code length after rate matching of the first sequence after the parity check polar encoding.

[0023] According to any of the first to fourth aspects, K3=19 and K2=52.

[0024] According to any of the first to fourth aspects, the check relationship between the information bit and the second check bit satisfies any one of the following polynomials:

[0025] E is a transmission code length after rate matching of the first sequence after the parity check polar encoding.

[0026] According to the above scheme, the application provides a corresponding relationship between the information bit and the second check bit corresponding to the information bit in the range of 12-52, so that the range of the number of information bits supported by the PC-CA polar encoding can be expanded.

[0027] According to any of the first to fourth aspects, the length of the polynomial satisfying the check relationship between the information bit and the second check bit is less than or equal to 4.

[0028] In any of the first to fourth aspects, K1=12, K3=19, the number of third check bits satisfies one of the following corresponding relationships, the third check bits are part of the second check bits, and the third check bits are determined according to the row weight:

[0029] wherein E is a transmission code length after rate matching of the first sequence after parity check polar encoding.

[0030] In any of the first to fourth aspects, K3=19, K2=52, the number of third check bits satisfies one of the following corresponding relationships, the third check bits are part of the second check bits, and the third check bits are determined according to the row weight:

[0031] wherein the third length range is K3~K2, and K3 is less than or equal to K2.

[0032] In any of the first to fourth aspects, the position set in which the second check bits are placed in the mother code sequence corresponding to the first sequence is determined according to K0 and a target transmission code length E, and E is a transmission code length after rate matching of the first sequence after parity check polar encoding.

[0033] Based on the above scheme, the present application provides a number of second check bits corresponding to a number of information bits in the range of 12~52, so that the range of information bits supported by PC-CA polar encoding can be expanded.

[0034] In a fifth aspect, a communication device is provided for implementing the above-described various methods. The communication device can be the first communication device in the first aspect, or a device containing the first communication device, or a device contained in the first communication device, such as a chip; or the communication device can be the second communication device in the second aspect, or a device containing the second communication device, or a device contained in the second communication device. The communication device includes modules, units, or means corresponding to the above methods, which can be implemented by hardware, software, or by hardware executing corresponding software. The hardware or software includes one or more modules or units corresponding to the above functions.

[0035] In a sixth aspect, a communication apparatus is provided, which comprises a processor and a communication interface; the communication interface is configured to communicate with a module outside the communication apparatus; the processor is configured to execute computer programs or instructions, so that the method in any of the aspects described above is executed. The communication apparatus can be the first communication apparatus in the first aspect, or a device comprising the first communication apparatus, or a device included in the first communication apparatus, such as a chip; or the communication apparatus can be the second communication apparatus in the second aspect, or a device comprising the second communication apparatus, or a device included in the second communication apparatus.

[0036] In a seventh aspect, a communication apparatus is provided, which comprises at least one processor; the processor is configured to execute computer programs or instructions stored in a memory, so as to implement the method in any of the aspects described above. The memory can be coupled with the processor, or can be independent of the processor. The communication apparatus can be the first communication apparatus in the first aspect, or a device comprising the first communication apparatus, or a device included in the first communication apparatus, such as a chip; or the communication apparatus can be the second communication apparatus in the second aspect, or a device comprising the second communication apparatus, or a device included in the second communication apparatus.

[0037] In an eighth aspect, the present application provides a communication system, which can comprise the first communication apparatus executing the method in the first aspect and the second communication apparatus executing the method in the second aspect.

[0038] In a ninth aspect, the present application provides a computer readable storage medium, which stores computer readable instructions, when a computer reads and executes the computer readable instructions, the computer executes the method in any possible implementation manner of any of the first aspect to the second aspect.

[0039] In a tenth aspect, the present application provides a computer program product, when a computer reads and executes the computer program product, the computer executes the method in any possible implementation manner of any of the first aspect to the second aspect.

[0040] In an eleventh aspect, the present application provides a chip, which is used to read computer programs stored in a memory, so as to execute the method in any possible implementation manner of any of the first aspect to the second aspect.

[0041] It can be understood that the technical effects of the fifth aspect to the eleventh aspect can refer to the technical effects of the first aspect to the fourth aspect, which will not be described herein. BRIEF DESCRIPTION OF DRAWINGS

[0042] FIG. 1 is a schematic diagram of a communication system architecture according to an embodiment of the present application;

[0043] FIG. 2 is a schematic diagram of a coding and decoding process according to an embodiment of the present application;

[0044] FIG. 3 is an exemplary flowchart of an encoding method according to an embodiment of the present application;

[0045] FIG. 4 is a schematic diagram of a process of determining positions of second check bits and information bits in a mother code sequence according to an embodiment of the present application;

[0046] FIG. 5 is a schematic diagram of a shift register according to an embodiment of the present application;

[0047] FIG. 6 is a schematic diagram of another shift register according to an embodiment of the present application;

[0048] FIG. 7 is an exemplary flowchart of a decoding method according to an embodiment of the present application;

[0049] FIG. 8A is a schematic diagram of a simulation result according to an embodiment of the present application;

[0050] FIG. 8B is a schematic diagram of another simulation result according to an embodiment of the present application;

[0051] FIG. 9 is a schematic diagram of a structure of a communication apparatus according to an embodiment of the present application;

[0052] FIG. 10 is a schematic diagram of a structure of another communication apparatus according to an embodiment of the present application;

[0053] FIG. 11 is a schematic diagram of a structure of another communication apparatus according to an embodiment of the present application;

[0054] FIG. 12 is a schematic diagram of a structure of another communication apparatus according to an embodiment of the present application. DETAILED DESCRIPTION

[0055] The technical solutions of the embodiments of the present application can be applied to various communication systems, for example: a global system for mobile communications (GSM), an enhanced data rate for GSM evolution (EDGE), a wideband code division multiple access (WCDMA) system, a time division-synchronization code division multiple access (TD-SCDMA) system, a long term evolution (LTE) system, a worldwide interoperability for microwave access (WiMAX) communication system, a 5th generation (5G) mobile communication system such as a new radio (NR) system, and the like. The technical solutions provided in the present application can also be applied to future communication systems such as a 6th generation (6G) mobile communication system, and the like. The communication system can also be a Bluetooth communication system, a wireless local area network (WLAN) / wireless communication technology (WiFi) communication system, a narrow band internet of things (NB-IoT) communication system, and the like. The technical solutions of the embodiments of the present application can also be applied to a satellite communication system, wherein the satellite communication system can be integrated with the above-mentioned communication systems.

[0056] In order to facilitate understanding of the embodiments of the present application, the application scenarios used in the present application are described by taking the communication system architecture shown in FIG. 1 as an example. Referring to FIG. 1, the communication system includes a network device 101 and a terminal device 102. The communication apparatus provided in the embodiments of the present application can be applied to the network device 101 or the terminal device 102. It can be understood that FIG. 1 only shows one possible communication system architecture to which the embodiments of the present application can be applied, and in other possible scenarios, other devices can also be included in the communication system architecture.

[0057] The network device 101 is a node in a radio access network (RAN), which can be referred to as an access network device, a RAN node, and the like. Optionally, the RAN can be a 3GPP related cellular system, for example, a 4G mobile communication system (such as an LTE system), a 5G mobile communication system (such as an NR system), or a future-oriented evolution system (for example, a 6G mobile communication system). The RAN can also be an open RAN (O-RAN or ORAN), a cloud radio access network (CRAN), or a wireless fidelity (WiFi) system. The RAN can also be a communication system that combines two or more of the above systems.

[0058] In a possible scenario, the access network device can be a base station, an evolved NodeB (eNodeB), an access point (AP), a transmission reception point (TRP), a next generation NodeB (gNB), a next generation base station in a 6th generation (6G) mobile communication system, a base station in a future mobile communication system, or an access node in a WiFi system, and the like. The access network device can also be a macro base station, a micro base station, or an indoor station, a relay node or a donor node, or a wireless controller in a CRAN scenario. Optionally, the access network device can also be a server, a wearable device, a vehicle or a vehicle-mounted device, and the like. For example, the access network device in vehicle to everything (V2X) technology can be a road side unit (RSU).

[0059] In another possible scenario, a terminal is assisted by multiple RAN nodes to implement wireless access in cooperation, and different RAN nodes respectively implement part of functions of a base station. For example, a RAN node can be a central unit (CU), a distributed unit (DU), a CU-control plane (CP), a CU-user plane (UP), or a radio unit (RU), etc. The CU and the DU can be separately arranged, or can be included in the same network element, for example, in a baseband unit (BBU). The RU can be included in a radio frequency device or a radio frequency unit, for example, in a remote radio unit (RRU), an active antenna processing unit (AAU), or a remote radio head (RRH).

[0060] In different systems, the CU (or CU-CP and CU-UP), DU or RU can also have different names, but those skilled in the art can understand their meanings. For example, in an ORAN system, the CU can also be referred to as an open centralized unit (O-CU) or an open CU, the DU can also be referred to as an open distributed unit (O-DU), the CU-CP can also be referred to as an open centralized unit control plane (O-CU-CP), the CU-UP can also be referred to as an open centralized unit user plane (O-CU-UP), and the RU can also be referred to as an open radio unit (O-RU). For the convenience of description, the CU, CU-CP, CU-UP, DU and RU are taken as examples for description in this application. Any one of the CU (or CU-CP, CU-UP), DU and RU in this application can be implemented by a software module, a hardware module, or a combination of a software module and a hardware module.

[0061] In the embodiments of this application, the functions of the network device can also be performed by a module (such as a chip) in the network device, or by a control subsystem containing network device functions. The control subsystem containing network device functions herein can be a control center in the above-mentioned application scenarios such as smart grid, industrial control, intelligent transportation, and smart city.

[0062] The terminal device 102, which can also be referred to as a user equipment (UE), a mobile station (MS), a mobile terminal (MT), or the like, is a device that provides voice or data connectivity to a user, and can also be an Internet of Things (IoT) device. For example, the terminal device includes a handheld device having wireless connection capability, a vehicle-mounted device, or the like. Currently, the terminal device can be a mobile phone, a tablet computer, a notebook computer, a palm computer, a mobile Internet device (MID), a wearable device (e.g., a smart watch, a smart bracelet, a pedometer, or the like), a vehicle-mounted device (e.g., a car, a bicycle, an electric vehicle, an airplane, a ship, a train, a high-speed rail, or the like), a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a smart home device (e.g., a refrigerator, a television, an air conditioner, an electricity meter, or the like), a smart robot, a plant device, a wireless terminal in unmanned driving, a wireless terminal in remote surgery, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, or a wireless terminal in a smart home, a flight device (e.g., a smart robot, a hot air balloon, a drone, an airplane), or the like. The terminal device can also be other devices having terminal functions, for example, the terminal device can also be a device that plays a terminal function in device-to-device (D2D) communication. In this application, the terminal device having wireless transceiving function and the chip that can be arranged in the terminal device are collectively referred to as the terminal device.

[0063] In the embodiments of the present application, the functions of the terminal device can also be performed by a module (such as a chip or a modem) in the terminal device, or by a device containing terminal functions.

[0064] The network device and the terminal can be fixed in position or movable. The network device and the terminal can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; can also be deployed on the water surface; and can also be deployed on an airplane, a balloon, and a man-made satellite in the air. The embodiments of the present application do not limit the application scenarios of the network device and the terminal.

[0065] In the embodiments of the present application, “at least one” means one or more, and “multiple” means two or more. “And / or” describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can represent the following three cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character “ / ” generally represents an “or” relationship between the front and rear associated objects. “At least one of the following” or similar expressions means any combination of these items, including single item or any combination of multiple items. For example, at least one of a, b and (or) c can represent a, b, c, a and b, a and c, b and c, or a, b and c, where each of a, b and c can be an element or a set containing one or more elements.

[0066] In the present application, “example”, “in some embodiments”, “in another embodiment” and the like are used to represent an example, illustration or description. Any embodiment or design scheme described as “example” in the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the use of the word “example” is intended to present the concept in a specific manner.

[0067] In the present application, “of”, “corresponding” and “corresponding” can be used interchangeably at times. It should be pointed out that when the distinction is not emphasized, the meanings expressed are consistent. In the embodiments of the present application, communication and transmission can be used interchangeably at times. It should be pointed out that when the distinction is not emphasized, the meanings expressed are consistent. For example, transmission can include sending and / or receiving, and can be a noun or a verb.

[0068] In the present application, “indication” can include direct indication, indirect indication, display indication and implicit indication. When describing that certain indication information is used to indicate A, it can be understood that the indication information carries A, directly indicates A, or indirectly indicates A.

[0069] It should be noted that the terms “first”, “second”, etc. involved in the embodiments of the present application are only used for the purpose of distinguishing description, and cannot be understood as indicating or implying relative importance, nor can it be understood as indicating or implying order.

[0070] Currently, when the NR UCI payload is greater than 11 bits, polar encoding is used. Among them, 12-19 bits of UCI payload need to add 6 CRC bits, and UCI payload of more than 19 bits needs to add 11 CRC bits, which is called CA polar.

[0071] It can be understood that the "payload" herein can be understood as information bits. For example, the payload of the UCI can be understood as the information bits contained by the UCI.

[0072] In the UCI with more than 11 bits, the polar encoding manner is different from that of the CRC addition manner. If the length K of the UCI after the CRC addition satisfies 18≤K≤25, PC needs to be performed before the polar encoding, that is, the polar encoding manner is PC-CA polar. The number of PC bits is equal to 3. The following is introduced through Table 1.

[0073] Table 1: An example of a UCI encoding mode

[0074] As shown in Table 1, when the number of UCI payload bits is 3-11 bits, LTE Reed-Muller (RM) encoding can be used. When the number of UCI payload bits is 12-19 bits, PC-CA polar encoding can be used, in which the number of PC bits is 3 and the number of CRC bits is 6. When the number of UCI payload bits is greater than 19, CA polar encoding is used, and the number of CRC bits is 11. It can be seen that the PC-CA polar currently can support a limited range of UCI payload bits (only 12-19), and therefore the applicable range of the PC-CA polar with error correction capability and error detection capability is limited, which is not conducive to fully exerting the capability of the PC-CA polar.

[0075] In view of this, an embodiment of the present application provides an encoding and decoding method. In the method, a sending end can obtain a first sequence, the first sequence being a bit sequence to be encoded. The first sequence can include K0 information bits, C1 first check bits and C2 second check bits. In the method, C1+C2 is greater than 0, C1 is greater than or equal to 0, and C2 is greater than or equal to 0; K0 belongs to [K1, K2], K2 is an integer greater than 19, and / or K1 is an integer less than 12. The sending end can perform parity check polar encoding on the first sequence. Based on the scheme, the sequence in the range of [K1, K2] can add C1 first check bits and C2 second check bits. Since K2 is greater than 19, the range of adding PC bits and CRC bits can be expanded, so that the coverage range of the PC-CA polar in the short code area can be improved. Compared with the PC-CA polar in the related art which only covers the interval of 8 information bits from 12 to 19, the present application provides an encoding manner of the PC-CA polar for a larger information bit interval, thereby providing stronger error correction capability for information bits falling outside the range of 12-19.

[0076] As shown in FIG. 1, in order to ensure the reliability of the communication between devices, the sending end can encode the information to be sent, and accordingly, the receiving end decodes the encoded information after receiving it. As shown in FIG. 2, the source of the sending end sequentially undergoes source encoding, channel encoding, rate matching and modulation, and then sends on the channel. The receiving end sequentially undergoes demodulation and rate dematching, channel decoding and source decoding after receiving the signal, and then obtains the sink. The sending end and the receiving end can be network devices or terminal devices. It can be understood that in downlink communication, the network device is the sending end and the terminal device is the receiving end; in uplink communication, the terminal device is the sending end and the network device is the receiving end. The network device can be the sending end or the receiving end. In addition, the application also does not exclude that the sending end and the receiving end are both terminal devices, at which time the sending end and the receiving end perform D2D communication. The method provided in the embodiments of the application can be used in the channel encoding process.

[0077] As shown in FIG. 3, a flowchart of an encoding method. The method can be applied to a first communication device. The first communication device can be the sending end in the encoding and decoding process shown in FIG. 2; accordingly, the second communication device can be the receiving end in the encoding and decoding process shown in FIG. 2. For example, when the first communication device is a terminal device or a module (such as a chip) in a terminal device, the second communication device can be a terminal device or a module (such as a chip) in a terminal device, or the second communication device can also be a network device or a module (such as a chip) in a network device; when the first communication device is a network device or a module (such as a chip) in a network device, the second communication device can be a module (such as a chip) in a terminal device. The method comprises:

[0078] S301: The first communication device acquires a first sequence.

[0079] The first sequence is a bit sequence to be encoded. The first sequence includes K0 information bits, C1 first check bits and C2 second check bits. For example, the information bits can be information bits after source encoding. For example, the first check bits can be CRC bits, and the second check bits can be PC bits.

[0080] In a possible implementation, K0 can belong to a first length range [K1, K2]. In an example, K2 can be an integer greater than 19, such as 20, 21, 52 or 53, etc. The following is illustrated in combination with Table 2.

[0081] Table 2: An example of an encoding code type of a first sequence

[0082] As shown in Table 2, compared with Table 1, the number of payload bits of the first sequence supporting PC-CA polar encoding can be enlarged from 12-19 bits to 12-K2, such as 12-52. Based on this scheme, the first sequence greater than 19 bits can improve the error correction capability through PC bits, and due to the presence of CRC bits, the error detection capability is not affected.

[0083] K1 is 12 in Table 2 as an example. In another example, K1 can be an integer less than 12, such as 11, 10, 7, or 3, etc. In other words, the lower limit of the number of payload bits of the first sequence supporting PC-CA polar encoding can be reduced from 12 to 11, 10, 7, or 3.

[0084] That is, in the encoding method provided by the embodiments of the present application, in one possible case, the number of payload bits of the first sequence supporting PC-CA polar encoding can increase the upper limit from 19 to an integer greater than 19, such as the upper limit increasing to 52, and then the number of payload bits of the first sequence supporting PC-CA polar encoding can be enlarged from 12-19 bits to 12-K2 (such as 52). In another possible case, the number of payload bits of the first sequence supporting PC-CA polar encoding can reduce the lower limit from 12 to an integer less than 12, such as the lower limit reducing to 3, and then the number of payload bits of the first sequence supporting PC-CA polar encoding can be enlarged from 12-19 bits to K1 (such as 3)-19. In another possible case, the number of payload bits of the first sequence supporting PC-CA polar encoding can increase the upper limit and reduce the lower limit, such as can be enlarged from 12-19 bits to [K1, K2]. Taking K1 as 3 and K2 as 52 as an example. Then the range of the number of payload bits of the first sequence supporting PC-CA polar encoding can be enlarged from 12-19 to 3-52. Based on this scheme, the coverage of PC-CA polar in the short code area can be enlarged. Optionally, in the embodiments of the present application, K1 is a code point of a first-order RM code of a mother code length N={32, 16, 64}, and a code point of a first-order RM code of a mother code length N=2^n is (n+1).

[0085] In S301, C1+C2 is greater than 0, C1 is greater than or equal to 0, and C2 is greater than or equal to 0. For example, in the case of C1 equal to 0 and C2 greater than 0, it can be understood that the first sequence includes C2 second check bits; in the case of C1 greater than 0 and C2 equal to 0, it can be understood that the first sequence includes C1 first check bits; in the case of C1 greater than 0 and C2 greater than 0, it can be understood that the first sequence includes C1 first check bits and C2 second check bits.

[0086] In one possible case, assuming the first check bits are CRC bits, the number of the first check bits can be fixed, such as 3, 6, 11 or other number, when K0 belongs to the range of K1~K2.

[0087] In another possible case, assuming the first check bits are CRC bits, the number of the first check bits can be related to the number of the payload bits of the first sequence, when K0 belongs to the range of K1~K2. For example, K1~K2 can be divided into P groups, the number of the payload bits in each group can be the same, that is, K1~K2 can be evenly divided into P groups; or the number of the payload bits in each group can be different. In the P groups, the number of the CRC bits corresponding to at least two groups is different, or the number of the CRC bits corresponding to each group is different.

[0088] For example, K1~K2 is divided into two groups. When K0 belongs to the range of [K1, K3), the number of the CRC bits, that is, C1, can be a first value, and when K0 belongs to the range of (K3, K2], the number of the CRC bits, that is, C1, can be a second value. When K0 = K3, the number of the CRC bits, that is, C1, can be the first value or the second value. The first value and the second value are different. It can be understood that K3 is greater than or equal to K1 and less than or equal to K2, such as 13, 14, 19 or 20, which is not limited in the present application.

[0089] It should be noted that the first value can be any positive integer, such as 5, 6 or 11, and the second value can be any positive integer, such as 6, 7 or 11, which is not limited in the present application. Optionally, the second value can be greater than the first value.

[0090] In the following, Table 3 is used for illustration.

[0091] Table 3: An example of the encoding code type of the first sequence

[0092] It can be understood that K1 is 12 and K3 is 19 in Table 3. As shown in Table 3, when the number of the payload bits (K0) of the first sequence is in the range of [12, 19], the number of the CRC bits can be 6, and when the number of the payload bits (K0) of the first sequence is in the range of (19, K2], the number of the CRC bits can be 11.

[0093] Based on the above scheme, using different numbers of CRC bits in PC-CA polar encoding can improve the flexibility of encoding, so as to be applicable to various scenarios, and the number of CRC bits can be configured to adapt to different scenarios.

[0094] S302: The first communication device performs parity check polar encoding on the first sequence.

[0095] The first communication device can perform parity check polar encoding on the first sequence to obtain a coded sequence of code words.

[0096] In a possible implementation, the first sequence can be understood as a precoding sequence. The first communication device can determine the positions of the second check bits and the information bits in a mother sequence, map the second check bits to the positions of the second check bit sequence in the mother sequence, map the information bits to the positions of the information bits in the mother sequence, and add CRC bits, to determine the first sequence. The mother sequence can be a mother sequence corresponding to the first sequence. It can be understood that the mother sequence can also be referred to as a reliability sequence, and the mother sequence can include indexes corresponding to N sub-channels, which can be sorted in order of reliability from low to high. For example, N is an integer greater than 0.

[0097] In an example, the length of the mother sequence can be a mother length N. For example, the mother length N can be the length of a sequence of code words obtained after encoding a sequence of bits to be encoded. When determining the mother sequence, the first communication device can determine the mother sequence according to the length K of the first sequence, or can determine the mother sequence according to the length K of the first sequence and a transmission code length E. The transmission code length E can be the actual transmission code length of a sequence of code words transmitted between the first communication device and the second communication device, or in other words, the transmission code length E is the transmission code length after rate matching of the first sequence after parity check polar encoding. E is an integer greater than 0.

[0098] It should be noted that the specific manner in which the first communication device determines the mother sequence can be implemented by conventional means, and the present application does not make specific limitations.

[0099] The determination process of the positions of the second check bits and the information bits in the mother sequence, and the determination process of the second check bits are described below.

[0100] I. The first communication device determines the positions of the second check bits and the information bits in the mother sequence.

[0101] The process in which the first communication device determines the positions of the second check bits in the mother sequence can be as shown in FIG. 4, and can include the following operations.

[0102] S401: The first communication device determines the number of second check bits.

[0103] wherein, is the number of second check bits, is an integer greater than or equal to 0.

[0104] In a possible scenario, the first communication apparatus can determine the number of second check bits included in the first sequence according to the first correspondence relationship The first correspondence relationship includes a correspondence relationship between the number K0 of information bits and the number of second check bits. The first correspondence relationship includes a correspondence relationship between the number K0 of information bits and the number of second check bits.

[0105] Optionally, when determining the number of second check bits, the transmission code length E can also be considered, and the first correspondence relationship can include a correspondence relationship between the number K0 of information bits, the transmission code length E, and the number of second check bits. One number K0 of information bits and one transmission code length E can correspond to one number of second check bits. It should be noted that, when the transmission code length E is considered, the number of second check bits corresponding to one number K0 of information bits and one transmission code length E is not greater than the difference between the transmission code length E and the number K0 of information bits.

[0106] Optionally, the first correspondence relationship in the embodiments of the present application can be pre-generated or predefined.

[0107] For example, the first correspondence relationship in the embodiments of the present application can include at least one first correspondence relationship in Table 4.

[0108] For example, in Table 4, the value range of K0 is [12, 19], and the value range of E is [19, 64].

[0109] Table 4: An example of a first correspondence relationship

[0110] For example, as shown in Table 4, a plurality of correspondence relationships are shown, each of which is a correspondence relationship between one number K0 of information bits, one transmission code length E, and the number of PC bits. It can be understood that the PC bits here can be a part of PC bits, that is, the PC bits included in the sequence after rate matching of the first sequence after the polar encoding of the parity check.

[0111] In Table 4, according to the row where the number K0 of information bits is located and the column where the transmission code length E is located, the determined value is the number of PC bits. For example, when K0 = 14 and E = 64, the corresponding number of PC bits is 1. For example, when K0 = 16 and E = 52, the corresponding number of PC bits is 1.

[0112] For example, the first correspondence relationship in the embodiments of the present application can include at least one first correspondence relationship in Table 5.

[0113] In Table 5, the value range of K0 is [20, 52], and the value range of E is [19, 64].

[0114] Table 5: An example of a first correspondence relationship

[0115] For example, the correspondence relationship shown in Table 5, where each correspondence relationship is a number of information bits K0, a transmission code length E, and a number of PC bits. It can be understood that the PC bits here can be a part of the PC bits, that is, the PC bits contained in the sequence after rate matching of the first sequence after parity check polar encoding.

[0116] In Table 5, according to the row where the number of information bits K0 is located and the column where the transmission code length E is located, the determined value is the number of PC bits. For example, when K0 = 24 and E = 61, the corresponding number of PC bits is 1. For another example, when K0 = 34 and E = 52, the corresponding number of PC bits is 5.

[0117] S402: The first communication device determines positions for placing information bits and second check bits from the mother code sequence.

[0118] The first communication device obtains a reliability sequence of the mother code length and performs rate matching to remove the punctured or shortened positions to obtain a reliability sequence after rate matching The length of the reliability sequence after rate matching is N minus the number of punctured or shortened bits.

[0119] For example, the mother code length N is equal to 32, Assuming that rate matching needs to puncture 2 bits, the punctured reliability sequence is a reliability sequence of length 30

[0120] The first communication device selects the positions with the highest reliability in the sequence The first communication device selects the positions with the highest reliability in the sequence The first communication device selects the positions with the highest reliability in the sequence

[0121] For example, K0 = 11, The first communication device selects the positions with the highest reliability in the sequence The first communication device selects the positions with the highest reliability in the sequence The first communication device selects the positions with the highest reliability in the sequence

[0122] S403: The first communication device determines​ determining the positions of the information bits and the positions of the second check bits in the positions.

[0123] Optionally, the first communication device determines the positions of the second check bits in the positions according to the sets corresponding to the positions of the row weights, from the positions. It can be understood that the row weight can also be understood as the Hamming weight or the polarization weight.

[0124] Exemplarily, the first communication device calculates the minimum row weight of the sets , denoted as w min . The first communication device determines, in the sets , at most positions with the row weight equal to w min in the order of the reliabilities from high to low. If the positions with the row weight equal to w min in the sets are less than , the first communication device continues to determine the positions of the second check bits in the positions with the row weight equal to 2*w min , until positions are determined from the sets as the positions of the second check bits.

[0125] Exemplarily, assuming that the minimum row weight of the sets is 8, the positions with the row weight equal to 8 and the maximum reliabilities are {27, 26, 23, 29}, that is, the set of the positions of the second check bits is {23, 26, 27, 29}, and the length is 4.

[0126] The first communication device determines a frozen set F from . Wherein, the positions except constitute the frozen set F. As obtained after removing is the frozen set F = {3, 4, 5, 6, 7, 8, 9, 17, 10, 18, 11, 19, 13, 21, 25}, and the length is 15.

[0127] The first communication device can obtain a dynamic frozen (DF) set, wherein the DF is a set constituted by the set F and the positions of the second check bits. Exemplarily, DF = {3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 17, 18, 19, 21, 23, 25, 26, 27, 29}, and the length is 19.

[0128] The first communication device can obtain a message bit set I of the placement information bits, the message bit set being a set The set after removing the set DF has a size equal to K0. For example, I = [12, 20, 14, 15, 22, 16, 24, 28, 30, 31, 32].

[0129] It should be noted that in a possible implementation, the first communication device can further refine the set DF after determining the set DF. Optionally, the first communication device can determine the positions of the valid check bits in the positions of the second check bits, and form a refined check bit position set DF simplified from the positions of the valid check bits. The valid check bit can be a check bit whose preceding subchannel carries information bits. For example, when determining the positions of the valid check bits, the first communication device can determine the positions of the second check bits in the determined check bit positions, which have message bits in front, as the positions of the valid check bits.

[0130] For example, the set DF determined by the first communication device is {3, 4, 5, 6, 7, 8, 9, 17, 10, 18, 11, 19, 13, 21, 25, 27, 26, 23, 29}, and the message bit set I is {12, 20, 14, 15, 22, 16, 24, 28, 30, 31, 32}. The positions of the valid check bits correspond to the set DF simplified {13, 17, 18, 19, 21, 23, 25, 26, 27, 29}. The final check bit position set determined by the first communication device can be the set DF simplified .

[0131] Based on the above technical solutions, the first communication device can determine the positions of the information bits in the mother code sequence and the positions of the second check bits in the mother code sequence.

[0132] II. The first communication device can determine the second check bits based on the check relationship between the information bits and the second check bits.

[0133] In one example, the first communication device can determine the second check bits using a single-tap feedback shift register of the PC-polar code in the NR standard, or in other words, the check relationship between the information bits and the second check bits can be implemented by the single-tap feedback shift register. Referring to FIG. 5, the shift register is in the form of a feedback shift register. The tap mode is write-in, and the number of taps is single tap. The direction of the shift register is left shift. The feedback tap position, the input tap position, and the output tap position are all located at the end of the moving direction, that is, the leftmost side. Moreover, only one bit register input bit is used when the shift register is in the message bit. When the shift register is in the check bit, the shift register output bit is used. The moving timing logic of the shift register is read at time t and written at time t+1.

[0134] For example, if the shift register is in a position in the message set I, the output is the current input, and the current input is stored in the shift register after being XORed with the value of the shift register and then left-circularly shifted. If the shift register is in the frozen bit, 0 is directly output. If the shift register is in a position in the set DF, the value in the leftmost shift register is output.

[0135] Currently, the process and pseudo code of PC encoding based on the shift register in the NR standard are as follows:

[0136] Based on the shift register shown in FIG. 5, the first communication device can obtain a sequence composed of the second check bits, the information bits, and the frozen bits. The first communication device can add CRC bits, for example, add CRC bits at the end, to generate a precoding sequence, that is, a first sequence. In S302, the first communication device can perform polar encoding on the precoding sequence.

[0137] In another example, the first communication device can determine the second check bits using a multi-tap shift register with feedback, or in other words, the check relationship between the information bits and the second check bits can be implemented by the multi-tap shift register with feedback. Referring to FIG. 6, the number of registers is L, and the tap positions are determined according to the polynomial q(D) = q0D 0 + q1D + q2D 2 + … + q m D m , where the tap direction is write-in. Among them, the number of shift registers L is generally equal to the highest power of the polynomial q(D), for example, the polynomial q(D) = 1 + D 2 + D 3 , the polynomial coefficients are q0 = 1, q1 = 0, q2 = 1, and q3 = 1, the highest power m = 3, and the corresponding number of registers L is also equal to 3.

[0138] In terms of time, q0 corresponds to the tap at the current time, q1 corresponds to the tap at the time one time ago, i.e. the time after one register; q2 corresponds to the tap at the time two times ago, i.e. the time after two registers; similarly, q m corresponds to the tap at the time m times ago. The output of the shift register at the i-th time is denoted as u , which represents the XOR operation in the binary field, is a binary switch, and the polynomial q(D) = q0D 0 + q1D + q2D 2 + … + q m D m is the coefficient of the polynomial q(D), and q i = 0 when the i-th time is not a message bit, otherwise = 1. = 1 when the i-th time is a message bit.

[0139] Before precoding, the values of the L shift registers need to be initialized, e.g. the value of each shift register is initialized to 0.

[0140] The output of the shift register can be independent of the set to which the position of the shift register belongs, i.e. the output is from a fixed position in the shift register regardless of whether the position of the shift register belongs to the message bits or not, e.g. the output is from the tap at the end of the shift register (u i = z i ), or the output of the shift register can be related to the message position. For example, if the position of the shift register belongs to the message bits, the output is the input (u i = v i ), and if the position of the shift register belongs to the set DF, the value read from the tap at the end of the shift register is taken as the output (u i = z i ). The position of the shift register is the puncturing and shortening position, and 0 is directly outputted.

[0141] In the embodiments of the present application, the flow and pseudo code of PC encoding based on the shift register shown in FIG. 6 are as follows:

[0142] In the embodiments of the present application, the first communication device can determine the polynomial based on the second correspondence. For example, the second correspondence can include the correspondence between the information bits and the polynomial. The first communication device can determine the polynomial corresponding to K0 according to the number of information bits K0. Optionally, when determining the polynomial, the transmission code length E can also be considered. Then the second correspondence can include the correspondence between the information bits, the transmission code length E and the polynomial.

[0143] The polynomial involved in the embodiments of the present application can be understood as a PC equation. The second correspondence can determine an indication parameter of the PC equation. Alternatively, the second correspondence in the embodiments of the present application can be pre-generated or predefined.

[0144] For example, the second correspondence in the embodiments of the present application can be at least one of the correspondences shown in Table 6.

[0145] For example, in Table 6, the value range of K0 is [12, 19], and the value range of E is [19, 64].

[0146] Table 6: An example of a second correspondence

[0147] For example, the second correspondence in the embodiments of the present application can be at least one of the correspondences shown in Table 6. 3 For example, when K0=12 and E=64, the indication parameter of the corresponding PC equation is 9, and the corresponding binary sequence is [0 1 0 0 1]. Then the corresponding polynomial or PC equation is 1+D 3 +D 4 .

[0148] For example, the second correspondence in the embodiments of the present application can be at least one of the correspondences shown in Table 6.

[0149] For example, in Table 7, the value range of K0 is [20, 52], and the value range of E is [19, 64].

[0150] Table 7: An example of a second correspondence

[0151] For example, the second correspondence in the embodiments of the present application can be at least one of the correspondences shown in Table 6. 3 For example, when K0=20 and E=64, the indication parameter of the corresponding PC equation is 19, and the corresponding binary sequence is [1 0 0 1 1]. Then the corresponding polynomial or PC equation is 1+D1 +D 4 For example, when K0= 38 and E = 62, the indication parameter of the corresponding PC equation is 11, and the corresponding binary sequence is [0 1 0 1 1]. Then the corresponding polynomial or PC equation is 1 + D 1 +D 3 .

[0152] Based on the above scheme, the first communication device can determine the second check bit, the information bit and the frozen bit, the first communication device can add the CRC bit, such as adding the CRC bit at the end, to generate the precoding sequence, that is, the first sequence. The first communication device can perform polar encoding on the first sequence.

[0153] As can be seen from Table 5 and Table 6, the polynomial length involved in the embodiments of the present application is less than or equal to 4, that is, the number of shift registers is less than or equal to 4.

[0154] After the first communication device performs polar encoding on the first sequence, the codeword sequence can be obtained. The first communication device can perform rate matching on the codeword sequence according to the transmission code length E to obtain the second sequence. The length of the second sequence can be the transmission code length E. The transmission code length E can be the actual transmission code length of the codeword sequence transmitted between the first communication device and the second communication device, or the transmission code length E is the transmission code length after rate matching of the first sequence after the parity check polar encoding, and E is an integer greater than 0.

[0155] Optionally, the first communication device can send the second sequence to the second communication device.

[0156] The embodiments of the present application also provide a decoding method. Referring to FIG. 7, an exemplary flowchart of a decoding method provided by the embodiments of the present application. The method can be applied to the second communication device. The second communication device can be the receiving end in the encoding and decoding process shown in FIG. 2. For example, when the first communication device is a terminal device or a module (such as a chip) in a terminal device, the second communication device can be a terminal device or a module (such as a chip) in a terminal device, or the second communication device can also be a network device or a module (such as a chip) in a network device; when the first communication device is a network device or a module (such as a chip) in a network device, the second communication device can be a module (such as a chip) in a terminal device. The method comprises:

[0157] S701: The second communication device receives the second sequence.

[0158] For example, the second communication device can receive the second sequence from the first communication device. Wherein, the second sequence can refer to the description of the second sequence generated by the aforementioned first communication device, which will not be repeated here. Exemplarily, the second sequence is the to-be-decoded sequence obtained in the second communication device after the first sequence transmitted by the first communication device is subjected to the operations of polar encoding with parity check, rate matching, modulation, frequency conversion, etc. and then transmitted through the wireless transmission environment. Wherein, the first sequence can refer to the description of the first sequence obtained by the aforementioned first communication device, which will not be repeated here.

[0159] S702: The second communication device decodes the second sequence based on the check relationship between the first check bit, the second check bit and the information bit, to obtain the information bit.

[0160] For example, the second communication device can determine the positions of the message bits, the second check bits and the first check bits. It should be noted that the second communication device can determine the positions of the message bits, the second check bits and the first check bits in the same way as the first communication device, which will not be repeated here.

[0161] The second communication device can determine the check relationship between the second check bit and the information bit. For example, the second communication device can determine the PC equation (polynomial). Exemplarily, the second communication device can determine the PC equation according to the second correspondence relationship.

[0162] In one possible case, the second communication device can decode the second sequence by using the SCL (successive cancellation list) decoding. The specific decoding process can include:

[0163] Step 1, performing de-rate matching on the second sequence to obtain a to-be-decoded sequence with a mother code length.

[0164] Step 2, determining the bit type at the current decoding position: if it is a frozen bit, the decoding output is fixed as 0, and no path splitting is performed; if the current decoding result is not 0, a penalty value greater than 0 is added to the metric value of the current path. If it is an information bit, it is split into 0 or 1 or 2 possible values, and is respectively stored as the current decoding path (i.e. path splitting), and the decoding metric value (e.g. the smaller the better) corresponding to each path is calculated. If the current position belongs to a check bit, the check bit at the current position is calculated according to the determined PC equation and the previous decoding result, and if the calculated result is consistent with the result of the current decoding of the decoder, the decoding metric of the current path is not added, otherwise a penalty value greater than 0 is added to the decoding metric of the current decoding path.

[0165] Step 3, repeat step 2 until the decoder decodes the bits in N (N is the length of the mother code) positions, from a maximum of List (such as List = 8) decoding paths, pick out the path with the smallest decoding metric value as the final decoding output sequence.

[0166] Step 4, according to the message bit position, take out K message bits from the decoding sequence in step 3, and the decoding is completed.

[0167] It can be understood that the above-mentioned SCL decoding mode is only an example of decoding the second sequence, and the second communication device can also use other decoding modes to decode the second sequence, which is not limited in the present application.

[0168] Referring to FIG. 8A, the number of Kr = K0 + CRC bits == 17 + 6 = 23, and the performance gain of the encoding method provided by the embodiment of the present application relative to the PC-CA polar encoding in the NR standard is shown. In FIG. 8A, the horizontal axis is the different transmission code length E, and the value range is [Kr+1, 63], and the vertical axis is the required signal to noise ratio (SNR) when the block error rate (BLER) is 0.01, and the unit is dB.

[0169] As can be seen from FIG. 8A, the encoding method provided by the embodiment of the present application has better error correction performance than the PC-CA polar encoding in the NR standard without losing the false alarm rate (FAR).

[0170] Referring to FIG. 8B, the number of Kr = K0 + CRC bits == 42 + 11 = 53, and the performance gain of the encoding method provided by the embodiment of the present application relative to the PC-CA polar encoding in the NR standard is shown. In FIG. 8B, the horizontal axis is the different transmission code length E, and the value range is [Kr+1, 63], and the vertical axis is the required SNR when the BLER is 0.01, and the unit is dB.

[0171] As can be seen from FIG. 8B, the encoding method provided by the embodiment of the present application has better error correction performance than the PC-CA polar encoding in the NR standard without losing the FAR.

[0172] Based on the above-mentioned embodiment, referring to FIG. 9, the embodiment of the present application provides a communication device 900, which comprises a processing unit 901 and a transceiver unit 902. The device 900 can be a communication device, or a device applied to a communication device, which can support the communication device to perform the notification method of the quality of service parameter.

[0173] The transceiving unit can also be referred to as a transceiving module, a transceiver, a transceiving device, etc. The processing unit can also be referred to as a processor, a processing board, a processing unit, a processing device, etc. Optionally, a device in the transceiving unit for implementing a receiving function can be regarded as a receiving unit, and it should be understood that the transceiving unit is configured to perform the transmitting operation and the receiving operation of the communication device in the above method embodiments, and a device in the transceiving unit for implementing a transmitting function can be regarded as a transmitting unit, i.e., the transceiving unit includes the receiving unit and the transmitting unit.

[0174] In addition, it should be noted that if the device is implemented by a chip / chip circuit, the transceiving unit can be an input / output circuit and / or a communication interface, and is configured to perform an input operation (corresponding to the above receiving operation) and an output operation (corresponding to the above transmitting operation); and the processing unit is an integrated processor or a microprocessor or an integrated circuit.

[0175] The following describes in detail the embodiments in which the device 900 is applied to the transmitting end and the receiving end.

[0176] For example, when the device 900 is applied to the transmitting end, the operations performed by each unit of the device 900 are described in detail.

[0177] In an optional embodiment, the communication device 900 can be applied to the transmitting end and perform the method performed by the transmitting end, for example, the method performed by the transmitting end in the embodiment shown in FIG. 3.

[0178] For example, the processing unit 901 is configured to obtain a first sequence, the first sequence being a bit sequence to be encoded, and the first sequence including K0 information bits, C1 first check bits, and C2 second check bits. K0 belongs to a first length range, the first length range being [K1, K2], K2 is an integer greater than 19, K1 is an integer less than 12, C1+C2 is greater than 0, C1 is greater than or equal to 0, and C2 is greater than or equal to 0. The processing unit 901 is further configured to perform parity check polarization encoding on the first sequence. The transceiving unit 902 is configured to transmit the sequence after the parity check polarization encoding.

[0179] For example, when the device 900 is applied to the receiving end, the operations performed by each unit of the device 900 are described in detail.

[0180] In an optional embodiment, the communication device 900 can be applied to the receiving end and perform the method performed by the receiving end, for example, the method performed by the receiving end in the embodiment shown in FIG. 7.

[0181] For example, the transceiver 902 is configured to receive a second sequence, the second sequence being obtained by performing the polar encoding on the first sequence. The first sequence is a bit sequence to be encoded, and the first sequence includes K0 information bits, C1 first check bits, and C2 second check bits. K0 belongs to a first length range, the first length range is [K1, K2], K2 is an integer greater than 19, K1 is an integer less than 12, C1+C2 is greater than 0, C1 is greater than or equal to 0, and C2 is greater than or equal to 0. The processing unit 901 is configured to decode the second sequence based on a check relationship among the first check bits, the second check bits, and the information bits, to obtain the information bits.

[0182] Based on the above-mentioned embodiment, the communication apparatus 1000 is provided, as shown in FIG. 10. The communication apparatus 1000 includes a processor 1010. Optionally, the communication apparatus 1000 further includes a memory 1020, which is configured to store instructions executed by the processor 1010 or store input data required by the processor 1010 to execute instructions or store data generated after the processor 1010 executes instructions. The processor 1010 can realize the method in the above-mentioned method embodiment by the instructions stored in the memory 1020.

[0183] Based on the above-mentioned embodiment, the communication apparatus 1100 is provided, as shown in FIG. 11. The communication apparatus 1100 can be a chip or a chip system. Optionally, the chip system in the embodiment of the application can be composed of a chip, or can include a chip and other discrete devices.

[0184] The communication apparatus 1100 can include at least one processor 1110 coupled to a memory. Optionally, the memory can be located in the apparatus or outside the apparatus. For example, the communication apparatus 1100 further includes at least one memory 1120. The memory 1120 stores necessary computer programs, configuration information, computer programs or instructions and / or data in any of the above-mentioned embodiments; the processor 1110 can execute the computer programs stored in the memory 1120 to complete the method in any of the above-mentioned embodiments. Optionally, the memory can be integrated with the processor.

[0185] The coupling in the embodiment of the application is indirect coupling or communication connection between the apparatuses, units or modules, which can be electrical, mechanical or other forms, and is used for information interaction between the apparatuses, units or modules. The processor 1110 can operate in cooperation with the memory 1120. The specific connection medium between the transceiver 1130, the processor 1110 and the memory 1120 is not limited in the embodiment of the application.

[0186] The communication apparatus 1100 can further include a transceiver 1130, and the communication apparatus 1100 can interact with other devices through the transceiver 1130. The transceiver 1130 can be a circuit, a bus, a transceiver, or any other device that can be used for information interaction, or a signal transceiving unit. As shown in FIG. 11, the transceiver 1130 includes a transmitter 1131, a receiver 1132, and an antenna 1133. In addition, when the communication apparatus 1100 is a chip-type device or a circuit, the transceiver in the communication apparatus 1100 can also be an input / output circuit and / or a communication interface, which can input data (or receive data) and output data (or send data), and the processor is an integrated processor or a microprocessor or an integrated circuit, and the processor can determine the output data according to the input data.

[0187] In a possible implementation, the communication apparatus 1100 can be applied to a communication apparatus, and specifically, the communication apparatus 1100 can be a communication apparatus or a device capable of supporting a communication apparatus, and can implement the functions of the sending end or the receiving end in any of the above-mentioned embodiments. The memory 1120 stores necessary computer programs, computer programs or instructions and / or data for implementing the functions of the sending end or the receiving end in any of the above-mentioned embodiments. The processor 1110 can execute the computer programs stored in the memory 1120 to complete the method executed by the sending end or the receiving end in any of the above-mentioned embodiments.

[0188] In the embodiments of the present application, the processor can be a general processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, and can implement or execute the methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general processor can be a microprocessor or any conventional processor. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as a hardware processor for execution, or executed by a combination of hardware and software modules in the processor.

[0189] In the embodiments of the present application, the memory can be a non-volatile memory such as a hard disk drive (HDD) or a solid-state drive (SSD), and can also be a volatile memory such as a random-access memory (RAM). The memory can also be any other medium capable of carrying or storing desired program codes in the form of instructions or data structures and capable of being accessed by a computer, but is not limited to this. The memory in the embodiments of the present application can also be a circuit or any other device capable of implementing a storage function, used for storing computer programs, computer programs or instructions and / or data.

[0190] Based on the above embodiments, referring to FIG. 12, the embodiments of the present application further provide another communication apparatus 1200, comprising: an input / output interface 1210 and a logic circuit 1220; the input / output interface 1210 is configured to receive code instructions and transmit the code instructions to the logic circuit 1220; the logic circuit 1220 is configured to run the code instructions to perform the method executed by the sending end or the receiving end in any of the above embodiments.

[0191] In the following, the operations of the apparatus 1200 applied to the sending end or the receiving end are described in detail.

[0192] In an optional implementation, the communication apparatus 1200 can be applied to the sending end to perform the method executed by the sending end, for example, the method executed by the sending end in the embodiment shown in FIG. 3.

[0193] For example, the logic circuit 1220 is configured to obtain a first sequence, the first sequence being a bit sequence to be encoded, the first sequence comprising K0 information bits, C1 first check bits and C2 second check bits. Wherein, K0 belongs to a first length range, the first length range being [K1, K2], K2 being an integer greater than 19, K1 being an integer less than 12, C1+C2 being greater than 0, C1 being greater than or equal to 0, and C2 being greater than or equal to 0. The logic circuit 1220 is further configured to perform parity check polar encoding on the first sequence. The input / output interface 1210 is configured to output the sequence after parity check polar encoding.

[0194] Since the communication apparatus 1200 provided by the present embodiment can be applied to the sending end to perform the method executed by the sending end, the technical effects that can be obtained thereby can refer to the above method embodiments, which will not be described herein again.

[0195] In an optional implementation, the communication apparatus 1200 can be applied to the receiving end to perform the method executed by the receiving end, for example, the method executed by the receiving end in the embodiment shown in FIG. 7.

[0196] For example, the input / output interface 1210 is configured to input a second sequence, the second sequence being obtained after parity check polar encoding on a first sequence. Wherein, the first sequence is a bit sequence to be encoded, the first sequence comprising K0 information bits, C1 first check bits and C2 second check bits. Wherein, K0 belongs to a first length range, the first length range being [K1, K2], K2 being an integer greater than 19, K1 being an integer less than 12, C1+C2 being greater than 0, C1 being greater than or equal to 0, and C2 being greater than or equal to 0. The logic circuit 1220 is configured to decode the second sequence based on the check relationship among the first check bits, the second check bits and the information bits to obtain the information bits.

[0197] Since the communication apparatus 1200 provided by the embodiment can be applied to the receiving end, the method performed by the receiving end is executed. Therefore, the technical effects that can be achieved by the communication apparatus 1200 can refer to the method embodiments described above, which will not be repeated here.

[0198] Based on the above embodiments, the embodiments of the present application further provide a communication system, which includes at least one receiving end and at least one sending end. The technical effects that can be achieved can refer to the method embodiments described above, which will not be repeated here.

[0199] Based on the above embodiments, the embodiments of the present application further provide a computer readable storage medium, which stores computer programs or instructions. When the instructions are executed, the method performed by the communication apparatus in any of the above embodiments is implemented. The computer readable storage medium can include a U disk, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk or an optical disk, and various media that can store program codes.

[0200] In order to realize the functions of the communication apparatuses in FIGS. 9-12, the embodiments of the present application further provide a chip including a processor for supporting the communication apparatus to realize the functions related to the sending end or the receiving end in the above method embodiments. In a possible design, the chip is connected with a memory or the chip includes a memory, and the memory is used to save the computer programs or instructions and data necessary for the sending end or the receiving end.

[0201] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can be in the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can be in the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0202] The present application is described with reference to flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of the flows and / or blocks in the flowcharts and / or block diagrams can be implemented by computer programs or instructions. These computer programs or instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices produce the device for implementing the functions specified in one or more flows in the flowcharts and / or one or more blocks in the block diagrams.

[0203] These computer programs or instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0204] These computer programs or instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0205] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application also intends to include these modifications and variations.

Claims

1. An encoding method characterized by comprising: The method comprises the following steps: obtaining a first sequence, the first sequence being a bit sequence to be encoded, the first sequence comprising K0 information bits, C1 first check bits and C2 second check bits; wherein C1+C2 is greater than 0, C1 is greater than or equal to 0, and C2 is greater than or equal to 0; K0 belongs to a first length range, the first length range being [K1, K2], K2 being an integer greater than 19, and / or K1 being an integer less than 12; performing parity check polar encoding on the first sequence.

2. A decoding method, comprising: The method comprises the following steps: receiving a second sequence, the second sequence being obtained after performing parity check polar encoding on a first sequence; wherein the first sequence is a bit sequence to be encoded, the first sequence comprising K0 information bits, C1 first check bits and C2 second check bits; wherein C1+C2 is greater than 0, C1 is greater than or equal to 0, and C2 is greater than or equal to 0; K0 belongs to a first length range, the first length range being [K1, K2], K2 being an integer greater than 19, and / or K1 being an integer less than 12; decoding the second sequence based on a check relationship between the first check bits, the second check bits and the information bits, to obtain the information bits.

3. The method according to claim 1 or 2, characterized in that, When K0 belongs to a second length range, C1 is a first length, the second length range being [K1, K3), K3 being less than or equal to K2. When K0 belongs to a third length range, C1 is a second length, the third length range being (K3, K2]. When K0=K3, C1 is the first length or the second length.

4. The method according to any one of claims 1 to 3, characterized in that, The second check bits are obtained based on a check relationship between the information bits and the second check bits.

5. The method of claim 4, wherein, The check relationship between the information bits and the second check bits is obtained through a multi-tap shift register with feedback.

6. The method of claim 5, wherein, When a position of the multi-tap shift register is a message bit for placing an information bit, an output of the multi-tap shift register is an input of the multi-tap shift register. Or, When a position of the multi-tap shift register is a dynamic frozen bit, an output of the multi-tap shift register is a value of a tap at an end of a moving direction of the multi-tap shift register. When a position of the multi-tap shift register is a frozen bit, the output of the multi-tap shift register is 0.

7. The method of any one of claims 4-6, wherein, The check relationship between the information bits and the second check bits is determined according to K0 and a target transmission code length E, the E being a transmission code length after rate matching on the first sequence after the parity check polar encoding.

8. The method according to any one of claims 3 to 7, characterized in that, K1=12 and K3=19.

9. The method of claim 8, wherein, The check relationship of the information bits and the second check bits satisfies any one of the following polynomials: The E is a transmission code length after rate matching on the first sequence after the parity check polar encoding.

10. The method according to any one of claims 3 to 7, characterized in that, K3=19 and K2=52.

11. The method of claim 10, wherein, The check relationship of the information bits and the second check bits satisfies any one of the following polynomials: The E is a transmission code length after rate matching on the first sequence after the parity check polar encoding.

12. The method according to any one of claims 1 to 11, characterized in that, A polynomial length (shift register quantity) satisfying the check relationship between the information bits and the second check bits is less than or equal to 4.

13. The method according to any one of claims 3 to 12, characterized in that, The K1=12, the K3=19, the number of third check bits satisfies one of the following corresponding relationships, the third check bits are part of the second check bits, and the third check bits are determined according to row redundancy: The E is a transmission code length after rate matching of the first sequence after the parity check polar encoding.

14. The method according to any one of claims 3 to 12, characterized in that, The K3=19, the K2=52, the number of third check bits satisfies one of the following corresponding relationships, the third check bits are part of the second check bits, and the third check bits are determined according to row redundancy: The third length range is K3-K2, and K3 is less than or equal to K2.

15. The method according to any one of claims 1 to 14, characterized in that, The position set in which the second check bits are placed in the mother code sequence corresponding to the first sequence is determined according to the K0 and a target transmission code length E, and the E is a transmission code length after rate matching of the first sequence after the parity check polar encoding.

16. A communications device, characterized by The communication device comprises a unit for executing the method of any one of claims 1, 3-15, or a unit for executing the method of any one of claims 2-15.

17. A communications device, characterized by The communication device comprises: A processor coupled with a memory, the memory being configured to store programs or instructions, when the programs or instructions are executed by the processor, the device executes the method of any one of claims 1, 3-15, or the device executes the method of any one of claims 2-15.

18. The apparatus of claim 17, wherein, The communication device further comprises the memory.

19. A chip system, characterized by The chip system comprises: A communication interface; A processor configured to call and run the instructions through the communication interface, so that the device installed with the chip system executes the method of any one of claims 1, 3-15, or the device installed with the chip system executes the method of any one of claims 2-15.

20. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer executable instructions, when the computer executable instructions are called by an electronic device, the electronic device executes the method of any one of claims 1, 3-15, or the electronic device executes the method of any one of claims 2-15.

21. A computer program product, characterised in that, The computer executable instructions, when running on a computer, make the computer execute the method of any one of claims 1, 3-15, or the electronic device executes the method of any one of claims 2-15.

22. A communication system, characterized by The communication device comprises a unit for executing the method of any one of claims 1, 3-15, and a unit for executing the method of any one of claims 2-15.

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