Josephson junction and superconducting field-effect transistor

Abstract

Josephson junction (2) comprising: - a GaAs substrate (8); - an InAlAs intermediate layer (6) placed on said GaAs substrate (8); - an InAs epitaxial layer (4) placed on said InAlAs intermediate layer (6) - a drain (10) and a source (12) placed on the InAs epitaxial layer (4) and comprising a superconductive material.

Description

[0001] DESCRIPTION “Josephson junction and superconducting field-effect transistor”

[0002] The present invention relates to a Josephson junction, in particular to a Josephson junction based on an indium arsenide epitaxial layer, and to a related superconducting field-effect transistor.

[0003] The semiconductor industry faces nowadays some technical issues such as for example the relative slowness of communication systems (satellite, terrestrial, etc.) and the increasingly pressing need for computing power in supercomputers (classical and quantum).

[0004] Hybrid devices based on semiconductor structures and superconducting metals are a known technology applied in classical computing.

[0005] Alongside this known field, a great deal of research work has been done in recent years because this kind of mixed structures are also interesting for the realization of quantum computers.

[0006] However, none of the prior art devices allows obtaining high switch speed and / or clock frequencies suitable for increasing the speed of communication systems, in particular for satellite applications, and / or for improving the performances of current superconducting quantum processors.

[0007] There is therefore the need to provide an innovative device that outperform with respect to the current ones in terms of switch speed, footprint, dissipated energy, etc., and that reach clock frequencies higher than the ones of current’s products to improve the performance of current superconducting quantum processors, thus overcoming the problems of the prior art.

[0008] These and other objects are fully achieved by virtue of a Josephson junction having the characteristics defined in independent claim 1 and of a superconducting field-effect transistor having the characteristics defined in independent claim 8. Preferred embodiments of the invention are specified in the dependent claims, whose subject-matter is to be understood as forming integral or integrating part of the present description.

[0009] Further characteristic and advantages of the present invention will become apparent from the following description, provided merely by way of non-limiting example, with reference to the attached drawings, in which:

[0010] - Figure 1 shows a sectional view of a Josephson junction according to the present invention;

[0011] - Figure 2 shows a sectional view of two Josephson junctions realized on a homogeneously doped InAs epitaxial layer;

[0012] - Figure 3 shows a sectional view of two Josephson junctions realized on a respective InAs epitaxial layer doped locally differently post- heterostructure growth;

[0013] - Figure 4 shows a superconducting field-effect transistor according to the present invention;

[0014] - Figure 5a shows the dependence of the critical current on the gatesource voltage in the superconducting field-effect transistor; and

[0015] - Figure 5b shows the dependence of the normal-state resistance on gate-source voltage in the superconducting field-effect transistor.

[0016] Briefly, the Josephson junction (JJ) according to an embodiment of the present invention comprises an indium arsenide (InAs) epitaxial layer, whose electrical properties are regulated by a doping induced during the growth phase, grown on an intermediate dielectric layer at cryogenic temperature of aluminum indium arsenide (InAIAs), which is in turn grown on a gallium arsenide (GaAs) substrate.

[0017] The Josephson junction can be used at cryogenic temperatures and in superconducting devices, in particular to get a superconducting fieldeffect transistor (JoFET) by providing an electrostatic gate to such Josephson junction.

[0018] Figure 1 shows a sectional view of a Josephson junction 2 according to the present invention. An InAs epitaxial layer 4 is synthesized, for example by Molecular Beam Epitaxy (MBE), on a InAIAs intermediate layer 6 grown on a GaAs substrate 8.

[0019] Advantageously, the InAs epitaxial layer 4 has a thickness comprised in the range 5nm to 500nm, the InAIAs intermediate layer 6 has a thickness comprised in the range 1 pm to 2pm and the GaAs substrate 8 has a thickness of about 500 pm oriented along the (001 ) crystallographic direction.

[0020] The GaAs substrate 8 is suitable for the growth of layers of alloys of lll-V compounds based on As, Al and Ga, due to the similarity of the crystal lattice of the various compounds.

[0021] The InAIAs intermediate layer 6 acts as a lattice adaptation layer between the GaAs substrate 8 (which represents the handling substrate of the Josephson junction) and the InAs epitaxial layer 4 (which represents the semiconductive layer to be used as the core of the Josephson junction).

[0022] For temperatures below 70 K, the InAIAs material is an insulator, this ensuring electrical decoupling between devices realized by patterning the overlying InAs epitaxial layer 4.

[0023] The structure of the Josephson junction of the present invention shows similarities with the classic silicon-on-insulator (SOI) structure established for current Si-based technology and can be referred as InAs - on-insulator (InAs Ol).

[0024] The electrical properties of the InAs epitaxial layer 4 can be adjusted by doping the material during the growth phase (e.g. by varying the concentration of Si atoms incorporated in the InAs epitaxial layer 4 from 1017to 1019atoms / cm3) or by doping the material after grown by using ion implantation or thermal diffusion followed by a drive-in step.

[0025] In the InAIAs intermediate layer 6, which can be referenced as Ini xAlxAs, the concentration x of the aluminum atoms (and also correspondingly the concentration of the indium atoms) can progressively vary, from bottom to top of the Josephson junction 2, for sub-layers having a thickness of tens of nanometers, thus reaching an atomic control of the stoichiometry and of the crystal composition.

[0026] Advantageously, the InAIAs intermediate layer 6 comprises three portions: a first portion 6a, placed directly above the GaAs substrate 8, comprising two GaAs sub-layers and a GaAs / AIGaAs superlattice sublayer placed in-between, a second portion 6b, placed on the first portion 6a, comprising an Im-xAIxAs metamorphic buffer layer wherein x is preferably comprised in the interval 0.15 - 0.81 , and third portion 6c, placed on the second portion 6b, comprising an lno.84Alo.i6As overshoot layer.

[0027] Advantageously, the thickness of the two GaAs sub-layers is 200nm, the thickness of the GaAs / AIGaAs superlattice sublayer is 100nm, the thickness of the I -xAIxAs metamorphic buffer layer is 1250nm and the thickness of the lno.84Alo.i6As overshoot layer is 400nm.

[0028] A film of superconductive material is then deposited and patterned on the surface of the InAs epitaxial layer 4, in a manner per se known, to get a drain 10 and a source 12 of the Josephson junction 2.

[0029] Figure 1 shows a sectional view of a single Josephson junction 2 made on a homogeneously doped InAs epitaxial layer 4, where LJJ represents the length of the Josephson junction 2.

[0030] Figure 2 shows in-section view of two Josephson junctions 2a, 2b having respective length LJJI and Ljj2 and respective drain 10a, 10b and source 12a, 12b, both Josephson junctions 2a, 2b being realized on a homogeneously doped InAs epitaxial layer 4.

[0031] The Josephson junctions 2a, 2b are electrically decoupled by the removal of a portion of length d of the InAs epitaxial layer 4.

[0032] Figure 3 shows a sectional view of two Josephson junctions 2c, 2d, having respective length LJJ3 and Ljj4 and respective drain 10c, 10d and source 12c, 12d, the Josephson junctions 2c, 2d being realized on a respective InAs epitaxial layer 4c, 4d doped locally differently post- heterostructure growth. The Josephson junctions 2c, 2d are electrically decoupled by the removal of a portion of length d of the InAs epitaxial layer 4.

[0033] Further to the realization of the Josephson junction 2, a superconducting field-effect transistor (JoFET) can be obtained as here below explained.

[0034] Figure 4 shows the Josephson junction 2 as above disclosed equipped with an electrostatic gate to obtain a superconducting field-effect transistor (JoFET) 20 according to the present invention.

[0035] The superconducting field-effect transistor 20 is realized by depositing on the InAs epitaxial layer 4, between the drain 10 and the source 12, a dielectric layer 14 and then, on the dielectric layer 14, a metal contact 16 acting as electrostatic gate.

[0036] The architecture above-disclosed defines a metal-insulator- semiconductor (MOS) structure and allows modulation of the charge density of the gated InAs epitaxial layer 4.

[0037] Figure 5a shows the dependence of the critical current on the voltage VGS (gate-source voltage) in the superconducting field-effect transistor 20.

[0038] Figure 5b shows the dependence of the normal-state resistance on the voltage VGS in the superconducting field-effect transistor 20.

[0039] The superconducting field-effect transistor 20 is capable of suppressing or increasing the critical current value by applying negative or positive voltage VGS, respectively. As a consequence of the charge density change in the InAs epitaxial layer 4 induced by the application of the voltage VGS, an appropriate increase or decrease of the normal-state resistance is detected for negative or positive VGS, respectively.

[0040] The Josephson junction 2 of the present invention has the following advantages:

[0041] - the critical current density can be adjusted by ~2 orders of magnitude, by changing the dimensions (width and length) of the Josephson junction 2, or by varying the doping concentration (from 1017to 1019atoms / cm3) of the InAs epitaxial layer 4; - the normal state resistance of the Josephson junction 2 can also be adjusted, by changing the size of the Josephson junction 2, and by varying the doping concentration of the InAs epitaxial layer 4;

[0042] - the specific properties of the Josephson junction 2 can be heterogeneously adjusted on the substrate by post-processing doping of the InAs epitaxial layer 4;

[0043] - the decoupling between different Josephson junctions 2 fabricated on a same substrate is excellent as they are fabricated on a cryogenic insulator.

[0044] Other key aspects of the present technology are:

[0045] - the presence of a proximity effect between a superconductor and a semiconductor: the use of an InAs heterostructure for the realization of Josephson junctions with high critical currents and the possibility of selective doping;

[0046] - the presence of a electrostatic field effect between a metal and a semiconductor through an insulator: the Josephson junction 2 allows, through the application of the dielectric layer 14 and metal contact 16, the realization of a voltage controllable platform capable of supporting large non-dissipative currents, which are an order of magnitude higher than the semiconductor structures known in the art;

[0047] - the use of MBE allows very precise control of the growth of the InAs epitaxial layer 4 on the GaAs substrate 8; this method is known for its ability to produce high quality crystalline layers with extreme precision in atomic proportions;

[0048] - the presence of the InAIAs intermediate layer 6 between the InAs epitaxial layer 4 and the GaAs substrate 8 helps overcoming the discrepancy in the crystal lattices between these two materials: this layer acts as a “bridge” between the different lattices, reducing stresses and defects that would otherwise compromise the electronic properties of the semiconductor, thus greatly improving the material properties and increasing the supercurrent that can be carried by the Josephson junction 2; In summary, the innovation of the Josephson junction 2 lies in its ability to integrate unique physical properties and advanced fabrication techniques to explore new quantum phenomena and develop potential applications in advanced technologies, such as quantum computation. The technology of the present invention makes it possible to build devices that outperform with respect to the current ones in terms of switching speed, footprint, dissipated energy, etc.

[0049] Furthermore, thanks to the structure of the present Josephson junction it is possible to reach clock frequencies at least 100 times higher than current’s products and to improve the performance of current superconducting quantum processors.

[0050] Clearly, the principle of the invention remaining the same, the embodiments and the details of production can be varied considerably from what has been described and illustrated purely by way of non-limiting example, without departing from the scope of protection of the present as defined in the attached claims.

Claims

CLAIMS1 . Josephson junction (2) comprising:- a GaAs substrate (8);- an InAIAs intermediate layer (6) placed on said GaAs substrate (8);- an InAs epitaxial layer (4) placed on said InAIAs intermediate layer (6)- a drain (10) and a source (12) placed on the InAs epitaxial layer (4) and comprising a superconductive material.

2. Josephson junction (2) according to claim 1 , wherein the InAs epitaxial layer (4) has a thickness comprised in the range 5nm to 500nm, the InAIAs intermediate layer (6) has a thickness comprised in the range 1 pm to 2pm and the GaAs substrate (8) has a thickness of 500nm.

3. Josephson junction (2) according to claims 1 or 2, wherein the InAs epitaxial layer (4) has a concentration of Si atoms comprised in the range from 1017to 1019atoms / cm3.

4. Josephson junction (2) according to any of the above claims, wherein the InAs epitaxial layer (4) is doped.

5. Josephson junction (2) according to any of the above claims, wherein in the InAIAs intermediate layer (6) the concentration of aluminum and indium atoms progressively vary, from bottom to top of the Josephson junction (2), for sub-layers having a thickness of tens of nanometers.

6. Josephson junction (2) according to any of the above claims, wherein the InAIAs intermediate layer (6) comprises:- a first portion (6a), placed directly above the GaAs substrate (8), comprising two GaAs sub-layers and a GaAs / AIGaAs superlattice sublayer placed in-between;- a second portion (6b), placed on the first portion (6a), comprising an Im-xAlxAs metamorphic buffer layer wherein x is comprised in the interval 0.15- 0.81 ; and- a third portion (6c), placed on the second portion (6b), comprising an lno.84Alo.i6As overshoot layer.

7. Josephson junction (2) according to any of the above claims, wherein the thickness of the two GaAs sub-layers is 200nm, the thickness of the GaAs / AIGaAs superlattice sublayer is 10Onm, the thickness of the Ini xAIxAs metamorphic buffer layer is 1250nm and the thickness of the lno.84Alo.i6As overshoot layer is 400nm.

8. A superconducting field-effect transistor (20) comprising:- a Josephson junction (2) according to any of the preceding claims;- a dielectric layer (14) placed between the drain (10) and the source (12); and- a metal contact (16), placed on the dielectric layer (14), acting as electrostatic gate.

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