Display device and electronic device comprising same

Abstract

This display device comprises: a substrate including a first area in which first sub-pixels are arranged and a second area in which units including sub-pixel groups and transmissive areas are arranged, the sub-pixel groups including second sub-pixels; first lines which extend in a first direction, are electrically connected to the first sub-pixels, and each include a first sub-line and a second sub-line that are spaced apart from each other with the second area therebetween; first connection lines arranged in the first area and respectively connecting the first sub-lines and the second sub-lines of the first lines; and second lines extending in the first direction and electrically connected to the second sub-pixels.

Description

Display device and electronic device including same

[0001] Embodiments of the present invention relate to a display device.

[0002] Typically, a display device includes electronic components for controlling display elements and electrical signals applied to the display elements. The electronic components include thin film transistors (TFTs), capacitors, and wiring.

[0003] Recently, display devices have become increasingly versatile. Furthermore, their use is expanding as they become thinner and lighter. As the number of users increases, research is actively underway to enhance their visual experience, one of which is expanding the display area of ​​display devices. Various studies are being conducted to expand the display area of ​​display devices.

[0004] Embodiments of the present invention aim to provide a display device with improved light transmittance in a component area. However, these tasks are exemplary and do not limit the scope of the present invention.

[0005] According to one aspect of the present invention, a display device includes a substrate including a first region in which first sub-pixels are arranged, and a second region in which unit units including sub-pixel groups and transparent regions including second sub-pixels are arranged; first wirings each including a first sub-wiring and a second sub-wiring extending in a first direction and electrically connected to the first sub-pixels and spaced apart from each other with the second region therebetween; first connecting wirings arranged in the first region and connecting the first sub-wiring and the second sub-wiring of each of the first wirings, respectively; and second wirings extending in the first direction and electrically connected to the second sub-pixels.

[0006] In one embodiment, the sub-pixel groups within each of the above units may be arranged spaced apart from each other.

[0007] In one embodiment, the subpixel groups and the transparent regions may be alternately arranged in the same row along a second direction perpendicular to the first direction.

[0008] In one embodiment, the second wiring lines may be electrically connected to second subpixels included in subpixel groups of a first row of the second region and first subpixels arranged in the same column as the second subpixels of the first row along the first direction.

[0009] In one embodiment, the total number of second wirings passing through each unit among the second wirings may be equal to the total number of second subpixels included in one subpixel group.

[0010] In one embodiment, the second wiring lines passing through each of the above units can be arranged continuously.

[0011] In one embodiment, each of the unit units includes a first subpixel group and a second subpixel group arranged in different rows, and each of the second wiring lines passing through each of the unit units can be electrically connected to a second subpixel included in the first subpixel group and a second subpixel included in the second subpixel group.

[0012] In one embodiment, each of the first connecting wires may be arranged at least in part in a different layer from a corresponding first wire among the first wires.

[0013] In one embodiment, each of the first connecting wires may include a first portion extending in the first direction, a second portion connected to one end of the first portion and extending in a direction intersecting the first direction, and a third portion connected to the other end of the first portion and extending in a direction intersecting the first direction.

[0014] In one embodiment, the first portion of each of the first connecting wires is disposed in the same layer as a corresponding first wire among the first wires, and the second portion and the third portion of each of the first connecting wires are disposed in different layers from the corresponding first wire and can be in contact with the corresponding first wire through contact holes of at least one insulating layer.

[0015] In one embodiment, each of the first subpixels may include a transistor and a capacitor, wherein the transistor may include a semiconductor layer, a gate electrode overlapping the semiconductor layer, and an electrode layer electrically connected to the semiconductor layer, and the capacitor may include the gate electrode as a lower electrode and an upper electrode arranged to overlap the lower electrode.

[0016] In one embodiment, each of the second portion and the third portion of the first connecting wires may comprise the same material as the electrode layer.

[0017] In one embodiment, each of the first subpixels includes a display element electrically connected to the transistor and having a subpixel electrode, a counter electrode, and an intermediate layer interposed between the subpixel electrode and the counter electrode, and may further include a contact metal layer connected to the electrode layer at a lower portion and connected to the subpixel electrode at an upper portion.

[0018] In one embodiment, each of the first connecting wires may comprise the same material as the contact metal layer.

[0019] In one embodiment, the first wires and the second wires may be data lines.

[0020] In one embodiment, the display device may further include third wirings each including a first sub-wiring and a second sub-wiring that extend in a second direction perpendicular to the first direction and are electrically connected to the first sub-pixels and are spaced apart from each other with the second region; and fourth wirings that extend in the second direction and are electrically connected to the second sub-pixels.

[0021] In one embodiment, the display device may further include second connecting wires arranged in the first region and connecting the first sub-wire and the second sub-wire included in each of the third wires among the third wires.

[0022] In one embodiment, the third wiring lines and the fourth wiring lines may be scan lines.

[0023] In one embodiment, the display device may further include a component overlapping the second region.

[0024] In one embodiment, the component may include a camera or a sensor.

[0025] As described above, the electronic devices (e.g., display devices) according to the present embodiments can improve the light transmittance of the component area by minimizing the wiring arranged in the component area. Of course, the scope of the present invention is not limited by these effects.

[0026] The above and other aspects, features and advantages of the embodiments of the present invention will become more apparent from the description taken in conjunction with the accompanying drawings.

[0027] FIG. 1 is a plan view schematically illustrating a display device according to one embodiment.

[0028] FIG. 2 is a cross-sectional view schematically illustrating a display device according to one embodiment, and is a cross-sectional view taken along line I-I' of FIG. 1.

[0029] FIG. 3A is a plan view schematically illustrating a display panel according to one embodiment.

[0030] FIG. 3b is a plan view showing a horizontal common voltage line and a vertical common voltage line of a display panel according to one embodiment.

[0031] FIGS. 4A and 4B are equivalent circuit diagrams of subpixels that may be included in a display panel according to one embodiment.

[0032] Fig. 5 is a schematic diagram showing the subpixel arrangement structure in the main display area according to one embodiment.

[0033] FIG. 6a and FIG. 6b are schematic diagrams showing a subpixel arrangement structure in a component area according to one embodiment.

[0034] Fig. 7 is a cross-sectional diagram schematically showing a subpixel circuit of a subpixel according to one embodiment.

[0035] FIG. 8 is a plan view schematically illustrating a portion of a display panel according to one embodiment.

[0036] FIGS. 9 and 10 are drawings explaining the application of scan signals and data signals to a component area of ​​a display panel according to one embodiment.

[0037] Fig. 11 is a plan view schematically showing a wiring arrangement structure around a component area of ​​a display panel according to one embodiment.

[0038] FIG. 12 is a cross-sectional view showing data lines and first connection wiring of a display panel according to one embodiment, and is a cross-sectional view taken along line II-II' of FIG. 11.

[0039] Fig. 13 is a cross-sectional view showing data lines and first connection wiring of a display panel according to another embodiment.

[0040] Fig. 14 is a cross-sectional view showing data lines and first connection wiring of a display panel according to another embodiment.

[0041] Fig. 15 is a plan view schematically illustrating a portion of a display panel according to one embodiment.

[0042] Fig. 16 is a plan view schematically showing a wiring arrangement structure around a component area of ​​a display panel according to one embodiment.

[0043] Fig. 17 is a block diagram illustrating an electronic device according to one embodiment.

[0044] FIG. 18 is a schematic diagram illustrating an electronic device according to various embodiments.

[0045] According to one aspect of the present invention, a display device includes a substrate including a first region in which first sub-pixels are arranged, and a second region in which unit units including sub-pixel groups and transparent regions including second sub-pixels are arranged; first wirings each including a first sub-wiring and a second sub-wiring extending in a first direction and electrically connected to the first sub-pixels and spaced apart from each other with the second region therebetween; first connecting wirings arranged in the first region and connecting the first sub-wiring and the second sub-wiring of each of the first wirings, respectively; and second wirings extending in the first direction and electrically connected to the second sub-pixels.

[0046] Reference will now be made in detail to embodiments illustrated in the accompanying drawings, wherein like reference numerals designate like elements throughout the drawings. In this regard, the embodiments may take various forms and should not be construed as limited to the description set forth herein. Accordingly, embodiments are described below with reference to the drawings to illustrate aspects of the present disclosure. The term "and / or" as used herein includes any combination of one or more of the associated listed items. "At least one of a, b, and c" or "at least one of a, b, or c" refers to a case of a, a case of b, a case of c, a case of a and b, a case of a and c, a case of b and c, a, b, and c, or variations thereof.

[0047] The present invention is capable of various modifications and embodiments. Specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, as well as the methods for achieving them, will become clearer with reference to the embodiments described in detail below, along with the drawings. However, the present invention is not limited to the embodiments disclosed below and can be implemented in various forms.

[0048] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals and redundant descriptions thereof will be omitted.

[0049] In the examples below, terms such as “first”, “second”, etc. are not used in a limiting sense but are used for the purpose of distinguishing one component from another.

[0050] In the examples below, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0051] In the following examples, terms such as “include” and / or “have” mean that a feature or component described in the specification is present, and do not preclude the possibility that one or more other features or components may be added.

[0052] In the following examples, when a part such as a film, region, component, etc. is said to be on or above another part, it includes not only a case where it is directly on top of the other part, but also a case where another film, region, component, etc. is interposed in between.

[0053] For convenience of explanation, the sizes of components in the drawings may be exaggerated or reduced. For example, the sizes and thicknesses of each component shown in the drawings are arbitrarily indicated for convenience of explanation, and thus the present invention is not necessarily limited to what is shown.

[0054] In some embodiments, where implementations are otherwise feasible, specific process sequences may be performed in a different order than described. For example, two processes described in succession may be performed substantially simultaneously, or in a reverse order from the described order.

[0055] In the following examples, when it is said that a film, region, component, etc. are connected, it includes cases where the films, regions, components, etc. are directly connected, and / or cases where other films, regions, components, etc. are interposed between the films, regions, components, etc. and are indirectly connected. For example, when it is said in this specification that a film, region, component, etc. are electrically connected, it refers to cases where the films, regions, components, etc. are directly electrically connected, and / or cases where other films, regions, components, etc. are interposed between them and are indirectly electrically connected.

[0056] The x-axis, y-axis, and z-axis are not limited to the three axes in the Cartesian coordinate system, but can be interpreted in a broader sense that includes them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but they can also refer to different directions that are not orthogonal to each other.

[0057] FIG. 1 is a plan view schematically illustrating a display device according to one embodiment of the present invention. The plan view used herein refers to a view viewed in the thickness direction (i.e., z direction) of the substrate (100).

[0058] Referring to FIG. 1, a display device (1) includes a display area (DA) and a peripheral area (PA) outside the display area (DA). The display area (DA) may be a portion that displays an image. The peripheral area (PA) may be a non-display area that does not display an image.

[0059] The display area (DA) can have various shapes, such as circular, elliptical, or polygonal, on a plane (or when viewed from a direction perpendicular to the substrate). Fig. 1 illustrates that the display area (DA) has a roughly rectangular shape with rounded corners.

[0060] The display area (DA) may include a main display area (MDA). The main display area (MDA) may occupy most of the area of ​​the display area (DA). Here, occupying most of the area may mean that the area of ​​the main display area (MDA) is approximately 50% or more of the area of ​​the display area (DA).

[0061] The display area (DA) may include a component area (CA), which is an area where components (40, FIG. 2) including optical elements, etc., are arranged at the bottom. The component area (CA) is arranged inside the main display area (MDA) and may be at least partially surrounded by the main display area (MDA). In one embodiment, the main display area (MDA) may be a first area, and the component area (CA) may be a second area.

[0062] Fig. 1 illustrates a component area (CA) arranged inside a main display area (MDA). In another embodiment, the number of component areas (CA) may be two or more. Although Fig. 1 illustrates that the component area (CA) is approximately circular, the present invention is not necessarily limited thereto. The shape of the component area (CA) on a plane (or when viewed in a direction perpendicular to the substrate) may be variously changed, such as a circular, oval, or polygonal shape such as a square.

[0063] A display device (1) can display an image using light emitted from subpixels arranged in a display area (DA). Each subpixel can include a display element such as an organic light-emitting diode. The subpixels can emit, for example, red, green, or blue light.

[0064] In this specification, among the subpixels arranged in the display area (DA), the subpixels arranged in the main display area (MDA) are called first subpixels (Pm), and the subpixels arranged in the component area (CA) are called second subpixels (Pa). The number of second subpixels (Pa) arranged in the component area (CA) may be smaller than the number of first subpixels (Pm) arranged in the main display area (MDA). An image displayed in the component area (CA) may have a lower resolution than an image displayed in the main display area (MDA).

[0065] Hereinafter, an organic light emitting display device is described as an example of a display device (1) according to an embodiment of the present invention, but the display device (1) of the present invention is not limited thereto. As another embodiment, the display device (1) of the present invention may be an inorganic light emitting display device or a quantum dot light emitting display device. For example, the light emitting layer of a display element included in the display device (1) may include an organic material, an inorganic material, a quantum dot, an organic material and a quantum dot, or an inorganic material and a quantum dot.

[0066] FIG. 2 is a cross-sectional view schematically showing a display device according to one embodiment of the present invention, and is a cross-sectional view taken along line I-I' of FIG. 1.

[0067] Referring to FIG. 2, the display device (1) may include a display panel (10) and a component (40) positioned below the display panel (10) and arranged corresponding to a component area (CA). The display panel (10) may include a substrate (100), an insulating layer (IL), a first subpixel (Pm), a second subpixel (Pa), an encapsulating layer (300), and a lower protective film (175).

[0068] The substrate (100) may include glass or a polymer resin. The polymer resin may include polyethersulfone, polyacrylate, polyether imide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate (100) including the polymer resin may have flexible, rollable, or bendable properties. In one embodiment, the substrate (100) may have a multilayer structure including a layer including the aforementioned polymer resin and an inorganic layer.

[0069] A first subpixel (Pm) including a transistor (TFT) and an organic light-emitting diode (OLED) as a display element electrically connected thereto may be arranged in the main display area (MDA). A second subpixel (Pa) including a transistor (TFT) and an organic light-emitting diode (OLED) as a display element electrically connected thereto may be arranged in the component area (CA). An insulating layer (IL) may be arranged between the components of the transistor (TFT).

[0070] A transparent area (TA) in which no transistor (TFT) or display element is disposed may be disposed in the component area (CA). The transparent area (TA) may be understood as an area through which light or sound output from the component (40) to the outside or traveling from the outside toward the component (40) is transmitted. In one embodiment, the light transmittance of the component area (CA) may be about 30% or more, more preferably about 50% or more, about 75% or more, about 80% or more, about 85% or more, or about 90% or more.

[0071] The component (40) may be an electronic element that utilizes light or sound. For example, the electronic element may be a sensor that measures distance, such as a proximity sensor, a sensor that recognizes a part of the user's body (e.g., a fingerprint, iris, face, etc.), an image sensor that captures an image (e.g., a camera), or a small lamp that outputs light. The electronic element that utilizes light may utilize light of various wavelength bands, such as visible light, infrared light, and ultraviolet light. The electronic element that utilizes sound may utilize ultrasound or sound of another frequency band.

[0072] The encapsulation layer (300) may cover an organic light-emitting diode (OLED). In one embodiment, the encapsulation layer (300) may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. The encapsulation layer (300) may include a first inorganic encapsulation layer (310), a second inorganic encapsulation layer (330), and an organic encapsulation layer (320) therebetween. In another embodiment, the encapsulation layer (300) may be an encapsulation substrate, such as a glass material. A sealant including a frit or the like may be disposed between the substrate (100) and the encapsulation substrate.

[0073] The first inorganic sealing layer (310) and the second inorganic sealing layer (330) may include one or more inorganic insulating materials such as aluminum oxide, titanium oxide, titanium dioxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The organic sealing layer (320) may include a polymer-based material. The polymer-based material may include an acrylic resin, an epoxy resin, polyimide, and polyethylene.

[0074] The lower protective film (175) can be attached to the lower portion of the substrate (100) to support and protect the substrate (100). The lower protective film (175) can define an opening (175OP) corresponding to the component area (CA). By providing the opening (175OP) in the lower protective film (175), the light transmittance of the transmission area (TA) can be improved. The lower protective film (175) can include, for example, polyethylene terephthalate or polyimide.

[0075] FIG. 3a is a plan view schematically illustrating a display panel according to one embodiment of the present invention. FIG. 3b is a plan view illustrating horizontal common voltage lines and vertical common voltage lines of a display panel according to one embodiment of the present invention.

[0076] Referring to Fig. 3a, the subpixel circuits included in the first subpixel (Pm) and the second subpixel (Pa) may include transistors connected to signal lines or voltage lines for controlling on / off and brightness of the corresponding display elements, respectively. In this regard, Fig. 3a illustrates a scan line (GL) and a data line (DL) as signal lines electrically connected to the transistors, and illustrates a driving voltage line (VDDL) and a common voltage line (VSSL) as voltage lines.

[0077] The peripheral area (PA) may entirely surround the display area (DA). Voltage supply lines and driving circuits may be arranged in the peripheral area (PA). In this regard, FIG. 3A illustrates a common voltage supply line (1010), a driving voltage supply line (2000), a first driving circuit (3031), a second driving circuit (3032), and a data driving circuit (4000) arranged in the peripheral area (PA).

[0078] The common voltage supply line (1010) may have a loop shape that partially surrounds the display area (DA) and has one open side. The common voltage supply line (1010) may include a first common voltage input unit (1011), a second common voltage input unit (1012), and a third common voltage input unit (1014) arranged adjacent to a first edge (E1) of the display area (DA). In one embodiment, the first common voltage input unit (1011) and the second common voltage input unit (1012) may be arranged adjacent to the first edge (E1) of the display area (DA) but spaced apart from each other. The third common voltage input unit (1014) may be located adjacent to the first edge (E1) of the display area (DA) but between the first common voltage input unit (1011) and the second common voltage input unit (1012).

[0079] The first common voltage input unit (1011) and the second common voltage input unit (1012) may be connected by a body portion (1013) extending along the second edge (E2), the third edge (E3), and the fourth edge (E4) of the display area (DA). In other words, the first common voltage input unit (1011), the second common voltage input unit (1012), and the body portion (1013) may be formed integrally. The common voltage supply line (1010) may have a loop shape with one end open, and both ends of the common voltage supply line (1010) may correspond to the first common voltage input unit (1011) and the second common voltage input unit (1012), respectively, and the area between the first common voltage input unit (1011) and the second common voltage input unit (1012) may correspond to the body portion (1013).

[0080] The first auxiliary common voltage supply line (1021) and the second auxiliary common voltage supply line (1022) may be arranged in the peripheral area (PA). The first auxiliary common voltage supply line (1021) and the second auxiliary common voltage supply line (1022) may each be a type of branch line extending from the common voltage supply line (1010).

[0081] The first auxiliary common voltage supply line (1021) is electrically connected to the common voltage supply line (1010), and may extend along the second edge (E2) of the display area (DA). The first auxiliary common voltage supply line (1021) may be located between the first driving circuit (3031) and the second edge (E2) of the display area (DA).

[0082] The second auxiliary common voltage supply line (1022) is electrically connected to the common voltage supply line (1010), and may extend along the fourth edge (E4) of the display area (DA). The second auxiliary common voltage supply line (1022) may be located between the second driving circuit (3032) and the fourth edge (E4) of the display area (DA). The common voltage supply line (1010), the first auxiliary common voltage supply line (1021), and the second auxiliary common voltage supply line (1022) may be electrically connected to common voltage lines (VSSL) passing through the display area (DA). The common voltage line (VSSL) may be electrically connected to a counter electrode (e.g., a cathode) of the display element.

[0083] The common voltage lines (VSSL) may include a first common voltage line and a second common voltage line that extend to intersect each other. For example, the common voltage lines (VSSL) may include a first common voltage line extending in the y direction and a second common voltage line extending in the x direction. Hereinafter, for convenience of explanation, the 'first common voltage line extending in the y direction' is referred to as a vertical common voltage line (VSL), and the 'second common voltage line extending in the x direction' is referred to as a horizontal common voltage line (HSL).

[0084] The vertical common voltage line (VSL) and the horizontal common voltage line (HSL) may pass through the display area (DA) so as to intersect each other. For example, as illustrated in FIG. 3b, the vertical common voltage lines (VSL) and the horizontal common voltage lines (HSL) that intersect each other may have a mesh structure on a plane. When the display area (DA) includes a component area (CA) that includes a transparent area (TA), the vertical common voltage line (VSL) and the horizontal common voltage line (HSL) may be arranged so as not to pass through the component area (CA) in order to sufficiently secure the transparent area (TA).

[0085] The vertical common voltage lines (VSL) can be electrically connected to the common voltage supply line (1010). Some of the vertical common voltage lines (VSL) can be electrically connected to the first common voltage input unit (1011) and the body unit (1013), others can be electrically connected to the second common voltage input unit (1012) and the body unit (1013), and still others can be electrically connected to the third common voltage input unit (1014) and the body unit (1013).

[0086] The horizontal common voltage line (HSL) can be electrically connected to the first auxiliary common voltage supply line (1021) and the second auxiliary common voltage supply line (1022). One end of each of the horizontal common voltage lines (HSL) can be electrically connected to the first auxiliary common voltage supply line (1021), and the other end of each of the horizontal common voltage lines (HSL) can be electrically connected to the second auxiliary common voltage supply line (1022).

[0087] The vertical common voltage line (VSL) and the horizontal common voltage line (HSL) may be positioned on different layers. In some embodiments, the vertical common voltage line (VSL) and the horizontal common voltage line (HSL) may be electrically connected to each other through a first contact hole (CNT1) defined in at least one insulating layer interposed therebetween. The first contact hole (CNT1) for connecting the vertical common voltage line (VSL) and the horizontal common voltage line (HSL) may be positioned in the display area (DA).

[0088] The driving voltage supply line (2000) may include a first driving voltage input unit (2021) and a second driving voltage input unit (2022) that are spaced apart from each other with a display area (DA) therebetween. The first driving voltage input unit (2021) and the second driving voltage input unit (2022) may extend substantially in parallel with the display area (DA) therebetween. The first driving voltage input unit (2021) may be arranged adjacent to a first edge (E1) of the display area (DA), and the second driving voltage input unit (2022) may be arranged adjacent to a third edge (E3) of the display area (DA).

[0089] The driving voltage supply line (2000) may be electrically connected to driving voltage lines (VDDL) passing through the display area (DA). The driving voltage line (VDDL) may include a first driving voltage line and a second driving voltage line that extend to intersect each other. For example, the driving voltage line (VDDL) may include a first driving voltage line extending in the y direction and a second driving voltage line extending in the x direction. Hereinafter, for convenience of explanation, the 'first driving voltage line extending in the y direction' is referred to as a vertical driving voltage line (VDL), and the 'second driving voltage line extending in the x direction' is referred to as a horizontal driving voltage line (HDL).

[0090] A vertical driving voltage line (VDL) and a horizontal driving voltage line (HDL) may pass through a display area (DA) so as to intersect each other. The vertical driving voltage line (VDL) and the horizontal driving voltage line (HDL) may be positioned on different layers, but may be connected through a second contact hole (CNT2) formed in at least one insulating layer positioned therebetween. The second contact hole (CNT2) for connecting the vertical driving voltage line (VDL) and the horizontal driving voltage line (HDL) may be positioned in the display area (DA).

[0091] The first driving circuit (3031) and the second driving circuit (3032) may be arranged in the peripheral area (PA). The scan lines (GL) may be electrically connected to the first driving circuit (3031) and / or the second driving circuit (3032). In some embodiments, some of the scan lines (GL) may be electrically connected to the first driving circuit (3031), and the remaining scan lines (GL) may be connected to the second driving circuit (3032). The first driving circuit (3031) and the second driving circuit (3032) include a scan driving unit that generates a scan signal, and the scan signal generated in the scan driving unit may be transmitted to one transistor of the subpixel circuit through the scan line (GL).

[0092] The data driving circuit (4000) can transmit a data signal to any one transistor included in each sub-pixel circuit through a data line (DL) passing through the display area (DA).

[0093] A first terminal portion (TD1) may be positioned on one side of the substrate (100). A printed circuit board (5000) may be attached to the first terminal portion (TD1). The printed circuit board (5000) includes a second terminal portion (TD2) electrically connected to the first terminal portion (TD1), and a control portion (6000) may be disposed on the printed circuit board (5000). Control signals of the control portion (6000) may be provided to the first and second driving circuits (3031, 3032), the data driving circuit (4000), the driving voltage supply line (2000), and the common voltage supply line (1010) via the first and second terminal portions (TD1, TD2), respectively.

[0094] FIGS. 4A and 4B are equivalent circuit diagrams schematically illustrating a subpixel circuit included in a subpixel of a display panel according to one embodiment of the present invention. The subpixel (PX) of FIGS. 4A and 4B may be a first subpixel (Pm) and / or a second subpixel (Pa), and the subpixel (PX) may include a subpixel circuit (PC) and an organic light-emitting diode (OLED) as a display element connected to the subpixel circuit (PC).

[0095] Referring to FIG. 4A, in one embodiment, a subpixel circuit (PC) may include a first transistor (T1), a second transistor (T2), and a capacitor (Cst). The subpixel circuit (PC) may be electrically connected to a scan line (GL) and a data line (DL). The first transistor (T1) may be a driving transistor, and the second transistor (T2) may be a switching transistor. The second transistor (T2) is electrically connected to the scan line (GL) and the data line (DL), and may transmit a data signal (Dm) input through the data line (DL) to the first transistor (T1) according to a scan signal (Gn) input through the scan line (GL).

[0096] The capacitor (Cst) is connected to the second transistor (T2) and the driving voltage line (VDDL), and stores a voltage corresponding to the difference between the voltage received from the second transistor (T2) and the driving voltage (ELVDD) supplied to the driving voltage line (VDDL).

[0097] The first transistor (T1) is connected to a driving voltage line (VDDL) and a capacitor (Cst), and can control a driving current flowing from the driving voltage line (VDDL) to the organic light-emitting diode (OLED) in response to a voltage value stored in the capacitor (Cst). The organic light-emitting diode (OLED) can emit light having a predetermined brightness according to the driving current.

[0098] In one embodiment, the subpixel circuit (PC) is illustrated as including two transistors and one capacitor, but the present invention is not necessarily limited thereto. In other embodiments, the subpixel circuit (PC) may include three or more transistors and / or two or more capacitors.

[0099] Referring to FIG. 4B, in one embodiment, the subpixel circuit (PC) may include first to eighth transistors (T1, T2, T3, T4, T5, T6, T7, T8) and a capacitor (Cst). The subpixel circuit (PC) may be electrically connected to a data line (DL), a first gate line (GWL), a second gate line (GIL), a third gate line (GCL), a fourth gate line (GBL), and an emission control line (EL). In addition, the subpixel circuit (PC) may be electrically connected to an initialization voltage line (VL), a node initialization voltage line (VIL), and a driving voltage line (VDDL).

[0100] In one embodiment, some of the first to eighth transistors (T1 to T8) may be provided as NMOS (n-channel MOSFETs), and the rest may be provided as PMOS (p-channel MOSFETs). FIG. 4b illustrates that the third transistor (T3) and the fourth transistor (T4) among the first to eighth transistors (T1 to T8) are provided as NMOS, and the rest are provided as PMOS. However, the present invention is not necessarily limited thereto. In another embodiment, all of the first to eighth transistors (T1 to T8) may be provided as PMOS or NMOS. Depending on the type and / or operating conditions of the transistor, the first terminal of the transistor may be a source electrode or a drain electrode, and the second terminal may be an electrode different from the first terminal. For example, when the first terminal is a source electrode, the second terminal may be a drain electrode.

[0101] A first transistor (T1) may be connected between a driving voltage line (VDDL) and an organic light-emitting diode (OLED). The first transistor (T1) may be connected between a first node (N1) and a third node (N3). The first transistor (T1) may be electrically connected to the driving voltage line (VDDL) via a fifth transistor (T5) and may be electrically connected to the organic light-emitting diode (OLED) via a sixth transistor (T6). The first transistor (T1) may include a gate electrode connected to a second node (N2), a first terminal connected to the first node (N1), and a second terminal connected to a third node (N3). The driving voltage line (VDDL) may transmit a driving voltage (ELVDD) to the first transistor (T1). The first transistor (T1) is a driving transistor, and can receive a data signal (Dm) according to the switching operation of the second transistor (T2) and supply driving current to the organic light-emitting diode (OLED).

[0102] A second transistor (T2) (data write transistor) may be connected between a data line (DL) and a first node (N1). The second transistor (T2) may be electrically connected to a driving voltage line (VDDL) via a fifth transistor (T5). The second transistor (T2) may include a gate electrode connected to a first gate line (GWL), a first terminal connected to the data line (DL), and a second terminal connected to the first node (N1). The second transistor (T2) may be turned on in response to a first scan signal (GW) received through the first gate line (GWL) and may perform a switching operation to transmit a data signal (Dm) transmitted to the data line (DL) to the first node (N1).

[0103] A third transistor (T3) (compensation transistor) may be connected between the second node (N2) and the third node (N3). The third transistor (T3) may be electrically connected to an organic light-emitting diode (OLED) via a sixth transistor (T6). The third transistor (T3) may include a gate electrode connected to a third gate line (GCL), a first terminal connected to a second node (N2), and a second terminal connected to the third node (N3). The third transistor (T3) may be turned on according to a third scan signal (GC) received through the third gate line (GCL) to diode-connect the first transistor (T1), thereby compensating for a threshold voltage of the first transistor (T1).

[0104] A fourth transistor (T4) (node ​​initialization transistor) may be connected between a second node (N2) and a node initialization voltage line (VIL). The fourth transistor (T4) may include a gate electrode connected to a second gate line (GIL), a first terminal connected to the second node (N2), and a second terminal connected to the node initialization voltage line (VIL). The fourth transistor (T4) may be turned on according to a second scan signal (GI) received through the second gate line (GIL) to transmit an initialization voltage (Vint) to a gate electrode of the first transistor (T1) to initialize the gate electrode of the first transistor (T1).

[0105] The fifth transistor (T5) (first light-emitting control transistor) may be connected between the driving voltage line (VDDL) and the first node (N1). The fifth transistor (T5) may include a gate electrode connected to the light-emitting control line (EL), a first terminal connected to the driving voltage line (VDDL), and a second terminal connected to the first node (N1).

[0106] The sixth transistor (T6) (second emission control transistor) may be connected between the organic light-emitting diode (OLED) and the third node (N3). The sixth transistor (T6) may include a gate electrode connected to the emission control line (EL), a first terminal connected to the third node (N3), and a second terminal connected to a subpixel electrode of the organic light-emitting diode (OLED). The fifth transistor (T5) and the sixth transistor (T6) may be simultaneously turned on according to an emission control signal (EM) received through the emission control line (EL), so that a driving current may flow to the organic light-emitting diode (OLED).

[0107] The seventh transistor (T7) (initialization transistor) may be connected between the organic light-emitting diode (OLED) and the initialization voltage line (VL). The seventh transistor (T7) may include a gate electrode connected to the fourth gate line (GBL), a first terminal connected to the second terminal of the sixth transistor (T6) and the subpixel electrode of the organic light-emitting diode (OLED), and a second terminal connected to the initialization voltage line (VL). The seventh transistor (T7) may be turned on according to the fourth scan signal (GB) received through the fourth gate line (GBL) to transmit the initialization voltage (Vaint) to the subpixel electrode of the organic light-emitting diode (OLED) to initialize the subpixel electrode of the organic light-emitting diode (OLED). The seventh transistor (T7) can be turned on simultaneously with the eighth transistor (T8) according to the fourth scan signal (GB). In some embodiments, the seventh transistor (T7) can include two seventh transistors connected in series.

[0108] The eighth transistor (T8) (bias transistor) may be connected between the first node (N1) and the bias voltage line (VBL). The eighth transistor (T8) may include a gate electrode connected to the fourth gate line (GBL), a first terminal connected to the bias voltage line (VBL), and a second terminal connected to the first node (N1). The eighth transistor (T8) may be turned on according to the fourth scan signal (GB) received through the fourth gate line (GBL) to apply a bias voltage (VOBS) to the first terminal of the first transistor (T1) so as to preset a voltage suitable for a subsequent operation of the first transistor (T1) at the first terminal.

[0109] The capacitor (Cst) may include a lower electrode connected to the gate electrode of the first transistor (T1) and an upper electrode connected to the driving voltage line (VDDL). The capacitor (Cst) may store and maintain a voltage corresponding to the difference between the voltages at both ends of the driving voltage line (VDDL) and the gate electrode of the first transistor (T1), thereby maintaining the voltage applied to the gate electrode of the first transistor (T1).

[0110] An organic light-emitting diode (OLED) includes a subpixel electrode and a counter electrode, and the counter electrode can receive a common voltage (ELVSS). The organic light-emitting diode (OLED) can display an image by emitting light by receiving a driving current from a first transistor (T1).

[0111] Although FIG. 4b illustrates an embodiment in which a sub-pixel circuit (PC) includes eight transistors and one capacitor, the present invention is not necessarily limited thereto. The number of transistors and capacitors included in the sub-pixel circuit (PC) and the circuit design may vary.

[0112] FIG. 5 is a schematic diagram showing a subpixel arrangement structure in a main display area according to one embodiment of the present invention.

[0113] Referring to FIG. 5, first sub-pixels (Pm) are arranged in the main display area (MDA). Each of the first sub-pixels (Pm) may include a display element such as an organic light-emitting diode. The first sub-pixels (Pm) arranged in the main display area (MDA) may include a first red sub-pixel (Pr), a first green sub-pixel (Pg), and a first blue sub-pixel (Pb), and each of the first red sub-pixel (Pr), the first green sub-pixel (Pg), and the first blue sub-pixel (Pb) may implement red, green, and blue, respectively.

[0114] In one embodiment, the first subpixels (Pm) may be arranged in a pentile structure. In the pentile structure, each first subpixel (Pm) may be a unit pixel that includes one red subpixel (Pr), two green subpixels (Pg), and one blue subpixel (Pb) and is repeatedly arranged in the x and y directions. In one embodiment, as illustrated in FIG. 5, the first blue subpixels (Pb) may be arranged at the first and third opposite vertices of a virtual rectangle (VS) with the center point of the first green subpixel (Pg) as the center point of the rectangle, and the first red subpixels (Pr) may be arranged at the second and fourth vertices, which are the remaining vertices of the virtual rectangle (VS). In another embodiment, the virtual rectangle (VS) may be variously modified, such as a rectangle, a rhombus, or a square. The size of the first green subpixel (Pg) may be smaller than the sizes of the first red subpixel (Pr) and the first blue subpixel (Pb).

[0115] In the first row (1N), first blue subpixels (Pb) and first red subpixels (Pr) may be arranged alternately. In the second row (2N), first green subpixels (Pg) may be arranged repeatedly. In the third row (3N), first red subpixels (Pr) and first blue subpixels (Pb) may be arranged alternately. In the fourth row (4N), first green subpixels (Pg) may be arranged repeatedly. The above-mentioned first rows (1N) to fourth rows (4N) may be arranged repeatedly along the y direction.

[0116] The first blue subpixels (Pb) and the first red subpixels (Pr) of the first row (1N) and the first green subpixels (Pg) of the second row (2N) are arranged alternately. In the first column (1M), the first blue subpixels (Pb) and the first red subpixels (Pr) are arranged alternately, in the second column (2M), the first green subpixels (Pg) are arranged repeatedly, in the third column (3M), the first red subpixels (Pr) and the first blue subpixels (Pb) are arranged alternately, and in the fourth column (4M), the first green subpixels (Pg) may be arranged repeatedly. The above-mentioned first column (1M) to fourth column (4M) may be arranged repeatedly along the x direction.

[0117] This pixel arrangement structure is called a PenTile Matrix structure, or PenTile structure, and by applying a rendering operation that expresses colors by sharing adjacent pixels, high resolution can be implemented with a small number of pixels.

[0118] Although Fig. 5 illustrates that the first subpixels (Pm) are arranged in a pentile structure, the present invention is not necessarily limited thereto. As another example, the first subpixels (Pm) may be arranged in various shapes, such as a stripe structure, a mosaic array structure, or a delta array structure.

[0119] The arrangement of the first subpixels (Pm) illustrated in FIG. 5 may correspond to the arrangement of the organic light-emitting diodes, which are display elements. For example, the position of the first red subpixel (Pr) illustrated in FIG. 5 may correspond to the position of the display element that emits red light. Similarly, the position of the first green subpixel (Pg) may correspond to the position of the display element that emits green light, and the position of the first blue subpixel (Pb) may correspond to the position of the display element that emits blue light.

[0120] FIG. 6a and FIG. 6b are schematic diagrams showing a subpixel arrangement structure in a component area according to one embodiment of the present invention.

[0121] Referring to FIGS. 6A and 6B, each of the second sub-pixels (Pa) arranged in the component area (CA) may include a second red sub-pixel (Pr'), a second green sub-pixel (Pg'), and a second blue sub-pixel (Pb'), and each of the second red sub-pixel (Pr'), the second green sub-pixel (Pg'), and the second blue sub-pixel (Pb') may implement red, green, and blue, respectively. Each of the second sub-pixels (Pa) may include a display element such as an organic light-emitting diode. In one embodiment, the size, shape, and / or arrangement structure of the second sub-pixels (Pa) of the component area (CA) may be different from the size, shape, and / or arrangement structure of the first sub-pixels (Pm) of the main display area (MDA).

[0122] A component area (CA) may include a subpixel group (PG) including second subpixels (Pa) and a transmissive area (TA). A plurality of subpixel groups (PG) and transmissive areas (TA) may be provided. A subpixel group (PG) may be defined as a subpixel collection that groups second subpixels (Pa) into preset units. The preset unit, the subpixel group (PG), may include a second red subpixel (Pr'), a second green subpixel (Pg'), and a second blue subpixel (Pb') that emit light of different colors. In the component area (CA), the subpixel groups (PG) may be arranged to be spaced apart from each other.

[0123] Referring to FIG. 6A, one subpixel group (PG) may include one second blue subpixel (Pb'), one second red subpixel (Pr'), and one second green subpixel (Pg'), so that three second subpixels (Pa) may be included. The second subpixels (Pa) included in one subpixel group (PG) may be arranged in two rows along the y direction and three columns along the x direction within the subpixel group (PG). In the first row (1N'), second blue subpixels (Pb') and second red subpixels (Pr') may be arranged alternately. In the second row (2N'), second green subpixels (Pg') may be arranged. A second blue subpixel (Pb') may be arranged in the first column (1M'), a second green subpixel (Pg') in the second column (2M'), and a second red subpixel (Pr') in the third column (3M'). For example, as illustrated in Fig. 6a, it can be expressed that a second blue subpixel (Pb'), a second red subpixel (Pr'), and a second green subpixel (Pg') are arranged at the vertices of an imaginary triangle (VT), respectively.

[0124] Referring to FIG. 6b, one subpixel group (PG) may include one second blue subpixel (Pb'), one second red subpixel (Pr'), and two second green subpixels (Pg'), so that four second subpixels (Pa) may be included. The second subpixels (Pa) included in one subpixel group (PG) may be arranged based on a pentile structure. The second subpixels (Pa) included in one subpixel group (PG) may be arranged in a structure of two rows in the y direction and four columns in the x direction within the subpixel group (PG). In the first row (1N'), second blue subpixels (Pb') and second red subpixels (Pr') may be arranged alternately. In the second row (2N'), second green subpixels (Pg') may be arranged. A second blue subpixel (Pb') may be arranged in the first column (1M'), a second green subpixel (Pg') in the second column (2M'), a second red subpixel (Pr') in the third column (3M'), and a second green subpixel (Pg') in the fourth column (4M'). For example, as illustrated in Fig. 6b, the four second subpixels (Pa) may have a pixel arrangement structure in which they are each arranged at the corners of an imaginary square (VS'). The imaginary square (VS') may be a parallelogram.

[0125] The transparent area (TA) may be arranged on one side of the subpixel group (PG). The transparent areas (TA) may be arranged adjacent to the subpixel groups (PG). No subpixels may be arranged in the transparent area (TA). That is, this may mean that the subpixel electrode, the intermediate layer, the counter electrode, and the subpixel circuit electrically connected thereto, which constitute the display element, are not arranged in the transparent area (TA). In one embodiment, some of the signal lines connected to supply a signal to the second subpixel (Pa) located in the component area (CA) may be arranged across the transparent area (TA). However, even in this case, in order to increase the light transmittance of the transparent area (TA), the signal lines may be arranged to be biased toward one side, bypassing the central portion of the transparent area (TA). In FIG. 6a and FIG. 6b, the transmission area (TA) is illustrated as being formed in a circular shape, but the present invention is not necessarily limited thereto, and the transmission area (TA) may be formed in various shapes such as a polygon, an octagon, an oval, etc.

[0126] Subpixel groups (PGs) and transparent areas (TAs) arranged in a component area (CA) may be alternately arranged along one direction. The subpixel groups (PGs) and transparent areas (TAs) arranged in the component area (CA) may be alternately arranged in the same column along the x direction (e.g., row direction). In one embodiment, the subpixel groups (PGs) and transparent areas (TAs) arranged in the component area (CA) may be alternately arranged in the same row or column along the x direction (e.g., row direction) and the y direction (e.g., column direction). A transparent area (TA) is arranged between the subpixel groups (PGs), and the transparent area (TA) may surround at least a portion of the subpixel groups (PGs).

[0127] In a component area (CA), unit units (AUs) including a predetermined number of subpixel groups (PGs) and a predetermined number of transparent areas (TAs) can be repeatedly arranged in the x and y directions. A unit unit (AU) is a segment of a repetitive shape and does not imply a break in the configuration.

[0128] A unit (AU) may include at least one subpixel group (PG). In one embodiment, the unit (AU) may include subpixel groups (PGs). The subpixel groups (PGs) within the unit (AU) may be arranged to be spaced apart from each other. The subpixel groups (PGs) within the unit (AU) may be provided in a plurality of rows and / or columns. FIG. 6A illustrates that the unit (AU) includes two subpixel groups (PGs) and two transparent areas (TAs) arranged around the subpixel groups (PGs), and that the two subpixel groups (PGs) and the two transparent areas (TAs) included in the unit (AU) are arranged alternately along a row direction (e.g., x direction) and a column direction (e.g., y direction). FIG. 6b illustrates that a unit unit (AU) includes two subpixel groups (PGs) and two transparent areas (TAs), and that the two subpixel groups (PGs) and two transparent areas (TAs) included in the unit unit (AU) are alternately arranged along the row direction (e.g., x direction) and the column direction (e.g., y direction). However, the present invention is not necessarily limited thereto, and the subpixel groups (PGs) and the transparent areas (TAs) may be arranged in various ways within the unit unit (AU).

[0129] A corresponding unit (MU, FIG. 5) having an area equal to that of a unit (AU) can be set in the main display area (MDA). The number of first sub-pixels (Pm) included in the corresponding unit (MU) may be greater than the number of second sub-pixels (Pa) included in the unit (AU). For example, FIG. 6a illustrates that the number of second sub-pixels (Pa) included in the unit (AU) is 6, and the number of first sub-pixels (Pm) included in the corresponding unit (MU) is 32. FIG. 6b illustrates that the number of second sub-pixels (Pa) included in the unit (AU) is 8, and the number of first sub-pixels (Pm) included in the corresponding unit (MU) is 32.

[0130] The pixel arrangement structure illustrated in FIGS. 6A and 6B is an example, and the present invention is not necessarily limited thereto. The arrangement structure and number of second subpixels (Pa) included in a unit (AU) may be modified and designed according to the resolution of the component area (CA).

[0131] The arrangement of the second subpixels (Pa) illustrated in FIGS. 6A and 6B may correspond to the arrangement of the organic light-emitting diode, which is a display element. For example, the position of the second red subpixel (Pr') illustrated in FIGS. 6A and 6B may correspond to the position of the display element that emits red light, the position of the second green subpixel (Pg') may correspond to the position of the display element that emits green light, and the position of the second blue subpixel (Pb') may correspond to the position of the display element that emits blue light. The subpixel group (PG) illustrated in FIGS. 6A and 6B may correspond to a display element group including a display element that emits red light, a display element that emits green light, and a display element that emits blue light.

[0132] Figure 7 is a cross-sectional view schematically showing a subpixel circuit of a subpixel according to one embodiment of the present invention.

[0133] Referring to FIG. 7, a first subpixel (Pm) is arranged in the main display area (MDA), and a second subpixel (Pa) is arranged in the component area (CA). The first subpixel (Pm) is a display element arranged in the main display area (MDA) and includes a subpixel circuit connected thereto. The second subpixel (Pa) includes a display element arranged in the component area (CA) and a subpixel circuit electrically connected thereto. The display element may be an organic light-emitting diode. The subpixel circuit may include transistors and at least one capacitor.

[0134] For convenience of explanation, the organic light-emitting diode arranged in the main display area (MDA) is referred to as a first organic light-emitting diode (OLEDm), and the organic light-emitting diode arranged in the component area (CA) is referred to as a second organic light-emitting diode (OLEDa). In addition, the subpixel circuit arranged in the main display area (MDA) is referred to as a first subpixel circuit (PCm), and the subpixel circuit arranged in the component area (CA) is referred to as a second subpixel circuit (PCa). Fig. 7 illustrates a transistor (TFT) and a capacitor (Cst) included in the first subpixel circuit (PCm), and a transistor (TFT') and a capacitor (Cst') included in the second subpixel circuit (PCa).

[0135] A first metal layer (BSM1) may be arranged under a transistor (TFT) of a first subpixel (Pm) on a plane so as to overlap with the transistor (TFT). The first metal layer (BSM1) may prevent the characteristics of the transistor (TFT) from deteriorating. A second metal layer (BSM2) may be arranged under a transistor (TFT') of a second subpixel (Pa) on a plane so as to overlap with the transistor (TFT'). The second metal layer (BSM2) may prevent the characteristics of the transistor (TFT') from deteriorating. In some embodiments, the first metal layer (BSM1) arranged so as to overlap with the transistor (TFT) may be omitted.

[0136] The first and second metal layers (BSM1, BSM2) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu). The first and second metal layers (BSM1, BSM2) may be a single layer or multiple layers of the aforementioned materials.

[0137] A transistor (TFT) and a transistor (TFT') may be arranged on the buffer layer (111). The transistor (TFT) may include a first semiconductor layer (A1), a first gate electrode (G1), a first source electrode (S1), and a first drain electrode (D1), and the transistor (TFT') may include a second semiconductor layer (A2), a second gate electrode (G2), a second source electrode (S2), and a second drain electrode (D2).

[0138] The first semiconductor layer (A1) and the second semiconductor layer (A2) are disposed on the buffer layer (111) and may include polysilicon. In another embodiment, the first semiconductor layer (A1) and the second semiconductor layer (A2) may include amorphous silicon. In another embodiment, the first semiconductor layer (A1) and the second semiconductor layer (A2) may include an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), stannum (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The first semiconductor layer (A1) and the second semiconductor layer (A2) may include a channel region and a source region and a drain region doped with impurities.

[0139] A first gate insulating layer (112) may be provided to cover the first semiconductor layer (A1) and the second semiconductor layer (A2). The first gate insulating layer (112) may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, or zinc oxide. The first gate insulating layer (112) may be a single layer or multiple layers including the above-described inorganic insulating material.

[0140] On a plane, first and second gate electrodes (G1, G2) may be arranged on the first gate insulating layer (112) to overlap the first and second semiconductor layers (A1, A2), respectively. The first and second gate electrodes (G1, G2) may include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a single layer or multiple layers. For example, the first and second gate electrodes (G1, G2) may be a single layer including molybdenum (Mo).

[0141] The second gate insulating layer (113) may be provided to cover the first and second gate electrodes (G1, G2). The second gate insulating layer (113) may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, or zinc oxide. The second gate insulating layer (113) may be a single layer or multiple layers including the above-described inorganic insulating material.

[0142] A first upper electrode (CE2) of a capacitor (Cst) and a second upper electrode (CE2') of a capacitor (Cst') may be arranged on the second gate insulating layer (113). On a plane, the first upper electrode (CE2) may overlap with the first gate electrode (G1) underneath it in the main display area (MDA). The first gate electrode (G1) and the first upper electrode (CE2) overlapping with the second gate insulating layer (113) interposed therebetween on a plane may form a capacitor (Cst). The first gate electrode (G1) may be the first lower electrode (CE1) of the capacitor (Cst).

[0143] On a plane, the second upper electrode (CE2') in the component area (CA) may overlap with the second gate electrode (G2) underneath. The second gate electrode (G2) and the second upper electrode (CE2'), which overlap with the second gate insulating layer (113) interposed therebetween on the plane, may form a capacitor (Cst'). The second gate electrode (G2) may be the second lower electrode (CE1') of the capacitor (Cst').

[0144] The first and second upper electrodes (CE2, CE2') may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be a single layer or multiple layers of the aforementioned materials.

[0145] An interlayer insulating layer (115) may be formed to cover the first and second upper electrodes (CE2, CE2'). The interlayer insulating layer (115) may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, or zinc oxide.

[0146] The first and second source electrodes (S1, S2) and the first and second drain electrodes (D1, D2) may be disposed on an interlayer insulating layer (115). The first and second source electrodes (S1, S2) and the first and second drain electrodes (D1, D2) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials. For example, the first and second source electrodes (S1, S2) and the first and second drain electrodes (D1, D2) may be formed as a multilayer structure of Ti / Al / Ti.

[0147] A first planarization layer (117) may be arranged to cover the first and second source electrodes (S1, S2) and the first and second drain electrodes (D1, D2). The first planarization layer (117) may have a flat upper surface so that the first and second subpixel electrodes (221, 221') arranged thereon may be formed flat.

[0148] A second planarization layer (118) may be disposed on the first planarization layer (117). A contact metal layer (CM, CM') may be disposed between the first planarization layer (117) and the second planarization layer (118). The contact metal layers (CM, CM') may electrically connect the first and second drain electrodes (D1, D2) and the first and second subpixel electrodes (221, 221') through contact holes defined in the first planarization layer (117), respectively.

[0149] The first and second planarization layers (117, 118) may be formed as a single layer or multiple layers of films made of organic or inorganic materials. The first and second planarization layers (117, 118) may include organic materials such as general-purpose polymers such as BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), Polymethylmethacrylate (PMMA), Polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof. Meanwhile, the first and second planarization layers (117, 118) may include inorganic materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, or zinc oxide. After forming the first and second planarization layers (117, 118), chemical and mechanical polishing may be performed to provide a flat upper surface. The first and second planarization layers (117, 118) may each function as an insulating layer.

[0150] The second planarization layer (118) defines a contact hole exposing a contact metal layer (CM, CM'), and the first subpixel electrode (221) contacts the contact metal layer (CM) through the contact hole and is electrically connected to the first source electrode (S1) or the first drain electrode (D1) through the contact metal layer (CM), thereby being electrically connected to the transistor (TFT).

[0151] In addition, the second subpixel electrode (221') may be electrically connected to the second source electrode (S2) or the second drain electrode (D2) through the contact metal layer (CM') and may be electrically connected to the transistor (TFT'). The first and second source electrodes (S1, S2) and the first and second drain electrodes (D1, D2) may be referred to as "electrode layers."

[0152] The first and second subpixel electrodes (221, 221') may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In another embodiment, the first and second subpixel electrodes (221, 221') may include a reflective film including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. In another embodiment, the first and second subpixel electrodes (221, 221') may further include a film formed of ITO, IZO, ZnO, or In2O3 above / below the aforementioned reflective film. In some embodiments, the first and second subpixel electrodes (221, 221') may be provided with a structure in which ITO / Ag / ITO is laminated.

[0153] The bank layer (119) can cover the edges of each of the first and second subpixel electrodes (221, 221'). The bank layer (119) overlaps each of the first and second subpixel electrodes (221, 221') on a plane and can provide first and second openings (OP1, OP2) that define light-emitting areas of the subpixels. The bank layer (119) can prevent arcs and the like from occurring at the edges of the first and second subpixel electrodes (221, 221') by increasing the distance between the edges of the first and second subpixel electrodes (221, 221') and the counter electrodes (223) on the upper portions of the first and second subpixel electrodes (221, 221'). The bank layer (119) may be formed of an organic insulating material such as polyimide, polyamide, acrylic resin, benzocyclobutene, HMDSO (hexamethyldisiloxane), and phenol resin, and may be formed by a method such as spin coating.

[0154] A first functional layer (222a) is arranged to cover the bank layer (119). The first functional layer (222a) may be a single layer or a multi-layer. The first functional layer (222a) may be a hole transport layer (HTL) having a single layer structure. Alternatively, the first functional layer (222a) may include a hole injection layer (HIL) and a hole transport layer (HTL). The first functional layer (222a) may be formed integrally to correspond to the first sub-pixels (Pm) included in the main display area (MDA) and the second sub-pixels (Pa) included in the component area (CA).

[0155] On the first functional layer (222a), first and second light-emitting layers (222b, 222b') corresponding to the first and second subpixel electrodes (221, 221') are arranged, respectively. The first and second light-emitting layers (222b, 222b') may include a high molecular weight material or a low molecular weight material, and may emit red, green, blue, or white light.

[0156] A second functional layer (222c) may be formed on the first and second light-emitting layers (222b, 222b'). The second functional layer (222c) may be a single layer or a multi-layer. The second functional layer (222c) may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The second functional layer (222c) may be formed integrally to correspond to the first sub-pixels (Pm) included in the main display area (MDA) and the second sub-pixels (Pa) included in the component area (CA). In another embodiment, the first functional layer (222a) and / or the second functional layer (222c) may be omitted.

[0157] A counter electrode (223) is arranged on the second functional layer (222c). The counter electrode (223) may include a conductive material having a low work function. For example, the counter electrode (223) may include a (semi-)transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. Alternatively, the counter electrode (223) may further include a layer such as ITO, IZO, ZnO, or In2O3 on the (semi-)transparent layer including the above-described material. The counter electrode (223) may be integrally formed to correspond to the first sub-pixels (Pm) included in the main display area (MDA) and the second sub-pixels (Pa) included in the component area (CA).

[0158] The layers from the first subpixel electrode (221) arranged in the main display area (MDA) to the counter electrode (223) can form a first organic light-emitting diode (OLEDm). The layers from the second subpixel electrode (221') arranged in the component area (CA) to the counter electrode (223) can form a second organic light-emitting diode (OLEDa).

[0159] A capping layer (250) may be formed on the counter electrode (223). The capping layer (250) may include LiF. Alternatively, the capping layer (250) may include an inorganic insulating material such as silicon nitride, and / or an organic insulating material. In some embodiments, the capping layer (250) may be omitted.

[0160] The first organic light emitting diode (OLEDm) and the second organic light emitting diode (OLEDa) can be sealed by an encapsulating layer (300). The encapsulating layer (300) can be disposed on the capping layer (250). The encapsulating layer (300) can prevent external moisture or foreign substances from penetrating into the first organic light emitting diode (OLEDm) and the second organic light emitting diode (OLEDa).

[0161] The encapsulating layer (300) may include at least one inorganic encapsulating layer and at least one organic encapsulating layer. In this regard, FIG. 7 illustrates, as an example, a structure in which the encapsulating layer (300) is formed by stacking a first inorganic encapsulating layer (310), an organic encapsulating layer (320), and a second inorganic encapsulating layer (330).

[0162] Fig. 8 is a plan view schematically illustrating a portion of a display panel according to one embodiment of the present invention. Fig. 8 illustrates a portion of a main display area (MDA), a component area (CA), and an intermediate area (MA) included in a display area (DA).

[0163] The display area (DA) may further include an intermediate area (MA). The intermediate area (MA) may be arranged between the main display area (MDA) and the component area (CA). The intermediate area (MA) may be an area corresponding to a boundary between the main display area (MDA) and the component area (CA). The intermediate area (MA) may be an area where the first subpixel (Pm) and the second subpixel (Pa) are not arranged. In Fig. 8, the intermediate area (MA) is described as being between the main display area (MDA) and the component area (CA), but in another embodiment, the intermediate area (MA) may be a part of the component area (CA), that is, a transparent area (TA) of the component area (CA). Wires extending from the main display area (MDA) to the component area (CA) may be arranged in the intermediate area (MA). If the wires extending from the main display area (MDA) to the component area (CA) decrease, the area of ​​the intermediate area (MA) may decrease.

[0164] Referring to Fig. 8, first subpixels (Pm) may be arranged in the main display area (MDA). For example, Fig. 8 illustrates that the first subpixels (Pm) (i.e., display elements of the first subpixels (Pm)) are arranged in the pentile structure of Fig. 5. On a plane, the first subpixel circuits (PCm) in the main display area (MDA) may be arranged to overlap the display elements of the first subpixels (Pm). The first subpixel circuits (PCm) may be arranged in a matrix shape along the x and y directions.

[0165] Second subpixels (Pa) may be arranged in the component area (CA). In the component area (CA), subpixel groups (PG) including the second subpixels (Pa) and transparent areas (TA) may be alternately arranged along the x direction. In one embodiment, the subpixel groups (PG) and transparent areas (TA) may be alternately arranged in the x direction and the y direction in the component area (CA). In the component area (CA), unit units (AU) including a predetermined number of subpixel groups (PG) and transparent areas (TA) may be repeatedly arranged in the x direction and the y direction. For example, FIG. 8 illustrates that second subpixels (Pa) (display elements of the second subpixels (Pa)) are arranged in the pixel array structure of FIG. 6A. In the component area (CA), second subpixel circuits (PCa) may be arranged to overlap the display elements of the second subpixels (Pa) on a plane. The second subpixel circuits (PCa) can be arranged in groups. The groups of the subpixel circuits can be arranged spaced apart from each other.

[0166] FIG. 8 illustrates a first unit (AU1) and a second unit (AU2) arranged in the same column as part of a component area (CA). Although FIG. 8 illustrates only two unit units (AU) in the component area (CA), this is merely for convenience of explanation, and three or more unit units (AU) may be arranged in the component area (CA). In one embodiment, one unit (AU) may include two subpixel groups (PGs) and two transmission areas (TAs) alternately arranged along the x and y directions. The first unit (AU1) may include a first subpixel group (PG1) and a second subpixel group (PG2) arranged in different rows and columns. The second unit (AU2) may include a third subpixel group (PG3) and a fourth subpixel group (PG4) arranged in different rows and columns.

[0167] Data lines (DL) may extend along the y direction (e.g., column direction) in the display area (DA). The data lines (DL) may include first data lines (DL1) and second data lines (DL2). In one embodiment, the first data line (DL1) may be a “first wiring” and the second data line (DL2) may be a “second wiring.” In FIG. 8, only eight data lines (DL) corresponding to a portion of the component area (CA) are illustrated, but this is merely for convenience of explanation, and nine or more data lines (DL) may be arranged in the display area (DA).

[0168] The first data lines (DL1) may be electrically connected to first sub-pixels (Pm) arranged along the same column in the main display area (MDA). In the present specification, connecting a wiring to a sub-pixel may mean that the wiring is connected to a sub-pixel circuit to supply a signal or power to the sub-pixel. For example, connecting a wiring to the first sub-pixel (Pm) may mean that the wiring is connected to a first sub-pixel circuit (PCm) included in the first sub-pixel (Pm). Connecting a wiring to a second sub-pixel (Pa) may mean that the wiring is connected to a second sub-pixel circuit (PCa) included in the second sub-pixel (Pa).

[0169] The first data lines (DL1) can bypass the component area (CA) via the first connection lines (DNL) arranged in the main display area (MDA). On a plane, the first data lines (DL1) may not overlap the component area (CA) including the transmission area (TA). This structure can improve the light transmittance of the transmission area (TA).

[0170] Each of the first data lines (DL1) may include a first sub-wire and a second sub-wire spaced apart with a component area (CA) therebetween, and the first connection wires (DNL) may electrically connect the first sub-wire and the second sub-wire of each of the first data lines (DL1). The wiring structure in which the first data lines (DL1) bypass the component area (CA) will be described in detail below with reference to FIG. 11.

[0171] The second data lines (DL2) may extend in the y direction (e.g., column direction) in the component area (CA). The second data lines (DL2) may be electrically connected to second sub-pixels (Pa) in the component area (CA). The second data lines (DL2) may be connected to sub-pixel groups (PG) of different rows constituting one unit (AU). Here, "the data line being connected to a sub-pixel group" may mean that the data line is connected to at least one sub-pixel among the sub-pixels included in the sub-pixel group. For example, the second data lines (DL2) may be connected to the first sub-pixel group (PG1) and the second sub-pixel group (PG2) arranged in different rows of the first unit (AU1). The second data lines (DL2) may be connected to the third sub-pixel group (PG3) and the fourth sub-pixel group (PG4) of the second unit (AU2) arranged in different rows.

[0172] Each of the second data lines (DL2) may be connected to second sub-pixels (Pa) arranged in the same column within each sub-pixel group (PG) when connected to sub-pixel groups (PG) of different rows constituting a unit (AU). As illustrated in FIG. 8, the second data line (DL2) connected to the second blue sub-pixel (Pb') of the first column of the first sub-pixel group (PG1) may be connected to the second blue sub-pixel (Pb') of the first column of the second sub-pixel group (PG2). Similarly, the second data line (DL2) connected to the second green sub-pixel (Pg') of the second column of the first sub-pixel group (PG1) may be connected to the second green sub-pixel (Pg') of the second column of the second sub-pixel group (PG2). The second data line (DL2) connected to the second red subpixel (Pr') of the third column of the first subpixel group (PG1) can be connected to the second red subpixel (Pr') connected to the third column of the second subpixel group (PG2).

[0173] The second data lines (DL2) can pass through the unit units (AU) arranged in the same column of each sub-pixel group. For example, the second data lines (DL2) can pass through the first unit unit (AU1) and the second unit unit (AU2) arranged in the same column of each sub-pixel group. The second data lines (DL2) can be connected to the sub-pixel groups (PG) constituting each of the unit units (AU) arranged in the same column. Similarly, each of the second data lines (DL2) can be connected to the second sub-pixels (Pa) arranged in the same column within each sub-pixel group (PG). For example, a second data line (DL2) connected to a second blue subpixel (Pb') of a first column of a second subpixel group (PG2) included in a first unit (AU1) may be connected to a second blue subpixel (Pb') of a first column of a third subpixel group (PG3) included in a second unit (AU2).

[0174] The number of second data lines (DL2) passing through the unit unit (AU) may be the same as the number of second sub-pixels (Pa) included in one sub-pixel group (PG) within the unit unit (AU). For example, one sub-pixel group (PG) of FIG. 8 includes three second sub-pixels (Pa), including one second blue sub-pixel (Pb'), one second green sub-pixel (Pg'), and one second red sub-pixel (Pr') arranged in different columns of the sub-pixel group (PG), and therefore, the number of second data lines (DL2) passing through the unit unit (AU) may be three. Accordingly, the number of second data lines (DL2) passing through the unit unit (AU) may vary depending on the arrangement structure of the second sub-pixels (Pa). In one embodiment, the second data lines (DL2) passing through the unit unit (AU) may be arranged continuously (i.e., may pass through the component area (CA).

[0175] In one embodiment, the second data lines (DL2) may be arranged to bypass the transparent area (TA) within the component area (CA). The second data lines (DL2) may extend between the sub-pixel groups (PG) and the transparent areas (TA). Alternatively, the second data lines (DL2) may overlap at least a portion of the transparent area (TA) located in the component area (CA) on a plane. In this case, in order to increase the light transmittance of the transparent area (TA), the second data lines (DL2) may be arranged to be biased toward one side, bypassing the central portion of the transparent area (TA).

[0176] The second data lines (DL2) may extend to the main display area (MDA) along the y direction (e.g., column direction). The second data lines (DL2) may be connected to the first subpixels (Pm) of the main display area (MDA) arranged along the same column as the second subpixels (Pa) included in the subpixel groups (PGs) arranged in the first row among the subpixel groups (PGs) of the component area (CA). The second data lines (DL2) may be connected to the first subpixels (Pm) of the main display area (MDA) arranged along the same column as the second subpixels (Pa) included in the subpixel groups (PGs) arranged in the first row among the subpixel groups (PGs) within the unit (AU) (i.e., the first subpixel group (PG1)). For example, as illustrated in FIG. 8, the second data lines (DL2) can be connected to the first sub-pixels (Pm) of the main display area (MDA) arranged along the same column as the second sub-pixels (Pa) included in the first sub-pixel group (PG1) arranged in the first row of the first unit (AU1).

[0177] In other words, among the data lines (DL) arranged in columns corresponding to the component area (CA) among the columns of the main display area (MDA), the second data lines (DL2) may extend to the component area (CA) and be connected to the second sub-pixels (Pa). Among the data lines (DL) arranged in columns corresponding to the component area (CA) among the columns of the main display area (MDA), the first data lines (DL1) may bypass the component area (CA) without passing through the component area (CA). The first sub-pixels (Pm) connected to the second data lines (DL2) in the main display area (MDA) may be arranged in the same column as the second sub-pixels (Pa) included in the sub-pixel groups (PG) of the first row of the component area (CA). The first sub-pixels (Pm) connected to the first data lines (DL1) in the main display area (MDA) may correspond to the transparent areas (TA) arranged in the first row of the component area (CA).

[0178] Depending on the arrangement structure of the second sub-pixels (Pa) in the component area (CA), the number of second data lines (DL2) passing through the component area (CA) and the number of first data lines (DL1) bypassing the component area (CA) may vary. For example, FIG. 8 illustrates that among eight data lines (DL) arranged in columns corresponding to the component area (CA) in the main display area (MDA), three second data lines (DL2) are connected to sub-pixel groups (PG) each including three second sub-pixels (Pa), and five first data lines (DL1) bypass the component area (CA).

[0179] Scan lines (GL) may extend along the x-direction (e.g., row direction) in the main display area (MDA). The scan lines (GL) may be connected to first sub-pixels (Pm) arranged in the same row in the main display area (MDA). Some of the scan lines (GL) may extend to the component area (CA). Some of the scan lines (GL) may extend along the x-direction (e.g., row direction) in the component area (CA) and may be connected to second sub-pixels (Pa) in the same row. The scan lines (GL) may receive scan signals from the first driving circuit (3031, FIG. 3A) and / or the second driving circuit (3032, FIG. 3A). Each of the second sub-pixels (Pa) may emit light with a brightness corresponding to a data signal received from the connected second data line (DL2) when a scan signal is applied from the connected scan line (GL).

[0180] FIGS. 9 and 10 are drawings explaining the application of scan signals and data signals to the component areas of a display panel according to one embodiment of the present invention. The numbers on the left side of FIG. 9 indicate the order of scan lines or scan signals, and the numbers on the upper side indicate the order of data lines arranged in columns corresponding to the component areas (CA) among the columns of the main display area (MDA). Here, the middle area (MA) is omitted. For example, FIG. 9 illustrates the order of 10 scan lines in the first to tenth rows of the main display area (MDA) and 16 data lines arranged in 16 columns corresponding to the component areas (CA). FIG. 10 illustrates data lines and emission colors connected to second sub-pixels included in sub-pixel groups within a unit.

[0181] Referring to FIGS. 9 and 10, the second sub-pixels (11, 12, 13) provided in the first sub-pixel group (PG1) of the first unit (AU1) can be sequentially connected to the first, second, and third data lines among the 16 data lines, respectively. The second sub-pixels (21, 22, 23) provided in the second sub-pixel group (PG2) of the first unit (AU1) can be sequentially connected to the first, second, and third data lines among the 16 data lines, respectively.

[0182] The second sub-pixels (31, 32, 33) provided in the third sub-pixel group (PG3) of the second unit (AU2) can be sequentially connected to the first, second, and third data lines among the 16 data lines, respectively. The second sub-pixels (41, 42, 43) provided in the fourth sub-pixel group (PG4) of the second unit (AU2) can be sequentially connected to the first, second, and third data lines among the 16 data lines, respectively.

[0183] The second sub-pixels (51, 52, 53) provided in the fifth sub-pixel group (PG5) of the third unit (AU3) can be sequentially connected to the 9th, 10th, and 11th data lines among the 16 data lines, respectively. The second sub-pixels (61, 62, 63) provided in the sixth sub-pixel group (PG6) of the third unit (AU3) can be sequentially connected to the 9th, 10th, and 11th data lines among the 16 data lines, respectively.

[0184] The second sub-pixels (71, 72, 73) provided in the 7th sub-pixel group (PG7) of the 4th unit (AU4) can be sequentially connected to the 9th, 10th, and 11th data lines among the 16 data lines, respectively. The second sub-pixels (81, 82, 83) provided in the 8th sub-pixel group (PG8) of the 4th unit (AU4) can be sequentially connected to the 9th, 10th, and 11th data lines among the 16 data lines, respectively.

[0185] As described above in FIG. 8, some of the data lines arranged in columns corresponding to the component area (CA) among the columns of the main display area (MDA) may not pass through the component area (CA). For example, the 4th to 8th, and the 12th to 16th data lines may not extend into the component area (CA). The 4th to 8th, and the 12th to 16th data lines may not be connected to the second sub-pixels of the component area (CA).

[0186] Among the 16 data lines, the 1st, 2nd, and 3rd data lines, and the 9th, 10th, and 11th data lines may correspond to the second data lines (DL2) of FIG. 8. Among the 16 data lines, the 4th to 8th, and the 12th to 16th data lines may correspond to the first data lines (DL1) of FIG. 8. The 4th to 8th, and the 12th to 16th data lines may bypass the component area (CA) through the first connection wire arranged in the main display area (MDA).

[0187] The second sub-pixels (11, 12, 13) provided in the first sub-pixel group (PG1) of the first unit (AU1) and the second sub-pixels (51, 52, 53) provided in the fifth sub-pixel group (PG5) of the third unit (AU3) can be connected to the third scan line among the ten scan lines.

[0188] The second sub-pixels (21, 22, 23) provided in the second sub-pixel group (PG2) of the first unit (AU1) and the second sub-pixels (61, 62, 63) provided in the sixth sub-pixel group (PG6) of the third unit (AU3) can be connected to the fifth scan line among the ten scan lines.

[0189] The second sub-pixels (31, 32, 33) provided in the third sub-pixel group (PG3) of the second unit (AU2) and the second sub-pixels (71, 72, 73) provided in the seventh sub-pixel group (PG7) of the fourth unit (AU4) can be connected to the seventh scan line among the ten scan lines.

[0190] The second sub-pixels (41, 42, 43) provided in the fourth sub-pixel group (PG4) of the second unit (AU2) and the second sub-pixels (81, 82, 83) provided in the eighth sub-pixel group (PG8) of the fourth unit (AU4) can be connected to the ninth scan line among the ten scan lines.

[0191] When a scan signal is applied to the third scan line, a data signal can be applied to the second sub-pixels (11 to 13, 51 to 53) provided in the first sub-pixel group (PG1) of the first unit (AU1) and the fifth sub-pixel group (PG5) of the third unit (AU3), respectively. When a scan signal is applied to the fifth scan line, a data signal can be applied to the second sub-pixels (21 to 23, 61 to 63) provided in the second sub-pixel group (PG2) of the first unit (AU1) and the sixth sub-pixel group (PG6) of the third unit (AU3), respectively.

[0192] Likewise, when a scan signal is applied to the 7th scan line, a data signal can be applied to the second sub-pixels (31 to 33, 71 to 73) provided in the 3rd sub-pixel group (PG3) of the 2nd unit (AU2) and the 7th sub-pixel group (PG7) of the 4th unit (AU4), respectively. When a scan signal is applied to the 9th scan line, a data signal can be applied to the second sub-pixels (41 to 43, 81 to 83) provided in the 4th sub-pixel group (PG4) of the 2nd unit (AU2) and the 8th sub-pixel group (PG8) of the 4th unit (AU4), respectively. The second sub-pixels can emit light with a brightness corresponding to the data signal provided from each connected data line.

[0193] The second data lines may be connected to the first sub-pixels of the main display area (MDA) arranged along the same column as the second sub-pixels of the sub-pixel groups of the first row within the component area (CA). In one embodiment, the scan lines connected to the second sub-pixels and the data signals applied thereto may be determined by the arrangement structure of the virtual first sub-pixels arranged in the component area (CA). For example, in FIG. 9, the scan lines connected to the second sub-pixels and the data signals applied thereto may be determined by the arrangement structure of the virtual first sub-pixels assuming that the first sub-pixels arranged in the first to third columns of the main display area (MDA) connected to the first to third data lines are also arranged consecutively in the first to third columns of the component area (CA). For example, in the first column of the main display area (MDA) corresponding to the component area (CA), blue subpixels and red subpixels may be alternately arranged, green subpixels may be alternately arranged in the second column, and red subpixels and blue subpixels may be alternately arranged in the third column. The second subpixels (11, 21, 31, 41) connected to the first data line and connected to the third, fifth, seventh, and ninth scan lines, respectively, may correspond to blue subpixels. The second subpixels (12, 22, 32, 42) connected to the second data line and connected to the third, fifth, seventh, and ninth scan lines, respectively, may correspond to green subpixels. The second sub-pixels (13, 23, 33, 43) connected to the third data line and connected to the third, fifth, seventh, and ninth scan lines, respectively, can correspond to red sub-pixels.

[0194] The application of scan signals and data signals to the second subpixel described with reference to FIGS. 9 and 10 can be equally applied to subsequent unit units.

[0195] FIG. 11 is a plan view schematically showing a wiring arrangement structure around a component area of ​​a display panel according to one embodiment of the present invention.

[0196] Referring to FIG. 11, data lines (DL) for applying data signals to each subpixel may be arranged in the display area (DA). The data lines (DL) extend in the y direction and may be arranged approximately parallel to each other. In FIG. 11, only the data lines (DL) adjacent to the component area (CA) are illustrated, and five data lines (DL) are illustrated, but this is merely for convenience of explanation, and six or more data lines (DL) may be arranged in the display area (DA). The data lines (DL) may include a first data line (DL1), a second data line (DL2), and a third data line (DL3). The first data line (DL1) and the second data line (DL2) illustrated in FIG. 11 may correspond to the first data line (DL1) and the second data line (DL2) described with reference to FIGS. 8 to 10.

[0197] Each of the first data lines (DL1) may include a first sub-wire and a second sub-wire spaced apart from each other with a component area (CA) therebetween. For example, the first data lines (DL1) may include a first-first data line (DL1-1), a first-second data line (DL1-2), and a first-third data line (DL1-3). The first-first data line (DL1-1) may include a first sub-wire (DL1-1a) and a second sub-wire (DL1-1b) spaced apart from each other with a component area (CA). The second sub-wire (DL1-1b) of the first-first data line (DL1-1) may be arranged to coincide with a virtual line extending in the y direction from the first sub-wire (DL1-1a). Similarly, the first-second data line (DL1-2) may include a first sub-wire (DL1-2a) and a second sub-wire (DL1-2b) separated by a component area (CA). The first-third data line (DL1-3) may include a first sub-wire (DL1-3a) and a second sub-wire (DL1-3b) separated by a component area (CA).

[0198] Unlike the first data line (DL1), the second data line (DL2) may be arranged to pass through the component area (CA). The third data line (DL3) may be formed integrally without any portion being disconnected or separated by the component area (CA). Unlike the second data line (DL2), the third data line (DL3) may not have a portion that overlaps the component area (CA) on a plane.

[0199] FIG. 11 illustrates three first data lines (DL1), one second data line (DL2), and one third data line (DL3), but this is for convenience of explanation, and four or more first data lines (DL1), two or more second data lines (DL2), and two or more third data lines (DL3) may be arranged in the display area (DA).

[0200] First connection wires (DNLs) may be arranged in the main display area (MDA) among the display areas (DA). The first connection wires (DNLs) may be arranged to bypass the component area (CA). The first connection wires (DNLs) may electrically connect the first sub-wire and the second sub-wire of each of the first data lines (DL1). For example, the first connection wires (DNLs) may include a 1-1 connection wire (DNL1), a 1-2 connection wire (DNL2), and a 1-3 connection wire (DNL3). The 1-1 connection wire (DNL1) may electrically connect the first sub-wire (DL1-1a) and the second sub-wire (DL1-1b) of the 1-1 data line (DL1-1). The 1-2 connection wire (DNL2) can electrically connect the first sub-wire (DL1-2a) and the second sub-wire (DL1-2b) of the 1-2 data line (DL1-2). The 1-3 connection wire (DNL3) can electrically connect the first sub-wire (DL1-3a) and the second sub-wire (DL1-3b) of the 1-3 data line (DL1-3).

[0201] The same signal can be applied to the first sub-wire (DL1-1a) and the second sub-wire (DL1-1b) of the first-first data line (DL1-1) through the first-first connection wire (DNL1). Although the description is based on the first-first connection wire (DNL1), the same can be applied to the first-second connection wire (DNL2) and the first-third connection wire (DNL3).

[0202] The 1-1 connection wire (DNL1) may or may not be connected to the 1-2 data line (DL1-2) and the 1-3 data line (DL1-3). Different signals may be applied to the 1-1 data line (DL1-1), the 1-2 data line (DL1-2), and the 1-3 data line (DL1-3).

[0203] In one embodiment, the first-first connection wire (DNL1) may be arranged closest to the component area (CA), the first-third connection wire (DNL3) may be arranged farthest from the component area (CA), and the first-second connection wire (DNL2) may be arranged between the first-first connection wire (DNL1) and the first-third connection wire (DNL3). However, the present invention is not necessarily limited thereto, and the shapes in which the first-first to first-third connection wires (DNL1, DNL2, DNL3) are arranged may vary.

[0204] The first connecting wire (DNL) may include a first portion extending in the y direction, a second portion connected to one end of the first portion and extending in the x direction, and a third portion connected to the other end of the first portion and extending in the x direction. For example, the 1-1 connecting wire (DNL1) may include a first portion (DNL1a) extending in the y direction, a second portion (DNL1b) extending in the x direction, and a third portion (DNL1c). The second portion (DNL1b) may be connected to one end of the first portion (DNL1a), and the third portion (DNL1c) may be connected to the other end of the first portion (DNL1a).

[0205] In one embodiment, the first portion (DNL1a) of the 1-1 connection wire (DNL1) may be arranged in the same column as any one of the vertical common voltage lines (VSL) described above with reference to FIGS. 3A and 3B. The second portion (DNL1b) and the third portion (DNL1c) of the 1-1 connection wire (DNL1) may be arranged in the same row as any one of the horizontal common voltage lines (HSL) described above with reference to FIGS. 3A and 3B. Although the description is based on the 1-1 connection wire (DNL1), the 1-2 connection wire (DNL2) and the 1-3 connection wire (DNL3) may also be applied in the same manner.

[0206] Fig. 12 is a cross-sectional view showing data lines and a first connection wire of a display panel according to an embodiment of the present invention, and is a cross-sectional view taken along line II-II' of Fig. 11, and Fig. 13 is a modified embodiment of Fig. 12. Figs. 12 and 13 illustrate cross-sections of a first-first connection wire (DNL1) electrically connecting a first sub-wire (DL1-1a) and a second sub-wire (DL1-1b) of a first-first data line (DL1-1), as an example of a first connection wire (DNL).

[0207] Referring to FIGS. 12 and 13, a buffer layer (111), a first gate insulating layer (112), a second gate insulating layer (113), and an interlayer insulating layer (115) can be sequentially arranged on a substrate (100).

[0208] In one embodiment, the second portion (DNL1b) and the third portion (DNL1c) of the first-first connection wiring (DNL1) may be disposed on a different layer from the first portion (DNL1a) of the first-first connection wiring (DNL1). The second portion (DNL1b) and the third portion (DNL1c) of the first-first connection wiring (DNL1) may be disposed on an interlayer insulating layer (115). A first planarization layer (117) may be disposed to cover the second portion (DNL1b) and the third portion (DNL1c) of the first-first connection wiring (DNL1).

[0209] The first sub-wiring (DL1-1a) and the second sub-wiring (DL1-1b) of the 1-1 data line (DL1-1), and the first portion (DNL1a) of the 1-1 connection wiring (DNL1) may be arranged on the first planarization layer (117). The first sub-wiring (DL1-1a) of the 1-1 data line (DL1-1) may be electrically connected to the second portion (DNL1b) of the 1-1 connection wiring (DNL1) through a contact hole of the first planarization layer (117). The second sub-wiring (DL1-1b) of the 1-1 data line (DL1-1) may be electrically connected to the third portion (DNL1c) of the 1-1 connection wiring (DNL1) through a contact hole of the first planarization layer (117). The first part (DNL1a) of the first-first connection wiring (DNL1) can be electrically connected to the second part (DNL1b) and the third part (DNL1c) of the first-first connection wiring (DNL1) through the contact holes of the first planarization layer (117).

[0210] Additionally, the first and second sub-wires (DL1-2a, DL1-2b) of the first-second data line (DL1-2) and the first and second sub-wires (DL1-3a, DL1-3b) of the first-third data line (DL1-3) may be arranged on the first planarization layer (117). The first-second data line (DL1-2) and the first-third data line (DL1-3) may or may not be in contact with the first-first connection wire (DNL1) of the first-first data line (DL1-1).

[0211] The second part (DNL1b) and the third part (DNL1c) of the first-first connection wiring (DNL1) are arranged on the same layer as the first and second source electrodes (S1, S2) and the first and second drain electrodes (D1, D2) of the transistor (TFT, TFT') of FIG. 7, and may include the same material as the first and second source electrodes (S1, S2) and the first and second drain electrodes (D1, D2).

[0212] The first part (DNL1a) of the first-first connection wire (DNL1), the first sub-wire (DL1-1a) and the second sub-wire (DL1-1b) of the first-first data line (DL1-1), the first-second data line (DL1-2), and the first-third data line (DL1-3) are arranged in the same layer as the contact metal layer (CM, CM') of FIG. 7, and may include the same material as the contact metal layer (CM, CM').

[0213] Referring to FIG. 13, in another embodiment, the first sub-wiring (DL1-1a) and the second sub-wiring (DL1-1b) of the 1-1 data line (DL1-1) may be arranged on the interlayer insulating layer (115). In another embodiment, the first sub-wiring (DL1-1a) and the second sub-wiring (DL1-1b) of the 1-1 data line (DL1-1) may be provided integrally with the second portion (DNL1b) and the third portion (DNL1c) of the 1-1 connection wire (DNL1), respectively. In this case, the first sub-wiring (DL1-1a) and the second sub-wiring (DL1-1b) of the first-first data line (DL1-1) are arranged in the same layer as the first and second source electrodes (S1, S2) and the first and second drain electrodes (D1, D2) of the transistor (TFT, TFT') of FIG. 7, and may include the same material as the first and second source electrodes (S1, S2) and the first and second drain electrodes (D1, D2).

[0214] Fig. 14 is a cross-sectional view showing data lines and a first connection wire of a display panel according to one embodiment of the present invention, and is a modified embodiment of Fig. 12. Fig. 14 illustrates a cross-section of a first-first connection wire (DNL1) electrically connecting a first sub-wire (DL1-1a) and a second sub-wire (DL1-1b) of a first-first data line (DL1-1), as an example of a first connection wire (DNL). Hereinafter, differences from the embodiment of Fig. 12 will be described, and duplicate descriptions will be omitted.

[0215] Referring to FIG. 14, in one embodiment, the second portion (DNL1b) and the third portion (DNL1c) of the 1-1 connection wiring (DNL1) may be arranged on the same layer as the first portion (DNL1a) of the 1-1 connection wiring (DNL1). In another embodiment, the first portion (DNL1a), the second portion (DNL1b), and the third portion (DNL1c) of the 1-1 connection wiring (DNL1) may be provided as one piece.

[0216] The first part (DNL1a), the second part (DNL1b), and the third part (DNL1c) of the first-first connection wiring (DNL1) may be arranged on the interlayer insulating layer (115). A first planarization layer (117) may be arranged on the first-first connection wiring (DNL1).

[0217] The first part (DNL1a), the second part (DNL1b), and the third part (DNL1c) of the first-first connection wiring (DNL1) are integrally arranged on the same layer as the first and second source electrodes (S1, S2), and the first and second drain electrodes (D1, D2) of the transistor (TFT, TFT') of FIG. 7, and may include the same material as the first and second source electrodes (S1, S2), and the first and second drain electrodes (D1, D2).

[0218] Fig. 15 is a plan view schematically illustrating a portion of a display panel according to one embodiment of the present invention. Fig. 15 illustrates a portion of a main display area (MDA), a component area (CA), and an intermediate area (MA) included in a display area (DA).

[0219] Referring to Fig. 15, first subpixels (Pm) may be arranged in the main display area (MDA). For example, Fig. 15 illustrates that the first subpixels (Pm) (i.e., display elements of the first subpixels (Pm)) are arranged in the pentile structure of Fig. 5. In the main display area (MDA), the first subpixel circuits (PCm) may be arranged to overlap the display elements of the first subpixels (Pm) on a plane. The first subpixel circuits (PCm) may be arranged in a matrix shape along the x and y directions.

[0220] Second subpixels (Pa) may be arranged in the component area (CA). In one embodiment, subpixel groups (PG) and transparent areas (TA) may be alternately arranged in the x-direction and the y-direction in the component area (CA). In the component area (CA), unit units (AU) including a predetermined number of subpixel groups (PG) and transparent areas (TA) may be repeatedly arranged in the x-direction and the y-direction. For example, FIG. 15 illustrates that second subpixels (Pa) (display elements of the second subpixel (Pa)) are arranged in the pixel array structure of FIG. 6A. In the component area (CA), second subpixel circuits (PCa) may be arranged to overlap display elements of the second subpixels (Pa) on a plane. The second subpixel circuits (PCa) may be arranged in groups. The groups of the subpixel circuits may be arranged to be spaced apart from each other.

[0221] FIG. 15 illustrates a first unit (AU1') and a second unit (AU2') arranged in the same row as part of a component area (CA). Although FIG. 15 illustrates that two unit units (AUs) are arranged in one row in the component area (CA), this is merely for convenience of explanation, and three or more unit units (AUs) may be arranged in one row of the component area (CA). The unit unit (AU') may include two subpixel groups (PGs) and two transparent areas (TAs) arranged alternately along the x and y directions. The first unit (AU') may include a first subpixel group (PG1') and a second subpixel group (PG2') arranged in different rows and columns. The second unit (AU') may include a third subpixel group (PG3') and a fourth subpixel group (PG4') arranged in different rows and columns.

[0222] Scan lines (GL) may extend along the x-direction (e.g., row direction) in the display area (DA). The scan lines (GL) may include first scan lines (GL1), second scan lines (GL2), and third scan lines (GL3). In one embodiment, the first scan line (GL1) and the second scan line (GL2) may be third wiring lines, and the third scan line (GL3) may be fourth wiring lines. In FIG. 15, only eight scan lines (GL) corresponding to a portion of the component area (CA) are illustrated, but this is merely for convenience of explanation, and nine or more scan lines (GL) may be arranged in the display area (DA).

[0223] Each of the first scan lines (GL1) and the second scan lines (GL2) may be electrically connected to first sub-pixels (Pm) arranged along the same row in the main display area (MDA). The first scan lines (GL1) may bypass the component area (CA) via second connection lines (GNL) arranged in the main display area (MDA). On a plane, the first scan lines (GL1) and the second scan lines (GL2) may not overlap the component area (CA). Each of the first scan lines (GL1) and the second scan lines (GL2) may include a first sub-line and a second sub-line spaced apart from each other with the component area (CA) therebetween. The second connection lines (GNL) may electrically connect the first sub-line and the second sub-line of each of the first scan lines (GL1). The wiring structure in which the first scan lines (GL1) bypass the component area (CA) is described in detail later with reference to Fig. 16.

[0224] The first scan lines (GL1) can be connected to either the first driving circuit (3031) arranged on the left side of the peripheral area (PA) or the second driving circuit (3032) arranged on the right side. The first scan lines (GL1) can receive scan signals from either the first driving circuit (3031) or the second driving circuit (3032).

[0225] The second scan lines (GL2) may be connected to the first driving circuit (3031) arranged on the left side of the peripheral area (PA) and the second driving circuit (3032) arranged on the right side. One end of each of the second scan lines (GL2) may be connected to the first driving circuit (3031) and the other end may be connected to the second driving circuit (3032). Accordingly, even if the second scan line (GL2) is provided with the first sub-wire and the second sub-wire spaced apart with the component area (CA) in between, the scan signal received from the first driving circuit (3031) and the second driving circuit (3032) can be applied to the first sub-pixels (Pm) arranged on the left side of the component area (CA) and connected to the second scan line (GL2) and the first sub-pixels (Pm) arranged on the right side of the component area (CA) and connected to the second scan line (GL2), respectively.

[0226] In one embodiment, the first gate line (GWL), the second gate line (GIL), the third gate line (GCL), and the emission control line (EL) illustrated in FIG. 4B may be connected to the first subpixel circuit (PCm) of the first subpixel (Pm) and the second subpixel circuit (PCa) of the second subpixel (Pa), or the first gate line (GWL), the second gate line (GIL), the third gate line (GCL), the fourth gate line (GBL), and the emission control line (EL) may be connected. In this case, the first scan lines (GL1) may be the second gate line (GIL), the third gate line (GCL), and / or the emission control line (EL). The second scan lines (GL2) may be the first gate line (GWL) and / or the fourth gate line (GBL).

[0227] The first scan lines (GL1) that are not connected to the second subpixels (Pa) of the component area (CA) can be arranged to bypass the component area (CA) via the second connection lines (GNL), and the second scan lines (GL2) can be arranged to be separated by the component area (CA). This can reduce the number of lines passing through the component area (CA). This structure can improve the light transmittance of the component area (CA).

[0228] The third scan lines (GL3) may extend in the x direction (e.g., row direction) in the component area (CA). The third scan lines (GL3) may be electrically connected to the second subpixels (Pa) in the component area (CA). The third scan lines (GL3) may pass through the unit units (AU) arranged in the same row. The third scan lines (GL3) may be connected to the subpixel groups (PG) arranged in the same row. In other words, the third scan lines (GL3) may be connected to the groups of the second subpixel circuits (PCa) arranged in the same row. For example, the third scan lines (GL3) may be arranged to pass through the first unit unit (AU1') and the second unit unit (AU2') arranged in the same row. The third scan lines (GL3) connected to the first sub-pixel group (PG1') of the first unit (AU1') can be connected to the third sub-pixel group (PG3') of the second unit (AU2') arranged in the same row. The third scan lines (GL3) connected to the second sub-pixel group (PG2') of the first unit (AU1') can be connected to the fourth sub-pixel group (PG4') of the second unit (AU2') arranged in the same row.

[0229] The third scan lines (GL3) may extend along the x-direction (e.g., row direction) to the main display area (MDA). In one embodiment, the third scan lines (GL3) may be arranged within the component area (CA) bypassing the transparent areas (TA). The third scan lines (GL3) may be arranged between the sub-pixel groups (PG) and the transparent areas (TA). Alternatively, the third scan lines (GL3) may overlap at least a portion of the transparent areas (TA) located in the component area (CA) on a plane. In this case, in order to increase the light transmittance of the transparent areas (TA), the third scan lines (GL3) may be arranged to be biased toward one side bypassing the center portion of the transparent areas (TA).

[0230] The third scan lines (GL3) can receive scan signals from the first driving circuit (3031) and / or the second driving circuit (3032).

[0231] FIG. 16 is a plan view schematically showing a wiring arrangement structure around a component area of ​​a display panel according to one embodiment of the present invention.

[0232] Referring to FIG. 16, scan lines (GL) for applying scan signals to each subpixel may be arranged in the display area (DA). The scan lines (GL) extend in the x direction and may be arranged approximately parallel to each other. In FIG. 16, only scan lines (GL) adjacent to the component area (CA) are illustrated, and five scan lines (GL) are illustrated, but this is merely for convenience of explanation, and six or more scan lines (GL) may be arranged in the display area (DA). The scan lines (GL) may include a first scan line (GL1), a second scan line (GL2), a third scan line (GL3), and a fourth scan line (GL4). The first scan line (GL1) to the third scan line (GL3) illustrated in FIG. 16 may correspond to the first scan line (GL1) to the third scan line (GL3) described with reference to FIG. 15.

[0233] Each of the first scan lines (GL1) may include a first sub-wire and a second sub-wire spaced apart from each other with a component area (CA) therebetween. For example, the first scan lines (GL1) may include a first-first scan line (GL1-1) and a first-second scan line (GL1-2). The first-first scan line (GL1-1) may include a first sub-wire (GL1-1a) and a second sub-wire (GL1-1b) spaced apart from each other with a component area (CA). The second sub-wire (GL1-1b) of the first-first scan line (GL1-1) may be arranged to coincide with an imaginary line extending in the x direction from the first sub-wire (GL1-1a). Similarly, the first and second scan lines (GL1-2) may include a first sub-wiring (GL1-2a) and a second sub-wiring (GL1-2b) separated by a component area (CA).

[0234] Unlike the first scan line (GL1), the second scan line (GL2) may include a first sub-wiring (GL2a) and a second sub-wiring (GL2b) spaced apart from each other with a component area (CA) therebetween. The second sub-wiring (GL2b) of the second scan line (GL2) may be arranged to coincide with an imaginary line extending in the x direction from the first sub-wiring (GL2a).

[0235] The third scan line (GL3) may be arranged to pass through the component area (CA) differently from the first scan line (GL1) and the second scan line (GL2). The third scan line (GL3) may be formed integrally without any portion being disconnected or separated by the component area (CA). On a plane, the fourth scan line (GL4) may not have any portion that overlaps the component area (CA) differently from the third scan line (GL3).

[0236] In FIG. 16, two first scan lines (GL1), one second scan line (GL2), one third scan line (GL3), and one fourth scan line (DL4) are illustrated, but this is for convenience of explanation, and three or more first scan lines (GL1), two or more second scan lines (GL2), two or more second data lines (DL2), and two or more third data lines (DL3) may be arranged in the display area (DA).

[0237] Second connection wires (GNL) may be arranged in the main display area (MDA) among the display areas (DA). The second connection wires (GNL) may be arranged by bypassing the component area (CA). The second connection wires (GNL) may electrically connect the first sub-wire and the second sub-wire of each of the first scan lines (GL1). For example, the second connection wire (GNL) may include the 2-1 connection wire (GNL1) and the 2-2 connection wire (GNL2). The 2-1 connection wire (GNL1) may electrically connect the first sub-wire (GL1-1a) and the second sub-wire (GL1-1b) of the 1-1 scan line (GL1-1). The 2nd-2 connection wire (GNL2) can electrically connect the 1st sub-wire (GL1-2a) and the 2nd sub-wire (GL1-2b) of the 1st-2 scan line (GL1-2).

[0238] Although not shown, in one embodiment, the second-first connection wire (GNL1) and the second-second connection wire (GNL2) may be arranged in different layers from the first-first scan line (GL1-1) and the first-second scan line (GL1-2). The first-first scan line (GL1-1) and the first-second scan line (GL1-2) may not be connected to each other. The first-first scan line (GL1-1) and the first-second scan line (GL1-2) may receive different signals.

[0239] In one embodiment, the 2-1 connection wire (GNL1) may be electrically connected to one end of the first sub-wire (GL1-1a) of the 1-1 scan line (GL1-1) through a contact hole. The 2-1 connection wire (GNL1) may be electrically connected to one end of the second sub-wire (GL1-1b) of the 1-1 scan line (GL1-1) through a contact hole.

[0240] The same signal can be applied to the first sub-wire (GL1-1a) and the second sub-wire (GL1-1b) of the first-first scan line (GL1-1) through the second-first connection wire (GNL1). Although the description is based on the second-first connection wire (GNL1), the same can be applied to the second-second connection wire (GNL2).

[0241] In one embodiment, the second-first connection wire (GNL1) may be arranged adjacent to the component area (CA), and the second-second connection wire (GNL2) may be arranged further from the component area (CA) than the second-first connection wire (GNL1). However, the present invention is not necessarily limited thereto, and the shapes in which the second-first connection wire and the second-second connection wire (GNL1, GNL2) are arranged may vary.

[0242] The display device according to the present embodiment can be applied to various electronic devices. An electronic device according to the present embodiment can include the display device described above (e.g., the display device of FIG. 1), and in addition to the display device, can further include a module or device having additional functions.

[0243] Fig. 17 is a block diagram illustrating an electronic device according to one embodiment.

[0244] Referring to FIG. 17, an electronic device (1000) according to one embodiment may include a display module (1001), a processor (1002), a memory (1003), and a power module (1004).

[0245] The processor (1002) may include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0246] The memory (1003) may store data information necessary for the operation of the processor (1002) or the display module (1001). When the processor (1002) executes an application stored in the memory (1003), an image data signal and / or an input control signal is transmitted to the display module (1001), and the display module (1001) can process the received signal and output image information through a display screen.

[0247] The power module (1004) may include a power supply module, such as a power adapter or a battery device, and a power conversion module that converts power supplied by the power supply module to generate power required for the operation of the electronic device (1000).

[0248] At least one of the components of the electronic device (1000) described above may be included in the display device according to the embodiments described above. In addition, some of the individual modules functionally included in one module may be included in the display device, while others may be provided separately from the display device. For example, the display device may include a display module (1001), and the processor (1002), memory (1003), and power module (1004) may be provided in the form of other devices within the electronic device (1000) other than the display device.

[0249] In one embodiment, a display module (1001) included in a display device can be driven according to an image data signal and an input control signal received from a processor (1002).

[0250] FIG. 18 is a schematic diagram illustrating an electronic device according to various embodiments.

[0251] Referring to FIG. 18, various electronic devices to which display devices according to embodiments are applied may include not only image display electronic devices such as a smart phone (1000a), a tablet PC (1000b), a laptop (1000c), a TV (1000d), and a desk monitor (1000e), but also wearable electronic devices including display modules such as smart glasses (1000f), a head-mounted display (1000g), and a smart watch (1000h), and vehicle electronic devices (1000i) including display modules such as a CID (Center Information Display) and a room mirror display placed on an instrument panel, center fascia, or dashboard of an automobile.

[0252] The embodiments described herein are to be considered illustrative only and not limiting. The description of features or aspects within each embodiment should generally be considered to apply to other similar features or aspects of other embodiments. While one or more embodiments have been described with reference to the drawings, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the spirit and scope defined by the following claims.

Claims

1. The first area where the first subpixels are arranged, and A substrate including a second region in which subpixel groups including second subpixels and unit units including transparent regions are arranged; First wires each including a first sub-wire and a second sub-wire extending in a first direction and electrically connected to the first sub-pixels and spaced apart with the second region therebetween; First connecting wires arranged in the first region and connecting the first sub-wire and the second sub-wire of each of the first wires; and A display device, comprising second wirings extending in the first direction and electrically connected to the second sub-pixels.

2. In paragraph 1, A display device in which the sub-pixel groups are arranged spaced apart from each other within each of the above units.

3. In paragraph 1, A display device in which the subpixel groups and the transparent areas are alternately arranged in the same row along a second direction perpendicular to the first direction.

4. In paragraph 3, A display device in which the second wiring lines are electrically connected to the second subpixels included in the subpixel groups of the first row of the second region and the first subpixels arranged in the same column as the second subpixels of the first row along the first direction.

5. In paragraph 3, A display device, wherein the total number of second wirings passing through each unit among the second wirings is the same as the total number of second subpixels included in one subpixel group.

6. In paragraph 5, A display device in which the second wiring passing through each of the above units is arranged continuously.

7. In paragraph 5, Each of the above units includes a first subpixel group and a second subpixel group arranged in different rows, Each of the second wiring lines passing through each of the above units, A display device electrically connected to a second subpixel included in the first subpixel group and a second subpixel included in the second subpixel group.

8. In paragraph 1, A display device, wherein at least some of the first connecting wires are arranged in a different layer from the corresponding first wire among the first wires.

9. In paragraph 8, A display device, wherein each of the first connecting wires includes a first portion extending in the first direction, a second portion connected to one end of the first portion and extending in a direction intersecting the first direction, and a third portion connected to the other end of the first portion and extending in a direction intersecting the first direction.

10. In paragraph 9, The first portion of each of the first connecting wires is arranged on the same layer as the corresponding first wire among the first wires, A display device, wherein the second portion and the third portion of each of the first connecting wires are arranged in a different layer from the corresponding first wire and are in contact with the corresponding first wire through contact holes of at least one insulating layer.

11. In paragraph 9, Each of the above first subpixels includes a transistor and a capacitor, The transistor includes a semiconductor layer, a gate electrode overlapping the semiconductor layer, and an electrode layer electrically connected to the semiconductor layer. A display device in which the capacitor has the gate electrode as the lower electrode and includes an upper electrode arranged to overlap the lower electrode.

12. In paragraph 11, A display device, wherein the second portion and the third portion of each of the first connecting wires include the same material as the electrode layer.

13. In paragraph 11, Each of the first subpixels is electrically connected to the transistor and includes a display element having a subpixel electrode, a counter electrode, and an intermediate layer interposed between the subpixel electrode and the counter electrode, A display device further comprising a contact metal layer connected to the electrode layer at the bottom and connected to the subpixel electrode at the top.

14. In paragraph 13, A display device, wherein the first portion of each of the first connecting wires comprises the same material as the contact metal layer.

15. In paragraph 1, A display device, wherein the first and second wires are data lines.

16. In paragraph 1, Third wirings each including a first sub-wiring and a second sub-wiring that extend in a second direction perpendicular to the first direction and are electrically connected to the first sub-pixels and are spaced apart from each other with the second region therebetween; and A display device further comprising fourth wiring lines extending in the second direction and electrically connected to the second sub-pixels.

17. In paragraph 16, A display device further comprising second connecting wires arranged in the first region and connecting the first sub-wire and the second sub-wire included in each of the third wires among the third wires.

18. In paragraph 16, A display device in which the third and fourth wirings are scan lines.

19. In paragraph 1, A display device further comprising a component overlapping the second region.

20. In paragraph 19, The above component is a display device including a camera or a sensor.

21. Display device; and a component overlapping the above display device; The above display device, The first area where the first subpixels are arranged, and A substrate including a second region in which subpixel groups including second subpixels and unit units including transparent regions are arranged; First wires each including a first sub-wire and a second sub-wire extending in a first direction and electrically connected to the first sub-pixels and spaced apart with the second region therebetween; First connecting wires arranged in the first region and connecting the first sub-wire and the second sub-wire of each of the first wires; and An electronic device comprising second wirings extending in the first direction and electrically connected to the second subpixels.

22. In paragraph 21, Within each of the above units, the sub-pixel groups are arranged spaced apart from each other, An electronic device wherein the subpixel groups and the transparent regions are alternately arranged in the same row along a second direction perpendicular to the first direction.

23. In paragraph 21, An electronic device, wherein the total number of second wirings passing through each unit among the second wirings is equal to the total number of second subpixels included in one subpixel group.

Images