Display substrate, display panel, and display device

Abstract

Provided are a display substrate (100), a display panel, and a display device. The display substrate (100) comprises: a base substrate (1), and a first conductive layer (11), a first insulating layer (31), a second conductive layer (12), a second insulating layer (32) and a third conductive layer (13) sequentially away from the base substrate (1), wherein the first conductive layer (11) comprises a plurality of data lines (DL) and electrode lines (CL) alternately arranged in a first direction and extending in a second direction, and a first electrode (S1) and a second electrode (D1) of a thin film transistor; the second conductive layer (12) comprises a common electrode (2) and a plurality of protective electrode blocks (120), the common electrode (2) comprises a plurality of openings (21), and the orthographic projection of the at least one protective electrode block (120) on the base substrate (1) falls within the orthographic projection of at least one opening (21) of the common electrode (2) on the base substrate (1); the third conductive layer (13) comprises a plurality of pixel electrodes (4), and the pixel electrodes (4) are connected to the protective electrode blocks (120) and the second electrode (D1) of the thin film transistor by means of first via holes (VH1); and the overlapping portion between the orthographic projections of the second electrode (D1) of the thin film transistor and the protective electrode blocks (120) on the base substrate (1) at least partially overlaps with the orthographic projection of the first via holes (VH1) on the base substrate (1).

Description

Display substrate, display panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically to a display substrate, a display panel, and a display device. Background Technology

[0002] Liquid crystal displays (LCDs) are widely used due to their advantages such as small size, low power consumption, and no radiation. As display product resolutions increase, pixel sizes decrease, and aperture ratios also shrink. Optimizing pixel design and improving pixel aperture ratios are therefore crucial for high-resolution display products.

[0003] The information disclosed in this section is only for understanding the background of the technical concept of this disclosure, and therefore may contain information that does not constitute prior art.

[0004] Summary of the Invention

[0005] In one aspect, a display substrate is provided, wherein the display substrate includes a plurality of sub-pixels arranged in an array along a first direction and a second direction, the first direction and the second direction intersecting; the display substrate includes: a substrate; a first conductive layer located on one side of the substrate, the first conductive layer including a plurality of data lines and electrode lines alternately arranged along the first direction, each of the data lines and the electrode lines extending along the second direction, each column of sub-pixels located between adjacent data lines and electrode lines; the first conductive layer further includes a first electrode and a second electrode of a thin-film transistor, wherein the data lines are connected to the first electrode of the thin-film transistor, and the second electrode of the thin-film transistor is located between adjacent data lines and electrode lines; a first insulating layer located on the side of the first conductive layer away from the substrate; a second conductive layer located on the side of the first insulating layer away from the substrate, the second conductive layer including a common electrode and a plurality of protective electrode blocks, the common electrode including The system includes multiple openings, wherein the orthographic projection of at least one of the protective electrode blocks on the substrate falls within the orthographic projection of at least one opening of the common electrode on the substrate; a second insulating layer located on the side of the second conductive layer away from the substrate; and a third conductive layer located on the side of the second insulating layer away from the substrate, the third conductive layer including multiple pixel electrodes, one pixel electrode being disposed in the region of each sub-pixel, wherein the pixel electrode is connected to the protective electrode block through a first via; and the pixel electrode is connected to the second electrode of the thin-film transistor through the first via, wherein the orthographic projection of the second electrode of the thin-film transistor on the substrate at least partially overlaps with the orthographic projection of the protective electrode block on the substrate; the overlapping portion of the orthographic projections of the second electrode of the thin-film transistor and the protective electrode block on the substrate at least partially overlaps with the orthographic projection of the first via on the substrate.

[0006] According to some exemplary embodiments, the first via includes a first sub-via and a second sub-via, wherein the first sub-via and the second sub-via are arranged adjacent to each other in a first direction; the first sub-via penetrates the first insulating layer and the second insulating layer, and the pixel electrode is connected to the second electrode of the thin film transistor through the first sub-via; the second sub-via penetrates the second insulating layer, and the pixel electrode is connected to the protection electrode block through the second sub-via.

[0007] According to some exemplary embodiments, the first sub-via has a first width in a first direction, the second sub-via has a second width in a first direction, and the first width is smaller than the second width.

[0008] According to some exemplary embodiments, the orthographic projection of the second electrode of the thin-film transistor on the substrate includes a first side and a second side extending along a second direction; the orthographic projection of the first via on the substrate includes a third side and a fourth side extending along a second direction; and the orthographic projection of the protection electrode block on the substrate includes a fifth side and a sixth side extending along a second direction, wherein the first side, the third side, the fifth side, the second side, the fourth side, and the sixth side are sequentially spaced apart in a first direction.

[0009] According to some exemplary embodiments, a first preset distance is provided between the first side and the third side.

[0010] According to some exemplary embodiments, a second preset distance is provided between the fifth side and the second side.

[0011] According to some exemplary embodiments, a third preset distance is provided between the fourth side and the sixth side.

[0012] According to some exemplary embodiments, the first insulating layer includes a first portion adjacent to the first sub-via and the orthographic projection of the first portion on the substrate does not overlap with the orthographic projection of the second sub-via on the substrate, wherein the first portion includes a first sidewall near the first sub-via, the first sidewall having a first slope angle; the second insulating layer includes a second portion adjacent to the first sub-via and the orthographic projection of the second portion on the substrate does not overlap with the orthographic projection of the second sub-via on the substrate, the second portion including a second sidewall near the first sub-via, the second sidewall having a second slope angle, wherein the first slope angle is greater than the second slope angle.

[0013] According to some exemplary embodiments, the first insulating layer further includes a third portion adjacent to the first sub-via, wherein the orthographic projection of the third portion on the substrate falls within the orthographic projection of the second electrode of the thin-film transistor on the substrate, and the orthographic projection of the third portion on the substrate falls within the orthographic projection of the protective electrode block on the substrate, wherein the third portion includes a third sidewall away from the first sub-via, the third sidewall having a third slope angle; the protective electrode block includes a fourth portion, wherein the orthographic projection of the fourth portion on the substrate falls within the orthographic projection of the third portion of the first insulating layer on the substrate, the fourth portion of the protective electrode block including a fourth sidewall away from the first sub-via, the fourth sidewall having a fourth slope angle, wherein the third slope angle is greater than or equal to twice the fourth slope angle.

[0014] According to some exemplary embodiments, the second insulating layer further includes a fifth portion, the fifth portion being adjacent to the second sub-via and the orthographic projection of the fifth portion on the substrate at least partially overlapping the orthographic projection of the protective electrode block on the substrate, wherein the fifth portion includes a fifth sidewall near the second sub-via, the fifth sidewall having a fifth slope angle greater than or equal to 30°.

[0015] According to some exemplary embodiments, the display substrate further includes: a third insulating layer located on the side of the first conductive layer near the substrate; and a fourth conductive layer located on the side of the third insulating layer near the substrate, the fourth conductive layer including a gate electrode of the thin-film transistor and a gate line connected to the gate electrode, the gate line including a widened portion and a connecting portion, the gate electrode being located in the widened portion, the orthographic projection of the second electrode of the thin-film transistor on the substrate at least partially overlapping the orthographic projection of the widened portion on the substrate; and the orthographic projection of the second electrode of the thin-film transistor on the substrate not overlapping the orthographic projection of the connecting portion on the substrate.

[0016] According to some exemplary embodiments, the orthographic projection of the protective electrode block on the substrate at least partially overlaps with the orthographic projection of the widened portion on the substrate; the orthographic projection of the protective electrode block on the substrate at least partially overlaps with the orthographic projection of the connecting portion on the substrate.

[0017] According to some exemplary embodiments, the display substrate includes multiple gate lines extending along the first direction and located between adjacent rows of sub-pixel regions; the pixel electrode includes multiple pixel electrode strips located in the region of the sub-pixel and arranged at intervals, the pixel electrode further includes a first connection portion and a second connection portion, the first connection portion is located at one end of the multiple pixel electrode strips and is connected to all of the multiple pixel electrode strips, the second connection portion is located at the other end of the multiple pixel electrode strips and is connected to all of the multiple pixel electrode strips, the first connection portion is connected to the second electrode of the corresponding thin film transistor through the first via, and the orthographic projection of the second connection portion on the substrate at least partially overlaps with the orthographic projection of the gate line on the corresponding side on the substrate.

[0018] According to some exemplary embodiments, the display substrate includes multiple gate lines extending along the first direction. The gate lines are located between adjacent rows of sub-pixel regions, and two gate lines are disposed between each pair of adjacent rows of sub-pixel regions. The multiple sub-pixels include multiple rows of sub-pixels located in the i-th row and the (i+1)-th row, and multiple columns of sub-pixels located in the j-th column and the (j+1)-th column, respectively, where i is greater than or equal to 1 and j is greater than or equal to 1. The gate lines include a first gate line and a second gate line located between the regions where the i-th row of sub-pixels and the regions where the (i+1)-th row of sub-pixels are located. The first gate line is connected to the gate electrode of the thin-film transistor of the sub-pixel in the i-th row and the (j+1)-th column; the second gate line is connected to the gate electrode of the thin-film transistor of the sub-pixel in the (i+1)-th row and the (j)-th column.

[0019] According to some exemplary embodiments, the first via includes a seventh side extending along a first direction; the seventh side in the i-th row of sub-pixels is located between the first gate line and the second gate line, and a fourth preset distance is provided between the seventh side and the second gate line.

[0020] According to some exemplary embodiments, the first via further includes an eighth side extending along a first direction, the orthographic projection of the eighth side on the substrate falling within the orthographic projection of the gate line on the substrate; the protective electrode block includes a ninth side extending along the first direction, the orthographic projection of the ninth side on the substrate at least partially overlapping the orthographic projection of the widened portion of the gate line on the substrate, wherein a fifth preset distance is provided between the eighth side and the ninth side.

[0021] According to some exemplary embodiments, the orthographic projection of the protective electrode block on the substrate at least partially overlaps with the orthographic projection of the gate line on the substrate, wherein the protective electrode block includes a protrusion protruding relative to the gate line in a second direction, the protrusion being located between two adjacent gate lines, wherein the protrusion has a first protrusion distance in the second direction.

[0022] According to some exemplary embodiments, the display substrate includes a first sub-pixel located in the i-th row and j-th column, a second sub-pixel located in the i-th row and j+1-th column, and a third sub-pixel located in the i-th row and j+2-th column, wherein the second sub-pixel includes a second sub-pixel electrode; the display substrate also includes a first data line located between the j-th column sub-pixel and the j+1-th column sub-pixel, and a first electrode line located between the j+1-th column sub-pixel and the j+2-th column sub-pixel, wherein the orthographic projection of the second sub-pixel electrode on the substrate at least partially overlaps with the orthographic projection of the first electrode line on the substrate.

[0023] According to some exemplary embodiments, the data line includes a main body and a connecting portion, the connecting portion being connected to a first electrode of the thin-film transistor, wherein the connecting portion extends along a second direction, and the orthographic projection of the connecting portion on the substrate at least partially overlaps with the orthographic projection of the main body on the substrate; the connecting portion has a third width in a first direction, the main body has a fourth width in the first direction, and the ratio of the third width to the fourth width is between 0.8 and 1.2.

[0024] According to some exemplary embodiments, the data line includes a main body and a connecting portion, the connecting portion being connected to a first electrode of the thin-film transistor, wherein the connecting portion protrudes a second protrusion distance relative to the main body in a first direction, the main body having a fourth width in the first direction, and the second protrusion distance being greater than the fourth width.

[0025] According to some exemplary embodiments, the orthographic projection of the common electrode on the substrate at least partially overlaps with the orthographic projection of the gate line on the substrate.

[0026] According to some exemplary embodiments, the display substrate includes multiple gate lines extending along the first direction. The gate lines are located between adjacent rows of sub-pixel regions. Each gate line includes a widened portion and a connecting portion. Two gate lines are disposed between each pair of adjacent rows of sub-pixel regions. The multiple sub-pixels include multiple rows of sub-pixels located in the i-th row and the (i+1)-th row, respectively, where i is greater than or equal to 1. The gate lines include a first gate line and a second gate line located between the regions where the i-th row of sub-pixels is located and the regions where the (i+1)-th row of sub-pixels is located. The orthographic projection of the common electrode on the substrate and the orthographic projection of the widened portion of the first gate line on the substrate at least partially overlap. The overlapping portion of the projections of the common electrode and the widened portion of the first gate line has a first overlap width in a second direction, where the first overlap width is greater than or equal to 0.85 micrometers.

[0027] According to some exemplary embodiments, the orthographic projection of the common electrode on the substrate and the orthographic projection of the connection portion of the second gate line on the substrate at least partially overlap, and the overlapping portion of the projections of the common electrode and the connection portion of the second gate line has a second overlap width in a second direction, the second overlap width being greater than or equal to 0.5 micrometers.

[0028] In another aspect, a display panel is provided, the display panel comprising a display substrate as described in any of the preceding claims.

[0029] In another aspect, a display device is provided, the display device comprising a display substrate as described in any of the preceding claims or a display panel as described above. Attached Figure Description

[0030] The foregoing contents, as well as other objects, features, and advantages of this disclosure, will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0031] Figure 1 is a partial plan view of a display substrate according to some illustrative embodiments of the present disclosure;

[0032] Figure 2 is an enlarged view of the dashed box area in Figure 1;

[0033] Figure 3A is a cross-sectional view taken along line AA' in Figure 2;

[0034] Figure 3B is a cross-sectional view taken along line BB' in Figure 2;

[0035] Figure 4 is a plan view of a display substrate according to some illustrative embodiments of the present disclosure;

[0036] Figure 5A is a partial plan view of a display substrate according to some exemplary embodiments of the present disclosure; Figure 5B is a cross-sectional view taken along line A1-A1' in Figure 5A; Figure 5C is a cross-sectional view taken along line B1-B1' in Figure 5A; Figure 5D is a partial plan view of a display substrate according to some other exemplary embodiments of the present disclosure; Figure 5E is a cross-sectional view taken along line A2-A2' in Figure 5D; Figure 5F is a cross-sectional view taken along line B2-B2' in Figure 5D; Figure 5G is a partial plan view of a display substrate according to some further exemplary embodiments; Figure 5H is a cross-sectional view taken along line A3-A3' in Figure 5G; Figure 5I is a cross-sectional view taken along line B3-B3' in Figure 5G.

[0037] Figure 6 is a partial plan view of a display substrate according to some illustrative embodiments of the present disclosure;

[0038] Figure 7 shows a partial planar schematic diagram of the fourth conductive layer in Figure 6;

[0039] Figure 8 shows a partial planar schematic diagram of the third insulating layer in Figure 6;

[0040] Figure 9 shows a partial planar schematic diagram of the first conductive layer in Figure 6;

[0041] Figure 10 shows a partial planar schematic diagram of the second conductive layer in Figure 6;

[0042] Figure 11 shows the multiple vias in Figure 6;

[0043] Figure 12 shows a partial planar schematic diagram of the third conductive layer in Figure 6;

[0044] Figures 13A and 13B are both magnified schematic diagrams of the dashed area S in Figure 6.

[0045] Figure 14 shows a schematic diagram of a cross section taken along the center line CC' of Figure 13A;

[0046] Figure 15 shows a schematic diagram of a cross section taken along the center line DD' in Figure 13A;

[0047] Figure 16 is a SEM image of a display substrate along a first direction in the first via region according to some illustrative embodiments of the present disclosure;

[0048] Figure 17 is a partial plan view of a display substrate according to some illustrative embodiments of the present disclosure;

[0049] Figure 18 is a partial plan view of a display substrate according to some illustrative embodiments of the present disclosure;

[0050] Figure 19A is a schematic cross-sectional view of a display substrate provided according to some embodiments of the present disclosure, taken along line EE' in Figure 17; Figure 19B is a schematic cross-sectional view of a display substrate provided according to some embodiments of the present disclosure, taken along line FF' in Figure 17; Figure 19C is a schematic cross-sectional view of a display substrate provided according to some embodiments of the present disclosure, taken along line GG' in Figure 18; Figure 19D is a schematic cross-sectional view of a display substrate provided according to some embodiments of the present disclosure, taken along line HH' in Figure 18.

[0051] Figure 20 is a schematic diagram of the structure of a display device provided according to some embodiments of the present disclosure;

[0052] Figure 21 is a schematic diagram of the structure of a display device provided according to some embodiments of the present disclosure.

[0053] It should be noted that, for clarity, the dimensions of layers, structures, or regions in the accompanying drawings used to describe embodiments of the present invention may be enlarged or reduced; that is, these drawings are not drawn to actual scale. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0055] It should be noted that, for clarity and / or descriptive purposes, the dimensions and relative dimensions of components may be enlarged in the accompanying drawings. Therefore, the dimensions and relative dimensions of the individual components are not necessarily limited to those shown in the drawings. In the specification and accompanying drawings, the same or similar reference numerals indicate the same or similar parts.

[0056] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0057] In this document, unless otherwise specified, directional terms such as "up," "down," "left," "right," "inner," and "outer" are used to indicate orientation or positional relationships based on the accompanying drawings, and are used only for the convenience of describing this disclosure, and are not intended to indicate or imply that the device, element, or component referred to must have a specific orientation, or be constructed or operated in a specific orientation. It should be understood that when the absolute position of the described object changes, the relative positional relationships they represent may also change accordingly. Therefore, these directional terms should not be construed as limitations on this disclosure.

[0058] It should be noted that in this paper, "same layer" refers to a layer structure formed by using the same film deposition process to form a film layer for a specific pattern, and then using the same mask to pattern that film layer in a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. That is, multiple elements, components, structures, and / or portions located in the "same layer" are made of the same material and formed by the same single patterning process. Typically, multiple elements, components, structures, and / or portions located in the "same layer" have approximately the same thickness.

[0059] Those skilled in the art will understand that, unless otherwise stated herein, the terms “height” or “thickness” refer to the dimensions along the surface of each film layer disposed perpendicular to the display substrate, i.e., the dimensions along the light-emitting direction of the display substrate, or the dimensions along the normal direction of the display device.

[0060] In this document, the directional terms "first direction" and "second direction" are used to describe different directions along a pixel unit, such as the vertical and horizontal directions of the pixel unit, or the row and column directions of a subpixel arrangement. It should be understood that such representations are merely exemplary descriptions and not limitations of this disclosure.

[0061] In this document, the term "transistor" can refer to a bipolar junction transistor (BJT), a thin-film transistor (TFT), a field-effect transistor (FET), or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of a transistor other than the control terminal, one terminal is referred to as the first terminal, and the other as the second terminal. In actual operation, when the transistor is a TFT or a FET, the first terminal can be the drain, and the second terminal can be the source; alternatively, the first terminal can be the source, and the second terminal can be the drain.

[0062] An LCD (Liquid Crystal Display) is a flat, ultra-thin display device, mainly consisting of a backlight module and a display panel. The backlight module provides light to the display panel, which then displays the image. In practical applications, only a small portion of the light emitted by the backlight module passes through the display panel, resulting in low light utilization. To ensure high brightness, the LCD requires significant power consumption. Pixels on the display panel include light-transmitting and opaque areas. The light-transmitting area includes the region where the pixel electrodes are located, while the opaque area includes the regions containing data lines, gate lines, and thin-film transistors. The ratio of the light-transmitting area to the pixel area is called the aperture ratio. The higher the aperture ratio, the higher the light utilization rate of the LCD. Therefore, increasing the pixel aperture ratio can improve light utilization, enabling the LCD to achieve high brightness with lower power consumption.

[0063] However, as display product resolutions increase and pixel sizes decrease, aperture ratios also decrease. Factors affecting aperture ratio include gate linewidth, data linewidth, black matrix linewidth, and pixel design structure. In high-resolution products, with small pixel pitch, gate linewidth, data linewidth, and black matrix linewidth significantly impact aperture ratio. The limits for gate linewidth and pitch, and data linewidth and pitch, are constrained by production line processes and equipment, and cannot be reduced indefinitely. Black matrix linewidth must consider cell alignment accuracy and light leakage.

[0064] Some exemplary embodiments of this disclosure provide a display substrate, the display substrate including a plurality of sub-pixels arranged in an array along a first direction and a second direction, the first direction and the second direction intersecting; the display substrate includes: a substrate; a first conductive layer located on one side of the substrate, the first conductive layer including a plurality of data lines and electrode lines arranged alternately along the first direction, each data line and electrode line extending along the second direction, each column of sub-pixels located between adjacent data lines and electrode lines; the first conductive layer further includes a first electrode and a second electrode of a thin-film transistor, wherein the data lines are connected to the first electrode of the thin-film transistor, and the second electrode of the thin-film transistor is located between adjacent data lines and electrode lines; a first insulating layer located on the first conductive layer away from the substrate. The substrate has a second conductive layer located on the side of the first insulating layer away from the substrate. The second conductive layer includes a common electrode and multiple protective electrode blocks. The common electrode includes multiple openings, wherein the orthographic projection of at least one protective electrode block onto the substrate falls within the orthographic projection of at least one opening of the common electrode onto the substrate. A second insulating layer is also located on the side of the second conductive layer away from the substrate. A third conductive layer is located on the side of the second insulating layer away from the substrate. The third conductive layer includes multiple pixel electrodes, with one pixel electrode disposed within the region of each sub-pixel. The pixel electrode is connected to the protective electrode block via a first via. The pixel electrode is also connected to the second electrode of a thin-film transistor via the first via. The orthographic projection of the second electrode of the thin-film transistor onto the substrate at least partially overlaps with the orthographic projection of the protective electrode block onto the substrate. The overlapping portion of the orthographic projections of the second electrode of the thin-film transistor and the protective electrode block onto the substrate at least partially overlaps with the orthographic projection of the first via onto the substrate.

[0065] Within the limited wiring space of a high-resolution display substrate, by employing a semi-drilled overlapping method at the second electrode of the thin-film transistor and adding a protective electrode block, the wiring area of ​​the second electrode of the thin-film transistor can be reduced while avoiding the insulating layer from being punctured through the gate insulating layer, which would cause the pixel electrode to connect to the gate line and result in display defects. Simultaneously, by adopting a top-pixel design and optimizing the wiring design, the black matrix linewidth can be reduced, effectively increasing the pixel aperture ratio, effectively improving the storage capacitance, and optimizing the display effect. Furthermore, the display substrate in this embodiment can utilize existing mature process flows without increasing production and process costs.

[0066] Figures 1-4 show schematic diagrams of a display substrate according to an embodiment of the present disclosure, wherein Figure 1 is a partial plan view of the display substrate, Figure 2 is an enlarged view of the dashed frame portion of Figure 1, Figure 3A is a cross-sectional view taken along line AA' in Figure 2, Figure 3B is a cross-sectional view taken along line BB' in Figure 2, and Figure 4 is a partial plan view of the display substrate.

[0067] As shown in the figure, a display substrate according to an embodiment of the present disclosure may include: a substrate 1 and a plurality of sub-pixels P located on the substrate 1 (as shown in Figure 4). The plurality of sub-pixels P are arranged in an array on the substrate 1, that is, including multiple rows of sub-pixels P and multiple columns of sub-pixels P. In this document, for ease of description, the horizontal direction in Figure 1 is referred to as the first direction X (row direction), and the vertical direction in Figure 1 is referred to as the second direction Y (column direction). In Figure 1, two adjacent sub-pixels P along the row direction are schematically shown, and for ease of description, they can be referred to as sub-pixel P01 and sub-pixel P02.

[0068] Specifically, the display substrate may include multiple gate lines GL extending along the row direction X, multiple data lines DL extending along the column direction Y, and multiple electrode lines CL extending along the column direction. For example, the multiple data lines DL and the multiple electrode lines CL are arranged alternately in the row direction, and both the multiple data lines DL and the multiple electrode lines CL intersect with the multiple gate lines GL respectively to define multiple sub-pixels P.

[0069] For example, the data line DL can be connected to at least some of the transistors in the driving circuit to provide data signals to the corresponding sub-pixels.

[0070] For example, the electrode line CL is located between two adjacent sub-pixel regions, so that metal traces (data lines DL or electrode lines CL) are provided between every two adjacent columns of sub-pixel regions. During the fabrication process, etching uniformity can be guaranteed and the etching effect can be improved.

[0071] In some embodiments, the display substrate includes a common electrode, and an electrode line CL can be connected to the common electrode to provide a common electrode signal.

[0072] Optionally, Figure 4 shows a partial plan view of the display substrate in Figure 1, schematically illustrating multiple sub-pixels P located on the substrate 1. As shown in Figure 4, a dual-gate-driven display substrate is illustrated. Specifically, the display substrate includes multiple gate lines extending along the first direction X. The gate lines are located between adjacent rows of sub-pixel regions, with two gate lines disposed between each pair of adjacent rows of sub-pixel regions. For example, the multiple sub-pixels include multiple rows of sub-pixels located in the i-th row and the (i+1)-th row, and multiple columns of sub-pixels located in the j-th column and the (j+1)-th column, where i is greater than or equal to 1 and j is greater than or equal to 1. The gate lines include a first gate line GL1 and a second gate line GL2 located between the regions of the i-th row of sub-pixels and the (i+1)-th row of sub-pixels. The first gate line GL1 is connected to the gate electrode of the thin-film transistor of the sub-pixel in the i-th row and the (j+1)-th column; the second gate line GL2 is connected to the gate electrode of the thin-film transistor of the sub-pixel in the (i+1)-th row and the (j)-th column. Adjacent sub-pixels P01 and P02 in the row direction X can form a sub-pixel group. A data line DL is set between two adjacent sub-pixel groups in the row direction. An electrode line CL is set between two sub-pixels P01 and P02 within a sub-pixel group.

[0073] Referring to Figures 3A and 3B, the display substrate may further include a common electrode 2 and a pixel electrode 4 disposed on the substrate 1. The common electrode 2 cooperates with the pixel electrode 4 to form an electric field that drives the liquid crystal molecules to deflect, thereby achieving the display of a specific grayscale. Specifically, the display substrate may further include an insulating layer 32 disposed on the substrate 1 and located between the common electrode 2 and the pixel electrode 4. For example, the common electrode 2 in each sub-pixel of the display substrate may be electrically connected to each other, and the pixel electrode 4 in each sub-pixel of the display substrate may be independent of each other.

[0074] In the embodiments shown in Figures 1-4, the common electrode 2, the insulating layer 32, and the pixel electrode 4 are sequentially disposed on the substrate 1 in a direction away from the substrate 1, that is, the common electrode 2 is below and the pixel electrode 4 is above. For example, the common electrode 2 is a planar electrode. The common electrode 2 in a sub-pixel group can be formed as a single planar electrode. The orthographic projection of the common electrode 2 in a sub-pixel group onto the substrate 1 can cover two sub-pixels P1 and P2, and the orthographic projection of the common electrode 2 in a sub-pixel group onto the substrate 1 can also cover the orthographic projection of the electrode line CL in a sub-pixel group onto the substrate 1. As another example, the pixel electrode 4 is a comb-shaped electrode with multiple slits 42, that is, the pixel electrode includes multiple pixel electrode strips 41 located in the area where the sub-pixel is located and arranged at intervals. Exemplarily, the display substrate is designed with the common electrode above and the pixel electrode below. In the display substrate with the common electrode above and the pixel electrode below, the arrangement of the pixel electrode can be similar to the pixel arrangement of the display substrate with the common electrode below and the pixel electrode above in the above embodiments. To prevent light leakage from the display substrate, a black matrix is ​​also provided on the side of the common electrode away from the substrate. The black matrix needs to have a sufficient area to cover part of the transistors or signal lines in the underlying driving circuit layer, such as gate lines, data lines, and electrode lines, thereby reducing electrical light leakage.

[0075] Because the common electrode is positioned above the pixel electrode, the distance between the common electrode and components such as transistors, data lines, and electrode lines located on the side of the common electrode closer to the substrate is relatively large in the light emission direction. This results in a weak shielding effect of the potential on the common electrode on the signals of the transistors, data lines, and electrode lines below. In this situation, to prevent electrical light leakage, the width of the black matrix needs to be increased to ensure that the black matrix has sufficient coverage width over at least a portion of the transistors, data lines, and electrode lines below, thereby reducing electrical light leakage. For example, the distance between the boundary of the orthographic projection of the black matrix on the substrate and the boundary of at least a portion of the corresponding gate line should be greater than or equal to 5 micrometers to ensure sufficient shielding effect and reduce electrical light leakage.

[0076] In a display substrate with the common electrode on top and the pixel electrode on the bottom, electrical light leakage can be reduced and the width of the black matrix can be decreased by increasing the width of the gate line wrapping the active layer in the corresponding transistor. At the same time, the leakage current in the transistor of the display substrate can also be reduced in high brightness or high temperature environments.

[0077] Figure 5A is a partial plan view of a display substrate according to some exemplary embodiments of the present disclosure; Figure 5B is a cross-sectional view taken along line A1-A1' in Figure 5A; Figure 5C is a cross-sectional view taken along line B1-B1' in Figure 5A; Figure 5D is a partial plan view of a display substrate according to some other exemplary embodiments of the present disclosure; Figure 5E is a cross-sectional view taken along line A2-A2' in Figure 5D; Figure 5F is a cross-sectional view taken along line B2-B2' in Figure 5D; Figure 5G is a partial plan view of a display substrate according to some further exemplary embodiments of the present disclosure; Figure 5H is a cross-sectional view taken along line A3-A3' in Figure 5G; Figure 5I is a cross-sectional view taken along line B3-B3' in Figure 5G.

[0078] In some display substrates where the common electrode is on top and the pixel electrode is on the bottom, referring to Figures 5A-5I, the orthographic projection of the active layer on the substrate falls into the orthographic projection of the gate line on the substrate. The distance m01 between the boundary of the orthographic projection of the gate line on the substrate and the boundary of the orthographic projection of the adjacent corresponding active layer on the substrate is approximately 2.75 micrometers.

[0079] For example, referring to Figures 5A-5C, the angle between the orthogonal projection of the data line DL or electrode line CL onto the substrate and the orthogonal projection of the gate line GL onto the substrate can be approximately 90°. For example, the width d01 of a portion of the data line DL or electrode line CL in the first direction X is approximately 2.8 micrometers. The spacing M11 between one of the data line DL or electrode line CL and the pixel electrode 4 can be approximately 4.22 micrometers. The common electrode 2 includes a first sub-part 201 of the common electrode that overlaps with the projection of the data line DL or electrode line CL. The width d10 of the orthogonal projection of the first sub-part 201 of the common electrode onto the substrate in the first direction is approximately 7.4 micrometers. The protrusion distance M10 of the first sub-part 201 of the common electrode relative to one of the corresponding data line DL or electrode line CL in the first direction X can be approximately 2.55 micrometers. By increasing the width of the first sub-part of the common electrode at the crossing point in the first direction X, the yield can be improved. Continuing to refer to Figures 5A-5C, the display substrate also includes a black matrix BM. The width of the black matrix BM needs to take into account the cell accuracy and light leakage effects. To ensure sufficient light-shielding effect of the black matrix, its orthographic projection onto the substrate needs to cover at least a portion of the data lines, electrode lines, and gate lines. For example, the width d11 of the orthographic projection of the black matrix BM onto the substrate in the first direction is approximately 4.5 micrometers, and its width d12 in the second direction is approximately 28.1 micrometers.

[0080] For example, the gate line GL includes a widened portion GL11 and a connecting portion GL12. The width d13 of the widened portion GL11 in the second direction Y is approximately 9.1 micrometers, and the width d14 of the connecting portion GL12 in the second direction Y is approximately 3 micrometers. For example, the minimum spacing M12 between two adjacent gate lines in the second direction Y is greater than or equal to 4 micrometers. The common electrode 2 protrudes approximately 1.55 micrometers relative to the corresponding gate line in the second direction Y by a distance M13. The spacing M14 between the gate line and the corresponding pixel electrode in the second direction is approximately 2.4 micrometers. The black matrix BM protrudes approximately 5 micrometers relative to the corresponding gate line widened portion GL11 in the second direction by a distance M15. With the above design, the aperture ratio of the display panel can reach approximately 44.8%.

[0081] For example, referring to Figures 5D-5F, the angle between the orthographic projection of the data line DL or electrode line CL onto the substrate and the orthographic projection of the gate line GL onto the substrate can be greater than 90° or less than 90°. The pixel electrode can be substantially parallel to the data line DL. The spacing M11 between one of the data line DL or electrode line CL and the pixel electrode 4 can be between 3.5 micrometers and 4.22 micrometers. The common electrode 2 includes a first sub-part 201 of the common electrode that overlaps with the projection of the data line DL or electrode line CL. The width d10 of the orthographic projection of the first sub-part 201 of the common electrode onto the substrate in the first direction is approximately 6.9 micrometers. The protrusion distance M10 of the first sub-part 201 of the common electrode relative to one of the corresponding data line DL or electrode line CL in the first direction X can be approximately 2.48 micrometers. For example, in order to ensure sufficient light-shielding effect of the black matrix, the width d11 of the orthographic projection of the black matrix BM onto the substrate in the first direction is approximately 4.5 micrometers, and the width d12 in the second direction is approximately 28.1 micrometers.

[0082] For example, the gate line GL includes a widened portion GL11 and a connecting portion GL12. The width d13 of the widened portion GL11 in the second direction Y is approximately 9.1 micrometers, and the width d14 of the connecting portion GL12 in the second direction Y is approximately 3 micrometers. For example, the minimum spacing M12 between two adjacent gate lines in the second direction Y is greater than or equal to 4 micrometers. The common electrode 2 protrudes approximately 1.55 micrometers relative to the corresponding gate line in the second direction Y by a distance M13. The spacing M14 between the gate line and the corresponding pixel electrode in the second direction is approximately 2.4 micrometers. The black matrix BM protrudes approximately 5 micrometers relative to the corresponding gate line widened portion GL11 in the second direction by a distance M15. With the above design, the aperture ratio of the display panel can be between 43.4% and 44.6%.

[0083] For example, the width of the gate lines enclosing the active layer can be reduced, thereby increasing the aperture ratio of the display substrate.

[0084] For display substrates with lower resolution requirements, the trace space between adjacent data lines DL and electrode lines CL can be increased. For example, referring to Figures 5G-5I, the spacing between adjacent data lines DL and electrode lines CL can be increased, thereby improving the aperture ratio. Exemplarily, the spacing M11 between one of the data lines DL or electrode lines CL and the pixel electrode can be approximately 4.5 micrometers. The common electrode includes a first sub-part 201 that overlaps with the projection of the data lines DL or electrode lines CL. The width d10 of the orthogonal projection of the first sub-part 201 on the substrate in a first direction is approximately 6.9 micrometers. The protrusion distance M10 of the first sub-part 201 relative to one of the corresponding data lines DL or electrode lines CL in the first direction X can be approximately 3.4 micrometers. Exemplarily, to ensure sufficient light-shielding effect of the black matrix, the width d11 of the orthogonal projection of the black matrix BM on the substrate in the first direction is approximately 4.5 micrometers, and the width d12 in the second direction is approximately 28.1 micrometers.

[0085] For example, the gate line GL includes a widened portion GL11 and a connecting portion GL12. The width d13 of the widened portion GL11 in the second direction Y is approximately 9.1 micrometers, and the width d14 of the connecting portion GL12 in the second direction Y is approximately 3 micrometers. For example, the minimum spacing M12 between two adjacent gate lines in the second direction Y is greater than or equal to 4 micrometers. The common electrode 2 protrudes approximately 1.55 micrometers relative to the corresponding gate line in the second direction Y by a distance M13. The spacing M14 between the gate line and the corresponding pixel electrode in the second direction is approximately 2.4 micrometers. The black matrix BM protrudes approximately 5 micrometers relative to the corresponding gate line widened portion GL11 in the second direction by a distance M15. With the above design, the aperture ratio of the display panel can be approximately 46.5%.

[0086] Figure 6 is a partial planar schematic diagram of a display substrate according to some illustrative embodiments of the present disclosure; Figure 7 shows a partial planar schematic diagram of the fourth conductive layer in Figure 6; Figure 8 shows a partial planar schematic diagram of the third insulating layer in Figure 6; Figure 9 shows a partial planar schematic diagram of the first conductive layer in Figure 6; Figure 10 shows a partial planar schematic diagram of the second conductive layer in Figure 6; Figure 11 shows a plurality of vias in Figure 6; Figure 12 shows a partial planar schematic diagram of the third conductive layer in Figure 6; Figures 13A and 13B are both partial enlarged schematic diagrams of the dashed region S in Figure 6; Figure 14 shows a cross-sectional schematic diagram taken along line CC' in Figure 13A; Figure 15 shows a cross-sectional schematic diagram taken along line DD' in Figure 13A.

[0087] For example, referring to FIG6, the pixel electrode further includes a first connecting portion 411 and a second connecting portion 412. The first connecting portion 411 is located at one end of the plurality of pixel electrode strips 41 and is connected to all of the plurality of pixel electrode strips 41. The second connecting portion 412 is located at the other end of the plurality of pixel electrode strips 41 and is connected to all of the plurality of pixel electrode strips. The number of the plurality of pixel electrode strips 41 may include 2 pixel electrode strips, 3 pixel electrode strips, or more pixel electrode strips, as shown in FIG6, which illustrates a display substrate including 2 pixel electrode strips. In some embodiments, the plurality of pixel electrode strips may extend along a third direction Y', wherein the third direction Y' has a predetermined tilt angle between the second direction Y. For example, the plurality of pixel electrode strips 41 may be substantially parallel to the data line DL. In the above-mentioned display substrate, the planar common electrode 2 and the comb-shaped pixel electrode 4 are stacked on the substrate of the display substrate. The electric field generated by the edge of the comb-shaped pixel electrode in the same plane and the electric field generated between the comb-shaped pixel electrode layer and the planar common electrode layer form a multidimensional electric field, which enables all the liquid crystal molecules oriented between the comb-shaped pixel electrodes and directly above the pixel electrodes in the liquid crystal cell to rotate, thereby realizing the display of various gray levels.

[0088] For example, each sub-pixel P of the display substrate may also include a thin-film transistor located on the substrate 1. The thin-film transistor may include a gate, a first electrode, and a second electrode; for example, the first electrode may be one of the source and drain electrodes, and the second electrode may be the other of the source and drain electrodes. The thin-film transistor may also include a gate insulating layer and an active layer.

[0089] Referring to Figure 4, within the same row of sub-pixels, the thin-film transistors (TFTs) of odd-numbered columns are connected to the same gate line, such as the first gate line GL1, while the TFTs of even-numbered columns are connected to the same gate line, such as the second gate line GL2. In adjacent columns of sub-pixels, the TFTs of adjacent columns can be connected to the same data line DL. During operation, valid signals can be input row by row onto the first gate line GL1 and the second gate line GL2 to activate the corresponding TFTs. Specifically, when an odd-numbered column of TFTs in a row is activated, a pixel voltage is input to that TFT via the data line DL. This pixel voltage is then transmitted to the pixel electrode for display of the corresponding grayscale level. Similarly, when an even-numbered column of TFTs in a row is activated, the same pixel voltage is input to the TFT via the data line DL, and the pixel voltage is transmitted to the pixel electrode for display of the corresponding grayscale level. In the dual-gate-line driving method, the number of gate lines is doubled, while the number of data lines is halved, reducing the cost of the driver IC. Simultaneously, the charging time is reduced to half that of the single-gate-line driving method, which affects the charging rate.

[0090] As the pixel density of display substrates increases, the wiring space of thin-film transistors (TFTs) becomes increasingly smaller. For example, in some embodiments, one of the first and second electrodes of the TFT is located between adjacent data lines DL and electrode lines CL. For instance, referring to Figure 9, the second electrode D1 of the TFT is located between adjacent data lines DL and electrode lines CL. The second electrode of the TFT and the data line DL can be located in the same layer, for example, both in the first conductive layer. In the pixel driving circuit, the second electrode of the TFT typically needs to form an electrical connection with the pixel electrode through a via, thereby writing the driving signal into the pixel unit. Due to the reduced wiring space of the TFT, the trace width of the metal conductive portion where the second electrode D1 of the TFT is located in the first direction X is also correspondingly reduced. However, limited by process precision, such as alignment precision and etching precision, a certain margin (including the via distance) needs to be ensured in the area where the via is formed to prevent the via from penetrating the insulating layer below the first conductive layer due to via etching deviation, causing poor display due to connection between the pixel electrode and the gate line.

[0091] Embodiments of this disclosure provide a semi-drilled overlapping display substrate. By setting a protective electrode block in the drilled area, the protective electrode block can be used for via protection during the etching process, preventing the insulating layer below the first conductive layer from being penetrated when forming the via, thus avoiding connection between the pixel electrode and the gate line. The protective electrode block can be located on a different film layer than the second electrode of the thin-film transistor, thereby making full use of vertical space and achieving high-resolution display.

[0092] For example, the protective electrode block can be located on the same layer as the common electrode, eliminating the need for an additional film layer and simplifying the process.

[0093] As exemplarily, referring to FIG10, the protective electrode block 120 and the common electrode 2 may be arranged at intervals. For example, the protective electrode block 120 may be partially surrounded by the common electrode 2.

[0094] Exemplarily, the protection electrode block 120 may not be directly connected to other signal lines. For example, the protection electrode block may be directly connected to the pixel electrode, which in turn is connected to other signal lines. Exemplarily, referring to Figures 6-15, the display substrate 100 may include: a substrate 1; a first conductive layer 11 located on one side of the substrate, the first conductive layer 11 including a plurality of data lines DL and electrode lines CL arranged alternately along a first direction X, each data line DL and electrode line CL extending generally along a second direction Y, and each column of sub-pixels located between adjacent data lines DL and electrode lines CL. The first conductive layer 11 may also include a first electrode S1 and a second electrode D1 of a thin-film transistor, for example, a portion of the data line DL may be connected to the first electrode region of the thin-film transistor to form the first electrode S1; the second electrode D1 of the thin-film transistor is located between adjacent data lines DL and electrode lines CL.

[0095] The display substrate may further include: a first insulating layer 31 located on the side of the first conductive layer 11 away from the substrate 1; and a second conductive layer 12 located on the side of the first insulating layer 31 away from the substrate 1. The second conductive layer 12 may include a common electrode 2 and a plurality of protective electrode blocks 120. The common electrode 2 may include a plurality of openings 21, wherein the orthographic projection of at least one protective electrode block 120 on the substrate falls within the orthographic projection of at least one opening 21 of the common electrode 2 on the substrate.

[0096] The display substrate may further include: a second insulating layer 32 located on the side of the second conductive layer 12 away from the substrate; and a third conductive layer 13 located on the side of the second insulating layer 32 away from the substrate, wherein the third conductive layer 13 includes a plurality of pixel electrodes 4, for example, one pixel electrode 4 is disposed in the region where each sub-pixel is located. Exemplarily, the pixel electrode 4 can be connected to the protective electrode block 120 through a first via VH1. The pixel electrode 4 can also be connected to the second electrode D1 of the thin-film transistor through the first via VH1, thereby achieving a semi-overlapping connection between the pixel electrode 4 and the second electrode D1 of the thin-film transistor. For example, referring to FIG13A, the orthographic projection of the second electrode D1 of the thin-film transistor on the substrate at least partially overlaps with the orthographic projection of the protective electrode block 120 on the substrate. The overlapping portion of the orthographic projections of both the second electrode D1 of the thin-film transistor and the protective electrode block 120 on the substrate at least partially overlaps with the orthographic projection of the first via VH1 on the substrate. By disposing a protective electrode block in the region near the second electrode D1 of the thin-film transistor, the protective electrode block can be a transparent conductive film layer, such as an ITO film layer. When forming the first via, the guard electrode block can block the etching process from etching the film layer below the guard electrode block. This allows for sufficient via-coverage distance to be achieved by utilizing both the second electrode D1 of the thin-film transistor and the guard electrode block 120. Since the second electrode D1 of the thin-film transistor and the guard electrode block 120 are located in different film layers, sufficient via-coverage distance can be ensured without increasing the width of the second electrode D1. This prevents the film layer below the second electrode D1 of the thin-film transistor from being penetrated during the via etching step, thereby reducing the probability of short circuits between the pixel electrode and the gate line and improving the yield of the display substrate.

[0097] For example, referring to FIG14, the first via VH1 may include a first sub-via VH11 and a second sub-via VH12, wherein the first sub-via VH11 and the second sub-via VH12 are adjacently connected in a first direction X. The first sub-via VH1 penetrates the first insulating layer 31 and the second insulating layer 32, and the pixel electrode 4 is connected to the second electrode D1 of the thin-film transistor through the first sub-via VH11. The second sub-via VH2 penetrates the second insulating layer 32, and the pixel electrode 4 is connected to the protection electrode block 120 through the second sub-via VH2. The first via VH1 adopts a half-overlapping method, with a portion located above the protection electrode block, so that a portion of the first via is cut off in the protection electrode block region during via formation. For example, a specific via etching process can be used, selecting an etching process that can etch the insulating layer but not ITO, so that during the formation of the first via, the first sub-via VH11 penetrating the first insulating layer 31 and the second insulating layer 32 and the second sub-via VH12 penetrating the second insulating layer 32 can be formed. The first sub-via VH11 ensures electrical connection between the pixel electrode 4 and the second electrode D1 of the thin-film transistor. The protection electrode block 120 cuts off the second sub-via VH12 at the surface of the protection electrode block away from the substrate. This prevents the insulating layer GI below the second electrode D1 of the thin-film transistor from being etched through during the formation of the first via VH1 due to factors such as misalignment or etching accuracy deviations, which would cause the pixel electrode to be electrically connected to the gate line GL located below the second electrode D1 of the thin-film transistor, resulting in display defects.

[0098] Exemplary examples, in some embodiments of this disclosure, referring to FIG14, the first sub-via VH11 has a first width M1 in the first direction, and the second sub-via VH12 has a second width M2 in the first direction, wherein the first width M1 is smaller than the second width M2. In a limited wiring space, by setting the first width of the first sub-via VH11 to be smaller in the first direction, sufficient clearance for the second electrode D1 of the thin-film transistor can be ensured, preventing the first via from exceeding the edge of the second electrode D1 of the thin-film transistor due to process variations and penetrating the insulating layer beneath the second electrode D1.

[0099] Exemplary examples, in some embodiments of this disclosure, referring to FIG13A, the orthographic projection of the second electrode D1 of the thin-film transistor on the substrate includes a first side L1 and a second side L2 extending along the second direction Y. The orthographic projection of the first via VH1 on the substrate includes a third side L3 and a fourth side L4 extending along the second direction Y. The orthographic projection of the protection electrode block 120 on the substrate includes a fifth side L5 and a sixth side L6 extending along the second direction Y. The first side L1, the third side L3, the fifth side L5, the second side L2, the fourth side L4, and the sixth side L6 are sequentially spaced apart in the first direction X. To ensure that the second electrode D1 of the thin-film transistor and the protection electrode block 120 below the first via VH1 in the semi-overlap structure have sufficient clearance for the via, a first preset distance d1 is provided between the first side L1 and the third side L3, for example, the first preset distance d1 can be greater than or equal to 9.6 μm. By designing a large distance between the first side L1 of the second electrode D1 of the thin-film transistor and the third side L3 of the first via VH1, it can be ensured that even in the event of process errors such as etching deviation or alignment deviation, the orthogonal projection of the third side L3 of the first via on the substrate can still fall within the orthogonal projection of the second electrode D1 of the thin-film transistor on the substrate. This prevents the first via from penetrating the insulating layer below the second electrode D1 of the thin-film transistor, thus avoiding connection between the pixel electrode and the gate line.

[0100] Exemplary, in some embodiments of this disclosure, continuing to refer to FIG13A, a second preset distance d2 is provided between the fifth side L5 and the second side L2. In the first direction X, the second electrode D1 of the thin-film transistor and the protective electrode block 120 include an overlapping portion, the width of which is the second preset distance d2. By designing the width of the overlapping portion of the second electrode D1 of the thin-film transistor and the protective electrode block 120 to be relatively large, after completing the etching of the second electrode D1 of the thin-film transistor, the etching of the protective electrode block 120, and the alignment of the second electrode D1 of the thin-film transistor and the protective electrode block 120, the second electrode D1 of the thin-film transistor and the protective electrode block 120 still have an overlapping portion. This can avoid the formation of a blank area without the protective electrode block and the second electrode D1 of the thin-film transistor between the second electrode D1 of the thin-film transistor and the protective electrode block 120 due to process deviations, and can prevent vias from penetrating the insulating layer under the second electrode D1 of the thin-film transistor, causing the pixel electrode to connect with the gate line.

[0101] For example, a third preset distance d3 is provided between the fourth side L4 and the sixth side L6. The third preset distance d3 is the distance between the protective electrode block and the via. By designing a larger distance between the sixth side L6 of the protective electrode block 120 and the fourth side L4 of the first via VH1, it can be ensured that the orthogonal projection of the fourth side L4 of the first via on the substrate falls within the orthogonal projection of the protective electrode block 120 on the substrate. This allows the portion of the first via located above the protective electrode block to only penetrate the second insulating layer 32, thereby preventing the via from penetrating the insulating layer below the second electrode D1 of the thin-film transistor and causing connection between the pixel electrode and the gate line. For example, the third preset distance d3 can be greater than or equal to 9.6 μm.

[0102] Figure 16 is a SEM image of a display substrate along a first direction in the first via region according to some illustrative embodiments of the present disclosure.

[0103] Exemplary, in some embodiments of this disclosure, referring to Figures 14 and 16, the first insulating layer 31 includes a first portion 311 adjacent to a first sub-via VH11, and the orthographic projection of the first portion 311 on the substrate does not overlap with the orthographic projection of the second sub-via VH12 on the substrate. The first portion 311 includes a first sidewall N1 adjacent to the first sub-via VH11, the first sidewall N1 having a first slope angle α1. The second insulating layer 32 includes a second portion 321 adjacent to the first sub-via VH11, and the orthographic projection of the second portion 321 on the substrate does not overlap with the orthographic projection of the second sub-via VH12 on the substrate. The second portion 321 includes a second sidewall N2 adjacent to the first sub-via VH11, the second sidewall N2 having a second slope angle α2, the first slope angle α1 being greater than the second slope angle α2. For example, the first slope angle α1 is approximately 67°, and the second slope angle α2 is approximately 42°.

[0104] By way of example, continuing to refer to Figures 14 and 16, the first insulating layer 31 further includes a third portion 313, which is adjacent to the first sub-via VH11. The orthographic projection of the third portion 313 onto the substrate falls within the orthographic projection of the second electrode D1 of the thin-film transistor onto the substrate, and also falls within the orthographic projection of the protective electrode block 120 onto the substrate. The third portion 313 includes a third sidewall N3 away from the first sub-via VH11, and the third sidewall N3 has a third slope angle α3. The protective electrode block 120 includes a fourth portion 1204, the orthographic projection of which falls within the orthographic projection of the third portion 313 of the first insulating layer onto the substrate. The fourth portion 1204 includes a fourth sidewall N4 away from the first sub-via VH11, and the fourth sidewall N4 has a fourth slope angle α4. The third slope angle α3 is greater than the fourth slope angle α4. In some embodiments, the third slope angle α3 can be greater than or equal to twice the fourth slope angle α4. For example, the third slope angle α3 is about 52° and the fourth slope angle is about 26°.

[0105] By way of example, continuing to refer to Figures 14 and 16, the second insulating layer 32 further includes a fifth portion 325, which is adjacent to the second sub-via VH12 and whose orthographic projection on the substrate at least partially overlaps with the orthographic projection of the protection electrode block 120 on the substrate. The fifth portion 325 includes a fifth sidewall N5 adjacent to the second sub-via VH12, the fifth sidewall N5 having a fifth slope angle α5. The fifth slope angle α5 is greater than or equal to 30°. For example, the fifth slope angle α5 is approximately 38°.

[0106] By optimizing the etching process, the tilt angles of some sidewalls of the first insulating layer, the second insulating layer, and the protective electrode block can be adjusted during the formation of the first via. This ensures that the tilt angle of the sidewalls of the film layers closer to the substrate is greater than that of the sidewalls of the film layers farther from the substrate. As a result, in the region where the first via is located, the film layers closer to the substrate, such as the first insulating layer, can provide support for the film layers farther from the substrate, such as the film layers where the protective electrode block is located or the second insulating layer. This helps to improve the etching accuracy of the via and reduce the probability of over-etching the via.

[0107] Exemplary, in some embodiments of this disclosure, referring to Figures 7, 8, 13A, 13B, and 14, the display substrate may further include: a third insulating layer GI located on the side of the first conductive layer 11 near the substrate, wherein the third insulating layer GI may be a gate insulating layer. The display substrate may further include a fourth conductive layer 14 located on the side of the third insulating layer GI near the substrate and a semiconductor layer 15 located between the third insulating layer 33 and the first conductive layer 11. The active layer ACT of the thin-film transistor may be located in the semiconductor layer 15. The portion of the fourth conductive layer 14 overlapping the active layer ACT is the gate electrode G1 of the thin-film transistor. The fourth conductive layer 14 also includes a gate line GL connected to the gate electrode G1. The gate line GL includes a widened portion GL11 and a connecting portion GL12. The gate electrode G1 is located in the widened portion GL11. The orthographic projection of the second electrode D1 of the thin-film transistor on the substrate at least partially overlaps with the orthographic projection of the widened portion GL11 on the substrate. The orthographic projection of the second electrode D1 of the thin-film transistor on the substrate does not overlap with the orthographic projection of the connecting portion GL12 on the substrate. By designing the projection of the second electrode D1 of the thin-film transistor onto the substrate to fall within the orthogonal projection of the widened portion GL11 onto the substrate, it is beneficial to increase the area of ​​the second electrode D1 and the area of ​​the gate electrode G1 of the thin-film transistor, thereby improving the transmission performance of the thin-film transistor.

[0108] Exemplary examples, in some embodiments of this disclosure, referring to Figures 7, 8, 13A, 13B, and 14, show that the orthographic projection of the protective electrode block 120 on the substrate at least partially overlaps with the orthographic projection of the widened portion GL11 on the substrate. The orthographic projection of the protective electrode block 120 on the substrate at least partially overlaps with the orthographic projection of the connecting portion GL12 on the substrate.

[0109] Referring to FIG6, the first connection portion 411 is connected to the second electrode D1 of the corresponding thin film transistor through the first via VH1, and the orthographic projection of the second connection portion 412 on the substrate overlaps at least partially with the orthographic projection of the gate line GL on the corresponding side on the substrate.

[0110] For example, referring to Figures 13B and 15, the first via VH1 further includes a seventh side L7 extending along the first direction X. For instance, the seventh side L7 in the i-th row of sub-pixels is located between the first gate line GL1 and the second gate line GL2, and a fourth preset distance d4 is provided between the seventh side L7 and the second gate line GL2. By optimizing the fourth preset distance d4, it can be ensured that the reserved distance between the seventh side L7 of the first via VH1 and the adjacent gate line is large enough to prevent the via from connecting to the adjacent gate line.

[0111] The first via VH1 also includes an eighth side L8 extending along the first direction, the orthographic projection of the eighth side L8 on the substrate falling within the orthographic projection of the gate line on the substrate. The protection electrode block 120 includes a ninth side L9 extending along the first direction, the orthographic projection of the ninth side L9 on the substrate at least partially overlapping the orthographic projection of the widened portion GL11 of the gate line on the substrate. A fifth preset distance d5 is provided between the eighth side L8 and the ninth side L9. By designing the via distance of the electrode protection block in the second direction, the via can be prevented from exceeding the range of the electrode protection block, and the via can be prevented from connecting to the gate line.

[0112] The orthographic projection of the protective electrode block 120 on the substrate at least partially overlaps with the orthographic projection of the gate line GL on the substrate. The protective electrode block includes a protrusion 1201 that protrudes relative to the gate line in a second direction. The protrusion 1201 is located between two adjacent gate lines and has a first protrusion distance d6 in the second direction Y. By designing the protective electrode block to protrude relative to the gate line in the second direction, thereby covering a portion of the side of the gate line, it is ensured that vias are placed on the protective electrode block and not on the gate line, thus preventing the pixel electrode from connecting to the gate line.

[0113] Exemplary examples, in some embodiments of this disclosure, continuing to refer to Figures 13B and 15, show that the first connection portion 411 in the pixel electrode includes a tenth side L10 extending along a first direction, and a seventh preset distance d7 is provided between the tenth side L10 and the seventh side L7 of the first via VH1. The seventh preset distance d7 can be the distance by which the pixel electrode covers the via, ensuring that the pixel electrode covers the via and guaranteeing the reliability of the connection between the pixel electrode and the second electrode of the thin-film transistor.

[0114] Exemplary, in an embodiment of this disclosure, referring to FIG6, the display substrate may include a first sub-pixel P1 located in the i-th row and j-th column, a second sub-pixel P2 located in the i-th row and j+1-th column, and a third sub-pixel P3 located in the i-th row and j+2-th column, wherein the second sub-pixel P2 includes a second sub-pixel electrode 42. The display substrate also includes a first data line DL1 located between the j-th column sub-pixel and the j+1-th column sub-pixel, and a first electrode line CL1 located between the j+1-th column sub-pixel and the j+2-th column sub-pixel, wherein the orthographic projection of the second sub-pixel electrode 42 on the substrate at least partially overlaps with the orthographic projection of the first electrode line CL1 on the substrate.

[0115] The pixel electrode is located in the third conductive layer. By adopting a top pixel design, the distance between the pixel electrode and the first conductive layer containing the source and drain of the thin-film transistor is greater in the direction perpendicular to the substrate. The orthogonal projection of the pixel electrode on the substrate can overlap with the orthogonal projection of at least one of the data line or electrode line on the substrate, which is beneficial to increase the storage capacitance in the thin-film transistor and optimize the display effect.

[0116] Figure 17 is a partial plan view of a display substrate according to some illustrative embodiments of the present disclosure.

[0117] Exemplary examples, in some embodiments of this disclosure, referring to FIG17, the data line DL includes a main body portion DL10 and a connecting portion DL20. The connecting portion DL20 is connected to the first electrode S1 of the thin-film transistor. The connecting portion DL20 extends substantially along the second direction Y, and the connecting portion DL20 may share a portion of conductive components with the main body portion DL10. The connecting portion DL20 has a third width M3 in the first direction X, and the main body portion DL10 has a fourth width M4 in the first direction X, the ratio of the third width M3 to the fourth width M4 being between 0.8 and 1.2. In some embodiments, the orthographic projection of the connecting portion DL20 on the substrate may substantially overlap with the orthographic projection of the main body portion DL10 on the substrate. This design can reduce the maximum width of the data line in the first direction, allowing more space for the routing of the second electrode of the thin-film transistor, which is beneficial for achieving high-resolution display design.

[0118] Figure 18 is a partial plan view of a display substrate according to some illustrative embodiments of the present disclosure.

[0119] Exemplary examples, in some embodiments of this disclosure, referring to FIG18, show a larger trace space between adjacent data lines and electrode lines, allowing for more flexible data line design. For instance, the data line DL includes a main body DL10 and a connecting portion DL20, with the connecting portion DL20 connected to the first electrode S1 of the thin-film transistor. The connecting portion DL20 protrudes a second protrusion distance d8 relative to the main body DL10 in a first direction X, and the main body DL10 has a fourth width M4 in the first direction X. The second protrusion distance d8 is greater than the fourth width M4. In lower-resolution display substrates, where the trace space between data lines and electrode lines is larger, designing the connecting portion of the data line to protrude along the first direction allows for full utilization of the trace space and improves data transmission reliability.

[0120] Figure 19A is a cross-sectional schematic diagram of a display substrate provided according to some embodiments of the present disclosure, taken along line EE' in Figure 17; Figure 19B is a cross-sectional schematic diagram of a display substrate provided according to some embodiments of the present disclosure, taken along line FF' in Figure 17; Figure 19C is a cross-sectional schematic diagram of a display substrate provided according to some embodiments of the present disclosure, taken along line GG' in Figure 18; Figure 19D is a cross-sectional schematic diagram of a display substrate provided according to some embodiments of the present disclosure, taken along line HH' in Figure 18.

[0121] Exemplary examples, in some embodiments of this disclosure, referring to Figures 6, 7, 10, 13B, and 19A-19D, show that the orthographic projection of the common electrode 2 onto the substrate at least partially overlaps with the orthographic projection of the gate line GL onto the substrate. For example, the display substrate includes multiple gate lines GL extending along the first direction X. The gate lines GL are located between adjacent rows of sub-pixel regions, and each gate line includes a widened portion GL11 and a connecting portion GL12. Two gate lines are disposed between each pair of adjacent rows of sub-pixel regions. For example, multiple sub-pixels include multiple rows of sub-pixels located in the i-th row and the (i+1)-th row, where i is greater than or equal to 1. The gate lines include a first gate line GL1 and a second gate line GL2 located between the regions of the i-th row of sub-pixels and the (i+1)-th row of sub-pixels. The orthographic projection of the common electrode 2 onto the substrate and the orthographic projection of the widened portion GL11 of the first gate line GL1 onto the substrate at least partially overlap. For example, the projected overlap of the common electrode 2 and the widened portion GL11 of the first gate line GL1 has a first overlap width M5 in the second direction Y, the first overlap width M5 being greater than or equal to 0.85 micrometers.

[0122] For example, the orthographic projection of the common electrode 2 on the substrate and the orthographic projection of the connection portion GL12 of the second gate line GL2 on the substrate at least partially overlap. The overlapping portion of the projections of the common electrode 2 and the connection portion GL12 of the second gate line GL2 has a second overlap width M6 in the second direction Y, which is greater than or equal to 0.5 micrometers. The common electrode is located on the side of the pixel electrode closer to the substrate, so the distance between the common electrode and the transistors, gate lines, data lines, and electrode lines below it in the light emission direction is small, and the potential of the common electrode has a good shielding effect on signal fluctuations in components such as transistors, gate lines, data lines, and electrode lines. Since the potential of the common electrode can shield the influence of signals in the gate lines on the pixel unit, the greater the overlap between the common electrode and the gate line, the more significant the shielding effect of the common electrode, and the tighter the wiring design in the second direction can be. The display substrate also includes a black matrix BM, the width of which needs to take into account cell accuracy and light leakage. When the shielding effect of the common electrode on the gate line signal is better, the trace width of the pixel driving circuit in the second direction is smaller, and correspondingly, the width of the black matrix BM is also smaller. This reduces the proportion of the opaque area in the display substrate, which is beneficial to improving the aperture ratio of the display substrate and thus improving the display effect. For example, the distance M15 between the boundary of the orthographic projection of the black matrix on the substrate and the boundary of at least a portion of the corresponding gate line is approximately 3.9 micrometers, thereby ensuring sufficient shielding effect and reducing electrical light leakage. Compared with 5 micrometers in the above embodiment, the distance between the boundary of the black matrix and the boundary of the corresponding gate line can be reduced, for example, from 5 micrometers to 3.9 micrometers, thereby reducing the overall width of the black matrix and improving the aperture ratio of the display panel.

[0123] For example, referring to Figures 17, 19A, and 19B, a portion of the data line DL or electrode line CL has a width d01 of approximately 2.8 micrometers in the first direction. The spacing M12 between adjacent gate lines in the second direction Y is approximately 4 micrometers. The spacing M16 between adjacent pixel electrodes 4 in the first direction is approximately 9.36 micrometers. The spacing M11 between one of the data line DL or electrode line CL and the pixel electrode 4 can be approximately 3.28 micrometers. The width d20 of the orthogonal projection of the electrode protection block 120 onto the substrate in the second direction Y is approximately 5.75 micrometers. The spacing d30 between the electrode protection block 120 and the adjacent common electrode 2 in the second direction Y is approximately 4 micrometers. For example, to ensure sufficient light-shielding effect of the black matrix, the width d11 of the orthogonal projection of the black matrix BM onto the substrate in the first direction is approximately 4.5 micrometers, and the width d12 in the second direction is approximately 25.1 micrometers. By optimizing the pixel arrangement and reducing the width of the black matrix, the aperture ratio of the display panel in the exemplary embodiments of this disclosure can reach 45.9% to 47.3%.

[0124] Compared to a display substrate with pixel electrodes at the bottom and common electrodes at the top, in the embodiment of this disclosure, where pixel electrodes are at the top and common electrodes are at the bottom combined with electrode protection blocks, the width of the black matrix BM in the second direction can be reduced, for example, from 28.1 micrometers to 25.1 micrometers, thereby increasing the aperture ratio of the display panel, for example, from 44.6% to 47.3%, and improving the display effect.

[0125] In some display substrates with low pixel density, the routing space between adjacent data lines and electrode lines is relatively large. By optimizing the pixel routing design, the aperture ratio of the display panel can be further improved.

[0126] For example, referring to Figures 19C and 19D, the spacing M11 between one of the data lines DL or CL and the pixel electrode can be approximately 3.21 micrometers. The width d20 of the orthogonal projection of the electrode protection block 120 onto the substrate in the second direction Y is approximately 6.45 micrometers. The spacing d30 between the electrode protection block 120 and the adjacent common electrode 2 in the second direction Y is approximately 3.8 micrometers. For example, to ensure sufficient light-shielding effect of the black matrix, the width d11 of the orthogonal projection of the black matrix BM onto the substrate in the first direction is approximately 4.5 micrometers, and the width d12 in the second direction is approximately 25.1 micrometers. By optimizing the pixel arrangement and reducing the width of the black matrix, the aperture ratio of the display panel in the exemplary embodiments of this disclosure can reach 54.5%.

[0127] Compared to display substrates with pixel electrodes at the bottom and common electrodes at the top, in the embodiments of this disclosure using a display substrate with pixel electrodes at the top and common electrodes at the bottom combined with electrode protection blocks, the width of the black matrix BM in the second direction can be reduced, for example, from 28.1 micrometers to 25.1 micrometers. This can increase the aperture ratio of the display panel, for example, from 46.5% to 54.5%, thus improving the display effect. Figure 20 is a schematic structural diagram of a display device provided according to some embodiments of this disclosure.

[0128] Optionally, embodiments of this disclosure also provide a display panel, referring to FIG20, the display panel 200 may include the above-described display substrate 100.

[0129] Figure 21 is a schematic diagram of the structure of a display device provided according to some embodiments of the present disclosure.

[0130] Optionally, embodiments of this disclosure also provide a display device. Referring to FIG21, the display device 300 may include the aforementioned display substrate 100 or the aforementioned display panel 200. The display device may include, but is not limited to, any product or component with display function such as electronic paper, mobile phone, tablet computer, monitor, laptop computer, digital photo frame, and navigator. It should be understood that this display device has the same beneficial effects as the display substrate provided in the foregoing embodiments.

[0131] While some embodiments of the general concept of this disclosure have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the general concept of this disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A display substrate, characterized in that, The display substrate includes a plurality of sub-pixels arranged in an array along a first direction and a second direction, wherein the first direction and the second direction intersect. The display substrate includes: Substrate; A first conductive layer is located on one side of the substrate. The first conductive layer includes multiple data lines and electrode lines arranged alternately along a first direction. Each data line and electrode line extends along a second direction. Each column of sub-pixels is located between adjacent data lines and electrode lines. The first conductive layer also includes a first electrode and a second electrode of a thin-film transistor, wherein the data lines are connected to the first electrode of the thin-film transistor, and the second electrode of the thin-film transistor is located between adjacent data lines and electrode lines. A first insulating layer is located on the side of the first conductive layer away from the substrate. The second conductive layer is located on the side of the first insulating layer away from the substrate. The second conductive layer includes a common electrode and a plurality of protective electrode blocks. The common electrode includes a plurality of openings, wherein at least one of the protective electrode blocks has its orthographic projection on the substrate falling within the orthographic projection of at least one opening of the common electrode on the substrate. A second insulating layer is located on the side of the second conductive layer away from the substrate; and A third conductive layer is located on the side of the second insulating layer away from the substrate. The third conductive layer includes a plurality of pixel electrodes, one of which is disposed within the region of each sub-pixel. The pixel electrodes are connected to the protective electrode block via a first via and to the second electrode of the thin-film transistor via the first via. Wherein, the orthographic projection of the second electrode of the thin-film transistor on the substrate at least partially overlaps with the orthographic projection of the protective electrode block on the substrate; The overlapping portion of the orthographic projections of the second electrode of the thin-film transistor and the protective electrode block on the substrate at least partially overlaps with the orthographic projection of the first via on the substrate.

2. The display substrate according to claim 1, wherein, The first via includes a first sub-via and a second sub-via, wherein the first sub-via and the second sub-via are arranged adjacent to each other in a first direction; The first sub-via penetrates the first insulating layer and the second insulating layer, and the pixel electrode is connected to the second electrode of the thin-film transistor through the first sub-via; The second sub-via penetrates the second insulating layer, and the pixel electrode is connected to the protective electrode block through the second sub-via.

3. The display substrate according to claim 2, wherein, The first sub-via has a first width in a first direction, and the second sub-via has a second width in a first direction, wherein the first width is smaller than the second width.

4. The display substrate according to any one of claims 1-3, wherein, The orthogonal projection of the second electrode of the thin-film transistor onto the substrate includes a first side and a second side extending along a second direction; The orthographic projection of the first via onto the substrate includes a third side and a fourth side extending along the second direction. The orthographic projection of the protective electrode block onto the substrate includes a fifth side and a sixth side extending along the second direction, wherein, The first side, the third side, the fifth side, the second side, the fourth side, and the sixth side are arranged at intervals in a first direction.

5. The display substrate according to claim 4, wherein, A first preset distance is provided between the first side and the third side.

6. The display substrate according to claim 4 or 5, wherein, A second preset distance is provided between the fifth side and the second side.

7. The display substrate according to any one of claims 4-6, wherein, A third preset distance is provided between the fourth side and the sixth side.

8. The display substrate according to claim 2, wherein, The first insulating layer includes a first portion, which is adjacent to the first sub-via and the orthographic projection of the first portion on the substrate does not overlap with the orthographic projection of the second sub-via on the substrate. The first portion includes a first sidewall near the first sub-via, and the first sidewall has a first slope angle. The second insulating layer includes a second portion, the second portion being adjacent to the first sub-via and the second The orthographic projection of a portion of the first sub-via on the substrate does not overlap with the orthographic projection of the second sub-via on the substrate. The second portion includes a second sidewall near the first sub-via, and the second sidewall has a second slope angle. Wherein, the first slope angle is greater than the second slope angle.

9. The display substrate according to claim 8, wherein, The first insulating layer further includes a third portion, which is adjacent to the first sub-via, and the orthographic projection of the third portion on the substrate falls within the orthographic projection of the second electrode of the thin film transistor on the substrate, and the orthographic projection of the third portion on the substrate falls within the orthographic projection of the protective electrode block on the substrate, wherein the third portion includes a third sidewall away from the first sub-via, and the third sidewall has a third slope angle. The protective electrode block includes a fourth portion, the orthographic projection of which falls within the orthographic projection of the third portion of the first insulating layer on the substrate. The fourth portion of the protective electrode block includes a fourth sidewall away from the first sub-via, the fourth sidewall having a fourth slope angle. Wherein, the third slope angle is greater than or equal to twice the fourth slope angle.

10. The display substrate according to claim 9, wherein, The second insulating layer further includes a fifth portion, which is adjacent to the second sub-via and whose orthographic projection on the substrate at least partially overlaps with the orthographic projection of the protective electrode block on the substrate. The fifth portion includes a fifth sidewall near the second sub-via, the fifth sidewall having a fifth slope angle greater than or equal to 30°.

11. The display substrate according to any one of claims 1-10, wherein, The display substrate further includes: a third insulating layer located on the side of the first conductive layer near the substrate; and a fourth conductive layer located on the side of the third insulating layer near the substrate, the fourth conductive layer including the gate electrode of the thin film transistor and a gate line connected to the gate electrode, the gate line including a widened portion and a connecting portion, the gate electrode being located in the widened portion, the orthographic projection of the second electrode of the thin film transistor on the substrate at least partially overlapping the orthographic projection of the widened portion on the substrate; and the orthographic projection of the second electrode of the thin film transistor on the substrate not overlapping the orthographic projection of the connecting portion on the substrate.

12. The display substrate according to claim 11, wherein, The orthographic projection of the protective electrode block on the substrate at least partially overlaps with the orthographic projection of the widened portion on the substrate; The orthographic projection of the protective electrode block on the substrate at least partially overlaps with the orthographic projection of the connecting portion on the substrate.

13. The display substrate according to any one of claims 1-12, wherein, The display substrate includes multiple gate lines that extend along the first direction and are located between two adjacent rows of sub-pixel regions. The pixel electrode includes a plurality of pixel electrode strips located in the region where the sub-pixel is located and arranged at intervals. The pixel electrode also includes a first connecting portion and a second connecting portion. The first connecting portion is located at one end of the plurality of pixel electrode strips and is connected to all of the plurality of pixel electrode strips. The second connecting portion is located at the other end of the plurality of pixel electrode strips and is connected to all of the plurality of pixel electrode strips. The first connecting portion is connected to the second electrode of the corresponding thin film transistor through the first via. The orthographic projection of the second connecting portion on the substrate overlaps at least partially with the orthographic projection of the gate line on the corresponding side on the substrate.

14. The display substrate according to any one of claims 1-12, wherein, The display substrate includes multiple gate lines, which extend along the first direction and are located between two adjacent rows of sub-pixel regions. Two gate lines are provided between each two adjacent rows of sub-pixel regions. The plurality of sub-pixels includes multiple rows of sub-pixels located in the i-th row and the (i+1)-th row, and multiple columns of sub-pixels located in the j-th column and the (j+1)-th column, where i is greater than or equal to 1, j is greater than or equal to 1, and so on. The gate line includes a first gate line and a second gate line located between the region where the sub-pixel in the i-th row is located and the region where the sub-pixel in the (i+1)-th row is located. The first gate line is connected to the gate electrode of the thin-film transistor of the sub-pixel in the i-th row and (j+1)-th column. The second gate line is connected to the gate electrode of the thin-film transistor of the sub-pixel in the (i+1)-th row and (j)-th column.

15. The display substrate according to claim 14, wherein, The first via includes a seventh side extending along a first direction; The seventh side of the i-th row of sub-pixels is located between the first gate line and the second gate line, and a fourth preset distance is provided between the seventh side and the second gate line.

16. The display substrate according to claim 14 or 15, wherein, The first via also includes an eighth side extending along a first direction, the orthographic projection of the eighth side on the substrate falling within the orthographic projection of the gate line on the substrate; The protective electrode block includes a ninth side extending along a first direction, the orthographic projection of the ninth side onto the substrate at least partially overlapping the orthographic projection of the widened portion of the gate line onto the substrate. A fifth preset distance is provided between the eighth side and the ninth side.

17. The display substrate according to any one of claims 14-16, wherein, The orthographic projection of the protective electrode block on the substrate at least partially overlaps with the orthographic projection of the gate line on the substrate, wherein the protective electrode block includes a protrusion that protrudes relative to the gate line in a second direction, the protrusion being located between two adjacent gate lines, wherein the protrusion has a first protrusion distance in the second direction.

18. The display substrate according to any one of claims 1-17, wherein, The display substrate includes a first sub-pixel located in the i-th row and j-th column, a second sub-pixel located in the i-th row and j+1-th column, and a third sub-pixel located in the i-th row and j+2-th column, wherein the second sub-pixel includes a second sub-pixel electrode; The display substrate further includes a first data line located between the j-th column sub-pixel and the (j+1)-th column sub-pixel, and a first electrode line located between the (j+1)-th column sub-pixel and the (j+2)-th column sub-pixel. Wherein, the orthographic projection of the second sub-pixel electrode on the substrate at least partially overlaps with the orthographic projection of the first electrode line on the substrate.

19. The display substrate according to any one of claims 1-18, wherein, The data line includes a main body and a connecting portion. The connecting portion is connected to a first electrode of the thin-film transistor. The connecting portion extends along a second direction. The orthographic projection of the connecting portion on the substrate at least partially overlaps with the orthographic projection of the main body on the substrate. The connecting portion has a third width in a first direction, and the main body has a fourth width in the first direction. The ratio of the third width to the fourth width is between 0.8 and 1.

2.

20. The display substrate according to any one of claims 1-18, wherein, The data line includes a main body and a connecting part. The connecting part is connected to the first electrode of the thin-film transistor. The connecting part protrudes a second distance from the main body in a first direction. The main body has a fourth width in the first direction. The second protrusion distance is greater than the fourth width.

21. The display substrate according to any one of claims 13-17, wherein, The orthographic projection of the common electrode on the substrate at least partially overlaps with the orthographic projection of the gate line on the substrate.

22. The display substrate according to any one of claims 1-12, wherein, The display substrate includes multiple gate lines extending along the first direction. The gate lines are located between two adjacent rows of sub-pixel regions. Each gate line includes a widened portion and a connecting portion. Two gate lines are provided between each two adjacent rows of sub-pixel regions. The plurality of sub-pixels includes multiple rows of sub-pixels located in the i-th row and the (i+1)-th row, respectively, where i is greater than or equal to 1. The gate line includes a first gate line and a second gate line located between the regions where the sub-pixels in the i-th row and the regions where the sub-pixels in the (i+1)-th row are located. Wherein, the orthographic projection of the common electrode on the substrate and the orthographic projection of the widened portion of the first gate line on the substrate at least partially overlap, and the overlapping portion of the projections of the common electrode and the widened portion of the first gate line has a first overlap width in a second direction, the first overlap width being greater than or equal to 0.85 micrometers.

23. The display substrate according to claim 22, wherein, The orthographic projection of the common electrode on the substrate and the orthographic projection of the connection portion of the second gate line on the substrate at least partially overlap, and the overlapping portion of the projections of the common electrode and the connection portion of the second gate line has a second overlap width in a second direction, the second overlap width being greater than or equal to 0.5 micrometers.

24. A display panel, wherein, The display panel includes a display substrate as described in any one of claims 1-23.

25. A display device, wherein, The display device includes a display substrate as described in any one of claims 1-23 or a display panel as described in claim 24.

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