Array substrate, display panel, and display device

Abstract

The present disclosure relates to an array substrate, a display panel, and a display device. The array substrate comprises: a base substrate, wherein the base substrate comprises a display area and a non-display area located on at least one side of the display area; a plurality of first wires extending in a first direction in the non-display area; a plurality of transistors, located in the non-display area, wherein first electrodes of the plurality of transistors are electrically connected to the plurality of first wires, the plurality of transistors include at least one first transistor and at least one second transistor, the orthographic projection of the first transistor in the first direction overlaps the orthographic projections of the plurality of first wires in the first direction, and the orthographic projection of the second transistor in the first direction overlaps the orthographic projections of some of the first wires in the first direction; and at least one first electrode part, extending in the first direction in the non-display area, wherein the orthographic projection of the at least one first electrode part on the base substrate is located between the orthographic projection of a gate of the second transistor on the base substrate and the orthographic projection of the first wire electrically connected to the second transistor on the base substrate.

Description

Array substrate, display panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0002] Over the decades, the television industry has undergone a dramatic transformation, much like the mobile phone industry, evolving from bulky black-and-white TVs to color TVs, and now to large-screen smart displays. Technological innovation has been relentless. With product updates and the increasing demands from users for TV displays, there is a need to continuously break with traditional technologies and innovate. Besides advancements in low cost, high transmittance, and high contrast, the integration of sensors into display products—such as adding light and temperature sensors—is also being proposed to enhance the user experience.

[0003] Summary of the Invention

[0004] The array substrate, display panel, and display device disclosed herein are specifically designed as follows:

[0005] On one hand, embodiments of this disclosure provide an array substrate, including:

[0006] A substrate, the substrate including a display area and a non-display area located on at least one side of the display area;

[0007] Multiple first traces extend along a first direction in the non-display area;

[0008] Multiple transistors are located in the non-display area. The first electrode of the multiple transistors is electrically connected to the multiple first traces. The multiple transistors include at least one first transistor and at least one second transistor. The orthographic projection of the first transistor in the first direction overlaps with the orthographic projection of the multiple first traces in the first direction. The orthographic projection of the second transistor in the first direction overlaps with the orthographic projection of a portion of the first traces in the first direction.

[0009] At least one first electrode portion is located in the non-display area, and the orthographic projection of the at least one first electrode portion on the substrate is located between the orthographic projection of the gate of the second transistor on the substrate and the orthographic projection of the first trace electrically connected to the second transistor on the substrate, and the extension direction of the first electrode portion is the same as the extension direction of the first trace.

[0010] In some embodiments, in the array substrate provided in this disclosure, the number of first electrode portions between the gate of the second transistor and the first trace electrically connected to the second transistor is positively correlated with the number of first traces of the second transistor that do not overlap.

[0011] In some embodiments, in the array substrate provided in the present disclosure, the extension line of the first electrode portion between the gate of the second transistor and the first trace electrically connected to the second transistor substantially coincides with the extension line of the first trace not electrically connected to the at least one first electrode portion.

[0012] In some embodiments, in the array substrate provided in the present disclosure, the plurality of first traces include first sub-traces and second sub-traces, and the at least one second transistor includes at least one first sub-transistor;

[0013] The first electrode of the first transistor is electrically connected to the first sub-trace, and the orthographic projection of the first transistor in the first direction overlaps with the orthographic projection of the plurality of first traces in the first direction.

[0014] The first electrode of the first sub-transistor is electrically connected to the second sub-line. The orthographic projection of the first sub-transistor in the first direction overlaps with the orthographic projection of other first lines in the first direction besides the first sub-line. The gate of the first sub-transistor and the second sub-line include a first electrode portion. The extension line of the first electrode portion substantially coincides with the extension line of the first sub-line.

[0015] In some embodiments, in the array substrate provided in the present disclosure, the plurality of first traces further include third sub-traces, and the at least one second transistor further includes at least one second sub-transistor;

[0016] The first electrode of the second sub-transistor is electrically connected to the third sub-line. The orthographic projection of the second sub-transistor in the first direction overlaps with the orthographic projections of the first sub-line and other first lines besides the second sub-line in the first direction. The gate of the second sub-transistor includes two first electrode portions between it and the third sub-line. The extension line of one of the first electrode portions substantially coincides with the extension line of the first sub-line, and the extension line of the other first electrode portion substantially coincides with the extension line of the second sub-line.

[0017] In some embodiments, in the array substrate provided in the present disclosure, the plurality of first traces further include a fourth sub-trace, and the at least one transistor further includes at least one third sub-transistor;

[0018] The first electrode of the third sub-transistor is electrically connected to the fourth sub-line. The orthographic projection of the third sub-transistor in the first direction overlaps with the orthographic projection of the fourth sub-line in the first direction. The gate of the third sub-transistor and the fourth sub-line include three first electrode portions. The extension lines of the three first electrode portions are substantially coincident with the extension lines of the first sub-line, the second sub-line, and the third sub-line, respectively.

[0019] In some embodiments, in the array substrate provided in the present disclosure, the first electrode of the transistor includes a second electrode portion extending along the first direction, and the orthographic projection of the second electrode portion on the substrate overlaps with the orthographic projection of the gate of the transistor on the substrate.

[0020] The second electrode portion includes a first boundary on the side away from the second electrode of the transistor, and the second electrode of the transistor includes a second boundary on the side away from the second electrode portion;

[0021] One of the two boundaries of the first electrode portion extending along the second direction is substantially collinear with the first boundary, or is disposed on the side of the first boundary near the second boundary adjacent to the extension line of the first boundary, and the other is substantially collinear with the second boundary, and the second direction intersects the first direction.

[0022] In some embodiments, in the array substrate provided in the present disclosure, the first electrode of the transistor further includes a third electrode portion extending along a second direction, and the third electrode portion of the first transistor is connected between the second electrode portion and the first trace.

[0023] In some embodiments, in the array substrate provided in the present disclosure, the first electrode of the second transistor includes the first electrode portion, and the third electrode portion of the second transistor is connected between the second electrode portion and the first electrode portion, between adjacent first electrode portions, and between the first electrode portion and the first trace.

[0024] In some embodiments, in the array substrate provided in the present disclosure, the first electrode portion is floating, and the third electrode portion of the second transistor is connected between the second electrode portion and the first trace.

[0025] In some embodiments, in the array substrate provided in the present disclosure, the second electrode of the transistor includes a U-shaped electrode portion, and a portion of the second electrode portion is located within the opening of the U-shaped electrode portion.

[0026] In some embodiments, the array substrate provided in this disclosure further includes a second trace and a third trace extending along the first direction, wherein the gates of the plurality of transistors are electrically connected to the second trace, and the second electrodes of the plurality of transistors are electrically connected to the third trace.

[0027] In some embodiments, in the array substrate provided in the present disclosure, the first trace, the second trace, and the third trace are disposed on the same layer as the first electrode of the transistor.

[0028] In some embodiments, the array substrate provided in the present disclosure further includes the light-transmitting electrode located in the display area, and a transfer electrode disposed on the same layer as the light-transmitting electrode, wherein the transfer electrode connects the gate of the transistor to the second trace.

[0029] In some embodiments, in the array substrate provided in the present disclosure, the transistor is a bottom-gate transistor.

[0030] On the other hand, this disclosure provides a display panel, including the array substrate provided in this disclosure and a counter substrate opposite to the array substrate;

[0031] The opposing substrate includes a black matrix, the black matrix including at least one cutout structure located in the non-display area, the orthographic projection of the at least one cutout structure on the substrate overlaps with the orthographic projection of at least a portion of the transistors on the substrate.

[0032] In some embodiments, in the display panel provided in the present disclosure, the orthogonal projection of the at least one hollow structure on the substrate overlaps with the orthogonal projections of the first transistor, the first sub-transistor, and the second sub-transistor on the substrate, and the orthogonal projection of the at least one hollow structure on the substrate does not overlap with the orthogonal projection of the third sub-transistor on the substrate.

[0033] In some embodiments, in the display panel provided in the present disclosure, the opposing substrate further includes a color resist layer located on the side of the black matrix facing the array substrate, the color resist layer including multiple color resists of different colors, the multiple color resists covering the at least one hollow structure.

[0034] On the other hand, this disclosure provides a display device, including the display panel provided in this disclosure and a backlight module located on the light-incident side of the display panel. Attached Figure Description

[0035] Figure 1 is a schematic diagram of a wiring design for ambient light detection in related technologies;

[0036] Figure 2 is a schematic diagram of an array substrate provided in an embodiment of this disclosure;

[0037] Figure 3 is a magnified structural diagram of region Z1 in Figure 1;

[0038] Figure 4 is an enlarged schematic diagram of the structure of one of the first transistors in Figure 3;

[0039] Figure 5 is an enlarged schematic diagram of the structure at one of the first sub-transistors in Figure 3;

[0040] Figure 6 is an enlarged structural diagram of a second sub-transistor in Figure 3;

[0041] Figure 7 is an enlarged schematic diagram of the structure at one of the third sub-transistors in Figure 3;

[0042] Figure 8 is a schematic diagram of another enlarged structure of region Z1 in Figure 1;

[0043] Figure 9 is an enlarged schematic diagram of the structure at one of the first sub-transistors in Figure 8;

[0044] Figure 10 is an enlarged structural diagram of a second sub-transistor in Figure 8;

[0045] Figure 11 is an enlarged schematic diagram of the structure at a third sub-transistor in Figure 8;

[0046] Figure 12 is an enlarged structural schematic diagram of a display panel provided in an embodiment of the present disclosure in the Z1 region shown in Figure 1;

[0047] Figure 13 is a schematic diagram of another enlarged structure of the display panel provided in the Z1 region shown in Figure 1 according to an embodiment of the present disclosure;

[0048] Figure 14 is an equivalent circuit diagram of the ambient light detection transistor provided in an embodiment of this disclosure;

[0049] Figure 15 is a schematic diagram of another structure of the display panel provided in an embodiment of this disclosure;

[0050] Figure 16 is a schematic diagram of the structure of the display device provided in the embodiment of this disclosure. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that, for clarity, the thickness of layers, films, panels, regions, etc., is enlarged in the drawings. Exemplary embodiments are described in this disclosure with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, deviations from the shape of the figures will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shape of the regions shown in this disclosure, but rather include deviations in shape caused, for example, by manufacturing processes. For example, a region illustrated or described as flat may typically have rough and / or non-linear characteristics; a sharp corner illustrated may be rounded, etc. Therefore, the regions shown in the figures are schematic in nature, and their dimensions and shapes are not intended to illustrate the precise shape of the regions or reflect true proportions; their purpose is merely to illustrate the content of this disclosure. And throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0052] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0053] In the following description, when an element or layer is referred to as "on" or "connected to" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as "located on one side of" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as "directly on" or "directly connected to" another element or layer, no intermediate elements or intermediate layers are present. The term "and / or" includes any and all combinations of one or more of the related listed items.

[0054] In some embodiments, a light-sensing design is added to the non-display area of ​​the display product. Its main function is to monitor changes in ambient light brightness and adjust the backlight (BLU) accordingly to ensure uniform brightness across the entire panel. However, as shown in Figure 1, when multiple transistors (e.g., T1, T2, T3, T4) are used for light sensing, differences in the wiring design of different areas (e.g., areas a, b, c, and d) lead to variations in film thickness. This results in differences in the rubbing environment of the alignment layer in different areas (e.g., areas a, b, c, and d), increasing the risk of rubbing mura.

[0055] To improve the above-mentioned technical problems, this disclosure provides an array substrate. Figure 2 is a structural schematic diagram of the array substrate provided in this disclosure. Figure 3 is an enlarged structural schematic diagram of region Z1 in Figure 1. Figure 4 is an enlarged structural schematic diagram of a first transistor in Figure 3. Figure 5 is an enlarged structural schematic diagram of a first sub-transistor in Figure 3. Figure 6 is an enlarged structural schematic diagram of a second sub-transistor in Figure 3. Figure 7 is an enlarged structural schematic diagram of a third sub-transistor in Figure 3. In the region between the first transistor T1 and the first sub-transistor T21 in Figure 3, "..." indicates that this region has at least one first transistor T1, and the arrangement of the first transistor T1 in this region is the same as the arrangement of the first transistor T1 shown in the figure. In the region between T21 and the second sub-transistor T22, “…” indicates that this region has at least one first sub-transistor T21 and the arrangement of the first sub-transistor T21 in this region is the same as the arrangement of the first sub-transistor T21 in the figure; in the region between the second sub-transistor T22 and the third sub-transistor T23, “…” indicates that this region has at least one second sub-transistor T22 and the arrangement of the second sub-transistor T22 in this region is the same as the arrangement of the second sub-transistor T22 in the figure; in the region of the third sub-transistor T23 away from the second sub-transistor T22, “…” indicates that this region has at least one third sub-transistor T23 and the arrangement of the third sub-transistor T23 in this region is the same as the arrangement of the third sub-transistor T23 in the figure.

[0056] As can be seen from Figures 2 to 7, the array substrate provided in the embodiments of this disclosure includes:

[0057] The substrate 101 includes a display area AA and a non-display area BB located on at least one side of the display area AA. Figure 2 specifically shows a first non-display area BB1, a second non-display area BB2, a third non-display area BB3, and a fourth non-display area BB4 connected sequentially around the display area AA. The first non-display area BB1 includes a fan-out area FA. Optionally, the display area AA includes an array of red sub-pixel areas, green sub-pixel areas, blue sub-pixel areas, etc. The substrate 101 is a substrate that allows visible light to pass through, such as glass, quartz, or plastic.

[0058] Multiple first traces 102 extend along the first direction X in the non-display area BB. It should be understood that when the multiple first traces 102 are located in the third non-display area BB3, the first direction X is horizontal; when the multiple first traces 102 are located in the second non-display area BB2 and / or the fourth non-display area BB4, the first direction X is vertical. This disclosure uses the example of multiple first traces 102 located in the third non-display area BB3 with the first direction X being horizontal for illustration and explanation.

[0059] Multiple transistors 103 are located in the non-display area BB. For example, multiple transistors 103 are located on the side of multiple first traces 102 away from the display area AA, or multiple transistors 103 are located between the multiple first traces 102 and the display area AA. This disclosure illustrates and describes the example of multiple transistors 103 located on the side of multiple first traces 102 away from the display area AA. Optionally, the first terminal D of multiple transistors 103 is electrically connected to multiple first traces 102. Multiple transistors 103 include at least one first transistor T1 and at least one second transistor T2. The orthographic projection of the first transistor T1 in the first direction X overlaps with the orthographic projection of all the first traces 102 in the first direction X, and the orthographic projection of the second transistor T2 in the first direction X overlaps with the orthographic projection of part of the first traces 102 in the first direction X. Optionally, the transistor 103 of this disclosure is a bottom-gate transistor, so as to block backlight through the gate G to prevent backlight from illuminating the active layer A of the transistor 103 and interfering with the detection of ambient light; or, the transistor 103 of this disclosure is a top-gate transistor, and in order to ensure that ambient light can illuminate the active layer A of the transistor 103, the gate G can be made of a light-transmitting conductive material. At the same time, in order to prevent backlight from illuminating the active layer A of the transistor 103 and interfering with the detection of ambient light, a light-shielding element (such as opaque metal, black resin, etc.) can be provided between the active layer A of the transistor 103 and the substrate 101 to block the backlight; or, the transistor 103 of this disclosure is a dual-gate transistor, and in order to ensure that ambient light can illuminate the active layer A of the transistor 103, the top gate can be made of a light-transmitting conductive material. At the same time, in order to prevent backlight from illuminating the active layer A of the transistor 103 and interfering with the detection of ambient light, the bottom gate can be made of a light-shielding metal material.

[0060] At least one first electrode portion D1 is located in the non-display area BB. Optionally, at least one first electrode portion D1 is disposed on the same layer and made of the same material as the first trace 102. The orthographic projection of the first electrode portion D1 on the substrate 101 is located between the orthographic projection of the gate G of the second transistor T2 on the substrate 101 and the orthographic projection of the first trace 102 electrically connected to the second transistor T2 on the substrate 101. The extension direction of the first electrode portion D1 is the same as the extension direction of the first trace 102.

[0061] As can be seen from Figures 2 to 7, in this disclosure, there are four first traces 102 between the gate G of the first transistor T1 and the display area AA, and one to three first traces 102 between the gate G of the second transistor T2 and the display area AA. As a result, before the alignment film is formed, the film thickness of the array substrate in the region between the gate G of the second transistor T2 and the first trace 102 electrically connected to the second transistor T2 is less than the film thickness in the region between the gate G of the first transistor T1 and the first trace 102 electrically connected to the first transistor T1. This will lead to uneven alignment after the alignment layer is formed by subsequent rubbing alignment.

[0062] This disclosure reduces the difference between the film thickness in the region between the gate G of the second transistor T2 and the first trace 102 electrically connected to the second transistor T2, and the film thickness in the region between the gate of the first transistor T1 and the first trace 102 electrically connected to the first transistor T2, by providing a first electrode portion D1 in the region between the gate G of the second transistor T2 and the first trace 102 electrically connected to the second transistor T2. This improves the uniformity of the alignment layer orientation environment and reduces the risk of orientation non-uniformity.

[0063] In some embodiments, in the array substrate provided in the present disclosure, as shown in Figures 3 to 7, the more non-overlapping first traces 102 of the second transistor T2, the greater the distance between the second transistor T2 and its electrically connected first traces 102. This results in a greater difference in film thickness between the region between the gate G of the second transistor T2 and the first traces 102 electrically connected to the second transistor T2 and the region between the gate G of the first transistor T1 and the first traces 102 electrically connected to the first transistor T1. This difference can be reduced by providing more first electrode portions D1. For example, in some embodiments, the number of first electrode portions D1 between the gate G of the second transistor T2 and the first traces 102 electrically connected to the second transistor T2 can be positively correlated with the number of non-overlapping first traces 102 of the second transistor T2.

[0064] In some embodiments, in the array substrate provided in this disclosure, as shown in Figures 3 to 7, the extension line of the first electrode portion D1 between the gate G of the second transistor T2 and the first trace 102 electrically connected to the second transistor T2 can substantially coincide with the extension line of the first trace 102 not electrically connected to the second transistor T2. That is, the relevant linewidth and line spacing of the first electrode portion D1 at the second transistor T2 are approximately the same as the relevant linewidth and line spacing of the first trace 102 at the first transistor T. This can minimize the difference in film thickness between the region between the gate G of the second transistor T2 and the first trace 102 electrically connected to the second transistor T2, and the region between the gate G of the first transistor T1 and the first trace 102 electrically connected to the first transistor T1, ensuring good uniformity of the alignment environment of the alignment layer, thereby reducing or even eliminating the risk of uneven alignment.

[0065] In some embodiments, the linewidth d3 of the first electrode portion D1 is approximately the same as the linewidth d4 of the first trace 102, for example, 14.3 μm; the spacing d5 between the first electrode portion D1 and the adjacent first electrode portion D1 or the adjacent first trace 102 is approximately the same as the spacing d6 between the adjacent first trace 102, for example, 11.7 μm; the spacing d8 between the first electrode portion D1 and the adjacent gate G, and the spacing d9 between the first trace 102 and the adjacent gate G are approximately the same, for example, 3.2 μm.

[0066] It should be noted that in the embodiments provided in this disclosure, due to limitations of process conditions or the influence of other factors such as measurement, "approximately coincident" may exactly coincide, or there may be some deviation (e.g., a deviation of ±2μm). Therefore, as long as the relationship of "approximately coincident" between related features meets the allowable error, it falls within the protection scope of this disclosure. "Approximately identical" may be completely identical, or there may be some deviation (e.g., a deviation of ±5%). Therefore, as long as the relationship of "approximately identical" between related features meets the allowable error, it falls within the protection scope of this disclosure.

[0067] To better understand the arrangement of the first electrode portion D1 between the gate G of the second transistor T2 and the first trace 102 electrically connected to the second transistor T2, this disclosure is illustrated with examples in Figures 3 to 7.

[0068] As shown in Figures 3 to 7, the multiple first traces 102 include a first sub-trace 1021, a second sub-trace 1022, a third sub-trace 1023, and a fourth sub-trace 1024, and at least one second transistor T2 includes at least one first sub-transistor T21, at least one second sub-transistor T22, and at least one third sub-transistor T23; wherein:

[0069] The first terminal D of the first transistor T1 is electrically connected to the first sub-line 1021. The orthographic projection of the first transistor T1 in the first direction X overlaps with the orthographic projections of the first sub-line 1021, the second sub-line 1022, the third sub-line 1023, and the fourth sub-line 1024 in the first direction X.

[0070] The first electrode D of the first sub-transistor T21 is electrically connected to the second sub-line 1022. The orthographic projection of the first sub-transistor T21 in the first direction X overlaps with the orthographic projections of the second sub-line 1022, the third sub-line 1023, and the fourth sub-line 1024 in the first direction X. The gate G of the first sub-transistor T21 and the second sub-line 1022 include a first electrode portion D1. The extension line of the first electrode portion D1 is approximately coincident with the extension line of the first sub-line 1021.

[0071] The first electrode D of the second sub-transistor T22 is electrically connected to the third sub-line 1023. The orthographic projection of the second sub-transistor T22 in the first direction X overlaps with the orthographic projections of the third sub-line 1023 and the fourth sub-line 1024 in the first direction X. The gate G of the second sub-transistor T22 and the third sub-line 1023 include two first electrode portions D1. The extension line of one of the first electrode portions D1 is approximately coincident with the extension line of the first sub-line 1021, and the extension line of the other first electrode portion D2 is approximately coincident with the extension line of the second sub-line 1022.

[0072] The first electrode D of the third sub-transistor T23 is electrically connected to the fourth sub-line 1024. The orthographic projection of the third sub-transistor T23 in the first direction X and the orthographic projection of the fourth sub-line 1024 in the first direction X overlap each other. The gate G of the third sub-transistor T23 and the fourth sub-line 1024 include three first electrode portions D1. The extension lines of the three first electrode portions D1 are approximately coincident with the extension lines of the first sub-line 1021, the second sub-line 1022, and the third sub-line 1023, respectively.

[0073] In some embodiments, in the array substrate provided in the present disclosure, as shown in FIGS. 5 to 11, the first electrode D of transistor 103 includes a second electrode portion D2 extending along a first direction X. The orthographic projection of the second electrode portion D2 on the substrate 101 overlaps with the orthographic projection of the gate G of transistor 103 on the substrate 101. The second electrode portion D2 includes a first boundary (i.e., the boundary contacted by the left end of d1) on the side away from the second electrode S of transistor 103, and the second electrode S of transistor 103 includes a second boundary (i.e., the boundary contacted by the left end of d1) on the side away from the second electrode portion D2. The first electrode portion D1 extends along the second direction Y. One of the two boundaries (e.g., the boundary where the left end of d2 contacts) is approximately collinear with the first boundary (i.e., the boundary where the left end of d1 contacts), or is located near the extension of the first boundary (i.e., the boundary where the left end of d1 contacts) on the side of the first boundary (i.e., the boundary where the left end of d1 contacts) close to the second boundary (i.e., the boundary where the right end of d1 contacts). The other boundary (e.g., the boundary where the right end of d2 contacts) is approximately collinear with the second boundary (i.e., the boundary where the left end of d1 contacts). The second direction intersects the first direction X. This arrangement avoids short-circuiting between the first electrode portion D1 and the adjacent transistor 103 due to a large d2, and also avoids reducing the improvement effect on the alignment environment due to a short d2.

[0074] In some embodiments, d1 and d2 in Figures 5 to 7 are approximately the same, for example, both are 86 μm; d1 and d2 in Figures 9 to 11 satisfy the relationship d2 = d1 - d7 - Δd, where d7 is the linewidth of the third electrode portion D3 which is integrally disposed with the second electrode portion D2 and extends along the second direction Y, and Δd is the process limit value that can avoid short circuit between the second electrode portion D2 and the first electrode portion D1. Optionally, if d1 is 86 μm, d7 is 10 μm, and Δd is 2 μm, then d2 is 74 μm.

[0075] In some embodiments, in the array substrate provided in the present disclosure, as shown in FIG3 to FIG7, the first electrode D of transistor 103 may further include a third electrode portion D3 extending along the second direction Y. The third electrode portion D3 of the first transistor T1 is connected between the second electrode portion D2 and the first trace 102 (e.g., the first sub-trace 1021). Optionally, for the purpose of simplifying the design, the third electrode portion D3 of the first transistor T1, the second electrode portion D2, and the first trace 102 (e.g., the first sub-trace 1021) electrically connected to the third transistor T1 are integrally disposed.

[0076] In some embodiments, in the array substrate provided in the present disclosure, as shown in FIGS. 5 to 7, the first electrode D of the second transistor T2 includes a first electrode portion D1. In other words, the first electrode portion D1 may belong to the first electrode D of the second transistor T2. In this case, the third electrode portion D3 of the second transistor T2 may be connected between the second electrode portion D2 and the first electrode portion D1, between adjacent first electrode portions D1, and between the first electrode portion D1 and the first trace 102. For example, the third electrode portion D3 of the first sub-transistor T21 is connected between the second electrode portion D2 and the first electrode portion D1, and between the first electrode portion D1 and the second sub-trace 1022. Optionally, to simplify the process, the first electrode portion D1, the second electrode portion D2, the third electrode portion D3, and the second sub-trace 1022 of the first sub-transistor T21 are integrally formed. For example, the third electrode portion D3 of the second sub-transistor T22 is connected between the second electrode portion D2 and the first electrode portion D1, between adjacent first electrode portions D1, and between the first electrode portion D1 and the third sub-line 1023. Optionally, to simplify the process, the first electrode portion D1, the second electrode portion D2, the third electrode portion D3, and the third sub-line 1023 of the second sub-transistor T22 are integrally formed. As another example, the third electrode portion D3 of the third sub-transistor T23 is connected between the second electrode portion D2 and the first electrode portion D1, between adjacent first electrode portions D1, and between the first electrode portion D1 and the fourth sub-line 1024. Optionally, to simplify the process, the first electrode portion D1, the second electrode portion D2, the third electrode portion D3, and the fourth sub-line 1024 of the third sub-transistor T23 are integrally formed.

[0077] In some instances, in the array substrate provided in the embodiments of this disclosure, as shown in Figures 8 to 11, the first electrode portion D1 can be disposed independently of the first electrode D of the second transistor T2. For example, the first electrode portion D1 can be floating. In this case, the third electrode portion D3 of the second transistor T2 is connected between the second electrode portion D2 and the first trace 102. For example, the third electrode portion D3 of the first sub-transistor T21 is connected between the second electrode portion D2 and the second sub-trace 1022. In some embodiments, the third electrode portion D3, the second electrode portion D2, and the second sub-trace 1022 of the first sub-transistor T21 can be integrally disposed. As another example, the third electrode portion D3 of the second sub-transistor T22 is connected between the second electrode portion D2 and the third sub-trace 1023. In some embodiments, the third electrode portion D3, the second electrode portion D2, and the third sub-trace 1023 of the second sub-transistor T22 can be integrally disposed. For example, the third electrode portion D3 of the third sub-transistor T23 is connected between the second electrode portion D2 and the fourth sub-line 1024. In some embodiments, the third electrode portion D3, the second electrode portion D2, and the fourth sub-line 1024 of the third sub-transistor T23 can be integrally formed.

[0078] In some instances, in the array substrate provided in the embodiments of this disclosure, as shown in Figures 3 to 11, the second electrode S of transistor 103 includes a U-shaped electrode portion S1, and a portion of the second electrode portion D2 is located within the opening of the U-shaped electrode portion S1. Compared to transistors with a "1"-shaped pattern, transistors with a U-shaped pattern in this disclosure have more stable performance, and since the extension direction of the U-shaped electrode portion S1 is the same as the extension direction of the first trace 102, the size of the U-shaped electrode portion S1 in the second direction Y can be smaller, reducing the space occupied by the U-shaped electrode portion S1 in the second direction Y, which is beneficial for narrow bezel design.

[0079] In some embodiments, the array substrate provided in this disclosure, as shown in Figures 3 to 10, may further include a second trace 104 and a third trace 105 extending along a first direction X. The gates G of a plurality of transistors 103 are electrically connected to the second trace 104, and the second terminals S of the plurality of transistors 103 are electrically connected to the third trace 105. In some embodiments, when it is necessary to detect ambient light brightness, voltage can be applied to the gates G and second terminals S of transistors 103 through the second trace 104 and the third trace 105, respectively, and the current value generated by ambient light irradiation can be detected through the first trace 102 electrically connected to the first terminal D of transistors 103. The greater the ambient light brightness, the greater the corresponding current value.

[0080] In some embodiments, the first trace 102, the second trace 104, and the third trace 105 may be disposed on the same layer and with the same material as the first electrode D of the transistor 103. The gate G of the transistor 103 may be electrically connected to the second trace 104 through the transition electrode 106. Optionally, the transition electrode 106 may be disposed on the same layer and with the same material as the light-transmitting electrode (e.g., pixel electrode, common electrode, etc.) of the display area AA.

[0081] In some embodiments, as shown in FIG2, the array substrate provided in this disclosure may further include a ground line 107 disposed in the non-display area BB, a common electrode trace 108, a short-circuit ring 109, a common electrode feedback line 110, a detection line 111, an electrostatic discharge structure 112, a gate drive circuit GOA, etc. Other essential components of the display panel are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0082] Based on the same inventive concept, this disclosure provides a display panel, as shown in Figures 12 to 15, including the array substrate 001 provided in this disclosure and a counter substrate 002 opposite to the array substrate 001; wherein, the counter substrate 002 includes a black matrix 201, the black matrix 201 includes at least one cutout structure k located in the non-display area BB, the orthographic projection of the cutout structure k on the substrate 101 overlaps with the orthographic projection of at least a portion of the transistors 103 on the substrate 101, so as to ensure that after the array substrate 001 and the counter substrate 002 are aligned, ambient light can pass through the cutout structure k to illuminate the transistors 103.

[0083] In some embodiments, as shown in Figures 12 and 13, the orthographic projection of the cutout structure k on the substrate 101 overlaps with the orthographic projections of the active layer A of the first transistor T1, the active layer A of the first sub-transistor T21, and the active layer A of the second sub-transistor T22 on the substrate 101 (for example, the orthographic projections of the active layer A of the first transistor T1, the active layer A of the first sub-transistor T21, and the active layer A of the second sub-transistor T22 on the substrate 101 are located within the orthographic projection of the cutout structure k on the substrate 101), and the orthographic projection of the cutout structure k on the substrate 101 does not overlap with the orthographic projection of the active layer A of the third sub-transistor T23 on the substrate 101. In this way, the third sub-transistor T23 can serve as a reference. Since the size and shape of the third sub-transistor T23 are the same as those of the first transistor T1, the first sub-transistor T21, and the second sub-transistor T22, and the second trace 104 applies a uniform gate voltage to the first transistor T1, the first sub-transistor T21, the second sub-transistor T22, and the third sub-transistor T23, and the third trace 105 applies a uniform voltage to the second electrode of the first transistor T1, the first sub-transistor T21, the second sub-transistor T22, and the third sub-transistor T23, the influence of transistor structure, voltage application, temperature, and other factors on the detection current is eliminated. Based on this, the current values ​​of the first transistor T1, the first sub-transistor T21, and the second sub-transistor T22 are respectively subtracted from the current value of the third sub-transistor T23 to obtain the current value generated by ambient light illumination, thereby realizing the detection of ambient light brightness.

[0084] It should be noted that one hollow structure k can correspond to the first transistor T1, the first sub-transistor T21, the second sub-transistor T22, and the third sub-transistor T23; or, there can be multiple hollow structures k, and the multiple hollow structures k can correspond one-to-one with the first transistor T1, the first sub-transistor T21, the second sub-transistor T22, and the third sub-transistor T23, or, the first hollow structure k corresponds to all the first transistors T1, the second hollow structure k corresponds to all the first sub-transistors T21, and the third hollow structure k corresponds to all the second sub-transistors T22. This disclosure does not make any specific limitations.

[0085] In some embodiments, as shown in Figures 12 to 14, the opposing substrate 002 further includes a color resist layer 202 located on the side of the black matrix 201 facing the array substrate 001. The color resist layer 202 includes multiple color resists of different colors, such as a first color resist R, a second color resist G, and a third color resist B. These multiple color resists can cover the cutout structure k. Optionally, the orthogonal projection of the first color resist R onto the substrate 101 covers the orthogonal projection of the first transistor T1 onto the substrate 101, the orthogonal projection of the second color resist G onto the substrate 101 covers the orthogonal projection of the first sub-transistor T21 onto the substrate 101, and the orthogonal projection of the third color resist B onto the substrate 101 covers the orthogonal projection of the second sub-transistor T22 onto the substrate 101. In some embodiments, the first color resist R can be a red color resist, the second color resist G can be green, and the third color resist B can be a blue color resist. The carrier concentration in the channels of the first transistor T1, the first sub-transistor T21, and the second sub-transistor T22 is greatly affected by illumination. When a fixed voltage is applied, the current in the channel changes as the brightness of the light illuminating the channel varies. By combining the first color resistor R, the second color resistor G, and the third color resistor B, the proportions of red, green, and blue light in ambient light can be detected, thus enabling the detection of both ambient light brightness and color temperature.

[0086] In some embodiments, the current values ​​of the first transistor T1, the first sub-transistor T21, the second sub-transistor T22, and the third sub-transistor T23 can be fed back to the system on chip (SOC) or the logic board (Timer Control Register, TCON) for processing, and the brightness and / or color temperature of the backlight module can be adjusted according to the processing results.

[0087] In some embodiments of the present disclosure, as shown in FIG15, a liquid crystal layer 003 may be disposed between an array substrate 001 and a counter substrate 002. A first polarizer 004 may be disposed on the side of the array substrate 001 away from the counter substrate 002, and a second polarizer 005 may be disposed on the side of the counter substrate 002 away from the array substrate 001. The polarization direction of the first polarizer 004 and the polarization direction of the second polarizer 005 are perpendicular to each other. Other essential components of the display panel are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the present disclosure.

[0088] Based on the same inventive concept, this disclosure provides a display device, as shown in FIG16, including the display panel PNL provided in this disclosure and a backlight module BLU located on the light-incident side of the display panel PNL. The backlight module BLU can be a direct-lit backlight module or an edge-lit backlight module. Optionally, the edge-lit backlight module may include LED strips, stacked reflective sheets, light guide plates, diffusers, prism groups, etc., with the LED strips located on one side of the thickness direction of the light guide plate. The direct-lit backlight module may include a matrix light source, a reflective sheet, a diffuser plate, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, with the reflective sheet including openings directly opposite the positions of the LEDs in the matrix light source. The LEDs in the LED strips and the LEDs in the matrix light source can be light-emitting devices (LEDs), such as quantum dot light-emitting devices.

[0089] In some embodiments, the LEDs can also be micro-light-emitting devices (such as Mini LEDs and Micro LEDs). Sub-millimeter or even micrometer-scale micro-light-emitting devices, like organic light-emitting devices (OLEDs), are self-emissive devices. Like OLEDs, they offer advantages such as high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic light-emitting devices emit light based on more stable and lower-resistance metal semiconductors, they offer advantages over organic light-emitting devices (based on organic materials) in terms of lower power consumption, greater resistance to high and low temperatures, and longer lifespan. Moreover, when micro-light-emitting devices are used as backlights, they can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while also solving the glare problem caused by traditional dynamic backlighting between bright and dark areas of the screen, thus optimizing the visual experience.

[0090] In some embodiments, the display device provided in this disclosure can be any product or component with display function, such as a monitor, projector, 3D printer, virtual reality device, mobile phone, tablet computer, television, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, or personal digital assistant. Optionally, the display device provided in this disclosure includes, but is not limited to, components such as: radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, and control chip. Optionally, the control chip is a central processing unit, digital signal processor, system-on-a-chip (SoC), etc. For example, the control chip may also include memory, a power module, etc., and achieve power supply and signal input / output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer-executable code. The hardware circuit may include conventional very large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc. Furthermore, the above structure does not constitute a limitation on the display device provided in the embodiments of this disclosure. In other words, the display device provided in the embodiments of this disclosure may include more or fewer of the above components, or combine certain components, or arrange different components.

[0091] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0092] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. An array substrate, wherein, include: A substrate, the substrate including a display area and a non-display area located on at least one side of the display area; Multiple first traces extend along a first direction in the non-display area; Multiple transistors are located in the non-display area. The first electrode of the multiple transistors is electrically connected to the multiple first traces. The multiple transistors include at least one first transistor and at least one second transistor. The orthographic projection of the first transistor in the first direction overlaps with the orthographic projection of the multiple first traces in the first direction. The orthographic projection of the second transistor in the first direction overlaps with the orthographic projection of a portion of the first traces in the first direction. At least one first electrode portion is located in the non-display area, and the orthographic projection of the at least one first electrode portion on the substrate is located between the orthographic projection of the gate of the second transistor on the substrate and the orthographic projection of the first trace electrically connected to the second transistor on the substrate, and the extension direction of the first electrode portion is the same as the extension direction of the first trace.

2. The array substrate as claimed in claim 1, wherein, The number of first electrode portions between the gate of the second transistor and the first trace electrically connected to the second transistor is positively correlated with the number of first traces of the second transistor that do not overlap.

3. The array substrate as described in claim 2, wherein, The extension line of the first electrode portion between the gate of the second transistor and the first trace electrically connected to the second transistor substantially coincides with the extension line of the first trace where the at least one first electrode portion is not electrically connected.

4. The array substrate according to any one of claims 1 to 3, wherein, The plurality of first traces include first sub-traces and second sub-traces, and the at least one second transistor includes at least one first sub-transistor; The first electrode of the first transistor is electrically connected to the first sub-trace, and the orthographic projection of the first transistor in the first direction overlaps with the orthographic projection of the plurality of first traces in the first direction. The first electrode of the first sub-transistor is electrically connected to the second sub-line. The orthographic projection of the first sub-transistor in the first direction overlaps with the orthographic projection of other first lines in the first direction besides the first sub-line. The gate of the first sub-transistor and the second sub-line include a first electrode portion. The extension line of the first electrode portion substantially coincides with the extension line of the first sub-line.

5. The array substrate as claimed in claim 4, wherein, The plurality of first traces further include a third sub-trace, and the at least one second transistor further includes at least one second sub-transistor; The first electrode of the second sub-transistor is electrically connected to the third sub-line. The orthographic projection of the second sub-transistor in the first direction overlaps with the orthographic projections of the first sub-line and other first lines besides the second sub-line in the first direction. The gate of the second sub-transistor includes two first electrode portions between it and the third sub-line. The extension line of one of the first electrode portions substantially coincides with the extension line of the first sub-line, and the extension line of the other first electrode portion substantially coincides with the extension line of the second sub-line.

6. The array substrate as claimed in claim 5, wherein, The plurality of first traces further includes a fourth sub-trace, and the at least one transistor further includes at least one third sub-transistor; The first electrode of the third sub-transistor is electrically connected to the fourth sub-line. The orthographic projection of the third sub-transistor in the first direction overlaps with the orthographic projection of the fourth sub-line in the first direction. The gate of the third sub-transistor and the fourth sub-line include three first electrode portions. The extension lines of the three first electrode portions are substantially coincident with the extension lines of the first sub-line, the second sub-line, and the third sub-line, respectively.

7. The array substrate according to any one of claims 1 to 6, wherein, The first electrode of the transistor includes a second electrode portion extending along the first direction, wherein the orthographic projection of the second electrode portion on the substrate overlaps with the orthographic projection of the gate of the transistor on the substrate. The second electrode portion includes a first boundary on the side away from the second electrode of the transistor, and the second electrode of the transistor includes a second boundary on the side away from the second electrode portion; One of the two boundaries of the first electrode portion extending along the second direction is substantially collinear with the first boundary, or is adjacent to the extension of the first boundary on the side of the first boundary near the second boundary. One direction is set as a long line, the other is approximately collinear with the second boundary, and the second direction intersects the first direction.

8. The array substrate as claimed in claim 7, wherein, The first electrode of the transistor further includes a third electrode portion extending along a second direction, wherein the third electrode portion of the first transistor is connected between the second electrode portion and the first trace.

9. The array substrate as claimed in claim 8, wherein, The first electrode of the second transistor includes the first electrode portion, and the third electrode portion of the second transistor is connected between the second electrode portion and the first electrode portion, between adjacent first electrode portions, and between the first electrode portion and the first trace.

10. The array substrate as claimed in claim 8, wherein, The first electrode portion is floating, and the third electrode portion of the second transistor is connected between the second electrode portion and the first trace.

11. The array substrate according to any one of claims 7 to 10, wherein, The second electrode of the transistor includes a U-shaped electrode portion, and a portion of the second electrode portion is located within the opening of the U-shaped electrode portion.

12. The array substrate according to any one of claims 1 to 11, wherein, It also includes a second trace and a third trace extending along the first direction, wherein the gates of the plurality of transistors are electrically connected to the second trace, and the second terminals of the plurality of transistors are electrically connected to the third trace.

13. The array substrate as claimed in claim 12, wherein, The first trace, the second trace, and the third trace are disposed on the same layer as the first electrode of the transistor.

14. The array substrate as claimed in claim 12 or 13, wherein, It also includes the light-transmitting electrode located in the display area, and a transfer electrode disposed on the same layer as the light-transmitting electrode, the transfer electrode connecting the gate of the transistor and the second trace.

15. The array substrate according to any one of claims 1 to 14, wherein, The transistor is a bottom-gate transistor.

16. A display panel, wherein, Includes the array substrate as described in any one of claims 1 to 15, and a counter substrate opposite to the array substrate; The opposing substrate includes a black matrix, the black matrix including at least one [missing information] located in the non-display area. A hollow structure, wherein the orthogonal projection of the at least one hollow structure on the substrate overlaps with the orthogonal projection of at least a portion of the transistors on the substrate.

17. The display panel as claimed in claim 16, wherein, The orthographic projection of the at least one hollow structure on the substrate overlaps with the orthographic projections of the first transistor, the first sub-transistor, and the second sub-transistor on the substrate, and the orthographic projection of the at least one hollow structure on the substrate does not overlap with the orthographic projection of the third sub-transistor on the substrate.

18. The display panel as claimed in claim 17, wherein, The opposing substrate further includes a color resist layer located on the side of the black matrix facing the array substrate. The color resist layer includes multiple color resists of different colors, and the multiple color resists cover the at least one cutout structure.

19. A display device, wherein, It includes a display panel as described in any one of claims 16 to 18, and a backlight module located on the light-incident side of the display panel.

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