Shift register units, gate driver circuit, display panel, and driving method therefor

Abstract

Shift register units, a gate driver circuit, a display panel, and a driving method therefor. The shift register units are applied to the gate driver circuit. The gate driver circuit comprises a plurality of cascaded shift register units, the shift register units comprising: a first output circuit (1) and a reset circuit (3), the first output circuit (1) being connected to a second control node (PD2) and a first output terminal (OUT1), the first output circuit (1) being configured for responding to a signal of the second control node (PD2) so as to input a signal to the first output terminal (OUT1), and the first output terminal (OUT1) being configured for connecting to an input signal terminal of a lower-stage shift register unit; the reset circuit (3), which is connected to the second control node (PD2), is configured for responding to a reset signal so as to input a signal to the second control node (PD2). A display panel using shift register units can prevent abnormal driving.

Description

Shift register unit, gate drive circuit, display panel and its driving method Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a shift register unit, a gate driving circuit, a display panel, and a driving method thereof. Background Technology

[0002] In related technologies, in order to reduce the power consumption of the gate drive circuit, the clock signal pulse frequency of the shift register unit corresponding to the local low-frequency refresh area of ​​the display panel is adjusted. However, the local adjustment of the clock signal pulse frequency can cause abnormal driving of the display panel.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art.

[0004] Summary of the Invention

[0005] According to one aspect of this disclosure, a shift register unit is provided, the shift register unit being applied to a gate driving circuit, the gate driving circuit including a plurality of cascaded shift register units, the shift register unit comprising:

[0006] A first output circuit is connected to a second control node and a first output terminal. The first output circuit is used to respond to the signal of the second control node to input a signal to the first output terminal. The first output terminal is used to connect to the input signal terminal of the next-level shift register unit.

[0007] A reset circuit is connected to the second control node, and the reset circuit is used to respond to a reset signal to input a signal to the second control node.

[0008] In an exemplary embodiment of this disclosure, the first output circuit is capable of responding to the signal of the second control node to input a valid signal to the first output terminal;

[0009] The reset circuit is used to respond to a reset signal to input an invalid signal to the second control node.

[0010] In an exemplary embodiment of this disclosure, the first output circuit is further connected to a first control node, and the first output circuit is further configured to respond to a signal from the first control node to input a signal to the first output terminal.

[0011] The reset circuit is also connected to the first control node, and the reset circuit is also used to respond to a reset signal to input a signal to the first control node.

[0012] In an exemplary embodiment of this disclosure, the first output circuit is capable of responding to a signal from the first control node to input an invalid level signal to the first output terminal;

[0013] The reset circuit is also used to respond to a reset signal to input a valid level signal to the first control node.

[0014] In one exemplary embodiment of this disclosure, the shift register unit further includes:

[0015] A first input circuit is connected to an input signal terminal and a first node. The first input circuit is used to respond to a control signal to transmit the signal from the input signal terminal to the first node.

[0016] The reset circuit includes:

[0017] A first reset circuit, comprising a first sub-reset circuit and a second sub-reset circuit, wherein the first sub-reset circuit is connected to the first node, the third control node, and a first reset signal terminal, and is used to respond to the signal of the first reset signal terminal to connect the first node and the third control node; and the second sub-reset circuit is connected to the first reset signal terminal and the third control node, and is used to respond to the signal of the first reset signal terminal to input an invalid level signal to the third control node.

[0018] The first sub-reset circuit and the second sub-reset circuit have different conduction level polarities, and the third control node is connected to the second control node.

[0019] In one exemplary embodiment of this disclosure, the first sub-reset circuit includes:

[0020] The eleventh transistor has its first terminal connected to the first node, its second terminal connected to the third control node, and its gate connected to the first reset signal terminal.

[0021] The second sub-reset circuit is also connected to the first power supply terminal. The second sub-reset circuit is used to respond to the signal from the first reset signal terminal by inputting an invalid level signal to the third control node using the first power supply terminal. The second sub-reset circuit includes:

[0022] The twelfth transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the third control node, and its gate connected to the first reset signal terminal.

[0023] The eleventh and twelfth transistors have different conduction level polarities.

[0024] In one exemplary embodiment of this disclosure, the shift register unit further includes:

[0025] A first input circuit is connected to an input signal terminal and a first node. The first input circuit is used to respond to a control signal to transmit the signal from the input signal terminal to the first node. The first node is connected to the third control node, and the third control node is connected to the second control node.

[0026] The reset circuit includes:

[0027] A first reset circuit is connected to a first reset signal terminal, a second reset signal terminal, a first output terminal, and a first node. The first reset circuit is used to respond to the signal of the first reset signal terminal to transmit the signal of the first output terminal to the second reset signal terminal, and to respond to the signal of the second reset signal terminal to input an invalid level signal to the first node.

[0028] In one exemplary embodiment of this disclosure, the first reset circuit is further connected to an input signal terminal, and the first reset circuit is used to input an invalid level signal to the first node using the input signal terminal in response to the signal from the second reset signal terminal.

[0029] In one exemplary embodiment of this disclosure, the first reset circuit is further connected to a first power supply terminal, and the first reset circuit is used to input an invalid level signal to the first node using the first power supply terminal in response to the signal of the second reset signal terminal.

[0030] In one exemplary embodiment of this disclosure, the first reset circuit includes:

[0031] The eleventh transistor has its first terminal connected to the input signal terminal, its second terminal connected to the first node, and its gate connected to the second reset signal terminal.

[0032] The twelfth transistor has its first terminal connected to the first output terminal, its second terminal connected to the second reset signal terminal, and its gate connected to the first reset signal terminal.

[0033] In one exemplary embodiment of this disclosure, the first reset circuit includes:

[0034] The eleventh transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the first node, and its gate connected to the second reset signal terminal.

[0035] The twelfth transistor has its first terminal connected to the first output terminal, its second terminal connected to the second reset signal terminal, and its gate connected to the first reset signal terminal.

[0036] In one exemplary embodiment of this disclosure, the reset circuit further includes:

[0037] The second reset circuit is connected to the second power supply terminal, the first reset signal terminal, and the first control node. The second reset circuit is used to respond to the signal of the first reset signal terminal to transmit the effective level signal of the second power supply terminal to the first control node.

[0038] In one exemplary embodiment of this disclosure, the second reset circuit includes:

[0039] The thirteenth transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the first control node, and its gate connected to the first reset signal terminal.

[0040] In one exemplary embodiment of this disclosure, the reset circuit further includes:

[0041] The second reset circuit is connected to the second power supply terminal, the second reset signal terminal, and the first control node. The second reset circuit is used to respond to the signal of the second reset signal terminal to transmit the effective level signal of the second power supply terminal to the first control node.

[0042] In one exemplary embodiment of this disclosure, the second reset circuit includes:

[0043] The thirteenth transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the first control node, and its gate connected to the second reset signal terminal.

[0044] In one exemplary embodiment of this disclosure, the first output circuit is further connected to a second clock signal terminal, and the first output circuit is used to input an effective level to the first output terminal using the second clock signal terminal in response to the signal of the second control node;

[0045] The shift register unit further includes:

[0046] A first input circuit is connected to an input signal terminal, a first node, and a first clock signal terminal. The first input circuit is used to respond to the signal of the first clock signal terminal to transmit the signal of the input signal terminal to the first node. The first node is connected to the third control node, and the third control node is connected to the second control node.

[0047] The second input circuit is connected to the second power supply terminal, the first control node, and the first clock signal terminal. The second input circuit is used to respond to the signal of the first clock signal terminal to transmit the signal of the second power supply terminal to the first control node.

[0048] A first control circuit is connected to a first clock signal terminal, a third control node, and a first control node. The first control circuit is used to respond to the signal of the third control node to transmit the signal of the first clock signal terminal to the first control node.

[0049] The second control circuit is connected to the first power supply terminal, the second clock signal terminal, the first control node, and the third control node. The second control circuit is used to respond to the signals of the second clock signal terminal and the first control node to transmit the signal of the first power supply terminal to the third control node.

[0050] An isolation circuit is provided to connect the third control node and the second control node in response to a control signal.

[0051] In one exemplary embodiment of this disclosure, the first output circuit includes:

[0052] The fourth transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the first output terminal, and its gate connected to the first control node.

[0053] The first capacitor has a first electrode connected to the first power supply terminal and a second electrode connected to the first control node.

[0054] The fifth transistor has its first terminal connected to the second clock signal terminal, its second terminal connected to the first output terminal, and its gate connected to the second control node.

[0055] The second capacitor has its first electrode connected to the second control node and its second electrode connected to the first output terminal.

[0056] The first input circuit includes:

[0057] The first transistor has a first terminal connected to the input signal terminal, a second terminal connected to the first node, and a gate connected to the first clock signal terminal.

[0058] The second input circuit includes:

[0059] The third transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the first control node, and its gate connected to the first clock signal terminal.

[0060] The first control circuit includes:

[0061] The second transistor has a first terminal connected to the first clock signal terminal, a second terminal connected to the first control node, and a gate connected to the third control node.

[0062] The second control circuit includes:

[0063] The sixth transistor has its first terminal connected to the first power supply terminal and its gate connected to the first control node.

[0064] The seventh transistor has its first terminal connected to the second terminal of the sixth transistor, the second terminal connected to the third control node, and its gate connected to the second clock signal terminal.

[0065] The isolation circuit is also connected to the second power supply terminal. The isolation circuit is used to respond to signals from the second power supply terminal to connect the third control node and the second control node. The isolation circuit includes:

[0066] The eighth transistor has its first terminal connected to the third control node, its second terminal connected to the second control node, and its gate connected to the second power supply terminal.

[0067] In one exemplary embodiment of this disclosure, the first output circuit is further connected to a second clock signal terminal, and the first output circuit is used to input an effective level to the first output terminal using the second clock signal terminal in response to the signal of the second control node;

[0068] The shift register unit further includes:

[0069] A first input circuit is connected to an input signal terminal, a first node, and a first clock signal terminal. The first input circuit is used to respond to the signal of the first clock signal terminal to transmit the signal of the input signal terminal to the first node. The first node is connected to the third control node, and the third control node is connected to the second control node.

[0070] The second input circuit is connected to the second power supply terminal, the first control node, and the third clock signal terminal. The second input circuit is used to respond to the signal of the third clock signal terminal to transmit the signal of the second power supply terminal to the first control node.

[0071] A first control circuit is connected to a third clock signal terminal, a third control node, and a first control node. The first control circuit is used to respond to the signal of the third control node to transmit the signal of the third clock signal terminal to the first control node.

[0072] The second control circuit is connected to the first power supply terminal, the second clock signal terminal, the first control node, and the third control node. The second control circuit is used to respond to the signals of the second clock signal terminal and the first control node to transmit the signal of the first power supply terminal to the third control node.

[0073] An isolation circuit is provided to connect the third control node and the second control node in response to a control signal.

[0074] In one exemplary embodiment of this disclosure, the first output circuit includes:

[0075] The fourth transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the first output terminal, and its gate connected to the first control node.

[0076] The first capacitor has a first electrode connected to the first power supply terminal and a second electrode connected to the first control node.

[0077] The fifth transistor has its first terminal connected to the second clock signal terminal, its second terminal connected to the first output terminal, and its gate connected to the second control node.

[0078] The second capacitor has its first electrode connected to the second control node and its second electrode connected to the first output terminal.

[0079] The third capacitor has its first electrode connected to the second power supply terminal and its second electrode connected to the first output terminal.

[0080] The first input circuit includes:

[0081] The first transistor has a first terminal connected to the input signal terminal, a second terminal connected to the first node, and a gate connected to the first clock signal terminal.

[0082] The second input circuit includes:

[0083] The third transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the first control node, and its gate connected to the third clock signal terminal.

[0084] The first control circuit includes:

[0085] The second transistor has its first terminal connected to the third clock signal terminal, its second terminal connected to the first control node, and its gate connected to the third control node.

[0086] The second control circuit includes:

[0087] The sixth transistor has its first terminal connected to the first power supply terminal and its gate connected to the first control node.

[0088] The seventh transistor has its first terminal connected to the second terminal of the sixth transistor, the second terminal connected to the third control node, and its gate connected to the second clock signal terminal.

[0089] The isolation circuit is also connected to the second power supply terminal. The isolation circuit is used to respond to signals from the second power supply terminal to connect the third control node and the second control node. The isolation circuit includes:

[0090] The eighth transistor has its first terminal connected to the third control node, its second terminal connected to the second control node, and its gate connected to the second power supply terminal.

[0091] In one exemplary embodiment of this disclosure, the first output circuit is further connected to a second clock signal terminal, and the first output circuit is used to input an effective level to the first output terminal using the second clock signal terminal in response to the signal of the second control node;

[0092] The shift register unit further includes:

[0093] A first input circuit is connected to an input signal terminal, a second node, a first node, and a first clock signal terminal. The first input circuit is used to respond to a signal from the first clock signal terminal to transmit the signal from the input signal terminal to the second node, and to respond to a signal from the first clock signal terminal to transmit the signal from the second node to the first node. The first node is connected to the third control node, and the third control node is connected to the second control node.

[0094] The second input circuit is connected to an input signal terminal, a first power supply terminal, a first control node, a second power supply terminal, and a third clock signal terminal. The second input circuit is used to respond to the signal of the input signal terminal to transmit the signal of the first power supply terminal to the first control node, and to respond to the signal of the third clock signal terminal to transmit the signal of the second power supply terminal to the first control node.

[0095] The first leakage protection circuit is connected to the second clock signal terminal, the second node, and the first output terminal. The first leakage protection circuit is used to respond to the signal of the first output terminal to transmit the signal of the second clock signal terminal to the second node.

[0096] A first control circuit is connected to a first power supply terminal, a first control node, a third control node, and a fourth control node. The first control circuit is used to respond to a signal from the first control node to transmit a signal from the first power supply terminal to the fourth control node, and to respond to a signal from the first control node to transmit a signal from the fourth control node to the third control node.

[0097] The second leakage protection circuit is connected to the third control node, the second power supply terminal, and the fourth control node. The second leakage protection circuit is used to respond to the signal of the third control node to transmit the signal of the second power supply terminal to the fourth control node.

[0098] In one exemplary embodiment of this disclosure, the first output circuit includes:

[0099] The fourth transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the first output terminal, and its gate connected to the first control node.

[0100] The first capacitor has its first electrode connected to the first power supply terminal and its second electrode connected to the first control node.

[0101] The fifth transistor has its first terminal connected to the second clock signal terminal, its second terminal connected to the first output terminal, and its gate connected to the second control node.

[0102] The second capacitor has its first electrode connected to the first control node and its second electrode connected to the first output terminal.

[0103] The first input circuit includes:

[0104] The fourteenth transistor has its first terminal connected to the input signal terminal, its second terminal connected to the second node, and its gate connected to the first clock signal terminal.

[0105] The first transistor has a first terminal connected to the second node, a second terminal connected to the first node, and a gate connected to the first clock signal terminal.

[0106] The second input circuit includes:

[0107] The seventh transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the first control node, and its gate connected to the input signal terminal.

[0108] The third transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the first control node, and its gate connected to the third clock signal terminal.

[0109] The first leakage protection circuit includes:

[0110] The second transistor has its first terminal connected to the second clock signal terminal, its second terminal connected to the second node, and its gate connected to the first output terminal.

[0111] The first control circuit includes:

[0112] The ninth transistor has its first terminal connected to the third control node, its second terminal connected to the fourth control node, and its gate connected to the first control node.

[0113] The tenth transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the fourth control node, and its gate connected to the first control node.

[0114] The second leakage protection circuit includes:

[0115] The sixth transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the fourth control node, and its gate connected to the third control node.

[0116] In one exemplary embodiment of this disclosure, the shift register unit is applied to a gate driving circuit in a display panel, the display panel including a pixel driving circuit, and the shift register unit includes:

[0117] The second output circuit is used to provide a gate drive signal to the pixel drive circuit in the first driving state and to provide an invalid level signal to the pixel drive circuit in the second driving state.

[0118] In one exemplary embodiment of this disclosure, the second output circuit is connected to the first output terminal, the enable signal terminal, and the second output terminal. The second output circuit is used to respond to the signals of the enable signal terminal and the first output terminal to input the gate drive signal or the invalid level signal to the second output terminal. The second output terminal is used to connect to the pixel drive circuit.

[0119] In one exemplary embodiment of this disclosure, the shift register unit further includes:

[0120] The first inverter has its input terminal connected to the first output terminal and its output terminal connected to the third output terminal.

[0121] The second output circuit includes:

[0122] A pre-storage circuit is connected to at least one of the first output terminal and the third output terminal in the upper-level shift register unit and a third node. The pre-storage circuit is used to respond to the signals of the first output terminal and / or the third output terminal to transmit the signal of the enable signal terminal to the third node.

[0123] A latching circuit is connected to the third node and the fourth node, and the latching circuit is used to latch the inverted signal of the third node to the fourth node;

[0124] A gating circuit is connected to the first output terminal, the fourth node, the second power supply terminal, and the fifth node of this stage shift register unit. The gating circuit is used to respond to the signal of the first output terminal to transmit the signal of the fourth node or the second power supply terminal to the fifth node.

[0125] The second inverter has its input connected to the fifth node and its output connected to the second output terminal.

[0126] In one exemplary embodiment of this disclosure, the first inverter includes:

[0127] The fifteenth transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the third output terminal, and its gate connected to the first output terminal.

[0128] The sixteenth transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the third output terminal, and its gate connected to the first output terminal.

[0129] Among them, the signal polarities on the first power supply terminal and the second power supply terminal are different, the conduction level of the fifteenth transistor is different from the signal polarity of the first power supply terminal, and the conduction level of the sixteenth transistor is different from the signal polarity of the second power supply terminal.

[0130] The pre-stored circuit includes:

[0131] The seventeenth transistor has its first terminal connected to the enable signal terminal, its second terminal connected to the third node, and its gate connected to the third output terminal of the upper-level shift register unit.

[0132] The eighteenth transistor has its first terminal connected to the enable signal terminal, its second terminal connected to the third node, and its gate connected to the first output terminal of the upper-level shift register unit.

[0133] Wherein, the conduction level of the seventeenth transistor is the same as the signal polarity of the first power supply terminal, and the conduction level of the eighteenth transistor is the same as the signal polarity of the second power supply terminal;

[0134] The latching circuit includes:

[0135] The nineteenth transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the fourth node, and its gate connected to the third node.

[0136] The twentieth transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the fourth node, and its gate connected to the third node.

[0137] The twenty-first transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the third node, and its gate connected to the fourth node.

[0138] The 22nd transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the third node, and its gate connected to the fourth node.

[0139] Wherein, the conduction level of the twentieth and twenty-second transistors is the same as the signal polarity of the first power supply terminal, and the conduction level of the nineteenth and twenty-first transistors is the same as the signal polarity of the second power supply terminal;

[0140] The gating circuit includes:

[0141] The 23rd transistor has its first terminal connected to the fourth node, its second terminal connected to the fifth node, and its gate connected to the first output terminal.

[0142] The 24th transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the fifth node, and its gate connected to the first output terminal.

[0143] The fourth capacitor has its first electrode connected to the second power supply terminal and its second electrode connected to the fifth node.

[0144] The conduction level of the 23rd transistor is the same as the signal polarity of the second power supply terminal, and the conduction level of the 24th transistor is the same as the signal polarity of the first power supply terminal.

[0145] In one exemplary embodiment of this disclosure, the shift register unit further includes:

[0146] The first inverter has its input terminal connected to the first output terminal and its output terminal connected to the third output terminal.

[0147] The second output circuit includes:

[0148] A pre-storage circuit is connected to at least one of the first output terminal and the third output terminal in the current shift register unit, and a third node. The pre-storage circuit is used to respond to the signals of the first output terminal and / or the third output terminal to transmit the signal of the enable signal terminal to the third node.

[0149] A latching circuit is connected to the third node and the fourth node, and the latching circuit is used to latch the inverted signal of the third node to the fourth node;

[0150] A gating circuit is connected to the first output terminal, the fourth node, the second power supply terminal, and the fifth node of this stage shift register unit. The gating circuit is used to respond to the signal of the first output terminal to transmit the signal of the fourth node or the second power supply terminal to the fifth node.

[0151] The second inverter has its input connected to the fifth node and its output connected to the second output terminal.

[0152] In one exemplary embodiment of this disclosure, the first inverter includes:

[0153] The fifteenth transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the third output terminal, and its gate connected to the first output terminal.

[0154] The sixteenth transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the third output terminal, and its gate connected to the first output terminal.

[0155] Among them, the signal polarities on the first power supply terminal and the second power supply terminal are different, the conduction level of the fifteenth transistor is different from the signal polarity of the first power supply terminal, and the conduction level of the sixteenth transistor is different from the signal polarity of the second power supply terminal.

[0156] The pre-stored circuit includes:

[0157] The seventeenth transistor has its first terminal connected to the enable signal terminal, its second terminal connected to the third node, and its gate connected to the third output terminal of the shift register unit of this stage.

[0158] The eighteenth transistor has its first terminal connected to the enable signal terminal, its second terminal connected to the third node, and its gate connected to the first output terminal of the shift register unit of this stage.

[0159] Wherein, the conduction level of the seventeenth transistor is the same as the signal polarity of the first power supply terminal, and the conduction level of the eighteenth transistor is the same as the signal polarity of the second power supply terminal;

[0160] The latching circuit includes:

[0161] The nineteenth transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the fourth node, and its gate connected to the third node.

[0162] The twentieth transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the fourth node, and its gate connected to the third node.

[0163] The twenty-first transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the third node, and its gate connected to the fourth node.

[0164] The 22nd transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the third node, and its gate connected to the fourth node.

[0165] Wherein, the conduction level of the twentieth and twenty-second transistors is the same as the signal polarity of the first power supply terminal, and the conduction level of the nineteenth and twenty-first transistors is the same as the signal polarity of the second power supply terminal;

[0166] The gating circuit includes:

[0167] The 23rd transistor has its first terminal connected to the fourth node, its second terminal connected to the fifth node, and its gate connected to the first output terminal.

[0168] The 24th transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the fifth node, and its gate connected to the first output terminal.

[0169] The conduction level of the 23rd transistor is the same as the signal polarity of the second power supply terminal, and the conduction level of the 24th transistor is the same as the signal polarity of the first power supply terminal.

[0170] In an exemplary embodiment of this disclosure, the latching circuit is connected to a first power supply terminal and a second power supply terminal, the first power supply terminal and the second power supply terminal are respectively used to provide power signals with different polarities to the latching circuit, and the second inverter is connected to the first power supply terminal and the second power supply terminal, the first power supply terminal and the second power supply terminal are respectively used to provide power signals with different polarities to the second inverter.

[0171] The second inverter includes:

[0172] The 25th transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the second output terminal, and its gate connected to the fifth node.

[0173] The 26th transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the second output terminal, and its gate connected to the fifth node.

[0174] The conduction level of the 25th transistor is the same as the signal polarity of the second power supply terminal, and the conduction level of the 26th transistor is the same as the signal polarity of the first power supply terminal.

[0175] In an exemplary embodiment of this disclosure, the latching circuit is connected to a first power supply terminal and a second power supply terminal, the first power supply terminal and the second power supply terminal are respectively used to provide power signals with different polarities to the latching circuit, and the second inverter is connected to a third power supply terminal and a fourth power supply terminal, the third power supply terminal and the fourth power supply terminal are respectively used to provide power signals with different polarities to the second inverter.

[0176] The second inverter includes:

[0177] The 25th transistor has its first terminal connected to the third power supply terminal, its second terminal connected to the second output terminal, and its gate connected to the fifth node.

[0178] The 26th transistor has its first terminal connected to the fourth power supply terminal, its second terminal connected to the second output terminal, and its gate connected to the fifth node.

[0179] The conduction level of the 25th transistor is the same as the signal polarity of the fourth power supply terminal, and the conduction level of the 26th transistor is the same as the signal polarity of the third power supply terminal.

[0180] When the first power supply terminal and the third power supply terminal are used to provide a high-level signal, and the second power supply terminal and the fourth power supply terminal are used to provide a low-level signal, the voltage of the first power supply terminal is greater than or equal to the voltage of the third power supply terminal, and the voltage of the second power supply terminal is less than or equal to the voltage of the fourth power supply terminal.

[0181] When the first power supply terminal and the third power supply terminal are used to provide a low-level signal, and the second power supply terminal and the fourth power supply terminal are used to provide a high-level signal, the voltage of the first power supply terminal is less than or equal to the voltage of the third power supply terminal, and the voltage of the second power supply terminal is greater than or equal to the voltage of the fourth power supply terminal.

[0182] In one exemplary embodiment of this disclosure, the shift register unit is applied to the gate driving circuit in the display panel, and the reset circuit is used to input an effective level to the first control node before the next frame and to input an invalid level to the second control node.

[0183] In one exemplary embodiment of this disclosure, the display panel driving method includes a blank period between frames, and the reset circuit is used to input a valid level to the first control node and an invalid level to the second control node during the blank period.

[0184] In one exemplary embodiment of this disclosure, the first output circuit is further connected to a second clock signal terminal, and the first output circuit is used to input an effective level to the first output terminal using the second clock signal terminal in response to the signal of the second control node;

[0185] When the second output circuit is in the first driving state, the pulse frequency of the effective level on the second clock signal terminal is n1;

[0186] When the second output circuit is in the second driving state, the pulse frequency of the effective level on the second clock signal terminal is n2;

[0187] Where n1 is greater than or equal to n2.

[0188] According to one aspect of this disclosure, a gate driving circuit is provided, wherein the gate driving circuit includes a plurality of the above-described shift register units, the plurality of shift register units being cascaded.

[0189] In one exemplary embodiment of this disclosure, the gate driving circuit includes:

[0190] Multiple shift register unit groups, wherein the shift register unit groups include multiple cascaded shift register units;

[0191] A switching unit is provided, in which two shift register units located in different shift register unit groups and cascaded are connected through the switching unit;

[0192] In each of the shift register unit groups, the first-level shift register unit is connected to a different initialization signal terminal.

[0193] According to one aspect of this disclosure, a display panel is provided, wherein the display panel includes the gate driving circuit described above.

[0194] According to one aspect of this disclosure, a display panel driving method is provided, wherein the method is used to drive the aforementioned display panel, and the driving method includes:

[0195] Within the same time period, control the number of frames in the second driving state of the shift register unit corresponding to different display areas in the display panel;

[0196] Among them, the refresh frequency of the display area corresponding to the shift register unit with a smaller frame number in the second driving state is greater than the refresh frequency of the display area corresponding to the shift register unit with a larger frame number in the second driving state.

[0197] In an exemplary embodiment of this disclosure, when the first output circuit is also connected to the second clock signal terminal, the first output circuit is used to respond to the signal of the second control node by using the second clock signal terminal to input an effective level to the first output terminal;

[0198] At least a portion of the low-frequency display area forms the last scan area of ​​the display panel, and within the same frame, the driving method includes:

[0199] When the shift register unit corresponding to the low-frequency display area that forms the end scan area is in the second driving state, the pulse frequency of the effective level on the second clock signal terminal is set to n2;

[0200] When the shift register unit corresponding to the high-frequency display area is in the first driving state, the pulse frequency of the effective level on the second clock signal terminal is set to n1;

[0201] Where n1 is greater than or equal to n2.

[0202] In one exemplary embodiment of this disclosure, the display panel includes a plurality of sub-display areas, and the gate driving circuit includes:

[0203] Multiple shift register unit groups, each group comprising multiple cascaded shift register units, are configured correspondingly with the sub-display areas. Each shift register unit group is used to provide gate drive signals to its corresponding sub-display area.

[0204] A switching unit is provided, in which two shift register units located in different shift register unit groups and cascaded are connected through the switching unit;

[0205] In each of the shift register unit groups, the first-level shift register unit is connected to a different initialization signal terminal;

[0206] At least a portion of the low-frequency display area forms the end scan area of ​​the sub-display area. Within the same frame of the same sub-display area, the driving method includes:

[0207] When the shift register unit corresponding to the low-frequency display area that forms the end scan area is in the second driving state, the pulse frequency of the effective level on the second clock signal terminal is set to n2;

[0208] When the shift register unit corresponding to the high-frequency display area is in the first driving state, the pulse frequency of the effective level on the second clock signal terminal is set to n1;

[0209] Where n1 is greater than or equal to n2.

[0210] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0211] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0212] Figure 1 is a schematic diagram of the structure of an exemplary embodiment of the display panel of this disclosure;

[0213] Figure 2 is a schematic diagram of an exemplary embodiment of the shift register unit of this disclosure;

[0214] Figure 3 is a timing diagram of each node in a driving method of the shift register unit of this disclosure;

[0215] Figure 4 is a schematic diagram of an exemplary embodiment of the gate drive circuit of this disclosure;

[0216] Figure 5 is a timing diagram of each signal line and node in an exemplary embodiment of the display panel driving method of this disclosure;

[0217] Figure 6 is a timing diagram of each signal line and node in an exemplary embodiment of the display panel driving method of this disclosure;

[0218] Figure 7 is a timing diagram of each signal line and node in another exemplary embodiment of the display panel driving method of this disclosure;

[0219] Figure 8 is a schematic diagram of an exemplary embodiment of the shift register unit of this disclosure;

[0220] Figure 9 is a schematic diagram of another exemplary embodiment of the shift register unit of this disclosure;

[0221] Figure 10 is a schematic diagram of another exemplary embodiment of the shift register unit of this disclosure;

[0222] Figure 11 is a schematic diagram of another exemplary embodiment of the shift register unit of this disclosure;

[0223] Figure 12 is a schematic diagram of another exemplary embodiment of the shift register unit of this disclosure;

[0224] Figure 13 is a schematic diagram of another exemplary embodiment of the shift register unit of this disclosure;

[0225] Figure 14 is a timing diagram of each node in the shift register unit shown in Figure 13;

[0226] Figure 15 is a schematic diagram of another exemplary embodiment of the shift register unit of this disclosure;

[0227] Figure 16 is a schematic diagram of another exemplary embodiment of the shift register unit of this disclosure;

[0228] Figure 17 is a schematic diagram of another exemplary embodiment of the shift register unit of this disclosure;

[0229] Figure 18 is a schematic diagram of an exemplary embodiment of the gate drive circuit of this disclosure;

[0230] Figure 19 is a timing diagram of each signal line and node in an exemplary embodiment of the display panel driving method of this disclosure;

[0231] Figure 20 is a schematic diagram of another exemplary embodiment of the shift register unit of this disclosure;

[0232] Figure 21 is a timing diagram of each node in a driving method of the shift register unit of this disclosure;

[0233] Figure 22 is a schematic diagram of another exemplary embodiment of the shift register unit of this disclosure;

[0234] Figure 23 is a schematic diagram of another exemplary embodiment of the shift register unit of this disclosure;

[0235] Figure 24 is a schematic diagram of another exemplary embodiment of the shift register unit of this disclosure;

[0236] Figure 25 is a schematic diagram of another exemplary embodiment of the gate drive circuit of this disclosure;

[0237] Figure 26 is a schematic diagram of another exemplary embodiment of the gate drive circuit of this disclosure. Detailed Implementation

[0238] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0239] The terms “a,” “one,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended meaning of inclusion and that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0240] Figure 1 shows a schematic diagram of an exemplary embodiment of the display panel of this disclosure. The display panel may include a timing controller, a source driving circuit, a gate driving circuit, and a pixel array. The timing controller is connected to both the source driving circuit and the gate driving circuit. The source driving circuit is connected to multiple data signal lines (Da1 to Dan). The gate driving circuit includes a scan driving circuit and a light-emitting driving circuit. The scan driving circuit is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driving circuit is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit, which may be connected to the scan signal lines, light-emitting signal lines, and data signal lines. In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the source driver circuit to the source driver circuit, clock signals, scan start signals, etc. of specifications suitable for the scan driver circuit to the scan driver circuit, and clock signals, transmit stop signals, etc. of specifications suitable for the light-emitting driver circuit to the light-emitting driver circuit. The source driver circuit can use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines Da1, Da2, Da3, ..., Dan. For example, the source driver circuit can sample the grayscale values ​​using a clock signal and apply the data voltage corresponding to the grayscale values ​​to data signal lines Da1 to Dan on a pixel-by-pixel basis, where n can be a natural number. The scan driver circuit can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver circuit can sequentially provide scan signals with conduction level pulses to scan signal lines S1 to Sm. For example, the scan driver circuit can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal, where m can be a natural number. The light-emitting driver circuit can generate transmit signals to be provided to the light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from a timing controller. For example, the light-emitting driver circuit can sequentially provide transmit signals with cutoff level pulses to the light-emitting signal lines E1 to Eo. For example, the light-emitting driver circuit can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals, provided in the form of cutoff level pulses, to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0241] Figure 2 shows a schematic diagram of an exemplary embodiment of the shift register unit of this disclosure. The shift register unit includes a first output circuit 1 and a second output circuit 2. The first output circuit 1 is connected to a first control node PU1, a second control node PD2, and a first output terminal OUT1. The first output circuit 1 is used to respond to the signal of the first control node PU1 to input an invalid level to the first output terminal OUT1, and to respond to the signal of the second control node PD2 to input an valid level to the first output terminal OUT1. The first output terminal OUT1 is used to connect to the input signal terminal IN of the next-level shift register unit. The second output circuit 2 is used to provide a gate drive signal to the pixel driving circuit in a first driving state, and to provide an invalid level signal to the pixel driving circuit in a second driving state.

[0242] This exemplary embodiment designs the first output circuit 1 and the second output circuit 2 independently. The first output circuit 1 can normally provide input signals to the lower-level shift register unit, and the second output circuit 2 can normally output gate drive signals when the pixel driving circuit needs to be refreshed, and output invalid level signals when the pixel driving circuit does not need to be refreshed. This exemplary embodiment can realize the adjustment of the refresh frequency of a local area of ​​the display panel, as well as the adjustment of the refresh frequency of the same display area at different time periods.

[0243] It should be noted that, in this exemplary embodiment, the gate drive signal includes an effective level period and an invalid level period. That is, the effective level and invalid level output by the shift register unit for a certain period of time (e.g., within one frame) together constitute the gate drive signal. In this exemplary embodiment, the effective level signal is a signal that can drive the target circuit to turn on, and the invalid level signal is a signal that drives the target circuit to turn off. For example, when the target circuit is an N-type transistor, the effective level signal is a high-level signal, and the invalid level signal is a low-level signal. The first output circuit 1 is used to provide input signals to the lower-level shift register unit, wherein the lower-level shift register unit can be an adjacent lower-level shift register unit or an intervening lower-level shift register unit.

[0244] In this exemplary embodiment, as shown in FIG2, the shift register unit may further include: a first input circuit 41, a second input circuit 42, a first control circuit 5, a second control circuit 6, and an isolation circuit 7. The first input circuit 41 is connected to the input signal terminal IN, the first node N1, and the first clock signal terminal CK1. The first input circuit 41 is used to respond to the signal of the first clock signal terminal CK1 to transmit the signal of the input signal terminal IN to the first node N1. The first node N1 is connected to the third control node PD3, and the third control node PD3 is connected to the second control node PD2. The second input circuit 42 is connected to the second power supply terminal VGL1, the first control node PU1, and the first clock signal terminal CK1. The second input circuit 42 is used to respond to the signal of the first clock signal terminal CK1 to transmit the signal of the second power supply terminal VGL1 to the first control node PU1. The first control circuit 5 is connected to the first clock signal terminal CK1, the third control node PD2, and the second control node PD2. Point PD3 and first control node PU1 are connected. The first control circuit 5 is used to respond to the signal of the third control node PD3 to transmit the signal of the first clock signal terminal CK1 to the first control node PU1. The second control circuit 6 is connected to the first power supply terminal VGH1, the second clock signal terminal CK2, the first control node PU1, and the third control node PD3. The second control circuit 6 is used to respond to the signal of the second clock signal terminal CK2 and the first control node PU1 to transmit the signal of the first power supply terminal VGH1 to the third control node PD3. The isolation circuit 7 is connected to the third control node PD3 and the second control node PD2. The isolation circuit 7 is used to respond to a control signal to connect the third control node PD3 and the second control node PD2.

[0245] In this exemplary embodiment, as shown in FIG2, the first output circuit 1 includes: a fourth transistor T4, a first capacitor C1, a fifth transistor T5, and a second capacitor C2. The first electrode of the fourth transistor T4 is connected to the first power supply terminal VGH1, the second electrode is connected to the first output terminal OUT1, and the gate is connected to the first control node PU1. The first electrode of the first capacitor C1 is connected to the first power supply terminal VGH1, and the second electrode is connected to the first control node PU1. The first electrode of the fifth transistor T5 is connected to the second clock signal terminal CK2, the second electrode is connected to the first output terminal OUT1, and the gate is connected to the second control node PD2. The first electrode of the second capacitor C2 is connected to the second control node PD2, and the second electrode is connected to the first output terminal OUT1. The first input circuit 41 includes: a first transistor T1, the first electrode of the first transistor T1 is connected to the input signal terminal IN, the second electrode is connected to the first node N1, and the gate is connected to the first clock signal terminal CK1. The second input circuit 42 includes: a third transistor T3, the first electrode of the third transistor T3 is connected to the second power supply terminal VGL1, the second electrode is connected to the first control node PU1, and the gate is connected to the first clock signal terminal CK1. The first control circuit 5 includes a second transistor T2, whose first terminal is connected to the first clock signal terminal CK1, its second terminal is connected to the first control node PU1, and its gate is connected to the third control node PD3. The second control circuit 6 includes a sixth transistor T6 and a seventh transistor T7. The first terminal of the sixth transistor T6 is connected to the first power supply terminal VGH1, and its gate is connected to the first control node PU1. The first terminal of the seventh transistor T7 is connected to the second terminal of the sixth transistor T6, its second terminal is connected to the third control node PD3, and its gate is connected to the second clock signal terminal CK2. The isolation circuit 7 is also connected to the second power supply terminal VGL1. The isolation circuit 7 is used to respond to a signal from the second power supply terminal VGL1 to connect the third control node PD3 and the second control node PD2. The isolation circuit 7 includes an eighth transistor T8, whose first terminal is connected to the third control node PD3, its second terminal is connected to the second control node PD2, and its gate is connected to the second power supply terminal VGL1. It should be understood that, in other exemplary embodiments, the isolation circuit 7 may also respond to signals from other signal terminals to connect the third control node PD3 and the second control node PD2. For example, the isolation circuit 7 may also connect to the first clock signal terminal CK1, and the isolation circuit 7 may be used to respond to the signal from the first clock signal terminal CK1 to connect the third control node PD3 and the second control node PD2.

[0246] In this exemplary embodiment, as shown in FIG2, the second output circuit 2 is connected to the first output terminal OUT1, the enable signal terminal EM, and the second output terminal OUT2. The second output circuit 2 is used to respond to the signals of the enable signal terminal EM and the first output terminal OUT1 to input the gate drive signal or the invalid level signal to the second output terminal OUT2. The second output terminal OUT2 is used to connect to the pixel drive circuit.

[0247] In this exemplary embodiment, as shown in FIG2, the shift register unit further includes: a first inverter 9, the input terminal of the first inverter 9 being connected to the first output terminal OUT1, and the output terminal being connected to the third output terminal OUT3. The second output circuit 2 includes: a pre-store circuit 21, a latch circuit 22, a gating circuit 23, and a second inverter 24. The pre-store circuit 21 is connected to the enable signal terminal EM, the first output terminal OUT1-0, the third output terminal OUT3-0 in the upper-level shift register unit, and the third node N3. The pre-store circuit 21 is used to respond to the signals of the first output terminal OUT1-0 and the third output terminal OUT3-0 to transmit the signal of the enable signal terminal to the third node N3. The latch circuit 22 is connected to the third node N3 and the fourth node N4. The latch circuit 22 is used to latch the inverted signal of the third node N3 to the fourth node N4. The gating circuit 23 is connected to the first output terminal OUT1, the fourth node N4, the second power supply terminal VGL1, and the fifth node N5 of this stage shift register unit. The gating circuit 23 is used to respond to the signal at the first output terminal OUT1 to transmit the signal at the fourth node N4 or the second power supply terminal VGL1 to the fifth node N5. The input terminal of the second inverter 24 is connected to the fifth node N5, and the output terminal is connected to the second output terminal OUT2.

[0248] It should be noted that the pre-stored circuit 21 is connected to the first output terminal OUT1-0 and the third output terminal OUT3-0 in the upper-level shift register unit. The upper-level shift register unit can be an adjacent upper-level shift register unit or an intervening upper-level shift register unit.

[0249] It should be understood that in other exemplary embodiments, the pre-store circuit 21 may also be connected only to the first output terminal OUT1-0 or the third output terminal OUT3-0 in the upper-level shift register unit. The pre-store circuit 21 can also respond to the signal of the first output terminal OUT1-0 or the third output terminal OUT3-0 to transmit the signal of the enable signal terminal EM to the third node N3.

[0250] In this exemplary embodiment, as shown in FIG2, the first inverter 9 includes a fifteenth transistor T15 and a sixteenth transistor T16. The first terminal of the fifteenth transistor T15 is connected to the first power supply terminal VGH1, the second terminal is connected to the third output terminal OUT3, and the gate is connected to the first output terminal OUT1. The first terminal of the sixteenth transistor T16 is connected to the second power supply terminal VGL1, the second terminal is connected to the third output terminal OUT3, and the gate is connected to the first output terminal OUT1. The signals on the first power supply terminal VGH1 and the second power supply terminal VGL1 have different polarities. The conduction level of the fifteenth transistor T15 has a different polarity than the signal on the first power supply terminal VGH1, and the conduction level of the sixteenth transistor T16 has a different polarity than the signal on the second power supply terminal VGL1. Different polarities mean that one signal is high and the other is low.

[0251] In this exemplary embodiment, as shown in FIG2, the pre-store circuit 21 includes: a seventeenth transistor T17 and an eighteenth transistor T18. The first terminal of the seventeenth transistor T17 is connected to the enable signal terminal EM, the second terminal is connected to the third node N3, and the gate is connected to the third output terminal OUT3-0 of the upper-level shift register unit. The first terminal of the eighteenth transistor T18 is connected to the enable signal terminal EM, the second terminal is connected to the third node N3, and the gate is connected to the first output terminal OUT1-0 of the upper-level shift register unit. The conduction level of the seventeenth transistor T17 is the same as the signal polarity of the first power supply terminal VGH1, and the conduction level of the eighteenth transistor T18 is the same as the signal polarity of the second power supply terminal VGL1.

[0252] In this exemplary embodiment, as shown in FIG2, the latch circuit 22 includes: a nineteenth transistor T19, a twentieth transistor T20, a twenty-first transistor T21, and a twenty-second transistor T22. The first terminal of the nineteenth transistor T19 is connected to the first power supply terminal VGH1, the second terminal is connected to the fourth node N4, and the gate is connected to the third node N3; the first terminal of the twentieth transistor T20 is connected to the second power supply terminal VGL1, the second terminal is connected to the fourth node N4, and the gate is connected to the third node N3; the first terminal of the twenty-first transistor T21 is connected to the first power supply terminal VGH1, the second terminal is connected to the third node N3, and the gate is connected to the fourth node N4; the first terminal of the twenty-second transistor T22 is connected to the second power supply terminal VGL1, the second terminal is connected to the third node N3, and the gate is connected to the fourth node N4; wherein the conduction level of the twentieth transistor T20 and the twenty-second transistor T22 has the same signal polarity as the first power supply terminal VGH1, and the conduction level of the nineteenth transistor T19 and the twenty-first transistor T21 has the same signal polarity as the second power supply terminal VGL1.

[0253] In this exemplary embodiment, as shown in FIG2, the gating circuit 23 includes: a twenty-third transistor T23, a twenty-fourth transistor T24, and a fourth capacitor C4. The first electrode of the twenty-third transistor T23 is connected to the fourth node N4, the second electrode is connected to the fifth node N5, and the gate is connected to the first output terminal OUT1. The first electrode of the twenty-fourth transistor T24 is connected to the second power supply terminal VGL1, the second electrode is connected to the fifth node N5, and the gate is connected to the first output terminal OUT1. The first electrode of the fourth capacitor C4 is connected to the second power supply terminal VGL1, and the second electrode is connected to the fifth node N5. The conduction level of the twenty-third transistor T23 and the signal polarity of the second power supply terminal VGL1 are the same, and the conduction level of the twenty-fourth transistor T24 and the signal polarity of the first power supply terminal VGH1 are the same. It should be understood that in other exemplary embodiments, the gating circuit 23 may not include the fourth capacitor C4.

[0254] In this exemplary embodiment, as shown in FIG2, the latch circuit 22 is connected to a first power supply terminal VGH1 and a second power supply terminal VGL1. The first power supply terminal VGH1 and the second power supply terminal VGL1 are respectively used to provide power signals of different polarities to the latch circuit. The second inverter 24 is connected to the first power supply terminal VGH1 and the second power supply terminal VGL1. The first power supply terminal VGH1 and the second power supply terminal VGL1 are respectively used to provide power signals of different polarities to the second inverter 24. The second inverter 24 includes a twenty-fifth transistor T25 and a twenty-sixth transistor T26. The first terminal of the twenty-fifth transistor T25 is connected to the first power supply terminal VGH1, the second terminal is connected to the second output terminal OUT2, and the gate is connected to the fifth node N5. The first terminal of the twenty-sixth transistor T26 is connected to the second power supply terminal VGL1, the second terminal is connected to the second output terminal OUT2, and the gate is connected to the fifth node N5. The conduction level of the twenty-fifth transistor T25 has the same polarity as the signal of the second power supply terminal VGL1, and the conduction level of the twenty-sixth transistor T26 has the same polarity as the signal of the first power supply terminal VGH1.

[0255] In this exemplary embodiment, as shown in FIG2, the first power supply terminal VGH1 can be a high-level signal terminal, and the second power supply terminal VGL1 can be a low-level power supply terminal. Correspondingly, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the fifteenth transistor T15, the eighteenth transistor T18, the nineteenth transistor T19, the twenty-first transistor T21, the twenty-third transistor T23, and the twenty-fifth transistor T25 are P-type transistors; the sixteenth transistor T16, the seventeenth transistor T17, the twentieth transistor T20, the twenty-second transistor T22, the twenty-fourth transistor T24, and the twenty-sixth transistor T26 are N-type transistors.

[0256] It should be understood that in other exemplary embodiments, the transistors may be of other types, and correspondingly, the polarity of the signals on the first power supply terminal and the second power supply terminal also needs to be adjusted accordingly.

[0257] Figure 3 shows the timing diagram of each node in a driving method of the shift register unit of this disclosure. CK1 is the timing diagram of the first clock signal terminal, CK2 is the timing diagram of the second clock signal terminal, IN is the timing diagram of the input signal terminal, OUT1 is the timing diagram of the first output terminal, and OUT3 is the timing diagram of the third output terminal.

[0258] The driving method of this shift register unit includes: first stage t1, second stage t2, third stage t3, fourth stage t4, and fifth stage t5.

[0259] In the first stage t1: the input signal terminal IN and the first clock signal terminal CK1 output low-level signals, and the second clock signal terminal CK2 outputs a high-level signal. The first transistor T1 is turned on, and the input signal terminal IN inputs low-level signals to the first node N1, the third control node PD3, and the second control node PD2. The fifth transistor T5 is turned on, and the second clock signal terminal CK2 inputs a high-level signal to the first output terminal OUT1. Simultaneously, the third transistor T3 is turned on, and the second power supply terminal VGL1 inputs a low-level signal to the first control node PU1. The fourth transistor is turned on, and the first power supply terminal VGH1 inputs a high-level signal to the first output terminal OUT1. The first output terminal OUT1 outputs a high-level signal, and the third output terminal OUT3 outputs a low-level signal.

[0260] In the second stage t2: Input signal terminal IN and first clock signal terminal CK1 output high-level signals, while second clock signal terminal CK2 outputs low-level signals. First node N1 and second control node PD2 maintain low-level signals, second transistor T2 is turned on, first clock signal terminal CK1 inputs a high-level signal to first control node PU1, and fourth transistor T4 is turned off. Second control node PD2 maintains a low-level signal, fifth transistor T5 is turned on, and second clock signal terminal CK2 inputs a low-level signal to first output terminal OUT1. First output terminal OUT1 outputs a low-level signal, and third output terminal OUT3 outputs a high-level signal.

[0261] In the third stage t3: the first clock signal terminal CK1 outputs a low-level signal, and the input signal terminal IN and the second clock signal terminal CK2 output high-level signals. The first transistor T1 is turned on, and the input signal terminal IN inputs a high-level signal to the first node N1, the third control node PD3, and the second control node PD2. The fifth transistor T5 is turned off. The third transistor T3 is turned on, and the second power supply terminal VGL1 inputs a low-level signal to the first control node PU1. The fourth transistor T4 is turned on, and the first power supply terminal VGH1 inputs a high-level signal to the first output terminal OUT1. The first output terminal OUT1 outputs a high-level signal, and the third output terminal OUT3 outputs a low-level signal.

[0262] In stage t4: Input signal terminal IN and first clock signal terminal CK1 output high-level signals, while second clock signal terminal CK2 outputs low-level signals. First control node PU1 maintains a low-level signal, sixth transistor T6 and seventh transistor T7 are turned on, and first power supply terminal VGH1 inputs high-level signals to first node N1, third control node PD3, and second control node PD2, while fifth transistor is turned off. Simultaneously, fourth transistor T4 is turned on, and first power supply terminal VGH1 inputs a high-level signal to first output terminal OUT1. First output terminal OUT1 outputs a high-level signal, and third output terminal OUT3 outputs a low-level signal.

[0263] In stage t5: The first clock signal terminal CK1 outputs a low-level signal, while the input signal terminal IN and the second clock signal terminal CK2 output high-level signals. The first transistor T1 is turned on, and the input signal terminal IN inputs a high-level signal to the first node N1, the third control node PD3, and the second control node PD2. The fifth transistor T5 is turned off. The third transistor T3 is turned on, and the second power supply terminal VGL1 inputs a low-level signal to the first control node PU1. The fourth transistor T4 is turned on, and the first power supply terminal VGH1 inputs a high-level signal to the first output terminal OUT1. The first output terminal OUT1 outputs a high-level signal, and the third output terminal OUT3 outputs a low-level signal.

[0264] After this, the shift register unit can repeat the fourth and fifth stages in sequence.

[0265] As shown in Figures 2 and 3, this exemplary embodiment can control the second output circuit 2 to be in either a first driving state or a second driving state by controlling the level of the enable signal terminal EM. When the enable signal terminal EM outputs a low-level signal, the second output circuit 2 is in the first driving state; when the enable signal terminal EM outputs a high-level signal, the second output circuit 2 is in the second driving state.

[0266] When the enable signal terminal EM outputs a high-level signal:

[0267] Before the first stage t1, the enable signal terminal EM inputs a high-level signal to the third node N3, the twentieth transistor T20 is turned on, the second power supply terminal VGL1 inputs a low-level signal to the fourth node N4, the twenty-first transistor T21 is turned on, and the first power supply terminal VGH1 inputs a high-level signal to the third node N3. That is, the latch circuit 22 latches the inverted level signal of the third node N3 to the fourth node.

[0268] In the first stage t1: the first output terminal OUT1 outputs a high-level signal, the twenty-fourth transistor T24 is turned on, the second power supply terminal VGL1 inputs a low-level signal to the fifth node N5, the twenty-fifth transistor T25 is turned on, and the first power supply terminal VGH1 inputs a high-level signal to the second output terminal OUT2.

[0269] In the second stage t2: the first output terminal OUT1 outputs a low-level signal, the twenty-third transistor T23 is turned on, the fourth node N4 inputs a low-level signal to the fifth node N5, the twenty-fifth transistor T25 is turned on, and the first power supply terminal VGH1 inputs a high-level signal to the second output terminal OUT2.

[0270] In the third stage t3: the first output terminal OUT1 outputs a high-level signal, the twenty-fourth transistor T24 is turned on, the second power supply terminal VGL1 inputs a low-level signal to the fifth node N5, the twenty-fifth transistor T25 is turned on, and the first power supply terminal VGH1 inputs a high-level signal to the second output terminal OUT2.

[0271] Similarly, in the fourth stage t4 and the fifth stage t5, the first output terminal OUT1 outputs a high-level signal, the twenty-fourth transistor T24 is turned on, the second power supply terminal VGL1 inputs a low-level signal to the fifth node N5, the twenty-fifth transistor T25 is turned on, and the first power supply terminal VGH1 inputs a high-level signal to the second output terminal OUT2.

[0272] As shown in Figures 2 and 3, when the enable signal terminal EM outputs a low-level signal:

[0273] Before the first stage t1, the enable signal terminal EM inputs a low-level signal to the third node N3, the nineteenth transistor T19 is turned on, the first power supply terminal VGH1 inputs a high-level signal to the fourth node N4, the twenty-second transistor T22 is turned on, and the second power supply terminal VGL1 inputs a low-level signal to the third node N3. That is, the latch circuit 22 latches the inverted level signal of the third node N3 to the fourth node.

[0274] In the first stage t1: the first output terminal OUT1 outputs a high-level signal, the twenty-fourth transistor T24 is turned on, the second power supply terminal VGL1 inputs a low-level signal to the fifth node N5, the twenty-fifth transistor T25 is turned on, and the first power supply terminal VGH1 inputs a high-level signal to the second output terminal OUT2.

[0275] In the second stage t2: the first output terminal OUT1 outputs a low-level signal, the twenty-third transistor T23 is turned on, the fourth node N4 inputs a high-level signal to the fifth node N5, the twenty-sixth transistor T26 is turned on, and the second power supply terminal VGL1 inputs a low-level signal to the second output terminal OUT2.

[0276] In the third stage t3: the first output terminal OUT1 outputs a high-level signal, the twenty-fourth transistor T24 is turned on, the second power supply terminal VGL1 inputs a low-level signal to the fifth node N5, the twenty-fifth transistor T25 is turned on, and the first power supply terminal VGH1 inputs a high-level signal to the second output terminal OUT2.

[0277] Similarly, in the fourth stage t4 and the fifth stage t5, the first output terminal OUT1 outputs a high-level signal, the twenty-fourth transistor T24 is turned on, the second power supply terminal VGL1 inputs a low-level signal to the fifth node N5, the twenty-fifth transistor T25 is turned on, and the first power supply terminal VGH1 inputs a high-level signal to the second output terminal OUT2.

[0278] In this exemplary embodiment, when the enable signal terminal EM outputs a low-level signal, the second output circuit 2 is in a first driving state, and the second output terminal OUT2 and the first output terminal OUT1 can output signals with the same or approximately the same timing. When the enable signal terminal EM outputs a high-level signal, the second output circuit 2 is in a second driving state, and the second output terminal OUT2 outputs an invalid level signal.

[0279] In this exemplary embodiment, as shown in FIG2, the first input circuit 41, the second input circuit 42, the first control circuit 5, the second control circuit 6, the isolation circuit 7, the first output circuit 1, and the first inverter 9 constitute the shift circuit 0.

[0280] It should be noted that the first output terminal OUT1 is used to provide input signals to the lower-level shift register unit. A valid input level to the first output terminal OUT1 is a level that enables the target circuit connected to OUT1 to conduct, and an invalid input level is a level that enables the target circuit connected to OUT1 to turn off. Similarly, the second output terminal OUT2 is used to provide gate drive signals to the pixel driving circuit. A valid input level to the second output terminal OUT2 is a level that enables the target circuit connected to OUT2 to conduct, and an invalid input level is a level that enables the target circuit connected to OUT2 to turn off. Furthermore, a valid input level to the third output terminal OUT3 is a level that enables the target circuit connected to OUT3 to conduct, and an invalid input level is a level that enables the target circuit connected to OUT3 to turn off.

[0281] Figure 4 shows a schematic diagram of an exemplary embodiment of the gate drive circuit of this disclosure. The initial stage shift register unit may only include shift circuit 0, and the first stage shift register unit of this gate drive circuit can be counted from the next stage of the initial stage shift register unit. The second clock signal line LCK2 provides clock signals to the first clock signal terminal CK1 of the odd-numbered stage shift register unit, the second clock signal terminal CK2 of the even-numbered stage shift register unit, and the second clock signal terminal of the initial stage shift register unit; the first clock signal line LCK1 provides clock signals to the second clock signal terminal CK2 of the odd-numbered stage shift register unit, the first clock signal terminal CK1 of the even-numbered stage shift register unit, and the first clock signal terminal of the initial stage shift register unit. The first output terminal OUT1 of this stage shift register unit can provide an input signal to the input signal terminal IN of the adjacent next stage shift register unit, and the input signal terminal of the initial stage shift register unit can provide an input signal through the initial signal line STV. It should be understood that in other exemplary embodiments, the initial stage shift register unit may also include a second output circuit 2. The initial stage shift register unit may be configured virtually, that is, the initial stage shift register unit is not connected to the pixel driving circuit.

[0282] Figure 5 shows a timing diagram of each signal line and node in an exemplary embodiment of the display panel driving method of this disclosure. LCK2 is the timing diagram of the signals on the second clock signal line, LCK1 is the timing diagram of the signals on the first clock signal line, STV is the timing diagram of the signals on the initial signal line, OUT2-1 represents the timing diagram of the second output terminal of the first-stage shift register unit, OUT2-2 represents the timing diagram of the second output terminal of the second-stage shift register unit, and so on, with OUT2-m representing the timing diagram of the second output terminal of the m-th stage shift register unit. OUT1-1 represents the timing diagram of the first output terminal of the first-stage shift register unit, OUT1-2 represents the timing diagram of the first output terminal of the second-stage shift register unit, and so on, with OUT1-m representing the timing diagram of the first output terminal of the m-th stage shift register unit.

[0283] Figure 5 shows the timing diagram of each signal line and node in three adjacent frames of the display panel. In the refresh frame, the second output circuit 2 of each shift register unit normally outputs the gate drive signal, and the first output circuit 1 of each shift register unit provides the input signal to the next lower shift register unit. In the partial refresh frame, the display panel includes a low-frequency display area-1, a high-frequency display area, and a low-frequency display area-2, with each display area and the corresponding shift register unit connected to the pixel drive circuit within it. In the shift register units corresponding to low-frequency display areas-1 and-2: the first output circuit 1 of the shift register unit provides the input signal to the next lower shift register unit, while the second output circuit 2 of the shift register unit outputs an invalid level signal, meaning that the pixel drive circuits in low-frequency display areas-1 and-2 are not scanned in the partial refresh frame. In the shift register unit corresponding to the high-frequency display area: the first output circuit 1 of the shift register unit provides the input signal to the next lower shift register unit, while the second output circuit 2 of the shift register unit normally outputs the gate drive signal. This driving method can adjust the refresh frequency of different areas of the display panel.

[0284] It should be noted that in this exemplary embodiment, the terms "low-frequency display area" and "high-frequency display area" are relative, meaning they refer to two regions with different refresh rates, one high and one low. The terms "low-frequency display area" and "high-frequency display area" do not specifically refer to a particular refresh rate range.

[0285] Figure 6 shows a timing diagram of each signal line and node in an exemplary embodiment of the display panel driving method of this disclosure. LCK2 is the timing diagram of the signal on the second clock signal line, LCK1 is the timing diagram of the signal on the first clock signal line, STV is the timing diagram of the signal on the initial signal line, OUT2-1 represents the timing diagram of the second output terminal of the first-stage shift register unit, OUT2-2 represents the timing diagram of the second output terminal of the second-stage shift register unit, and so on, with OUT2-m representing the timing diagram of the second output terminal of the m-th stage shift register unit. OUT1-1 represents the timing diagram of the first output terminal of the first-stage shift register unit, OUT1-2 represents the timing diagram of the first output terminal of the second-stage shift register unit, and so on, with OUT2-m representing the timing diagram of the first output terminal of the m-th stage shift register unit.

[0286] In this exemplary embodiment, as shown in FIG6, at least a portion of the low-frequency display area forms the end scan area of ​​the display panel, meaning that in the same frame, there is no high-frequency display area following the low-frequency display area. As shown in FIG6, low-frequency display area-2 forms the end display area of ​​the display panel. In the same frame, the display panel driving method includes: when the shift register unit corresponding to the low-frequency display area forming the end scan area is in a second driving state, setting the pulse frequency of the effective level on the second clock signal terminal CK2 to n2; when the shift register unit corresponding to the high-frequency display area is in a first driving state, setting the pulse frequency of the effective level on the second clock signal terminal to n1; wherein, n1 is greater than or equal to n2. That is, this exemplary embodiment reduces the power consumption of the display panel by reducing the pulse frequency of the effective level on the second clock signal terminal CK2 in the low-frequency display area-2. In this exemplary embodiment, because the first clock signal line LCK1 simultaneously provides clock signals to the second clock signal terminal of the odd-level shift register unit and the first clock signal terminal of the even-level shift register unit, and the second clock signal line LCK2 simultaneously provides clock signals to the first clock signal terminal of the odd-level shift register unit and the second clock signal terminal of the even-level shift register unit, the pulse frequency of the effective level on both the first clock signal line LCK1 and the second clock signal line LCK2 is reduced. In this exemplary embodiment, the reduced pulse frequency of the effective level on the second clock signal terminal of the shift register unit correspondingly reduces the frequency and speed at which the first output terminal OUT1 inputs input signals to the lower-level shift register unit. Furthermore, since the low-frequency display area -2 is the last scanning area of ​​the display panel, this setting will not affect the normal scanning of the current frame, even if the frequency and speed at which the first output terminal OUT1 inputs input signals to the lower-level shift register unit are reduced.

[0287] As shown in Figure 6, this exemplary embodiment can reduce the pulse frequency of the effective level on the second clock signal terminal by increasing the duration of the signal period on the second clock signal terminal CK2. One signal period includes an adjacent effective level pulse and an ineffective level pulse. As shown in Figure 6, this exemplary embodiment lengthens the duration of the effective level pulse on the second clock signal terminal to S1 and lengthens the duration of the ineffective level pulse on the second clock signal terminal to S2. S1 may or may not be equal to S2.

[0288] It should be understood that, in other exemplary embodiments, there are other methods to reduce the pulse frequency of the effective level on the second clock signal terminal. Figure 7 shows a timing diagram of each signal line and node in another exemplary embodiment of the display panel driving method of this disclosure. LCK2 is the timing diagram of the signals on the second clock signal line, LCK1 is the timing diagram of the signals on the first clock signal line, and STV is the timing diagram of the signals on the initial signal line. The second clock signal terminal can output several signal cycles, pause for a period of time, and then output several more signal cycles. The pause time between signal cycles can be 100µs-100000µs, for example, the pause time can be 100µs, 1000µs, 10000µs, 100000µs, etc. Several signal cycles can be one or more signal cycles. This driving method can also reduce the pulse frequency of the effective level on the second clock signal terminal. Similarly, since the first clock signal line LCK1 simultaneously provides clock signals to the second clock signal terminal of the odd-level shift register unit and the first clock signal terminal of the even-level shift register unit, and the second clock signal line LCK2 simultaneously provides clock signals to the first clock signal terminal of the odd-level shift register unit and the second clock signal terminal of the even-level shift register unit, the pulse frequency of the effective level on the first clock signal line LCK1 and the second clock signal line LCK2 is reduced.

[0289] It should be noted that the display panel driving method is not limited to the gate driving circuit provided in this exemplary embodiment, and can also be applied to gate driving circuits with other structures.

[0290] However, as shown in Figure 6, due to the reduced frequency and speed of the input signal from the first output terminal OUT1 to the lower-level shift register unit, the effective level output of the first output terminal OUT1 of some shift register units may be carried over to the next frame. For example, the effective level pulse W output by the first output terminal of the nth-level shift register unit may be carried over to the next frame, which may lead to driving chaos in the next frame.

[0291] Based on this, Figure 8 shows a schematic diagram of an exemplary embodiment of the shift register unit of this disclosure. The shift register unit is applied to a gate driving circuit, which includes multiple cascaded shift register units. Each shift register unit includes: a first output circuit 1 and a reset circuit 3. The first output circuit 1 is connected to a second control node PD2 and a first output terminal OUT1. The first output circuit 1 is used to respond to the signal of the second control node PD2 to input a valid level to the first output terminal OUT1. The first output terminal OUT1 is used to connect to the input signal terminal IN of the next-level shift register unit. The reset circuit 3 is connected to the second control node PD2 and is used to respond to a reset signal to input an invalid level to the second control node PD2.

[0292] The display panel using this shift register unit can reset all shift register units via a reset circuit before the next frame. During the current frame scan, the first output terminal OUT1 will no longer provide a valid level to the adjacent lower-level shift register unit, thus solving the problem of driving chaos in the next frame.

[0293] As shown in Figure 8, the first output circuit 1 is also connected to the first control node PU1, and the first output circuit 1 is also used to respond to the signal of the first control node PU1 to input an invalid level to the first output terminal OUT1; the reset circuit 3 is also connected to the first control node PU1, and the reset circuit 3 is also used to respond to the reset signal to input a valid level to the first control node PU1. This setting can further prevent the first output terminal OUT1 from providing a valid level to the adjacent lower-level shift register unit.

[0294] It should be noted that the reset signal responded to by the reset circuit 3 may include one or more reset signals. The reset signal responded to by the reset circuit 3 inputting an effective level to the first control node PU1 and the reset signal responded to by inputting an invalid level to the second control node PD2 may be the same reset signal or different reset signals.

[0295] As shown in Figure 8, the reset circuit 3 can be used to respond to the signal at the first reset signal terminal Tre to input a valid level to the first control node PU1, and to respond to the signal at the first reset signal terminal Tre to input an invalid level to the second control node PD2. The duration for which the reset circuit 3 inputs a valid level to the first control node PU1 can be greater than or equal to the scan duration of the two rows of pixel driving circuits; the duration for which the reset circuit 3 inputs an invalid level to the second control node PD2 can be greater than or equal to the scan duration of the two rows of pixel driving circuits.

[0296] In this exemplary embodiment, there may be a blank period between frames, during which the display panel can reset all shift register units via a reset circuit.

[0297] Figure 9 shows a schematic diagram of another exemplary embodiment of the shift register unit of this disclosure. Based on the shift register unit shown in Figure 2, the shift register unit may further include a reset circuit 3. The reset circuit 3 includes a first reset circuit 31 and a second reset circuit 32. The first reset circuit 31 includes a first sub-reset circuit 311 and a second sub-reset circuit 312. The first sub-reset circuit 311 is connected to the first node N1, the third control node PD3, and the first reset signal terminal Tre. The first sub-reset circuit 311 is used to respond to the signal of the first reset signal terminal Tre to connect the first node N1 and the third control node PD3. The second sub-reset circuit 312 is connected to the first reset signal terminal Tre and the third control node PD3. The second sub-reset circuit 312 is used to respond to the signal of the first reset signal terminal Tre to input an invalid level signal to the third control node PD3. The conduction level polarities of the first sub-reset circuit 311 and the second reset circuit 312 are different.

[0298] As shown in Figure 9, the second reset circuit 32 is connected to the second power supply terminal VGL1, the first reset signal terminal Tre, and the first control node PU1. The second reset circuit 32 is used to respond to the signal of the first reset signal terminal Tre to transmit the signal of the second power supply terminal VGL1 to the first control node PU1.

[0299] In this exemplary embodiment, as shown in FIG9, the first sub-reset circuit 311 includes an eleventh transistor T11, the first terminal of which is connected to the first node N1, the second terminal of which is connected to the third control node PD3, and the gate of which is connected to the first reset signal terminal Tre. The second sub-reset circuit 312 is also connected to a first power supply terminal VGH1. The second sub-reset circuit 312 is used to provide an invalid level signal to the third control node PD3 using the first power supply terminal VGH1 in response to the signal from the first reset signal terminal Tre. The second sub-reset circuit 312 may include a twelfth transistor T12, the first terminal of which is connected to the first power supply terminal VGH1, the second terminal of which is connected to the third control node PD3, and the gate of which is connected to the first reset signal terminal Tre. The eleventh transistor T11 and the twelfth transistor T12 have different conduction polarities. For example, the eleventh transistor T11 is a P-type transistor, and the twelfth transistor T12 is an N-type transistor.

[0300] In this exemplary embodiment, as shown in FIG9, the second reset circuit 32 may include a thirteenth transistor T13, the first terminal of the thirteenth transistor T13 being connected to the second power supply terminal VGL1, the second terminal being connected to the first control node PU1, and the gate being connected to the first reset signal terminal Tre. The thirteenth transistor T13 may be an N-type transistor.

[0301] Before the next frame, a high-level signal can be input to the first reset signal terminal Tre. The eleventh transistor T11 turns off, the twelfth transistor T12 turns on, and the first power supply terminal VGH1 inputs an invalid level to the third control node PD3. The first output circuit 1 no longer outputs a valid level signal (low-level signal) to the first output terminal OUT1. Simultaneously, the eleventh transistor T11 disconnects the connection between the input signal terminal IN and the third control node PD3, and the input signal terminal IN no longer inputs a valid level signal to the third control node PD3. Furthermore, the thirteenth transistor T13 turns on, and the second power supply terminal VGL1 inputs a low-level signal to the first control node PU1 through the thirteenth transistor T13. The fourth transistor T4 turns on, and the first power supply terminal VGH1 inputs an invalid level signal (high-level signal) to the first output terminal OUT1 through the fourth transistor T4.

[0302] When the first reset signal terminal Tre outputs a low-level signal, the eleventh transistor T11 is turned on, and the twelfth transistor T12 and the thirteenth transistor T13 are turned off, and the shift register unit is driven normally as shown in Figure 3.

[0303] The polarity of the effective level input to the first control node PU1 and the polarity of the effective level input to the second control node PD2 are determined by the polarity of the conduction level of the first output circuit 1. For example, the fourth transistor T4 is a P-type transistor, and the effective level input to the first control node PU1 is low; the fifth transistor T5 is a P-type transistor, and the effective level input to the second control node PD2 is low.

[0304] Figure 10 shows a schematic diagram of another exemplary embodiment of the shift register unit of this disclosure. Based on the shift register unit shown in Figure 2, the shift register unit further includes a reset circuit 3, which may include a first reset circuit 31 and a second reset circuit 32. The first reset circuit 31 is connected to a first reset signal terminal Tre, a second reset signal terminal Re, a first output terminal OUT1, and a first node N1. The first reset circuit 31 is used to respond to the signal of the first reset signal terminal Tre to transmit the signal of the first output terminal OUT1 to the second reset signal terminal Re, and to respond to the signal of the second reset signal terminal Re to input an invalid level signal to the first node N1. The second reset circuit 32 is connected to a second power supply terminal VGL1, a second reset signal terminal Re, and a first control node PU1. The second reset circuit 32 is used to respond to the signal of the second reset signal terminal Re to transmit the signal of the second power supply terminal VGL1 to the first control node PU1.

[0305] In this exemplary embodiment, as shown in FIG10, the first reset circuit 31 is also connected to the input signal terminal IN. The first reset circuit 31 is used to input an invalid level signal to the first node N1 via the input signal terminal IN in response to the signal of the second reset signal terminal Re. As shown in FIG10, the first reset circuit 31 may include: an eleventh transistor T11 and a twelfth transistor T12. The first terminal of the eleventh transistor T11 is connected to the input signal terminal IN, the second terminal is connected to the first node N1, and the gate is connected to the second reset signal terminal Re. The first terminal of the twelfth transistor T12 is connected to the first output terminal OUT1, the second terminal is connected to the second reset signal terminal Re, and the gate is connected to the first reset signal terminal Tre. The second reset circuit 32 may include: a thirteenth transistor T13. The first terminal of the thirteenth transistor T13 is connected to the second power supply terminal VGL1, the second terminal is connected to the first control node PU1, and the gate is connected to the second reset signal terminal Re. The eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 can all be P-type transistors.

[0306] This exemplary embodiment utilizes the characteristic that the first output terminal OUT1 and the input signal terminal are not simultaneously low-level to achieve self-reset of the shift register unit. Before the next frame, a low-level signal can be input to the first reset signal terminal Tre, turning on the twelfth transistor T12. When the first output terminal OUT1 outputs a low level, the first output terminal OUT1 inputs a low-level signal to the second reset signal terminal Re through the twelfth transistor T12, turning on the eleventh transistor T11. The input signal terminal IN inputs a high-level signal to the first node N1 through the eleventh transistor T11, and the fifth transistor T5 is turned off. The first output circuit 1 no longer inputs a low-level signal to the first output terminal OUT1. Simultaneously, the thirteenth transistor T13 turns on, the second power supply terminal VGL1 inputs a low-level signal to the first control node PU1, the fourth transistor T4 turns on, and the first power supply terminal VGH1 inputs a high-level signal to the first output terminal OUT1.

[0307] When the first reset signal terminal Tre outputs a high-level signal, the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 are turned off, and the shift register unit is driven normally as shown in Figure 3.

[0308] Figure 11 shows a schematic diagram of another exemplary embodiment of the shift register unit of this disclosure. The twelfth transistor T12 can also be an N-type transistor. Accordingly, when the first reset signal terminal outputs a high level, the reset circuit 3 inputs a low-level signal to the first control node PU1 and simultaneously inputs a high-level signal to the first node N1. When the first reset signal terminal Tre outputs a low-level signal, the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 are turned off, and the shift register unit is driven normally using the driving method shown in Figure 3.

[0309] Figure 12 shows a schematic diagram of another exemplary embodiment of the shift register unit of this disclosure. Unlike the shift register unit shown in Figure 11, the first reset circuit 31 is connected to the first power supply terminal VGH1. The first reset circuit 31 is used to input an invalid level signal to the first node N1 via the first power supply terminal VGH1 in response to the signal of the second reset signal terminal Re.

[0310] In this exemplary embodiment, as shown in FIG12, the first reset circuit 31 includes an eleventh transistor T11 and a twelfth transistor T12. The first terminal of the eleventh transistor T11 is connected to the first power supply terminal VGH1, the second terminal is connected to the first node N1, and the gate is connected to the second reset signal terminal Re. The first terminal of the twelfth transistor T12 is connected to the first output terminal OUT1, the second terminal is connected to the second reset signal terminal Re, and the gate is connected to the first reset signal terminal Tre.

[0311] This exemplary embodiment also utilizes the characteristic that the first output terminal OUT1 and the input signal terminal are not simultaneously low-level to achieve self-reset of the shift register unit. Before the next frame, a high-level signal can be input to the first reset signal terminal Tre, and the twelfth transistor T12 is turned on. When the first output terminal OUT1 outputs a low level, the first output terminal OUT1 inputs a low-level signal to the second reset signal terminal Re through the twelfth transistor T12, and the eleventh transistor T11 is turned on. The first power supply terminal VGH1 inputs a high-level signal to the first node N1 through the eleventh transistor T11, and the fifth transistor T5 is turned off. The first output circuit 1 no longer inputs a low-level signal to the first output terminal OUT1. At the same time, the thirteenth transistor T13 is turned on, the second power supply terminal VGL1 inputs a low-level signal to the first control node PU1, the fourth transistor T4 is turned on, and the first power supply terminal VGH1 inputs a high-level signal to the first output terminal OUT1.

[0312] When the first reset signal terminal Tre outputs a low-level signal, the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 are turned off, and the shift register unit is driven normally as shown in Figure 3.

[0313] In this exemplary embodiment, the eleventh transistor T11 and the thirteenth transistor T13 are P-type transistors, and the twelfth transistor T12 is an N-type transistor. It should be understood that in other exemplary embodiments, the twelfth transistor T12 may also be a P-type transistor. Correspondingly, when the first reset signal terminal outputs a low level, the reset circuit 3 inputs a low-level signal to the first control node PU1 and simultaneously inputs a high-level signal to the first node N1. When the first reset signal terminal Tre outputs a high-level signal, the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 are turned off, and the shift register unit is driven normally as shown in Figure 3.

[0314] Figure 13 shows a schematic diagram of another exemplary embodiment of the shift register unit of this disclosure. The shift register unit may include: a first output circuit 1, a first input circuit 41, a second input circuit 42, a first control circuit 5, a second control circuit 6, an isolation circuit 7, and a first inverter 9. The first output circuit 1 is connected to a first control node PU1, a second control node PD2, and a first output terminal OUT1. The first output circuit 1 is used to respond to the signal of the first control node PU1 to input an invalid level to the first output terminal OUT1, and to respond to the signal of the second control node PD2 to input a valid level to the first output terminal OUT1. The first output terminal OUT1 is used to connect to the input signal terminal IN of the next-level shift register unit. The first output circuit 1 may be connected to a second clock signal terminal CK2. The first output circuit 1 is used to respond to the signal of the second control node PD2 by using the second clock signal terminal CK2 to input a valid level to the first output terminal OUT1. The first input circuit 41 is connected to the input signal terminal IN, the first node N1, and the first clock signal terminal CK1. The first input circuit 41 is used to respond to the signal of the first clock signal terminal CK1 to transmit the signal of the input signal terminal IN to the first node N1. The first node N1 is connected to the third control node PD3, and the third control node PD3 is connected to the second control node PD2. The second input circuit 42 is connected to the second power supply terminal VGL1, the first control node PU1, and the third clock signal terminal CK3. The second input circuit 42 is used to respond to the signal of the third clock signal terminal CK3 to transmit the signal of the second power supply terminal VGL1 to the first control node PU1. The first control circuit 5 is connected to the third clock signal terminal CK3 and the third control node. Point PD3 and first control node PU1 are connected. The first control circuit 5 is used to respond to the signal of the third control node PD3 to transmit the signal of the third clock signal terminal CK3 to the first control node PU1. The second control circuit 6 is connected to the first power supply terminal VGH1, the second clock signal terminal CK2, the first control node PU1, and the third control node PD3. The second control circuit 6 is used to respond to the signals of the second clock signal terminal CK2 and the first control node PU1 to transmit the signal of the first power supply terminal VGH1 to the third control node PD3. The isolation circuit 7 is connected to the third control node PD3 and the second control node PD2. The isolation circuit 7 is used to respond to a control signal to connect the third control node PD3 and the second control node PD2. The input terminal of the first inverter 9 is connected to the first output terminal OUT1, and the output terminal is connected to the third output terminal OUT3.

[0315] In this exemplary embodiment, as shown in FIG13, the first output circuit 1 includes: a fourth transistor T4, a first capacitor C1, a fifth transistor T5, a second capacitor C2, and a third capacitor C3. The first electrode of the fourth transistor T4 is connected to the first power supply terminal VGH1, the second electrode is connected to the first output terminal OUT1, and the gate is connected to the first control node PU1. The first electrode of the first capacitor C1 is connected to the first power supply terminal VGH1, and the second electrode is connected to the first control node PU1. The first electrode of the fifth transistor T5 is connected to the second clock signal terminal CK2, the second electrode is connected to the first output terminal OUT1, and the gate is connected to the second control node PD2. The first electrode of the second capacitor C2 is connected to the second control node PD2, and the second electrode is connected to the first output terminal OUT1. The first electrode of the third capacitor C3 is connected to the second power supply terminal VGL1, and the second electrode is connected to the first output terminal OUT1.

[0316] It should be understood that in other exemplary embodiments, the first output circuit 1 may also not include the third capacitor C3.

[0317] In this exemplary embodiment, as shown in FIG13, the first input circuit 41 includes: a first transistor T1, the first terminal of the first transistor T1 is connected to the input signal terminal IN, the second terminal is connected to the first node N1, the gate is connected to the first clock signal terminal CK1, the first node N1 is connected to the third control node PD3, and the second control node PD2 is connected to the third control node PD3.

[0318] In this exemplary embodiment, as shown in FIG13, the second input circuit 42 may include: a third transistor T3, the first terminal of the third transistor T3 being connected to the second power supply terminal VGL1, the second terminal being connected to the first control node PU1, and the gate being connected to the third clock signal terminal CK3.

[0319] In this exemplary embodiment, as shown in FIG13, the first control circuit 5 includes: a second transistor T2, the first terminal of the second transistor T2 is connected to the third clock signal terminal CK3, the second terminal is connected to the first control node PU1, and the gate is connected to the third control node PD3.

[0320] In this exemplary embodiment, as shown in FIG13, the second control circuit 6 includes: a sixth transistor T6 and a seventh transistor T7. The first terminal of the sixth transistor T6 is connected to the first power supply terminal VGH1, and the gate is connected to the first control node PU1. The first terminal of the seventh transistor T7 is connected to the second terminal of the sixth transistor T6, the second terminal is connected to the third control node PD3, and the gate is connected to the second clock signal terminal CK2.

[0321] In this exemplary embodiment, as shown in FIG13, the isolation circuit 7 is also connected to the second power supply terminal VGL1. The isolation circuit 7 is used to respond to the signal of the second power supply terminal VGL1 to connect the third control node PD3 and the second control node PD2. The isolation circuit 7 includes an eighth transistor T8, the first terminal of the eighth transistor T8 is connected to the third control node PD3, the second terminal is connected to the second control node PD2, and the gate is connected to the second power supply terminal VGL1. It should be understood that in other exemplary embodiments, the isolation circuit 7 may also respond to other control signals to connect the third control node PD3 and the second control node PD2. For example, the isolation circuit 7 may also be connected to the first clock signal terminal CK1, and the isolation circuit 7 may be used to respond to the signal of the first clock signal terminal CK1 to connect the third control node PD3 and the second control node PD2.

[0322] In this exemplary embodiment, as shown in FIG13, the first inverter 9 may include: a fifteenth transistor T15 and a sixteenth transistor T16. The first terminal of the fifteenth transistor T15 is connected to the first power supply terminal VGH1, the second terminal is connected to the third output terminal OUT3, and the gate is connected to the first output terminal OUT1. The first terminal of the sixteenth transistor T16 is connected to the second power supply terminal VGL1, the second terminal is connected to the third output terminal OUT3, and the gate is connected to the first output terminal OUT1. The signal polarities on the first power supply terminal VGH1 and the second power supply terminal VGL1 are different. The conduction level of the fifteenth transistor T15 is different from the signal polarity of the first power supply terminal VGH1, and the conduction level of the sixteenth transistor T16 is different from the signal polarity of the second power supply terminal VGL1.

[0323] In this exemplary embodiment, as shown in FIG13, the first power supply terminal VGH1 can be a high-level signal terminal, and the second power supply terminal VGL1 can be a low-level power supply terminal. Correspondingly, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the fifteenth transistor T15 are P-type transistors; the sixteenth transistor T16 is an N-type transistor. It should be understood that in other exemplary embodiments, the transistors can be of other types, and accordingly, the polarity of the signals on the first and second power supply terminals needs to be adjusted accordingly.

[0324] Figure 14 shows the timing diagrams of each node in the shift register unit shown in Figure 13. CK1 is the timing diagram for the first clock signal terminal, CK2 is the timing diagram for the second clock signal terminal, CK3 is the timing diagram for the third clock signal terminal, IN is the timing diagram for the input signal terminal, OUT1 is the timing diagram for the first output terminal, and OUT3 is the timing diagram for the third output terminal.

[0325] The driving method of this shift register unit includes: first stage t1, second stage t2, third stage t3, fourth stage t4, fifth stage t5, and sixth stage t6.

[0326] In the first stage t1: the input signal terminal IN and the first clock signal terminal CK1 output low-level signals, while the second clock signal terminal CK2 and the third clock signal terminal CK3 output high-level signals. The first transistor T1 is turned on, and the input signal terminal IN inputs low-level signals to the first node N1, the third control node PD3, and the second control node PD2. The fifth transistor T5 is turned on, and the second clock signal terminal CK2 inputs a high-level signal to the first output terminal OUT1. Simultaneously, the first control node PU1 maintains the low-level signal from the previous stage, and the fourth transistor T4 is turned on, allowing the first power supply terminal VGH1 to input a high-level signal to the first output terminal through the fourth transistor T4. The first output terminal OUT1 outputs a high-level signal, and the third output terminal OUT3 outputs a low-level signal.

[0327] In the second stage t2: Input signal terminal IN, first clock signal terminal CK1, and second clock signal terminal CK2 output high-level signals, while third clock signal terminal CK3 outputs a low-level signal. Third transistor T3 is turned on, and second power supply terminal VGL1 inputs a low-level signal to first control node PU1 through third transistor T3. Fourth transistor T4 is turned on, and first power supply terminal VGH1 inputs a high-level signal to first output terminal OUT1. Simultaneously, first node N1 maintains a low-level signal. Second transistor T2 is turned on, and third clock signal terminal CK3 inputs a low-level signal to first control node PU1. Second control node PD2 maintains the low-level signal from the previous stage. Fifth transistor T5 is turned on, and second clock signal terminal CK2 inputs a high-level signal to first output terminal OUT1. First output terminal OUT1 outputs a high-level signal, and third output terminal OUT3 outputs a low-level signal.

[0328] In the third stage t3: the second clock signal terminal CK2 outputs a low-level signal, while the input signal terminal IN, the first clock signal terminal CK1, and the third clock signal terminal CK3 output high-level signals. The first node N1 maintains a low-level signal, the second transistor T2 is turned on, the third clock signal terminal CK3 inputs a high-level signal to the first control node PU1, the second control node PD2 maintains the low-level signal from the previous stage, the fifth transistor T5 is turned on, and the second clock signal terminal CK2 inputs a low-level signal to the first output terminal OUT1. The first output terminal OUT1 outputs a low-level signal, and the third output terminal OUT3 outputs a high-level signal.

[0329] In the fourth stage t4: the first clock signal terminal CK1 outputs a low-level signal, while the input signal terminal IN, the second clock signal terminal CK2, and the third clock signal terminal CK3 output high-level signals. The first transistor T1 is turned on, and the input signal terminal IN inputs a high-level signal to the first node, the third control node PD3, and the second control node PD2. The fifth transistor is turned off. Simultaneously, the first control node PU1 maintains the low-level signal from the previous stage, the fourth transistor T4 is turned on, and the first power supply terminal VGH1 inputs a high-level signal to the first output terminal OUT1. The first output terminal OUT1 outputs a high-level signal, and the third output terminal OUT3 outputs a low-level signal.

[0330] In stage t5: the third clock signal terminal CK3 outputs a low-level signal, while the input signal terminal IN, the first clock signal terminal CK1, and the second clock signal terminal CK2 output high-level signals. The second control node PD2 maintains the high-level signal from the previous stage, and the fifth transistor is turned off. Simultaneously, the third transistor T3 is turned on, the second power supply terminal VGL1 inputs a low-level signal to the first control node PU1, the fourth transistor T4 is turned on, and the first power supply terminal VGH1 inputs a high-level signal to the first output terminal OUT1. The first output terminal OUT1 outputs a high-level signal, and the third output terminal OUT3 outputs a low-level signal.

[0331] In stage t6: the second clock signal terminal CK2 outputs a low-level signal, while the input signal terminal IN, the first clock signal terminal CK1, and the third clock signal terminal CK3 output high-level signals. The first control node PU1 maintains the low-level signal from the previous stage, the fourth transistor T4 is turned on, and the first power supply terminal VGH1 inputs a high-level signal to the first output terminal OUT1. Simultaneously, the sixth transistor T6 and the seventh transistor T7 are turned on, and the first power supply terminal VGH1 inputs a high-level signal to the third control node PD3 and the second control node PD2 through the sixth transistor T6 and the seventh transistor T7, while the fifth transistor T5 is turned off. The first output terminal OUT1 outputs a high-level signal, and the third output terminal OUT3 outputs a low-level signal.

[0332] After that, the shift register unit can repeat the fourth, fifth, and sixth stages in sequence.

[0333] As shown in Figure 13, the shift register unit further includes a second output circuit 2. The second output circuit 2 may also include a pre-store circuit 21, a latch circuit 22, a gating circuit 23, and a second inverter 24. The pre-store circuit 21 is connected to the enable signal terminal EM, the first output terminal OUT1, the third output terminal OUT3, and the third node N3 in this shift register unit. The pre-store circuit 21 is used to respond to the signals of the first output terminal OUT1 and the third output terminal OUT3 to transmit the signal of the enable signal terminal EM to the third node N3. The latch circuit 22 is connected to the third node N3 and the fourth node N4. The latch circuit 22 is used to latch the inverted signal of the third node N3 to the fourth node N4. The gating circuit 23 is connected to the first output terminal OUT1, the fourth node N4, the second power supply terminal VGL1, and the fifth node N5 in this shift register unit. The gating circuit 23 is used to respond to the signal of the first output terminal OUT1 to transmit the signal of the fourth node N4 or the signal of the second power supply terminal VGL1 to the fifth node N5. The input of the second inverter 24 is connected to the fifth node N5, and the output is connected to the second output terminal OUT2.

[0334] In this exemplary embodiment, as shown in FIG13, the latch circuit 22 is connected to a first power supply terminal VGH1 and a second power supply terminal VGL1. The first power supply terminal VGH1 and the second power supply terminal VGL1 are respectively used to provide power signals of different polarities to the latch circuit. For example, the first power supply terminal VGH1 can be used to provide a high-level signal, and the second power supply terminal VGL1 can be used to provide a low-level signal. Unlike the second output circuit shown in FIG3, the second inverter 24 is connected to a third power supply terminal VGH2 and a fourth power supply terminal VGL2. The third power supply terminal VGH2 and the fourth power supply terminal VGL2 are respectively used to provide power signals of different polarities to the second inverter 24. The second inverter 24 includes a twenty-fifth transistor T25 and a twenty-sixth transistor T26. The first terminal of the twenty-fifth transistor T25 is connected to the third power supply terminal VGH2, the second terminal is connected to the second output terminal OUT2, and the gate is connected to the fifth node N5. The first terminal of the twenty-sixth transistor T26 is connected to the fourth power supply terminal VGL2, the second terminal is connected to the second output terminal OUT2, and the gate is connected to the fifth node N5. The conduction level of the twenty-fifth transistor T25 has the same polarity as the signal at the second power supply terminal VGL1, and the conduction level of the twenty-sixth transistor T26 has the same polarity as the signal at the third power supply terminal VGH2. For example, the twenty-fifth transistor T25 can be a P-type transistor, and the twenty-sixth transistor T26 can be an N-type transistor. The third power supply terminal VGH2 provides a high-level signal, and the fourth power supply terminal VGL2 provides a low-level signal.

[0335] In this exemplary embodiment, as shown in FIG13, the voltage of the first power supply terminal VGH1 can be greater than or equal to the voltage of the third power supply terminal VGH2, and the voltage of the second power supply terminal VGL1 can be less than or equal to the voltage of the fourth power supply terminal VGL2. As shown in FIG13, the channel width of the transistors (the 25th transistor T25 and the 26th transistor T26) used to output the gate drive signal is relatively large, and the threshold voltages of the 25th transistor T25 and the 26th transistor T26 are close to 0. When the 26th transistor T26 is negatively biased, the threshold voltage of the 26th transistor T26 may be less than 0. If the connection method of the 26th transistor T26 is as shown in FIG3, and the 26th transistor T26 is connected to the second power supply terminal VGL1, the minimum gate-source voltage difference of the 26th transistor T26 is 0, which causes the 26th transistor T26 to be unable to be completely turned off. When the second output terminal OUT2 outputs a high-level signal, there is leakage through the 26th transistor T26 at the second output terminal OUT2, thereby increasing the power consumption of the gate drive circuit. This exemplary embodiment separates the low-power terminals of the second inverter 24 and the latch circuit 22, thereby increasing the fourth power supply terminal VGL2 to ensure that the minimum gate-source voltage difference of the 26th transistor T26 is less than 0, thus reducing the leakage current of the 26th transistor T26. Similarly, when the 25th transistor T25 is forward biased, its threshold voltage may be greater than 0. If the 25th transistor T25 is connected as shown in Figure 3, with the 25th transistor T25 connected to the first power supply terminal VGH1, the maximum gate-source voltage difference of the 25th transistor T25 is 0, causing the 25th transistor T25 to be unable to be completely turned off. When the second output terminal OUT2 outputs a low-level signal, there is leakage current through the 25th transistor T25 at the second output terminal OUT2, thereby increasing the power consumption of the gate drive circuit. This exemplary embodiment separates the high-power terminals of the second inverter and the latch circuit, thereby decreasing the third power supply terminal VGH2 to ensure that the minimum gate-source voltage difference of the 25th transistor T25 is greater than 0, thus reducing the leakage current of the 25th transistor T25.

[0336] Furthermore, in other exemplary embodiments, when the first power supply terminal VGH1 and the third power supply terminal VGH2 provide low-level signals, and the second power supply terminal VGL1 and the fourth power supply terminal VGL2 provide high-level signals, the voltage of the first power supply terminal VGH1 is less than or equal to the voltage of the third power supply terminal VGH2, and the voltage of the second power supply terminal VGL1 is greater than or equal to the voltage of the fourth power supply terminal VGL2.

[0337] In this exemplary embodiment, the second output circuit 2 can be controlled to be in either a first driving state or a second driving state by controlling the potential of the enable signal terminal EM. When the enable signal terminal EM outputs a low level, the second output circuit 2 is in the first driving state; when the enable signal terminal EM outputs a high level, the second output circuit 2 is in the second driving state.

[0338] As shown in Figure 13, when the enable signal terminal EM outputs a high-level signal:

[0339] In the first stage t1 and the second stage t2: the first output terminal OUT1 outputs a high-level signal, the twenty-fourth transistor T24 is turned on, the second power supply terminal VGL1 inputs a low-level signal to the fifth node N5, the twenty-fifth transistor T25 is turned on, and the first power supply terminal VGH1 inputs a high-level signal to the second output terminal OUT2.

[0340] In the third stage t3: the first output terminal OUT1 outputs a low-level signal, the third output terminal OUT3 outputs a high-level signal, the seventeenth transistor T17 and the eighteenth transistor T18 are turned on, the enable signal terminal EM inputs a high-level signal to the third node N3, the twentieth transistor T20 is turned on, the second power supply terminal VGL1 inputs a low-level signal to the fourth node N4, the twenty-first transistor T21 is turned on, the first power supply terminal VGH1 inputs a high-level signal to the third node N3, that is, the latch circuit 22 latches the inverted level signal of the third node N3 to the fourth node. The twenty-third transistor T23 is turned on, the fourth node N4 inputs a low-level signal to the fifth node N5, the twenty-fifth transistor T25 is turned on, the third power supply terminal VGH2 inputs a high-level signal to the second output terminal OUT2.

[0341] Similarly, in the fourth stage t4, the fifth stage t5, and the sixth stage t6, the first output terminal OUT1 outputs a high-level signal, the twenty-fourth transistor T24 is turned on, the second power supply terminal VGL1 inputs a low-level signal to the fifth node N5, the twenty-fifth transistor T25 is turned on, and the first power supply terminal VGH1 inputs a high-level signal to the second output terminal OUT2.

[0342] When the enable signal terminal EM outputs a low-level signal:

[0343] In the first stage t1 and the second stage t2: the first output terminal OUT1 outputs a high-level signal, the twenty-fourth transistor T24 is turned on, the second power supply terminal VGL1 inputs a low-level signal to the fifth node N5, the twenty-fifth transistor T25 is turned on, and the first power supply terminal VGH1 inputs a high-level signal to the second output terminal OUT2.

[0344] In the third stage t3: the first output terminal OUT1 outputs a low-level signal, the third output terminal OUT3 outputs a high-level signal, the seventeenth transistor T17 and the eighteenth transistor T18 are turned on, the enable signal terminal EM inputs a low-level signal to the third node N3, the nineteenth transistor T19 is turned on, the first power supply terminal VGH1 inputs a high-level signal to the fourth node N4, the twenty-second transistor T22 is turned on, the second power supply terminal VGL1 inputs a low-level signal to the third node N3, that is, the latch circuit 22 latches the inverted level signal of the third node N3 to the fourth node. The twenty-third transistor T23 is turned on, the fourth node inputs a high-level signal to the fifth node N5, the twenty-sixth transistor T26 is turned on, the fourth power supply terminal VGL2 inputs a low-level signal to the second output terminal OUT2.

[0345] In the fourth stage t4, the fifth stage t5, and the sixth stage t6, the first output terminal OUT1 outputs a high-level signal, the twenty-fourth transistor T24 is turned on, the second power supply terminal VGL1 inputs a low-level signal to the fifth node N5, the twenty-fifth transistor T25 is turned on, and the first power supply terminal VGH1 inputs a high-level signal to the second output terminal OUT2.

[0346] That is, when the enable signal terminal EM outputs a low-level signal, the second output circuit 2 is in the first driving state, and the second output terminal OUT2 and the first output terminal OUT1 can output signals with the same or similar timing.

[0347] In this exemplary embodiment, as shown in FIG13, compared with the shift register unit shown in FIG3, the gating circuit 23 does not include the fourth capacitor C4. In other exemplary embodiments, the shift register unit shown in FIG13 may also include the fourth capacitor, which is connected between the fifth node N5 and the second power supply terminal VGL1. Furthermore, it should be noted that the second output circuit 2 shown in FIG13 can replace the second output circuit 2 in FIG3, and the second output circuit 2 shown in FIG3 can also replace the second output circuit 2 in FIG13.

[0348] Figure 15 shows a schematic diagram of another exemplary embodiment of the shift register unit of this disclosure. Based on the shift register unit shown in Figure 13, the shift register unit may further include a reset circuit, which includes a first reset circuit 31 and a second reset circuit 32. The first reset circuit 31 includes a first sub-reset circuit 311 and a second sub-reset circuit 312. The first sub-reset circuit 311 is connected to the first node N1, the third control node PD3, and the first reset signal terminal Tre. The first sub-reset circuit 311 is used to respond to the signal of the first reset signal terminal Tre to connect the first node N1 and the third control node PD3. The second sub-reset circuit 312 is connected to the first reset signal terminal Tre and the third control node PD3. The second sub-reset circuit 312 is used to respond to the signal of the first reset signal terminal Tre to input an invalid level signal to the third control node PD3. The conduction polarities of the first sub-reset circuit 311 and the second sub-reset circuit 312 are different. The second reset circuit 32 is connected to the second power supply terminal VGL1, the first reset signal terminal Tre, and the first control node PU1. The second reset circuit 32 is used to respond to the signal of the first reset signal terminal Tre to transmit the signal of the second power supply terminal VGL1 to the first control node PU1.

[0349] In this exemplary embodiment, as shown in FIG15, the first sub-reset circuit 311 includes an eleventh transistor T11, the first terminal of which is connected to the first node N1, the second terminal of which is connected to the third control node PD3, and the gate of which is connected to the first reset signal terminal Tre. The second sub-reset circuit 312 is also connected to a first power supply terminal VGH1. The second sub-reset circuit 312 is used to provide an invalid level signal to the third control node PD3 using the first power supply terminal VGH1 in response to the signal from the first reset signal terminal Tre. The second sub-reset circuit 312 may include a twelfth transistor T12, the first terminal of which is connected to the first power supply terminal VGH1, the second terminal of which is connected to the third control node PD3, and the gate of which is connected to the first reset signal terminal Tre. The eleventh transistor T11 and the twelfth transistor T12 have different conduction polarities. For example, the eleventh transistor T11 is a P-type transistor, and the twelfth transistor T12 is an N-type transistor.

[0350] In this exemplary embodiment, as shown in FIG15, the second reset circuit 32 includes a thirteenth transistor T13. The first terminal of the thirteenth transistor T13 is connected to the second power supply terminal VGL1, the second terminal is connected to the first control node PU1, and the gate is connected to the first reset signal terminal Tre. The thirteenth transistor T13 can be an N-type transistor.

[0351] Before the next frame, a high-level signal can be input to the first reset signal terminal Tre. The eleventh transistor T11 turns off, the twelfth transistor T12 turns on, and the first power supply terminal VGH1 inputs an invalid level to the third control node PD3. The first output circuit 1 no longer outputs a low-level signal to the first output terminal OUT1. Simultaneously, the eleventh transistor T11 disconnects the connection between the input signal terminal IN and the third control node PD3, and the input signal terminal IN no longer inputs a valid level signal to the third control node PD3. Furthermore, the thirteenth transistor T13 turns on, and the second power supply terminal VGL1 inputs a low-level signal to the first control node PU1 through the thirteenth transistor T13. The fourth transistor T4 turns on, and the first power supply terminal VGH1 inputs a high-level signal to the first output terminal OUT1 through the fourth transistor T4.

[0352] When the first reset signal terminal Tre outputs a low-level signal, the eleventh transistor T11 is turned on, and the twelfth transistor T12 and the thirteenth transistor T13 are turned off, and the shift register unit is driven normally as shown in Figure 14.

[0353] It should be understood that, in other exemplary embodiments, the twelfth transistor T12 and the thirteenth transistor T13 may also be P-type transistors.

[0354] Figure 16 shows a schematic diagram of another exemplary embodiment of the shift register unit of this disclosure. Based on the shift register unit shown in Figure 13, the shift register unit further includes a reset circuit 3, which may include a first reset circuit 31 and a second reset circuit 32. The first reset circuit 31 is connected to a first reset signal terminal Tre, a second reset signal terminal Re, a first output terminal OUT1, and a first node N1. The first reset circuit 31 is used to respond to the signal of the first reset signal terminal Tre to transmit the signal of the first output terminal OUT1 to the second reset signal terminal Re, and to respond to the signal of the second reset signal terminal Re to input an invalid level signal to the first node N1. The second reset circuit 32 is connected to a second power supply terminal VGL1, a second reset signal terminal Re, and a first control node PU1. The second reset circuit 32 is used to respond to the signal of the second reset signal terminal Re to transmit the signal of the second power supply terminal VGL1 to the first control node PU1.

[0355] In this exemplary embodiment, as shown in FIG16, the first reset circuit 31 is also connected to the input signal terminal IN. The first reset circuit 31 is used to input an invalid level signal to the first node N1 via the input signal terminal IN in response to the signal of the second reset signal terminal Re. As shown in FIG16, the first reset circuit 31 may include: an eleventh transistor T11 and a twelfth transistor T12. The first terminal of the eleventh transistor T11 is connected to the input signal terminal IN, the second terminal is connected to the first node N1, and the gate is connected to the second reset signal terminal Re. The first terminal of the twelfth transistor T12 is connected to the first output terminal OUT1, the second terminal is connected to the second reset signal terminal Re, and the gate is connected to the first reset signal terminal Tre. The second reset circuit 32 may include: a thirteenth transistor T13. The first terminal of the thirteenth transistor T13 is connected to the second power supply terminal VGL1, the second terminal is connected to the first control node PU1, and the gate is connected to the second reset signal terminal Re. The eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 can all be P-type transistors.

[0356] This exemplary embodiment utilizes the characteristic that the first output terminal OUT1 and the input signal terminal are not simultaneously low-level to achieve self-reset of the shift register unit. Before the next frame, a low-level signal can be input to the first reset signal terminal Tre, turning on the twelfth transistor T12. When the first output terminal OUT1 outputs a low level, the first output terminal OUT1 inputs a low-level signal to the second reset signal terminal Re through the twelfth transistor T12, turning on the eleventh transistor T11. The input signal terminal IN inputs a high-level signal to the first node N1 through the eleventh transistor T11, and the fifth transistor T5 is turned off. The first output circuit 1 no longer inputs a low-level signal to the first output terminal OUT1. Simultaneously, the thirteenth transistor T13 turns on, the second power supply terminal VGL1 inputs a low-level signal to the first control node PU1, the fourth transistor T4 turns on, and the first power supply terminal VGH1 inputs a high-level signal to the first output terminal OUT1.

[0357] When the first reset signal terminal Tre outputs a high-level signal, the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 are turned off, and the shift register unit is driven normally as shown in Figure 13.

[0358] It should be understood that in other exemplary embodiments, the twelfth transistor T12 can also be an N-type transistor. Accordingly, when the first reset signal terminal outputs a high level, the reset circuit 3 inputs a low-level signal to the first control node PU1 and a high-level signal to the first node N1. When the first reset signal terminal Tre outputs a low-level signal, the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 are turned off, and the shift register unit is driven normally as shown in Figure 14.

[0359] Figure 17 shows a schematic diagram of another exemplary embodiment of the shift register unit of this disclosure. Unlike the shift register unit shown in Figure 16, the first reset circuit 31 is connected to the first power supply terminal VGH1. The first reset circuit 31 is used to input an invalid level signal to the first node N1 using the first power supply terminal VGH1 in response to the signal of the second reset signal terminal Re.

[0360] Figure 18 shows a schematic diagram of an exemplary embodiment of the gate driving circuit of this disclosure. The first output terminal OUT1 of the m-th stage shift register unit is connected to the input signal terminal IN of the (m+2)-th stage shift register unit. m can be an integer greater than or equal to 0. The 0-th stage shift register unit forms the initial stage shift register unit, which can be virtual, meaning it is not connected to the pixel driving circuit. The input signal terminals IN of the initial stage shift register unit and the first stage shift register unit are connected to the initial signal line STV. Furthermore, this exemplary embodiment includes four clock signal lines: a first clock signal line LCK1, a second clock signal line LCK2, a third clock signal line LCK3, and a fourth clock signal line LCK4. The first, third, and second clock signal terminals of the initial stage shift register unit are connected to the first clock signal line LCK1, the third clock signal line LCK3, and the second clock signal line LCK2, respectively. The first, third, and second clock signal terminals of the first stage shift register unit are connected to the third clock signal line LCK3, the second clock signal line LCK2, and the fourth clock signal line LCK4, respectively. The first, third, and second clock signal terminals of the second stage shift register unit are connected to the second clock signal line LCK2 and the fourth clock signal line LCK4, respectively. 4. The first clock signal line LCK1; the first, third, and second clock signal terminals of the third-stage shift register unit are respectively connected to the fourth clock signal line LCK4, the first clock signal line LCK1, and the third clock signal line LCK3; the first, third, and second clock signal terminals of the fourth-stage shift register unit are reconnected to the first clock signal line LCK1, the third clock signal line LCK3, and the second clock signal line LCK2, and so on, selecting three of the four clock signal lines in sequence to provide clock signals to the three clock signal terminals in the shift register unit.

[0361] Figure 19 shows a timing diagram of each signal line and node in an exemplary embodiment of the display panel driving method of this disclosure. LCK1 is the timing diagram of the signals on the first clock signal line, LCK2 is the timing diagram of the signals on the second clock signal line, LCK3 is the timing diagram of the signals on the third clock signal line, LCK4 is the timing diagram of the signals on the fourth clock signal line, STV is the timing diagram of the signals on the initial signal line, OUT2-0 represents the timing diagram of the second output terminal of the initial stage shift register unit, OUT2-1 represents the timing diagram of the second output terminal of the first stage shift register unit, OUT1-0 represents the timing diagram of the first output terminal of the initial stage shift register unit, and OUT1-1 represents the timing diagram of the first output terminal of the first stage shift register unit.

[0362] In this exemplary embodiment, FIG19 illustrates the output mode of the shift register unit in a frame of the display panel. The display panel includes a low-frequency display area and a high-frequency display area. In the low-frequency display area: the first output terminal OUT1 of the shift register unit normally outputs the input signal to realize the cascading setting of the shift register units. At the same time, the second output terminal OUT2 of the shift register unit outputs an invalid level signal (high level) to realize partial refresh of the display panel. In the high-frequency display area: the first output terminal OUT1 and the second output terminal OUT2 of the shift register unit output the input signal and the gate drive signal, respectively.

[0363] Figure 20 shows a schematic diagram of another exemplary embodiment of the shift register unit of this disclosure. The shift register unit includes: a first output circuit 1, a first input circuit 41, a second input circuit 42, a first leakage protection circuit 8, a first control circuit 5, a second leakage protection circuit 6, and a first inverter 9. The first output circuit 1 is used to respond to the signal of the first control node PU1 to input an invalid level to the first output terminal OUT1, and to respond to the signal of the second control node PD2 to input a valid level to the first output terminal OUT1. The first output terminal OUT1 is used to connect to the input signal terminal IN of the next-level shift register unit. The first output circuit 1 can be connected to the second clock signal terminal CK2. The first output circuit 1 is used to respond to the signal of the second control node PD2 by using the second clock signal terminal CK2 to input a valid level to the first output terminal OUT1.The first input circuit 41 is connected to the input signal terminal IN, the second node N2, the first node N1, and the first clock signal terminal CK1. The first input circuit 41 is used to respond to the signal from the first clock signal terminal CK1 to transmit the signal from the input signal terminal IN to the second node N2, and to respond to the signal from the first clock signal terminal CK1 to transmit the signal from the second node N2 to the first node N1. The first node N1 is connected to the third control node PD3, and the third control node PD3 is connected to the second control node PD2. The second input circuit 42 is connected to the input signal terminal IN, the first power supply terminal VGH1, the first control node PU1, the second power supply terminal VGL1, and the third clock signal terminal CK3. The second input circuit 42 is used to respond to the signal from the input signal terminal IN to transmit the signal from the first power supply terminal VGH1 to the first control node PU1, and to respond to the signal from the third clock signal terminal CK3 to transmit the signal from the second power supply terminal VGL1 to the first control node PU1. 1. A first leakage protection circuit 8 is connected to a second clock signal terminal CK2, a second node N2, and a first output terminal OUT1. The first leakage protection circuit 8 is used to respond to the signal of the first output terminal OUT1 to transmit the signal of the second clock signal terminal CK2 to the second node N2. A first control circuit 5 is connected to a first power supply terminal VGH1, a first control node PU1, a third control node PD3, and a fourth control node PD4. The first control circuit 5 is used to respond to the signal of the first control node PU1 to transmit the signal of the first power supply terminal VGH1 to the fourth control node PD4, and to respond to the signal of the first control node PU1 to transmit the signal of the fourth control node PD4 to the third control node PD3. A second leakage protection circuit 6 is connected to the third control node PD3, a second power supply terminal VGL1, and the fourth control node PD4. The second leakage protection circuit 6 is used to respond to the signal of the third control node PD3 to transmit the signal of the second power supply terminal VGL1 to the fourth control node PD4. The input terminal of a first inverter 9 is connected to the first output terminal OUT1, and the output terminal is connected to the third output terminal OUT3.

[0364] In this exemplary embodiment, as shown in FIG20, the first output circuit 1 includes: a fourth transistor T4, a first capacitor C1, a fifth transistor T5, and a second capacitor C2. The first electrode of the fourth transistor T4 is connected to the first power supply terminal VGH1, the second electrode is connected to the first output terminal OUT1, and the gate is connected to the first control node PU1. The first electrode of the first capacitor C1 is connected to the first power supply terminal VGH1, and the second electrode is connected to the first control node PU1. The first electrode of the fifth transistor T5 is connected to the second clock signal terminal CK2, the second electrode is connected to the first output terminal OUT1, and the gate is connected to the second control node PD2. The first electrode of the second capacitor C2 is connected to the first control node PU1, and the second electrode is connected to the first output terminal OUT1.

[0365] As shown in Figure 20, the first input circuit 41 includes: a fourteenth transistor T14 and a first transistor T1. The first terminal of the fourteenth transistor T14 is connected to the input signal terminal IN, the second terminal is connected to the second node N2, and the gate is connected to the first clock signal terminal CK1. The first terminal of the first transistor T1 is connected to the second node N2, the second terminal is connected to the first node N1, and the gate is connected to the first clock signal terminal CK1.

[0366] As shown in Figure 20, the second input circuit 42 includes: a seventh transistor T7 and a third transistor T3. The first terminal of the seventh transistor T7 is connected to the first power supply terminal VGH1, the second terminal is connected to the first control node PU1, and the gate is connected to the input signal terminal IN. The first terminal of the third transistor T3 is connected to the second power supply terminal VGL1, the second terminal is connected to the first control node PU1, and the gate is connected to the third clock signal terminal CK3.

[0367] As shown in Figure 20, the first leakage protection circuit 8 includes: a second transistor T2, the first terminal of the second transistor T2 is connected to the second clock signal terminal CK2, the second terminal is connected to the second node N2, and the gate is connected to the first output terminal OUT1.

[0368] As shown in Figure 20, the first control circuit 5 includes: a ninth transistor T9 and a tenth transistor T10. The first terminal of the ninth transistor T9 is connected to the third control node PD3, the second terminal is connected to the fourth control node PD4, and the gate is connected to the first control node PU1. The first terminal of the tenth transistor T10 is connected to the first power supply terminal VGH1, the second terminal is connected to the fourth control node PD4, and the gate is connected to the first control node PU1.

[0369] As shown in Figure 20, the second leakage protection circuit 6 includes: a sixth transistor T6, the first terminal of the sixth transistor T6 is connected to the second power supply terminal VGL1, the second terminal is connected to the fourth control node PD4, and the gate is connected to the third control node PD3.

[0370] As shown in Figure 20, the first inverter 9 includes a fifteenth transistor T15 and a sixteenth transistor T16. The first terminal of the fifteenth transistor T15 is connected to the first power supply terminal VGH1, the second terminal is connected to the third output terminal OUT3, and the gate is connected to the first output terminal OUT1. The first terminal of the sixteenth transistor T16 is connected to the second power supply terminal VGL1, the second terminal is connected to the third output terminal OUT3, and the gate is connected to the first output terminal OUT1. The signal polarities on the first power supply terminal VGH1 and the second power supply terminal VGL1 are different. The conduction level of the fifteenth transistor T15 is different from the signal polarity of the first power supply terminal VGH1, and the conduction level of the sixteenth transistor T16 is different from the signal polarity of the second power supply terminal VGL1.

[0371] In this exemplary embodiment, as shown in FIG20, the first power supply terminal VGH1 can be a high-level signal terminal, and the second power supply terminal VGL1 can be a low-level power supply terminal. Correspondingly, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the ninth transistor T9, the tenth transistor T10, the fourteenth transistor T14, and the fifteenth transistor T15 are P-type transistors; the sixteenth transistor T16 is an N-type transistor. It should be understood that in other exemplary embodiments, the transistors can be of other types, and correspondingly, the polarity of the signals on the first and second power supply terminals needs to be adjusted accordingly.

[0372] Figure 21 shows the timing diagram of each node in a driving method of the shift register unit of this disclosure. CK1 is the timing diagram of the first clock signal terminal, CK2 is the timing diagram of the second clock signal terminal, CK3 is the timing diagram of the third clock signal terminal, IN is the timing diagram of the input signal terminal, OUT1 is the timing diagram of the first output terminal, and OUT3 is the timing diagram of the third output terminal.

[0373] The driving method of this shift register unit includes: first stage t1, second stage t2, third stage t3, fourth stage t4, fifth stage t5, and sixth stage t6.

[0374] In the first stage t1: the input signal terminal IN and the first clock signal terminal CK1 output low-level signals, while the second clock signal terminal CK2 and the third clock signal terminal CK3 output high-level signals. The first transistor T1 and the fourteenth transistor T14 are turned on, and the input signal terminal IN inputs low-level signals to the first node N1, the third control node PD3, and the second control node PD2. The fifth transistor T5 is turned on, and the second clock signal terminal CK2 inputs a high-level signal to the first output terminal OUT1. At the same time, the seventh transistor T7 is turned on, and the first power supply terminal VGH1 inputs a high-level signal to the first control node PU1. The fourth transistor T4 is turned off, and the first output terminal OUT1 outputs a high-level signal, while the third output terminal OUT3 outputs a low-level signal.

[0375] In the second stage t2: Input signal terminal IN, first clock signal terminal CK1, and third clock signal terminal CK3 output high-level signals, while second clock signal terminal CK2 outputs a low-level signal. First node N1 and second control node PD2 maintain low-level signals. Fifth transistor T5 is turned on, and second clock signal terminal CK2 inputs a low-level signal to first output terminal OUT1. Simultaneously, second transistor T2 is turned on, and second clock signal terminal CK2 inputs a low-level signal to second node N2. This setting reduces leakage current from first node N1 to input signal terminal IN. Sixth transistor T6 is turned on, and second power supply terminal VGL1 inputs a low-level signal to fourth control node PD4. This setting reduces leakage current from first node N1 to first power supply terminal VGH1. First control node PU1 maintains a high-level signal, and fourth transistor T4 remains off. First output terminal OUT1 outputs a low-level signal, and third output terminal OUT3 outputs a high-level signal.

[0376] In the third stage t3: the third clock signal terminal CK3 outputs a low-level signal, while the input signal terminal IN, the first clock signal terminal CK1, and the second clock signal terminal CK2 output high-level signals. The third transistor T3 is turned on, and the second power supply terminal VGL1 inputs a low-level signal to the first control node PU1. The fourth transistor T4 is turned on, and the first power supply terminal VGH1 inputs a high-level signal to the first output terminal OUT1. Simultaneously, the ninth transistor T9 and the tenth transistor T10 are turned on, and the first power supply terminal VGH1 inputs a high-level signal to the third control node PD3. The fifth transistor T5 is turned off. The first output terminal OUT1 outputs a high-level signal, and the third output terminal OUT3 outputs a low-level signal.

[0377] In the fourth stage t4: the first clock signal terminal CK1 outputs a low-level signal, while the input signal terminal IN, the second clock signal terminal CK2, and the third clock signal terminal CK3 output high-level signals. The first transistor T1 and the fourteenth transistor T14 are turned on. The input signal terminal IN inputs a high-level signal to the first node N1, the third control node PD3, and the second control node PD2. The fifth transistor T5 is turned off. The first control node PU1 maintains the low-level signal from the previous stage. The fourth transistor T4 is turned on. The first power supply terminal VGH1 inputs a high-level signal to the first output terminal OUT1. The first output terminal OUT1 outputs a high-level signal, and the third output terminal OUT3 outputs a low-level signal.

[0378] In stage t5: the second clock signal terminal CK2 outputs a low-level signal, while the input signal terminal IN, the first clock signal terminal CK1, and the third clock signal terminal CK3 output high-level signals. The first control node PU1 maintains the low-level signal from the previous stage, the fourth transistor T4 is turned on, the first power supply terminal VGH1 inputs a high-level signal to the first output terminal OUT1, the ninth transistor T9 and the tenth transistor T10 are turned on, the first power supply terminal VGH1 inputs a high-level signal to the third control node PD3, and the fifth transistor T5 is turned off. The first output terminal OUT1 outputs a high-level signal, and the third output terminal OUT3 outputs a low-level signal.

[0379] In stage t6: the third clock signal terminal CK3 outputs a low-level signal, while the input signal terminal IN, the first clock signal terminal CK1, and the second clock signal terminal CK2 output high-level signals. The third transistor T3 is turned on, and the second power supply terminal VGL1 inputs a low-level signal to the first control node PU1. The fourth transistor T4 is turned on, and the first power supply terminal VGH1 inputs a high-level signal to the first output terminal OUT1. Simultaneously, the ninth transistor T9 and the tenth transistor T10 are turned on, and the first power supply terminal VGH1 inputs a high-level signal to the third control node PD3. The fifth transistor T5 is turned off. The first output terminal OUT1 outputs a high-level signal, and the third output terminal OUT3 outputs a low-level signal.

[0380] After that, the shift register unit can repeat the fourth, fifth, and sixth stages in sequence.

[0381] Figure 22 shows a schematic diagram of another exemplary embodiment of the shift register unit of this disclosure. Based on the shift register unit shown in Figure 20, the shift register unit may further include a reset circuit, which includes a first reset circuit 31 and a second reset circuit 32. The first reset circuit 31 includes a first sub-reset circuit 311 and a second sub-reset circuit 312. The first sub-reset circuit 311 is connected to the first node N1, the third control node PD3, and the first reset signal terminal Tre. The first sub-reset circuit 311 is used to respond to the signal of the first reset signal terminal Tre to connect the first node N1 and the third control node PD3. The second sub-reset circuit 312 is connected to the first reset signal terminal Tre and the third control node PD3. The second sub-reset circuit 312 is used to respond to the signal of the first reset signal terminal Tre to input an invalid level signal to the third control node PD3. The conduction polarities of the first sub-reset circuit 311 and the second sub-reset circuit 312 are different. The second reset circuit 32 is connected to the second power supply terminal VGL1, the first reset signal terminal Tre, and the first control node PU1. The second reset circuit 32 is used to respond to the signal of the first reset signal terminal Tre to transmit the signal of the second power supply terminal VGL1 to the first control node PU1.

[0382] In this exemplary embodiment, as shown in FIG22, the first sub-reset circuit 311 includes an eleventh transistor T11, the first terminal of which is connected to the first node N1, the second terminal of which is connected to the third control node PD3, and the gate of which is connected to the first reset signal terminal Tre. The second sub-reset circuit 312 is also connected to a first power supply terminal VGH1. The second sub-reset circuit 312 is used to provide an invalid level signal to the third control node PD3 via the first power supply terminal VGH1 in response to the signal from the first reset signal terminal Tre. The second sub-reset circuit 312 may include a twelfth transistor T12, the first terminal of which is connected to the first power supply terminal VGH1, the second terminal of which is connected to the third control node PD3, and the gate of which is connected to the first reset signal terminal Tre. The eleventh transistor T11 and the twelfth transistor T12 have different conduction polarities. For example, the eleventh transistor T11 is a P-type transistor, and the twelfth transistor T12 is an N-type transistor.

[0383] In this exemplary embodiment, as shown in FIG22, the second reset circuit 32 includes a thirteenth transistor T13. The first terminal of the thirteenth transistor T13 is connected to the second power supply terminal VGL1, the second terminal is connected to the first control node PU1, and the gate is connected to the first reset signal terminal Tre. The thirteenth transistor T13 can be an N-type transistor.

[0384] Before the next frame, a high-level signal can be input to the first reset signal terminal Tre. The eleventh transistor T11 turns off, the twelfth transistor T12 turns on, and the first power supply terminal VGH1 inputs an invalid level to the third control node PD3. The first output circuit 1 no longer outputs a valid level signal (low-level signal) to the first output terminal OUT1. Simultaneously, the eleventh transistor T11 disconnects the connection between the input signal terminal IN and the third control node PD3, and the input signal terminal IN no longer inputs a valid level signal to the third control node PD3. Furthermore, the thirteenth transistor T13 turns on, and the second power supply terminal VGL1 inputs a low-level signal to the first control node PU1 through the thirteenth transistor T13. The fourth transistor T4 turns on, and the first power supply terminal VGH1 inputs a high-level signal to the first output terminal OUT1 through the fourth transistor T4.

[0385] When the first reset signal terminal Tre outputs a low-level signal, the eleventh transistor T11 is turned on, and the twelfth transistor T12 and the thirteenth transistor T13 are turned off, and the shift register unit is driven normally as shown in Figure 21.

[0386] Figure 23 shows a schematic diagram of another exemplary embodiment of the shift register unit of this disclosure. Based on the shift register unit shown in Figure 20, the shift register unit further includes a reset circuit 3, which may include a first reset circuit 31 and a second reset circuit 32. The first reset circuit 31 is connected to a first reset signal terminal Tre, a second reset signal terminal Re, a first output terminal OUT1, and a first node N1. The first reset circuit 31 is used to respond to the signal of the first reset signal terminal Tre to transmit the signal of the first output terminal OUT1 to the second reset signal terminal Re, and to respond to the signal of the second reset signal terminal Re to input an invalid level signal to the first node N1. The second reset circuit 32 is connected to a second power supply terminal VGL1, a second reset signal terminal Re, and a first control node PU1. The second reset circuit 32 is used to respond to the signal of the second reset signal terminal Re to transmit the signal of the second power supply terminal VGL1 to the first control node PU1.

[0387] In this exemplary embodiment, as shown in FIG23, the first reset circuit 31 is also connected to the input signal terminal IN. The first reset circuit 31 is used to input an invalid level signal to the first node N1 via the input signal terminal IN in response to the signal of the second reset signal terminal Re. As shown in FIG23, the first reset circuit 31 may include: an eleventh transistor T11 and a twelfth transistor T12. The first terminal of the eleventh transistor T11 is connected to the input signal terminal IN, the second terminal is connected to the first node N1, and the gate is connected to the second reset signal terminal Re. The first terminal of the twelfth transistor T12 is connected to the first output terminal OUT1, the second terminal is connected to the second reset signal terminal Re, and the gate is connected to the first reset signal terminal Tre. The second reset circuit 32 may include: a thirteenth transistor T13. The first terminal of the thirteenth transistor T13 is connected to the second power supply terminal VGL1, the second terminal is connected to the first control node PU1, and the gate is connected to the second reset signal terminal Re. The eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 can all be P-type transistors.

[0388] This exemplary embodiment utilizes the characteristic that the first output terminal OUT1 and the input signal terminal are not simultaneously low-level to achieve self-reset of the shift register unit. Before the next frame, a low-level signal can be input to the first reset signal terminal Tre, turning on the twelfth transistor T12. When the first output terminal OUT1 outputs a low level, the first output terminal OUT1 inputs a low-level signal to the second reset signal terminal Re through the twelfth transistor T12, turning on the eleventh transistor T11. The input signal terminal IN inputs a high-level signal to the first node N1 through the eleventh transistor T11, and the fifth transistor T5 is turned off. The first output circuit 1 no longer inputs a low-level signal to the first output terminal OUT1. Simultaneously, the thirteenth transistor T13 turns on, the second power supply terminal VGL1 inputs a low-level signal to the first control node PU1, the fourth transistor T4 turns on, and the first power supply terminal VGH1 inputs a high-level signal to the first output terminal OUT1.

[0389] When the first reset signal terminal Tre outputs a high-level signal, the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 are turned off, and the shift register unit is driven normally as shown in Figure 21.

[0390] It should be understood that in other exemplary embodiments, the twelfth transistor T12 can also be an N-type transistor. Accordingly, when the first reset signal terminal outputs a high level, the reset circuit 3 inputs a low-level signal to the first control node PU1 and a high-level signal to the first node N1. When the first reset signal terminal Tre outputs a low-level signal, the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 are turned off, and the shift register unit is driven normally as shown in Figure 21.

[0391] Figure 24 shows a schematic diagram of another exemplary embodiment of the shift register unit of this disclosure. Unlike the shift register unit shown in Figure 23, the first reset circuit 31 is connected to the first power supply terminal VGH1. The first reset circuit 31 is used to input an invalid level signal to the first node N1 via the first power supply terminal VGH1 in response to the signal of the second reset signal terminal Re.

[0392] In this exemplary embodiment, the shift register unit shown in Figures 20, 22, 23, and 24 may further include the second output circuit shown in Figure 3 or Figure 13.

[0393] In all the above embodiments, only the low-frequency display area forming the end scan area can reduce power consumption by adjusting the pulse frequency of the signal on the second clock signal terminal. For example, the display panel includes 1080 rows of pixel driving circuits, where the first row of pixel driving circuits to the 360th row are low-frequency scanning areas, the 361st row of pixel driving circuits to the 720th row are high-frequency scanning areas, and the 721st row of pixel driving circuits to the 1080th row are low-frequency scanning areas. To prevent the shift register unit corresponding to the 360th row of pixel driving circuits from inputting abnormal input signals to the shift register unit corresponding to the 361st row of pixel driving circuits, this exemplary embodiment can only adjust the pulse frequency of the second clock signal terminal signal of the shift register units corresponding to the 721st row of pixel driving circuits to the 1080th row of pixel driving circuits.

[0394] In this exemplary embodiment, to significantly reduce the power consumption of the gate driving circuit, an exemplary embodiment also proposes a gate driving circuit, which includes multiple shift register units as described above, and the multiple shift register units are cascaded. Figure 25 shows a schematic diagram of another exemplary embodiment of the gate driving circuit disclosed herein. The gate driving circuit may include: multiple shift register unit groups GOAz and a switching unit K. The shift register unit group GOAz includes multiple cascaded shift register units GOA; two cascaded shift register units located in different shift register unit groups GOAz are cascaded through the switching unit K; wherein the first-stage shift register unit in each shift register unit group is connected to different initialization signal terminals.

[0395] As shown in Figure 25, the gate drive circuit may include three shift register unit groups: GOAz1, GOAz2, and GOAz3. Shift register unit group GOAz1 includes shift register units from level 1 GOA1 to level 360 GOA360; shift register unit group GOAz2 includes shift register units from level 361 GOA361 to level 720 GOA720; and shift register unit group GOAz3 includes shift register units from level 721 GOA721 to level 1080 GOA1080. The first-level shift register unit GOA1 to the 360th-level shift register unit GOA360 provide gate drive signals to the first to the 360th row pixel drive circuits, respectively. The 361st-level shift register unit GOA361 to the 720th-level shift register unit GOA720 provide gate drive signals to the 361st to the 720th row pixel drive circuits, respectively. The 721st-level shift register unit GOA721 to the 1080th-level shift register unit GOA1080 provide gate drive signals to the 721st to the 1080th row pixel drive circuits, respectively. Simultaneously, the gate drive circuit may include two switching units K1 and K2, and three initial signal lines STV1, STV2, and STV3. Switching unit K1 is connected between shift register unit groups GOAz1 and GOAz2, and switching unit K2 is connected between shift register unit groups GOAz2 and GOAz3. The initial signal line STV1 provides the input signal to the first shift register unit in shift register unit group GOAz1; the initial signal line STV2 provides the input signal to the first shift register unit in shift register unit group GOAz2; and the initial signal line STV3 provides the input signal to the first shift register unit in shift register unit group GOAz3.

[0396] When the pixel driving circuits from row 1 to row 360 are in the low-frequency scanning area, the pixel driving circuits from row 361 to row 720 are in the high-frequency scanning area, and the pixel driving circuits from row 721 to row 1080 are in the low-frequency scanning area, this exemplary embodiment can turn off the switching unit K1 to disconnect the shift register unit group GOAz1 and shift register unit group GOAz2. The initial signal line STV2 can provide an input signal to the first-level shift register unit of shift register unit group GOAz2. The shift register units in shift register unit group GOAz2 do not need to provide input signals from the shift register units in shift register unit group GOAz1. Therefore, the low-frequency display area corresponding to shift register unit group GOAz1 can also reduce power consumption by adjusting the pulse frequency on the second clock signal terminal.

[0397] Accordingly, this exemplary embodiment provides a display panel driving method, the display panel including a plurality of sub-display areas, at least a portion of the low-frequency display area forming the end scan area of ​​the sub-display area, and in the same frame of the same sub-display area, the driving method includes:

[0398] When the shift register unit corresponding to the low-frequency display area that forms the end scan area is in the second driving state, the pulse frequency of the effective level on the second clock signal terminal CK2 is set to n2;

[0399] When the shift register unit corresponding to the high-frequency display area is in the first driving state, the pulse frequency of the effective level on the second clock signal terminal CK2 is set to n1;

[0400] Where n1 is greater than or equal to n2.

[0401] As shown in Figure 25, this exemplary embodiment divides the display panel into three sub-display areas, each corresponding to one of three shift register unit groups. It should be understood that in other exemplary embodiments, the display panel can be divided into other numbers of sub-display areas, each sub-display area corresponding to one shift register unit group. Furthermore, each sub-display area may include a different number of rows of pixel driving circuits, and the number of rows of pixel driving circuits in each sub-display area may be the same or different.

[0402] As shown in Figure 25, this exemplary embodiment provides input signals to different initial signal terminals through different initial signal lines. When the number of shift register unit groups in the gate drive circuit is large, the number of initial signal lines required by the gate drive circuit is also large, which is not conducive to the narrow bezel design of the display panel.

[0403] Figure 26 shows a schematic diagram of another exemplary embodiment of the gate driving circuit of this disclosure. This gate driving circuit includes eight shift register unit groups GOAz. Furthermore, the gate driving circuit may also include a decoder 10, which can be connected to three initial signal lines STV1, STV2, and STV3. The decoder 10 can provide input signals to the first-stage shift register unit in the eight shift register unit groups based on the signals from the three initial signal lines STV1, STV2, and STV3. For example, the signals on the three initial signal lines STV1, STV2, and STV3 can form a 2 3 With various combinations, the decoder 10 can select to provide input signals to any group of shift register units based on different combinations of signals on the three clock signal lines.

[0404] According to one aspect of this disclosure, a display panel is provided, wherein the display panel includes the gate driving circuit described above.

[0405] According to one aspect of this disclosure, a display panel driving method is provided, wherein the method is used to drive the aforementioned display panel, and the driving method further includes:

[0406] Within the same time period, control the number of frames in the second driving state of the shift register unit corresponding to different display areas in the display panel;

[0407] Among them, the refresh frequency of the display area corresponding to the shift register unit with a smaller frame number in the second driving state is greater than the refresh frequency of the display area corresponding to the shift register unit with a larger frame number in the second driving state.

[0408] This exemplary embodiment also provides a display device, which may include the display panel described above, and may be a mobile phone, a laptop computer, a television, a computer monitor, etc.

[0409] In one exemplary embodiment of this disclosure, other embodiments of the disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of the disclosure that follow the general principles of the disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of the disclosure are indicated by the claims.

[0410] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0411] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. A shift register unit, wherein, The shift register unit is applied to a gate driving circuit, which includes multiple cascaded shift register units, each of which includes: A first output circuit is connected to a second control node and a first output terminal. The first output circuit is used to respond to the signal of the second control node to input a signal to the first output terminal. The first output terminal is used to connect to the input signal terminal of the next-level shift register unit. A reset circuit is connected to the second control node, and the reset circuit is used to respond to a reset signal to input a signal to the second control node.

2. The shift register unit according to claim 1, wherein, The first output circuit can respond to the signal of the second control node to input a valid signal to the first output terminal; The reset circuit is used to respond to a reset signal to input an invalid signal to the second control node.

3. The shift register unit according to claim 1, wherein, The first output circuit is also connected to the first control node, and the first output circuit is also used to respond to the signal of the first control node to input a signal to the first output terminal; The reset circuit is also connected to the first control node, and the reset circuit is also used to respond to a reset signal to input a signal to the first control node.

4. The shift register unit according to claim 3, wherein, The first output circuit can respond to the signal of the first control node to input an invalid level signal to the first output terminal; The reset circuit is also used to respond to a reset signal to input a valid level signal to the first control node.

5. The shift register unit according to any one of claims 1-4, wherein, The shift register unit further includes: A first input circuit is connected to an input signal terminal and a first node. The first input circuit is used to respond to a control signal to transmit the signal from the input signal terminal to the first node. The reset circuit includes: A first reset circuit, the first reset circuit including a first sub-reset circuit and a second sub-reset circuit. The first sub-reset circuit is connected to the first node, the third control node, and the first reset signal terminal. The first sub-reset circuit is used to respond to the signal of the first reset signal terminal to connect the first node and the third control node. The second sub-reset circuit is connected to the first reset signal terminal and the third control node. The second sub-reset circuit is used to respond to the signal of the first reset signal terminal to input an invalid level signal to the third control node. The first sub-reset circuit and the second sub-reset circuit have different conduction level polarities, and the third control node is connected to the second control node.

6. The shift register unit according to claim 5, wherein, The first sub-reset circuit includes: The eleventh transistor has its first terminal connected to the first node, its second terminal connected to the third control node, and its gate connected to the first reset signal terminal. The second sub-reset circuit is also connected to the first power supply terminal. The second sub-reset circuit is used to respond to the signal from the first reset signal terminal by inputting an invalid level signal to the third control node using the first power supply terminal. The second sub-reset circuit includes: The twelfth transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the third control node, and its gate connected to the first reset signal terminal. The eleventh and twelfth transistors have different conduction level polarities.

7. The shift register unit according to any one of claims 1-4, wherein, The shift register unit further includes: A first input circuit is connected to an input signal terminal and a first node. The first input circuit is used to respond to a control signal to transmit the signal from the input signal terminal to the first node. The first node is connected to a third control node, and the third control node is connected to a second control node. The reset circuit includes: A first reset circuit is connected to a first reset signal terminal, a second reset signal terminal, a first output terminal, and a first node. The first reset circuit is used to respond to the signal of the first reset signal terminal to transmit the signal of the first output terminal to the second reset signal terminal, and to respond to the signal of the second reset signal terminal to input an invalid level signal to the first node.

8. The shift register unit according to claim 7, wherein, The first reset circuit is also connected to an input signal terminal. The first reset circuit is used to respond to the signal from the second reset signal terminal by using the input signal terminal to input an invalid level signal to the first node.

9. The shift register unit according to claim 7, wherein, The first reset circuit is also connected to a first power supply terminal. The first reset circuit is used to respond to the signal of the second reset signal terminal by using the first power supply terminal to input an invalid level signal to the first node.

10. The shift register unit according to claim 8, wherein, The first reset circuit includes: The eleventh transistor has its first terminal connected to the input signal terminal, its second terminal connected to the first node, and its gate connected to the second reset signal terminal. The twelfth transistor has its first terminal connected to the first output terminal, its second terminal connected to the second reset signal terminal, and its gate connected to the first reset signal terminal.

11. The shift register unit according to claim 9, wherein, The first reset circuit includes: The eleventh transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the first node, and its gate connected to the second reset signal terminal. The twelfth transistor has its first terminal connected to the first output terminal, its second terminal connected to the second reset signal terminal, and its gate connected to the first reset signal terminal.

12. The shift register unit according to claim 5 or 6, wherein, The reset circuit also includes: The second reset circuit is connected to the second power supply terminal, the first reset signal terminal, and the first control node. The second reset circuit is used to respond to the signal of the first reset signal terminal to transmit the effective level signal of the second power supply terminal to the first control node.

13. The shift register unit according to claim 12, wherein, The second reset circuit includes: The thirteenth transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the first control node, and its gate connected to the first reset signal terminal.

14. The shift register unit according to any one of claims 7-11, wherein, The reset circuit also includes: The second reset circuit is connected to the second power supply terminal, the second reset signal terminal, and the first control node. The second reset circuit is used to respond to the signal from the second reset signal terminal to reset the second power supply terminal. The effective level signal at the source end is transmitted to the first control node.

15. The shift register unit according to claim 14, wherein, The second reset circuit includes: The thirteenth transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the first control node, and its gate connected to the second reset signal terminal.

16. The shift register unit according to any one of claims 1-15, wherein, The first output circuit is also connected to the second clock signal terminal. The first output circuit is used to respond to the signal of the second control node by using the second clock signal terminal to input an effective level to the first output terminal. The shift register unit further includes: A first input circuit is connected to an input signal terminal, a first node, and a first clock signal terminal. The first input circuit is used to respond to the signal of the first clock signal terminal to transmit the signal of the input signal terminal to the first node. The first node is connected to a third control node, and the third control node is connected to a second control node. The second input circuit is connected to the second power supply terminal, the first control node, and the first clock signal terminal. The second input circuit is used to respond to the signal of the first clock signal terminal to transmit the signal of the second power supply terminal to the first control node. A first control circuit is connected to a first clock signal terminal, a third control node, and a first control node. The first control circuit is used to respond to the signal of the third control node to transmit the signal of the first clock signal terminal to the first control node. The second control circuit is connected to the first power supply terminal, the second clock signal terminal, the first control node, and the third control node. The second control circuit is used to respond to the signals of the second clock signal terminal and the first control node to transmit the signal of the first power supply terminal to the third control node. An isolation circuit is provided to connect the third control node and the second control node in response to a control signal.

17. The shift register unit according to claim 16, wherein, The first output circuit includes: The fourth transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the first output terminal, and its gate connected to the first control node. The first capacitor has its first electrode connected to the first power supply terminal and its second electrode connected to the first... Control node; The fifth transistor has its first terminal connected to the second clock signal terminal, its second terminal connected to the first output terminal, and its gate connected to the second control node. The second capacitor has its first electrode connected to the second control node and its second electrode connected to the first output terminal. The first input circuit includes: The first transistor has a first terminal connected to the input signal terminal, a second terminal connected to the first node, and a gate connected to the first clock signal terminal. The second input circuit includes: The third transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the first control node, and its gate connected to the first clock signal terminal. The first control circuit includes: The second transistor has a first terminal connected to the first clock signal terminal, a second terminal connected to the first control node, and a gate connected to the third control node. The second control circuit includes: The sixth transistor has its first terminal connected to the first power supply terminal and its gate connected to the first control node. The seventh transistor has its first terminal connected to the second terminal of the sixth transistor, the second terminal connected to the third control node, and its gate connected to the second clock signal terminal. The isolation circuit is also connected to the second power supply terminal. The isolation circuit is used to respond to signals from the second power supply terminal to connect the third control node and the second control node. The isolation circuit includes: The eighth transistor has its first terminal connected to the third control node, its second terminal connected to the second control node, and its gate connected to the second power supply terminal.

18. The shift register unit according to any one of claims 1-15, wherein, The first output circuit is also connected to the second clock signal terminal. The first output circuit is used to respond to the signal of the second control node by using the second clock signal terminal to input an effective level to the first output terminal. The shift register unit further includes: The first input circuit connects the input signal terminal, the first node, and the first clock signal terminal. The first input circuit is used to respond to the signal of the first clock signal terminal to transmit the signal of the input signal terminal to the first node, the first node is connected to the third control node, and the third control node is connected to the second control node; The second input circuit is connected to the second power supply terminal, the first control node, and the third clock signal terminal. The second input circuit is used to respond to the signal of the third clock signal terminal to transmit the signal of the second power supply terminal to the first control node. A first control circuit is connected to a third clock signal terminal, a third control node, and a first control node. The first control circuit is used to respond to the signal of the third control node to transmit the signal of the third clock signal terminal to the first control node. The second control circuit is connected to the first power supply terminal, the second clock signal terminal, the first control node, and the third control node. The second control circuit is used to respond to the signals of the second clock signal terminal and the first control node to transmit the signal of the first power supply terminal to the third control node. An isolation circuit is provided to connect the third control node and the second control node in response to a control signal.

19. The shift register unit according to claim 18, wherein, The first output circuit includes: The fourth transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the first output terminal, and its gate connected to the first control node. The first capacitor has a first electrode connected to the first power supply terminal and a second electrode connected to the first control node. The fifth transistor has its first terminal connected to the second clock signal terminal, its second terminal connected to the first output terminal, and its gate connected to the second control node. The second capacitor has its first electrode connected to the second control node and its second electrode connected to the first output terminal. The third capacitor has its first electrode connected to the second power supply terminal and its second electrode connected to the first output terminal. The first input circuit includes: The first transistor has a first terminal connected to the input signal terminal, a second terminal connected to the first node, and a gate connected to the first clock signal terminal. The second input circuit includes: The third transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the first control node, and its gate connected to the third clock signal terminal. The first control circuit includes: The second transistor has its first terminal connected to the third clock signal terminal, its second terminal connected to the first control node, and its gate connected to the third control node. The second control circuit includes: The sixth transistor has its first terminal connected to the first power supply terminal and its gate connected to the first control node. The seventh transistor has its first terminal connected to the second terminal of the sixth transistor, the second terminal connected to the third control node, and its gate connected to the second clock signal terminal. The isolation circuit is also connected to the second power supply terminal. The isolation circuit is used to respond to signals from the second power supply terminal to connect the third control node and the second control node. The isolation circuit includes: The eighth transistor has its first terminal connected to the third control node, its second terminal connected to the second control node, and its gate connected to the second power supply terminal.

20. The shift register unit according to any one of claims 1-15, wherein, The first output circuit is also connected to the second clock signal terminal. The first output circuit is used to respond to the signal of the second control node by using the second clock signal terminal to input an effective level to the first output terminal. The shift register unit further includes: A first input circuit is connected to an input signal terminal, a second node, a first node, and a first clock signal terminal. The first input circuit is used to respond to the signal of the first clock signal terminal to transmit the signal of the input signal terminal to the second node, and to respond to the signal of the first clock signal terminal to transmit the signal of the second node to the first node. The first node is connected to a third control node, and the third control node is connected to the second control node. The second input circuit is connected to an input signal terminal, a first power supply terminal, a first control node, a second power supply terminal, and a third clock signal terminal. The second input circuit is used to respond to the signal of the input signal terminal to transmit the signal of the first power supply terminal to the first control node, and to respond to the signal of the third clock signal terminal to transmit the signal of the second power supply terminal to the first control node. The first leakage protection circuit is connected to the second clock signal terminal, the second node, and the first output terminal. The first leakage protection circuit is used to respond to the signal of the first output terminal to transmit the signal of the second clock signal terminal to the second node. A first control circuit is connected to a first power supply terminal, a first control node, a third control node, and a fourth control node. The first control circuit is used to respond to a signal from the first control node to transmit a signal from the first power supply terminal to the fourth control node, and to respond to a signal from the first control node to transmit a signal from the fourth control node to the third control node. The second leakage protection circuit is connected to the third control node, the second power supply terminal, and the fourth control node. The second leakage protection circuit is used to respond to the signal of the third control node to transmit the signal of the second power supply terminal to the fourth control node.

21. The shift register unit according to claim 20, wherein, The first output circuit includes: The fourth transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the first output terminal, and its gate connected to the first control node. The first capacitor has its first electrode connected to the first power supply terminal and its second electrode connected to the first control node. The fifth transistor has its first terminal connected to the second clock signal terminal, its second terminal connected to the first output terminal, and its gate connected to the second control node. The second capacitor has its first electrode connected to the first control node and its second electrode connected to the first output terminal. The first input circuit includes: The fourteenth transistor has its first terminal connected to the input signal terminal, its second terminal connected to the second node, and its gate connected to the first clock signal terminal. The first transistor has a first terminal connected to the second node, a second terminal connected to the first node, and a gate connected to the first clock signal terminal. The second input circuit includes: The seventh transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the first control node, and its gate connected to the input signal terminal. The third transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the first control node, and its gate connected to the third clock signal terminal. The first leakage protection circuit includes: The second transistor has its first terminal connected to the second clock signal terminal, its second terminal connected to the second node, and its gate connected to the first output terminal. The first control circuit includes: The ninth transistor has its first terminal connected to the third control node, its second terminal connected to the fourth control node, and its gate connected to the first control node. The tenth transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the fourth control node, and its gate connected to the first control node. The second leakage protection circuit includes: The sixth transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the fourth control node, and its gate connected to the third control node.

22. The shift register unit according to any one of claims 1-21, wherein, The shift register unit is used in the gate driving circuit of the display panel, the display panel including a pixel driving circuit, and the shift register unit includes: The second output circuit is used to provide a gate drive signal to the pixel drive circuit in the first driving state and to provide an invalid level signal to the pixel drive circuit in the second driving state.

23. The shift register unit according to claim 22, wherein, The second output circuit is connected to the first output terminal, the enable signal terminal, and the second output terminal. The second output circuit is used to respond to the signals of the enable signal terminal and the first output terminal to input the gate drive signal or the invalid level signal to the second output terminal. The second output terminal is used to connect to the pixel drive circuit.

24. The shift register unit according to claim 23, wherein, The shift register unit further includes: The first inverter has its input terminal connected to the first output terminal and its output terminal connected to the third output terminal. The second output circuit includes: A pre-storage circuit is connected to at least one of the first output terminal and the third output terminal in the upper-level shift register unit and a third node. The pre-storage circuit is used to respond to the signals of the first output terminal and / or the third output terminal to transmit the signal of the enable signal terminal to the third node. A latching circuit is connected to the third node and the fourth node, and the latching circuit is used to latch the inverted signal of the third node to the fourth node; A gating circuit is connected to the first output terminal, the fourth node, the second power supply terminal, and the fifth node of this stage shift register unit. The gating circuit is used to respond to the signal of the first output terminal to transmit the signal of the fourth node or the second power supply terminal to the fifth node. The second inverter has its input connected to the fifth node and its output connected to the second output terminal.

25. The shift register unit according to claim 24, wherein, The first inverter includes: The fifteenth transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the third output terminal, and its gate connected to the first output terminal. The sixteenth transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the third output terminal, and its gate connected to the first output terminal. Among them, the signal polarities on the first power supply terminal and the second power supply terminal are different, the conduction level of the fifteenth transistor is different from the signal polarity of the first power supply terminal, and the conduction level of the sixteenth transistor is different from the signal polarity of the second power supply terminal. The pre-stored circuit includes: The seventeenth transistor has its first terminal connected to the enable signal terminal, its second terminal connected to the third node, and its gate connected to the third output terminal of the upper-level shift register unit. The eighteenth transistor has its first terminal connected to the enable signal terminal, its second terminal connected to the third node, and its gate connected to the first output terminal of the upper-level shift register unit. Wherein, the conduction level of the seventeenth transistor is the same as the signal polarity of the first power supply terminal, and the conduction level of the eighteenth transistor is the same as the signal polarity of the second power supply terminal; The latching circuit includes: The nineteenth transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the fourth node, and its gate connected to the third node. The twentieth transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the fourth node, and its gate connected to the third node. The twenty-first transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the third node, and its gate connected to the fourth node. The 22nd transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the third node, and its gate connected to the fourth node. Wherein, the conduction level of the twentieth and twenty-second transistors is the same as the signal polarity of the first power supply terminal, and the conduction level of the nineteenth and twenty-first transistors is the same as the signal polarity of the second power supply terminal; The gating circuit includes: The 23rd transistor has its first terminal connected to the fourth node, its second terminal connected to the fifth node, and its gate connected to the first output terminal. The 24th transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the fifth node, and its gate connected to the first output terminal. The fourth capacitor has its first electrode connected to the second power supply terminal and its second electrode connected to the fifth node. The conduction level of the 23rd transistor is the same as the signal polarity of the second power supply terminal, and the conduction level of the 24th transistor is the same as the signal polarity of the first power supply terminal.

26. The shift register unit according to claim 23, wherein, The shift register unit further includes: The first inverter has its input terminal connected to the first output terminal and its output terminal connected to the third output terminal. The second output circuit includes: A pre-storage circuit is connected to at least one of the first output terminal and the third output terminal in the current shift register unit, and a third node. The pre-storage circuit is used to respond to the signals of the first output terminal and / or the third output terminal to transmit the signal of the enable signal terminal to the third node. A latching circuit is connected to the third node and the fourth node, and the latching circuit is used to latch the inverted signal of the third node to the fourth node; A gating circuit is connected to the first output terminal, the fourth node, the second power supply terminal, and the fifth node of this stage shift register unit. The gating circuit is used to respond to the signal of the first output terminal to transmit the signal of the fourth node or the second power supply terminal to the fifth node. The second inverter has its input connected to the fifth node and its output connected to the second output terminal.

27. The shift register unit according to claim 26, wherein, The first inverter includes: The fifteenth transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the third output terminal, and its gate connected to the first output terminal. The sixteenth transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the third output terminal, and its gate connected to the first output terminal. Among them, the signal polarities on the first power supply terminal and the second power supply terminal are different, the conduction level of the fifteenth transistor is different from the signal polarity of the first power supply terminal, and the conduction level of the sixteenth transistor is different from the signal polarity of the second power supply terminal. The pre-stored circuit includes: The seventeenth transistor has its first terminal connected to the enable signal terminal, its second terminal connected to the third node, and its gate connected to the third output terminal of the shift register unit of this stage. The eighteenth transistor has its first terminal connected to the enable signal terminal, its second terminal connected to the third node, and its gate connected to the first output terminal of the shift register unit of this stage. Wherein, the conduction level of the seventeenth transistor is the same as the signal polarity of the first power supply terminal, and the conduction level of the eighteenth transistor is the same as the signal polarity of the second power supply terminal; The latching circuit includes: The nineteenth transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the fourth node, and its gate connected to the third node. The twentieth transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the fourth node, and its gate connected to the third node. The twenty-first transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the third node, and its gate connected to the fourth node. The 22nd transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the third node, and its gate connected to the fourth node. Wherein, the conduction level of the twentieth and twenty-second transistors is the same as the signal polarity of the first power supply terminal, and the conduction level of the nineteenth and twenty-first transistors is the same as the signal polarity of the second power supply terminal; The gating circuit includes: The twenty-third transistor has its first terminal connected to the fourth node and its second terminal connected to the fifth node. The node has its gate connected to the first output terminal; The 24th transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the fifth node, and its gate connected to the first output terminal. The conduction level of the 23rd transistor is the same as the signal polarity of the second power supply terminal, and the conduction level of the 24th transistor is the same as the signal polarity of the first power supply terminal.

28. The shift register unit according to any one of claims 24-27, wherein, The latching circuit is connected to a first power supply terminal and a second power supply terminal. The first power supply terminal and the second power supply terminal are respectively used to provide power signals with different polarities to the latching circuit. The second inverter is connected to the first power supply terminal and the second power supply terminal. The first power supply terminal and the second power supply terminal are respectively used to provide power signals with different polarities to the second inverter. The second inverter includes: The 25th transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the second output terminal, and its gate connected to the fifth node. The 26th transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the second output terminal, and its gate connected to the fifth node. The conduction level of the 25th transistor is the same as the signal polarity of the second power supply terminal, and the conduction level of the 26th transistor is the same as the signal polarity of the first power supply terminal.

29. The shift register unit according to any one of claims 24-27, wherein, The latching circuit is connected to a first power supply terminal and a second power supply terminal. The first power supply terminal and the second power supply terminal are respectively used to provide power signals with different polarities to the latching circuit. The second inverter is connected to a third power supply terminal and a fourth power supply terminal. The third power supply terminal and the fourth power supply terminal are respectively used to provide power signals with different polarities to the second inverter. The second inverter includes: The 25th transistor has its first terminal connected to the third power supply terminal, its second terminal connected to the second output terminal, and its gate connected to the fifth node. The 26th transistor has its first terminal connected to the fourth power supply terminal, its second terminal connected to the second output terminal, and its gate connected to the fifth node. The conduction level of the 25th transistor is the same as the signal polarity of the fourth power supply terminal, and the conduction level of the 26th transistor is the same as the signal polarity of the third power supply terminal. When the first power supply terminal and the third power supply terminal are used to provide a high-level signal, and the second power supply terminal and the fourth power supply terminal are used to provide a low-level signal, the voltage of the first power supply terminal is greater than or equal to the voltage of the third power supply terminal, and the voltage of the second power supply terminal is less than or equal to the voltage of the fourth power supply terminal. When the first power supply terminal and the third power supply terminal are used to provide a low-level signal, and the second power supply terminal and the fourth power supply terminal are used to provide a high-level signal, the voltage of the first power supply terminal is less than or equal to the voltage of the third power supply terminal, and the voltage of the second power supply terminal is greater than or equal to the voltage of the fourth power supply terminal.

30. The shift register unit according to any one of claims 3-29, wherein, The shift register unit is used in the gate drive circuit in the display panel, and the reset circuit is used to input a valid level to the first control node before the next frame and to input an invalid level to the second control node.

31. The shift register unit according to claim 30, wherein, The driving method of the display panel includes a blank period between frames, and the reset circuit is used to input a valid level to the first control node and an invalid level to the second control node during the blank period.

32. The shift register unit according to claim 22, wherein, The first output circuit is also connected to the second clock signal terminal. The first output circuit is used to respond to the signal of the second control node by using the second clock signal terminal to input an effective level to the first output terminal. When the second output circuit is in the first driving state, the pulse frequency of the effective level on the second clock signal terminal is n1; When the second output circuit is in the second driving state, the pulse frequency of the effective level on the second clock signal terminal is n2; Where n1 is greater than or equal to n2.

33. A gate driving circuit, wherein, The gate drive circuit includes a plurality of shift register units as described in any one of claims 1-32, wherein the plurality of shift register units are cascaded.

34. The gate driving circuit according to claim 33, wherein, The gate driving circuit includes: Multiple shift register unit groups, wherein the shift register unit groups include multiple cascaded shift register units. The shift register unit described above; A switching unit is provided, in which two shift register units located in different shift register unit groups and cascaded are connected through the switching unit; In each of the shift register unit groups, the first-level shift register unit is connected to a different initialization signal terminal.

35. A display panel, wherein, The display panel includes the gate driving circuit as described in claim 33 or 34.

36. A display panel driving method, wherein, For driving the display panel of claim 35, wherein the driving method includes: Within the same time period, control the number of frames in the second driving state of the shift register unit corresponding to different display areas in the display panel; Among them, the refresh frequency of the display area corresponding to the shift register unit with a smaller frame number in the second driving state is greater than the refresh frequency of the display area corresponding to the shift register unit with a larger frame number in the second driving state.

37. The display panel driving method according to claim 36, wherein, When the first output circuit is also connected to the second clock signal terminal, the first output circuit is used to respond to the signal of the second control node by using the second clock signal terminal to input an effective level to the first output terminal. At least a portion of the low-frequency display area forms the last scan area of ​​the display panel, and within the same frame, the driving method includes: When the shift register unit corresponding to the low-frequency display area that forms the end scan area is in the second driving state, the pulse frequency of the effective level on the second clock signal terminal is set to n2; When the shift register unit corresponding to the high-frequency display area is in the first driving state, the pulse frequency of the effective level on the second clock signal terminal is set to n1; Where n1 is greater than or equal to n2.

38. The display panel driving method according to claim 36, wherein, The display panel includes multiple sub-display areas, and the gate driving circuit includes: Multiple shift register unit groups, each group comprising multiple cascaded shift register units, are configured correspondingly with the sub-display areas. Each shift register unit group is used to provide gate drive signals to its corresponding sub-display area. Switching units, located in different shift register unit groups and cascaded with two shift registers The register units are cascaded through the switch units; In each of the shift register unit groups, the first-level shift register unit is connected to a different initialization signal terminal; At least a portion of the low-frequency display area forms the end scan area of ​​the sub-display area. Within the same frame of the same sub-display area, the driving method includes: When the shift register unit corresponding to the low-frequency display area that forms the end scan area is in the second driving state, the pulse frequency of the effective level on the second clock signal terminal is set to n2; When the shift register unit corresponding to the high-frequency display area is in the first driving state, the pulse frequency of the effective level on the second clock signal terminal is set to n1; Where n1 is greater than or equal to n2.

Images